Electro-optical devices and electronic equipment

Abstract

To provide an electrooptical device and electronic equipment in each of which coupling capacitance between a sensor element and wiring is suppressed and the output voltage of a sensor circuit can be thereby improved.SOLUTION: In an electrooptical device 100, a light-shielding layer 2a is provided between a sensor element 11 located outside a display region 10a and a substrate main body 10w, and wiring 6m is provided while being spaced apart from the sensor element 11. A plurality of diode elements D are electrically connected in series in the sensor element 11. The light-shielding layer 2a includes a first light-shielding layer 2a15 that overlaps a semiconductor layer 31h of the sensor element 11 in a plan view and a second light-shielding layer 2a14 that overlaps the wiring 6m in a plan view. The first light-shielding layer 2a15 and the second light-shielding layer 2a14 are separated from each other in a plan view, so that coupling capacitance between the sensor element 11 and the wring 6m is small. The output voltage of a sensor circuit 1 can be therefore stabilized.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device provided with a sensor element such as a temperature sensor. [Background technology]

[0002] In electro-optical devices such as liquid crystal devices, a technology has been proposed in which a sensor element such as a temperature sensor is provided outside the display area, and driving conditions are corrected based on the detection results of the sensor element. In this case, if wiring that supplies an AC signal is provided near the output line extending from the temperature sensor, changes in the potential of the wiring may affect the output signal of the temperature sensor, causing fluctuations in the detected value of the temperature sensor. To address this, a technology has been proposed in which a shield layer to which a constant potential is applied is provided between the output line of the temperature sensor and the wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-73810 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, in electro-optical devices used in projectors, when light emitted from a light source enters the display area, stray light to the periphery can cause peripheral circuit patterns, including sensor elements located outside the display area, to appear in the projected image. To address this issue, a light-shielding layer is sometimes provided in the area that overlaps the sensor element in a planar view. However, if the electrically floating light-shielding layer faces the signal wiring in the area that overlaps the sensor element in a planar view, parasitic capacitance between the sensor element and the light-shielding layer, and between the light-shielding layer and the signal wiring, can affect the sensor element and cause fluctuations in the output value of the sensor circuit. As an example of avoiding the effects of coupling capacitance between the signal wiring and the sensor element, Patent Document 1 discloses a configuration in which a constant-potential wiring is placed between the signal wiring and the sensor element in a planar view to provide shielding. However, even with this configuration, parasitic capacitance still exists between the sensor element and the light-shielding layer, and between the light-shielding layer and the signal wiring, so the problem remains. Furthermore, the constant-potential wiring itself can become a noise source when the electro-optical device is driven. Therefore, there is a problem that it is necessary to stabilize the output voltage of the sensor circuit by suppressing the coupling capacitance between the sensor element and the wiring. [Means for solving the problem]

[0005] In order to solve the above problems, one aspect of the electro-optical device according to the present invention is a substrate body and a display area. A sensor element having a semiconductor layer is provided outside the area, and a semiconductor layer is provided so as not to overlap with the semiconductor layer in a plan view. and a wiring disposed between the substrate body and the semiconductor layer and planar with the semiconductor layer. a first light-shielding layer that overlaps the wiring in plan view, the first light-shielding layer being disposed between the substrate body and the wiring and being in a plane with the wiring; The second light-shielding layer overlaps the another light-shielding layer adjacent to the second light-shielding layer in a plan view; Equipped with The first light-shielding layer and the second light-shielding layer are formed between the semiconductor layer and the wiring in plan view. They are spaced apart by less than 2 μm. and the distance between the first light-shielding layer and the second light-shielding layer is is longer than the distance between the second light-shielding layer and the other light-shielding layer. It is characterized by:

[0006] The electro-optical device according to the present invention is used in electronic equipment. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a plan view showing an example of the configuration of an electro-optical device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is an explanatory diagram schematically showing a cross section of the electro-optical device shown in FIG. [Figure 3] FIG. 2 is a circuit block diagram showing the electrical configuration of the electro-optical device shown in FIG. [Figure 4] FIG. 2 is a cross-sectional view schematically showing an example of the configuration of a pixel of the electro-optical device shown in FIG. [Figure 5] FIG. 2 is an explanatory diagram of a sensor circuit of the electro-optical device shown in FIG. [Figure 6] FIG. 6 is a plan view schematically showing the planar configuration of the sensor element and its periphery shown in FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view schematically showing a cross section of the sensor element etc. shown in FIG. 6. [Figure 8] FIG. 4 is an explanatory diagram of the inspection area shown in FIG. 3. [Figure 9] FIG. 10 is a plan view of a comparative example of the present invention. [Figure 10] FIG. 10 is an explanatory diagram schematically showing the BB′ cross section of FIG. 9. [Figure 11] An explanatory diagram of a spike noise model that occurs in wiring. [Figure 12] 10 is a graph showing the relationship between the capacitance coupled to the relay portion of the diode element and the output voltage of the sensor circuit. [Figure 13] FIG. 4 is an explanatory diagram of an electro-optical device according to a second embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view schematically showing a cross section of the sensor element etc. shown in FIG. [Figure 15] FIG. 6 is an explanatory diagram of an inspection area of ​​an electro-optical device according to a second embodiment of the present invention. [Figure 16] FIG. 10 is an explanatory diagram of a diode element used to demonstrate the effects of the second embodiment. [Figure 17]17 is a graph showing a comparison of the temperature characteristics of the forward voltage of the diode elements of type (a) and type (b) shown in FIG. 16. [Figure 18] 17 is a graph showing the temperature characteristics of the forward voltage of the diode element of type (a) shown in FIG. 16. [Figure 19] 1 is a block diagram showing an example of the configuration of a projection display device to which the present invention is applied. [Figure 20] FIG. 20 is an explanatory diagram of the light path shift element shown in FIG. 19. DETAILED DESCRIPTION OF THE INVENTION

[0008] An embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, each layer and each component is shown at a different scale so that they can be easily recognized. When describing the arrangement of layers formed on the first substrate, the upper layer side or surface side refers to the side opposite the side where the first substrate is located (the side where the counter substrate and liquid crystal layer are located), and the lower layer side refers to the side where the first substrate is located. When describing the arrangement of layers formed on the second substrate, the upper layer side or surface side refers to the side opposite the side where the counter substrate is located (the side where the first substrate and liquid crystal layer are located), and the lower layer side refers to the side where the second substrate is located. In the present invention, the term "planar view" refers to a view from the normal direction to the first substrate 10 or the second substrate 20.

[0009] 1. Embodiment 1-1. Specific configuration of the electro-optical device 100 FIG. 1 is a plan view showing an example of the configuration of an electro-optical device 100 according to a first embodiment of the present invention. FIG. 2 is an explanatory diagram schematically showing a cross section of the electro-optical device 100 shown in FIG. 1. The electro-optical device 100 shown in FIGS. 1 and 2 is a liquid crystal device and includes a liquid crystal panel 100p. In the electro-optical device 100, a first substrate 10 and a second substrate 20 are bonded together with a predetermined gap therebetween by a sealant 107. The sealant 107 is provided in a frame shape along the outer edge of the second substrate 20. The sealant 107 is an adhesive made of a photocurable resin, a thermosetting resin, or the like, and contains a gap material 107a such as glass fiber or glass beads to maintain a predetermined distance between the two substrates. In the electro-optical device 100, an electro-optical layer 50 made of a liquid crystal layer is provided between the first substrate 10 and the second substrate 20 within a region surrounded by the sealant 107. The sealant 107 has a discontinuous portion 107c formed therein to serve as a liquid crystal injection port, and this discontinuous portion 107c is sealed with a sealing material 108 after the liquid crystal material is injected. Note that if the liquid crystal material is injected using a dropping method, the discontinuous portion 107c is not formed. The first substrate 10 and the second substrate 20 are both rectangular, and a display area 10a is provided as a rectangular area approximately in the center of the electro-optical device 100. Corresponding to this shape, the sealant 107 is also provided in a substantially rectangular shape, and the outside of the display area 10a is a rectangular frame-shaped peripheral area 10c.

[0010] In the display region 10a, two sides extending in the first direction X are defined as a first side 10a1 and a second side 10a2, and two sides extending in the second direction Y are defined as a third side 10a3 and a fourth side 10a4. In the peripheral region 10c of the first substrate 10, a data line driving circuit 101 is provided between an end of the first substrate 10 and the first side 10a1 of the display region 10a, and a precharge circuit 105 is provided between the end of the first substrate 10 and the second side 10a2 of the display region 10a. Furthermore, a scanning line driving circuit 104 is provided between the end of the first substrate 10 and the third side 10a3 of the display region 10a and between the end of the first substrate 10 and the fourth side 10a4 of the display region 10a. Furthermore, a plurality of mounting terminals 102 to which a flexible wiring board (not shown) is connected are arranged on the end of the first substrate 10 on the data line driving circuit 101 side.

[0011] The first substrate 10 has a translucent substrate body 10w such as a quartz substrate or a glass substrate. A display region 10a on one surface 10s of the first substrate 10, facing the second substrate 20, is provided with a matrix of pixel transistors and pixel electrodes 9a electrically connected to each of the pixel transistors. A first alignment film 16 is formed on the upper layer of the pixel electrodes 9a. A rectangular frame region 10b on the one surface 10s of the first substrate 10 extends between the outer edge of the display region 10a and the sealing material 107. Dummy pixel electrodes 9b, formed simultaneously with the pixel electrodes 9a, are provided in portions extending along each side of the display region 10a. The surface of the first substrate 10 opposite the one surface 10s facing the second substrate 20 is labeled 10t.

[0012] The second substrate 20 has a light-transmitting substrate body 20w such as a quartz substrate or a glass substrate. A common electrode 21 is formed on one surface 20s of the second substrate 20, facing the first substrate 10. The common electrode 21 is formed on substantially the entire surface of the one surface 20s of the second substrate 20. On the one surface 20s of the second substrate 20, a light-shielding parting line 29 is formed below the common electrode 21 in the frame-shaped region 10b, and a second alignment film 26 is laminated on the surface of the common electrode 21. The inner edge of the parting line 29 defines the display region 10a. A light-transmitting planarizing film 22 is formed between the parting line 29 and the common electrode 21. The light-shielding layer constituting the parting line 29 may be formed as a black matrix portion overlapping the inter-pixel region 10f sandwiched between adjacent pixel electrodes 9a. The parting line 29 is formed at a position overlapping the dummy pixel electrodes 9b in plan view. The parting line 29 is made of a light-shielding metal film or black resin. The surface of the second substrate 20 opposite to the surface 20s facing the first substrate 10 is marked with the symbol 20t.

[0013] The first alignment film 16 and the second alignment film 26 are made of SiO X The electro-optical device 100 is an inorganic alignment film made of an obliquely evaporated film of TiO2, MgO, Al2O3, or the like (x≦2), and is made of a columnar structure layer in which pillar-shaped bodies called columns are formed obliquely with respect to the first substrate 10 and the second substrate 20. Therefore, the first alignment film 16 and the second alignment film 26 align the nematic liquid crystal molecules with negative dielectric anisotropy used in the electro-optical layer 50 at an oblique angle with respect to the first substrate 10 and the second substrate 20, imparting a pretilt to the liquid crystal molecules. In this way, the electro-optical device 100 is configured as a normally black VA (Vertical Alignment) mode liquid crystal device.

[0014] On the first substrate 10, outside the sealing material 107, electrode portions 14t for inter-substrate conduction are formed at positions overlapping four corner portions 24t of the second substrate 20. The electrode portions 14t for inter-substrate conduction are electrically connected to wiring 6g, and the wiring 6g is electrically connected to a terminal 102g, of the terminals 102, for applying a common potential COM. An inter-substrate conductive material 109 containing conductive particles is disposed between the electrode portions 14t for inter-substrate conduction and the corner portions 24t of the second substrate 20, and the common electrode 21 of the second substrate 20 is electrically connected to the first substrate 10 via the electrode portions 14t for inter-substrate conduction and the inter-substrate conductive material 109. Therefore, a common potential COM is applied to the common electrode 21 from the first substrate 10 side.

[0015] The terminals 102 include a terminal 102g for supplying a common potential COM. The terminals 102 also include a cathode terminal 102c electrically connected to a cathode wiring Lc of the sensor circuit 1 (described later) and an anode terminal 102a electrically connected to an anode wiring La. The terminals 102 also include terminals for supplying an output control signal ENBY, a constant potential VDDY, and a constant potential VSSY (described later with reference to FIG. 6).

[0016] The electro-optical device 100 of this embodiment is a transmissive liquid crystal device. Therefore, the pixel electrodes 9a and the common electrode 21 are formed of a translucent conductive film such as an ITO (Indium Tin Oxide) film or an IZO (Indium Zinc Oxide) film. In such a transmissive liquid crystal device, for example, light from a light source incident from the second substrate 20 side is modulated while being emitted from the first substrate 10, thereby displaying an image. Note that if the pixel electrodes 9a are made of a reflective metal such as aluminum, the electro-optical device 100 can be made into a reflective liquid crystal device.

[0017] The electro-optical device 100 can be used as a color display device for electronic devices such as mobile computers and mobile phones, and in this case, a color filter (not shown) is formed on the second substrate 20 or the first substrate 10. The electro-optical device 100 can also be used as an RGB light valve in a projection display device, which will be described later. In this case, no color filter is formed on each of the RGB electro-optical devices 100, because light of each color separated by, for example, a dichroic mirror for RGB color separation is incident on each of the RGB electro-optical devices 100 as projected light.

[0018] 1-2. Electrical configuration of the electro-optical device 100 Figure 3 is a circuit block diagram showing the electrical configuration of the first substrate 10 shown in Figure 2. Figure 3 shows the state before the first substrate 10 is separated from the large substrate 150, with the portion corresponding to the first substrate 10 indicated by the thick line L10. On the four sides of the first substrate 10, scribe areas of the same width are set based on the scribe center line 10e. Therefore, the rectangle defined by the thick line L10 is smaller than the rectangle defined by the scribe center line 10e.

[0019] In FIG. 3, the first substrate 10 has a display area 10a in which a plurality of pixels 100a are arranged in a matrix in a substantially central region. Inside the display area 10a of the first substrate 10, a plurality of scanning lines 3a extending in a first direction X from a scanning line driving circuit 104 and a plurality of data lines 6a extending in a second direction Y from a data line driving circuit 101 are provided. The pixels 100a are configured corresponding to the intersections of the scanning lines 3a and the data lines 6a. The plurality of data lines 6a are electrically connected to a precharge circuit 105 disposed on a second side 10a2 of the display area 10a. Each of the plurality of pixels 100a includes a pixel transistor 30, such as a field-effect transistor, and a pixel electrode 9a electrically connected to the pixel transistor 30. The source of the pixel transistor 30 is electrically connected to the data line 6a, the gate of the pixel transistor 30 is electrically connected to the scanning line 3a, and the drain of the pixel transistor 30 is electrically connected to the pixel electrode 9a. An image signal is supplied to the data line 6a by a data line driving circuit 101, and a scanning signal is supplied to the scanning line 3a by a scanning line driving circuit 104. Although not shown, the precharge circuit 105 is a transistor array in which one source-drain electrode is electrically connected to the data line 6a, the other source-drain electrode is electrically connected to a precharge power supply line, and the gate is electrically connected to a control signal line.

[0020] In each pixel 100a, the pixel electrode 9a faces the common electrode 21 of the second substrate 20 described with reference to FIG. 2 via the electro-optical layer 50, forming a liquid crystal capacitance 50a. A storage capacitance 55 is added to each pixel 100a in parallel with the liquid crystal capacitance 50a to prevent fluctuations in the image signal stored in the liquid crystal capacitance. In this embodiment, to form the storage capacitance 55, a capacitance line 8a extending across the multiple pixels 100a is formed on the first substrate 10, and a common potential COM is supplied to the capacitance line 8a. The capacitance line 8a is arranged to overlap at least one of the scanning line 3a and the data line 6a in a planar view. FIG. 3 illustrates an example in which the capacitance line 8a overlaps both the scanning line 3a and the data line 6a in a planar view. The capacitance line 8a may also be configured to overlap the data line 6a in a planar view without overlapping the scanning line 3a. Although not shown, the capacitance line 8a is electrically connected to the wiring 6g described in FIG. 1.

[0021] On the first substrate 10, a sensor circuit 1, which will be described later with reference to Fig. 5 and the like, is configured outside the display region 10a. Also, on the first substrate 10, an inspection region 17 for inspecting the electrical characteristics of elements constituting the sensor circuit 1 and the like may be provided outside the display region 10a. In this embodiment, the sensor circuit 1 is a sensor circuit for detecting temperature.

[0022] As shown in FIG. 3 , components of the first substrate 10, such as pixel transistors 30 and pixel electrodes 9a, are formed in the form of a large substrate 150 from which multiple first substrates 10 can be obtained. After the second substrate 20 is attached, the large substrate 150 is divided into multiple first substrates 10 along the scribe center line 10e. Short-circuiting wires 10g are formed on the large substrate 150 along the scribe center line 10e so as to surround the first substrate 10, and multiple terminals 102 are electrically connected to the short-circuiting wires 10g via resistor elements R. This prevents static electricity from damaging circuit elements such as transistors during the manufacturing process. The short-circuiting wires 10g are made of a conductive film such as a conductive polysilicon film, a metal film, or a metal compound film. For example, the short-circuiting wires 10g are made of a laminated film of tungsten silicide (WSi) and a conductive polysilicon film. Note that the resistor elements R are destroyed when the large substrate is divided. The resistor elements R are made of conductive polysilicon or the like having a resistance value of approximately 1 M to 10 MΩ.

[0023] 1-3. Specific configuration of pixel 100a FIG. 4 is a cross-sectional view schematically illustrating an example of the configuration of a pixel 100a of the electro-optical device 100 shown in FIG. 1. As shown in FIG. 4, a lower light-shielding layer 2a made of a conductive film such as a metal silicide film, a metal film, or a metal compound film is formed on the first substrate 10. The light-shielding layer 2a is formed along the scanning lines 3a. In this embodiment, the light-shielding layer 2a is made of tungsten silicide or the like. A light-transmitting insulating film 41 made of a silicon oxide film or the like is formed on the upper layer side of the light-shielding layer 2a, and a pixel transistor 30 including a semiconductor layer 31a is formed on the surface side of the insulating film 41. The light-shielding layer 2a prevents return light, etc., incident from the substrate main body 10w side from entering the pixel transistor 30.

[0024] The pixel transistor 30 includes a semiconductor layer 31a and a gate electrode 33g made of a part of the scanning line 3a that intersects with the semiconductor layer 31a. A light-transmitting gate insulating layer 32 made of a silicon oxide film or the like is provided between the semiconductor layer 31a and the gate electrode 33g. The gate electrode 33g is a conductive film formed simultaneously in the same layer as the short-circuit line 10g shown in FIG. 3. More specifically, the gate electrode 33g is a laminated film of tungsten silicide and conductive polysilicon. The semiconductor layer 31a is made of a polysilicon film or the like. The pixel transistor 30 has an LDD (Lightly Doped Drain) structure. More specifically, in the pixel transistor 30, the source region 31s includes a high-concentration region 31s1 separated from the channel region 31g and a low-concentration region 31s2 sandwiched between the channel region 31g and the high-concentration region 31s1, and the drain region 31d includes a high-concentration region 31d1 separated from the channel region 31g and a low-concentration region 31d2 sandwiched between the channel region 31g and the high-concentration region 31d1. Note that the light-shielding layer 2a may be used as the scanning line 3a, and the gate electrode 33g may be electrically connected to the light-shielding layer 2a via a contact hole (not shown) that penetrates the gate insulating layer 32 and the insulating film 41.

[0025] Light-transmitting insulating films 42, 43, 44, 45, 46, and 47 made of silicon oxide films or the like are stacked in this order on the upper layer side of the gate electrode 33g, and the storage capacitor 55 described with reference to Fig. 3 is configured between the insulating films 42, 43, 44, and 45. In this embodiment, the storage capacitor 55 includes a first storage capacitor 551 configured between the insulating film 42 and the insulating film 44, and a second storage capacitor 552 configured between the insulating film 43 and the insulating film 45, and the first storage capacitor 551 and the second storage capacitor 552 are electrically connected in parallel.

[0026] More specifically, a first electrode 4a is formed between the insulating film 42 and the insulating film 43. The insulating film 43 has an opening 43a formed by removing a portion of the insulating film 43 that overlaps with the first electrode 4a in a planar view, and a portion of the first electrode 4a is exposed from the insulating film 43 at the bottom of the opening 43a. An insulating film 48 and a second electrode 5a are stacked in this order between the insulating films 43 and 44, and the first electrode 4a and the second electrode 5a overlap at the bottom of the opening 43a in a planar view via the insulating film 48. Therefore, the first electrode 4a and the second electrode 5a form a first storage capacitor 551, whose main dielectric film is the insulating film 48. The insulating film 43 protects the first electrode 4a when the second electrode 5a and the insulating film 48 are patterned. Therefore, the first electrode 4a and the second electrode 5a overlap outside the opening 43a via the insulating films 43 and 48, but overlap inside the opening 43a only via the insulating film 48. The portion outside the opening 43a where the first electrode 4a and the second electrode 5a overlap each other accounts for a small proportion of the capacitance of the first storage capacitor 551.

[0027] A third electrode 5b is formed between the insulating films 43 and 44. In this embodiment, the second electrode 5a and the third electrode 5b are made of the same conductive film. Therefore, in this embodiment, the second electrode 5a and the third electrode 5b are the same electrode. The insulating film 44 has an opening 44a formed by removing a portion of the insulating film 44 that overlaps with the third electrode 5b (second electrode 5a) in a planar view. A portion of the third electrode 5b is exposed from the insulating film 44 at the bottom of the opening 44a. An insulating film 49 and a fourth electrode 7a are stacked in this order between the insulating films 44 and 45. The third electrode 5b (second electrode 5a) and the fourth electrode 7a overlap with each other at the bottom of the opening 44a via the insulating film 49 in a planar view. Therefore, the third electrode 5b (second electrode 5a) and the fourth electrode 7a constitute a second storage capacitor 552, whose dielectric film is mainly the insulating film 49. The insulating film 44 protects the third electrode 5b (second electrode 5a) when the fourth electrode 7a and the insulating film 49 are patterned. Therefore, the third electrode 5b (second electrode 5a) and the fourth electrode 7a overlap with each other outside the opening 44a via the insulating films 44 and 49, whereas inside the opening 44a they overlap with each other only via the insulating film 49. The portion where the third electrode 5b (second electrode 5a) and the fourth electrode 7a overlap with each other outside the opening 44a accounts for a small proportion of the capacitance of the second storage capacitor 552.

[0028] In this embodiment, the first electrode 4a is, for example, a conductive polysilicon film, and the insulating film 43 is, for example, a silicon oxide film. The insulating film 48 is, for example, silicon oxide, silicon nitride, or a laminated film thereof. The conductive film constituting the second electrode 5a and the third electrode 5b is, for example, a conductive polysilicon film, and the insulating film 44 is, for example, a silicon oxide film. The insulating film 49 is, for example, silicon oxide, silicon nitride, or a laminated film thereof. The fourth electrode 7a is, for example, tungsten silicide, and also functions as a light-shielding layer that suppresses light from entering the pixel transistor 30 from the pixel electrode 9a side.

[0029] In the first storage capacitor 551 and the second storage capacitor 552 configured in this manner, the conductive film constituting the second electrode 5a (third electrode 5b) is electrically connected to the drain region 31d of the pixel transistor 30 via a contact hole 43d that penetrates the gate insulating layer 32 and the insulating films 42 and 43. In addition, the relay electrode 6c formed between the insulating film 45 and the insulating film 46 is electrically connected to the first electrode 4a via a contact hole 45c that penetrates the insulating films 43, 44, and 45, and is also electrically connected to the fourth electrode 7a via a contact hole 45e that penetrates the insulating film 45. Therefore, a storage capacitor 55 in which the first storage capacitor 551 and the second storage capacitor 552 are electrically connected in parallel is configured between the conductive film constituting the second electrode 5a (third electrode 5b) and the relay electrode 6c.

[0030] A data line 6a is formed between the insulating films 45 and 46, and the data line 6a is electrically connected to the source region 31s of the pixel transistor 30 via a contact hole 45s that penetrates the gate insulating layer 32 and the insulating films 42, 43, 44, and 45. The data line 6a is, for example, a low-resistance wiring that is mainly made of aluminum. A relay electrode 6d is formed between the insulating films 45 and 46, and the relay electrode 6d is electrically connected to the conductive film that constitutes the second electrode 5a (third electrode 5b) via a contact hole 45d that penetrates the insulating films 44 and 45. The data line 6a and the relay electrodes 6c and 6d are made of conductive films that are simultaneously formed in the same layer.

[0031] A capacitance line 8a and a relay electrode 8d are formed between the insulating film 46 and the insulating film 47. The capacitance line 8a is electrically connected to the relay electrode 6c via a contact hole 46c that penetrates the insulating film 46. The relay electrode 8d is electrically connected to the relay electrode 6d via a contact hole 46d that penetrates the insulating film 46. The surface of the insulating film 46 is flattened by a CMP (Chemical Mechanical Polishing) process or the like. The capacitance line 8a and the relay electrode 8d are made of a conductive film that is simultaneously formed in the same layer, and is, for example, a conductive film mainly made of aluminum.

[0032] A pixel electrode 9a is formed on the insulating film 47. The pixel electrode 9a is electrically connected to the relay electrode 8d via a contact hole 47d that penetrates the insulating film 47. Therefore, the pixel electrode 9a is electrically connected to the conductive film that constitutes the second electrode 5a (third electrode 5b), and is further electrically connected to the drain region 31d of the pixel transistor 30.

[0033] 1.4-Sensor circuit 1 configuration Fig. 5 is an explanatory diagram of the sensor circuit 1 of the electro-optical device 100 shown in Fig. 1. Note that Fig. 5 also shows capacitances Cd, Ce, and Cd with a common potential COM wiring, which will be described later.

[0034] 3, in the electro-optical device 100 of this embodiment, a sensor circuit 1 is provided on the first substrate 10 outside the display region 10a. The sensor circuit 1 includes a sensor element 11 for detecting temperature and an electrostatic protection circuit 12 for protecting the sensor element 11 from surge currents. On the first substrate 10, the sensor element 11 is disposed near the display region 10a, and the electrostatic protection circuit 12 is provided between the sensor element 11 and an end of the first substrate 10 where the terminals 102 are arranged.

[0035] As shown in FIG. 5, the sensor element 11 includes, for example, a plurality of diode elements D connected in series. For example, if five diode elements D are electrically connected in series, the temperature sensitivity of the forward voltage VF can be set to approximately −10 mV / °C. For ease of explanation, FIG. 5 illustrates an example in which three diode elements D1 to D3 are electrically connected in series. An anode wiring La extending from the anode terminal 102a is electrically connected to the anode 11a of the diode element D1 of the sensor element 11. A cathode wiring Lc extending from the cathode terminal 102c is electrically connected to the cathode 11c of the diode element D3 of the sensor element 11.

[0036] With the electro-optical device 100 mounted on an electronic device, a minute forward drive current IF of approximately 100 nA to several μA is supplied from the temperature detection drive circuit 15 to the sensor element 11 of the sensor circuit 1 via the anode terminal 102a and the cathode terminal 102c via a flexible wiring board (not shown) connected to the first substrate 10. The temperature detection drive circuit 15 has a constant current circuit 151. In addition, the temperature detection drive circuit 15 may have a stabilizing capacitor 152 added between the constant current circuit 151 and ground to stabilize the output voltage of the sensor circuit 1. Unless otherwise specified, the output voltage of the sensor circuit 1 will be described as being synonymous with the forward voltage VF of the sensor element 11.

[0037] Here, the forward voltage VF of the sensor element 11, which is made of a diode element D, has a linear characteristic with respect to temperature. Therefore, by detecting the voltage VF between the anode terminal 102a and the cathode terminal 102c when a forward drive current IF of approximately 100 nA to several μA is supplied to the sensor element 11, the temperature of the display area 10a of the liquid crystal panel 100p can be detected. More specifically, within the specified temperature range when the electro-optical device 100 is used as a light valve or the like of a projection display device (described later), the voltage VF has a good linear characteristic with respect to temperature. Therefore, if the voltage VF is calibrated in advance, the temperature of the liquid crystal panel 100p can be detected. Since the sensor element 11 is disposed near the display area 10a, the sensor element 11 can properly detect the temperature of the display area 10a. Therefore, by correcting the image signal based on the temperature detection by the sensor circuit 1, the electro-optical device 100 can be driven under appropriate conditions corresponding to the temperature of the display area 10a, thereby displaying high-quality images.

[0038] In this embodiment, the electrostatic protection circuit 12 includes a transistor Tr connected between an anode wiring La and a cathode wiring Lc, and the transistor Tr is electrically connected in parallel to the sensor element 11. One source-drain region 31i of the transistor Tr is connected between the cathode terminal 102c of the cathode wiring Lc and the cathode 11c of the diode element D3 of the sensor element 11, and the other source-drain region 31j of the transistor Tr is connected between the anode terminal 102a of the anode wiring La and the anode 11a of the diode element D1 of the sensor element 11. In this embodiment, the transistor Tr is an N-channel thin-film transistor, similar to the pixel transistor 30.

[0039] In the electrostatic discharge protection circuit 12, a first capacitance element C1 and a second capacitance element C2 are connected in series between an anode wiring La and a cathode wiring Lc. More specifically, one end of the first capacitance element C1 is electrically connected to the cathode wiring Lc, one end of the second capacitance element C2 is electrically connected to the anode wiring La, and the other end of the first capacitance element C1 and the other end of the second capacitance element C2 are electrically connected to each other. Therefore, the first capacitance element C1 and the second capacitance element C2 are electrically connected in series between the anode wiring La and the cathode wiring Lc.

[0040] A first resistor R1 is inserted between the anode terminal 102a and the connection point between the anode line La and the second capacitor C2, and a second resistor R2 is inserted between the cathode terminal 102c and the connection point between the cathode line Lc and the first capacitor C1. A connection node Cn between the first capacitor C1 and the second capacitor C2 is electrically connected to the gate of the transistor Tr.

[0041] The electrostatic protection circuit 12 includes a resistor R3 electrically connected in parallel to the first capacitor C1. More specifically, the gate wiring Lg extending from the gate electrode 33t of the transistor Tr is electrically connected to the connection node Cn between the first capacitor C1 and the second capacitor C2, and is electrically connected to the cathode wiring Lc via the resistor R3. The transistor Tr functions as a discharge path. Because the gate electrode 33t of the transistor Tr is connected to the cathode wiring Lc via the resistor R3, the gate electrode 33t and the cathode wiring Lc are at the same potential in a static state. Therefore, since the transistor Tr is off, when the sensor element 11 detects temperature, the drive current IF supplied to the anode wiring La flows to the sensor element 11, not to the transistor Tr.

[0042] As described above, the electrostatic protection circuit 12 includes a transistor Tr electrically connected in parallel to the sensor element 11, a first capacitance element C1 electrically connected to the transistor Tr, and a resistance element R3 electrically connected in parallel to the first capacitance element C1. The electrostatic protection circuit 12 also includes a second capacitance element C2 electrically connected in series with the first capacitance element C1. Therefore, for example, when a surge current caused by static electricity flows in from the anode terminal 102a, the electrostatic protection circuit 12 protects the sensor element 11 from static electricity.

[0043] More specifically, in the electrostatic protection circuit 12, in a static state, the gate-source voltage of the transistor Tr is 0V, and the transistor Tr is off. When a surge current due to static electricity flows into the anode terminal 102a, the first resistor R1 suppresses voltage fluctuations, while the potential of the gate electrode 33t of the transistor Tr, which corresponds to the potential of the connection node Cn between the first capacitor C1 and the second capacitor C2, rises. This turns the transistor Tr on, and the surge current flows to the cathode terminal 102c via the transistor Tr and the cathode wiring Lc. The first resistor R1 reduces the surge current flowing from the anode terminal 102a, and the second resistor R2 reduces the surge current flowing from the cathode terminal 102c. The duration during which the transistor Tr is on is determined by the first capacitor C1, the second capacitor C2, the resistor R3, and the gate capacitance of the transistor Tr. After the discharge, the potential of the gate electrode 33t of the transistor Tr returns to the off potential by the resistance element R3. Therefore, the surge current flowing through the sensor element 11 is suppressed by the electrostatic protection circuit 12, and the sensor element 11 can be protected.

[0044] 1-5. Wiring around the sensor element 11 FIG. 6 is a plan view schematically illustrating the planar configuration around the sensor element 11 shown in FIG. 5. In FIG. 6, a portion of the capacitance line 8a is removed to clearly show the layout below the capacitance line 8a, and the removed portion is indicated by a dashed line. FIG. 6 also illustrates the outer edge 29a of the parting line 29. FIG. 7 is a cross-sectional view schematically illustrating the cross section of the sensor element 11 shown in FIG. 6. FIG. 7 corresponds to the cross section AA′ in FIG. 6. However, FIG. 7 also illustrates a cross section passing through the contact hole 45m. The driving signals supplied to the scanning line driving circuit 104 include a clock signal, a scanning direction designation signal, a start pulse signal, and an output control signal ENBY. FIG. 6 illustrates the output control signal ENBY being wired near the diode elements D1 to D3 that form the sensor element 11. The output control signal ENBY is basically a binary logic signal that periodically switches between logic “L” and “H” or vice versa under control of an external higher-level circuit. Typically, one of the scanning lines 3a is selected according to the logic of the output control signal ENBY.

[0045] In this embodiment, as shown in FIGS. 6 and 7 , a sample-and-hold circuit 101a constituting a data line driving circuit 101 is provided on the first substrate 10 adjacent to the display area 10a on one side in the second direction Y. Data lines 6a extend from the sample-and-hold circuit 101a to the other side in the second direction Y. The sample-and-hold circuit 101a is, for example, an N-type transistor constituting a demultiplexer. One demultiplexer includes, for example, eight sample-and-hold circuits 101a. Therefore, in the FHD standard, 1920 / 8=240, so 240 demultiplexers are provided. Image signals transmitted from an external circuit via the terminal 102 and image signal lines are supplied to each data line 6a in a time-division manner by transistors 30e and 30f of the sample-and-hold circuit 101a, whose on / off states are controlled by a control signal line (not shown).

[0046] On the first substrate 10, an inverter circuit 104a of the scanning line driving circuit 104 is provided along the third side 10a3 and the fourth side 10a4 of the display area 10a, and the scanning lines 3a extend from the inverter circuit 104a in the first direction X. The inverter circuit 104a includes an N-type transistor 30n and a P-type transistor 30p. The N-type transistor 30n includes a gate electrode 33n and has an LDD structure. More specifically, in N-type transistor 30n, one source-drain region 31j electrically connected to electrode 6b includes a high-concentration region 31j1 spaced apart from channel region 31k and a low-concentration region 31j2 sandwiched between channel region 31k and high-concentration region 31j1, while the other source-drain region 31i electrically connected to wiring 6s includes a high-concentration region 31i1 spaced apart from channel region 31k and a low-concentration region 31i2 sandwiched between channel region 31k and high-concentration region 31i1. The drain of N-type transistor 30n and the drain of P-type transistor 30p are electrically connected by electrode 6b and are electrically connected to scan line 3a by a contact structure (not shown).

[0047] On the first substrate 10, from terminals 102g, 102r, 102t, and 102s, which are part of the terminal 102 shown in FIG. 3, toward the region where the scanning line driving circuit 104 is provided, a line 6g that supplies a common potential COM, a line 6r that supplies an output control signal ENBY, a line 6t that supplies a constant potential VDDY, and a line 6s that supplies a constant potential VSSY extend. For example, the constant potential VSSY is GND, and the constant potential VDDY is 15.5 V. The lines 6g, 6r, 6t, and 6s are formed simultaneously with the data line 6a in the same layer. The output control signal ENBY is, for example, an AC signal whose logic is selected once per horizontal period. Alternatively, it may be an AC signal whose logic is selected once per multiple horizontal periods. Its voltage amplitude is, for example, 15.5 V.

[0048] A common potential COM is supplied to the wiring 6g, and as shown in FIG. 1, the wiring 6g is arranged so as to generally surround the display area 10a. The wiring 6g is electrically connected to the capacitance line 8a in the display area 10a through a contact hole 46n. The capacitance line 8a extends in a first direction X between the sensor element 11 and the scanning line driving circuit 104 in a plan view, then extends toward the display area 10a, and in the display area 10a extends in a second direction Y so as to overlap with the data line 6a in a plan view. Therefore, a large parasitic capacitance exists between the data line 6a and the capacitance line 8a.

[0049] A wiring 6m is electrically connected to the capacitance line 8a through a contact hole 45m. In a plan view, the wiring 6m extends along the first direction X between the sensor element 11 and the scanning line driving circuit 104 so as to overlap with the capacitance line 8a, and then extends along the second direction Y toward between the scanning line driving circuit 104 and the display area 10a.

[0050] The wiring 6s extends in the second direction Y toward the scanning line drive circuit 104, then extends in the first direction X between the wiring 6m and the scanning line drive circuit 104, and further extends in the second direction Y toward the scanning line drive circuit 104. Therefore, in a plan view, the capacitance line 8a and the wiring 6m extend in the first direction X between the sensor element 11 and the scanning line drive circuit 104 so as to overlap in a plan view, and the wiring 6s extends in the first direction X between the wiring 6m and the sensor element 11. The wiring 6s is part of a supply network of a constant potential VSSY to the scanning line drive circuit 104.

[0051] The wiring 6t extends in the second direction Y toward the scanning line driving circuit 104 in a plan view. The wiring 6t is part of a supply network for a constant potential VDDY to the scanning line driving circuit 104. The wiring 6r extends in the second direction Y toward the scanning line driving circuit 104 in a plan view. The wiring 6r is part of a supply network for an output control signal ENBY to the scanning line driving circuit 104. An output line of a higher-level circuit of the scanning line driving circuit 104 is electrically connected to the input line of the inverter, i.e., the node of the gate electrode 33n of the N-type transistor 30n. The higher-level circuit is, for example, a logical AND circuit of the output control signal ENBY and the output signal of a shift register that constitutes the scanning line driving circuit 104. This configuration allows the waveform of the selection signal from the shift register to be shaped, thereby optimizing the display.

[0052] Although the common potential COM is shared between the system electrically connected to the common electrode 21 and the system electrically connected to the storage capacitor 55, it may also be supplied as independent systems. Furthermore, the wiring to which the common potential COM is supplied crosses other signal wirings, and therefore may be switched from a first wiring below the insulating film 46 to a second wiring above the insulating film 46. Furthermore, the wiring to which the common potential COM is supplied may be wired using both the first wiring and the second wiring to achieve low resistance wiring. Furthermore, the wiring to which the common potential COM is supplied may be arranged so as to surround the display region 10a.

[0053] 1-6. Configuration of sensor element 11 As shown in FIGS. 6 and 7, the sensor element 11 is constructed by providing multiple semiconductor layers 31h separated from each other like islands, and each of the multiple semiconductor layers 31h is used to form a diode element D. More specifically, each of the multiple semiconductor layers 31h has an N-type region and a P-type region. In this embodiment, the N-type region includes a high-concentration N-type region 31n1 and a low-concentration N-type region 31n2, and the P-type region includes a high-concentration P-type region 31p1 and a low-concentration P-type region 31p2, with the low-concentration N-type region 31n2 and the low-concentration P-type region 31p2 forming a PN junction surface. Note that the diode element D can also be constructed using a high-concentration P-type region, a low-concentration N-type region, and a high-concentration N-type region. In either case, whether or not the diode element D is a diode element D can be determined by measuring its electrical characteristics.

[0054] A plurality of electrodes 6e1 and 6e2 are formed on the upper layer of the insulating film 45. The plurality of electrodes 6e1 and 6e2 are electrically connected to a high-concentration P-type region of the semiconductor layer 31h and a high-concentration N-type region of the adjacent semiconductor layer 31h via contact holes 45p and 45n that penetrate the gate insulating layer 32 and the insulating films 42, 43, 44, and 45, respectively. Therefore, the electrode 6e1 forms a relay portion P1 that electrically connects the diode element D1 and the diode element D2, and the electrode 6e2 forms a relay portion P2 that electrically connects the diode element D2 and the diode element D3. Needless to say, one pole of the diode element D electrically connected to each relay portion forms the same node. The relay portions P1 and P2 may sometimes be referred to simply as relay portions. In contrast, an anode wiring La is electrically connected to the high concentration P-type region of the semiconductor layer 31h of the diode element D1 via a contact hole 45p, and a cathode wiring Lc is electrically connected to the high concentration N-type region of the semiconductor layer 31h of the diode element D3 via a contact hole 45n.

[0055] Semiconductor layer 31h is formed in the same layer as semiconductor layer 31a shown in Fig. 4 at the same time, and therefore has the same thickness as semiconductor layer 31a. The N-type region and P-type region are formed using the manufacturing processes for the drive transistors that make up the scanning line drive circuit shown in Fig. 3 and the pixel transistors shown in Fig. 4. Electrodes 6e1 and 6e2 are formed in the same layer as data line 6a at the same time.

[0056] Although not shown, the transistor Tr, the first capacitance element C1, the second capacitance element C2, the first resistance element R1, the second resistance element R2, and the resistance element R3 of the electrostatic discharge protection circuit 12 are formed using the layers shown in FIG. 4. For example, the first resistance element R1, the second resistance element R2, and the resistance element R3 are formed using a conductive polysilicon film. For example, the first resistance element R1 and the second resistance element R2 are formed simultaneously in the same layer as the gate electrode 33g shown in FIG. 4. For example, the resistance element R3 is formed simultaneously in the same layer as the semiconductor layer 31a. The first resistance element R1, the second resistance element R2, and the resistance element R3 are not limited to conductive polysilicon films and may be formed using metal materials such as tungsten silicide or aluminum. The transistor Tr is formed simultaneously in the same layer as the pixel transistor 30. The first capacitance element C1 and the second capacitance element C2 are formed simultaneously in the same layer as the storage capacitor 55.

[0057] 1-7. Configuration of light-shielding layer 2a, etc. On the first substrate 10, a light-shielding layer 2a is also provided between the substrate body 10w and the insulating film 41 outside the display region 10a, similar to the display region 10a. The light-shielding layer 2a is made of tungsten silicide or the like and has a thermal expansion coefficient significantly different from that of the substrate body 10w. Therefore, when the light-shielding layer 2a is patterned to have a large area, strong stress is likely to be generated in the light-shielding layer 2a. Such stress can cause cracks in the light-shielding layer 2a. Therefore, in this embodiment, the light-shielding layer 2a is divided into multiple regions. For example, along line AA′ in FIG. 6, the light-shielding layer 2a is divided into light-shielding layers 2a11, 2a12, ... 2a16 and arranged, and slits s11, s12, ... s15 are provided between the light-shielding layers 2a11, 2a12, ... 2a16. The width of the slits s11, s12, ... s15 is, for example, 1 μm. The light-shielding layers 2a11, 2a12, . . . 2a16 are electrically floating.

[0058] Here, the first light-shielding layer 2a15 is disposed between the substrate main body 10w and the semiconductor layer 31h and overlaps with the semiconductor layer 31h in a planar view. The second light-shielding layer 2a14 is disposed between the substrate main body 10w and the semiconductor layer 31h and overlaps with the wiring 6m in a planar view. In this embodiment, the first light-shielding layer 2a15 and the second light-shielding layer 2a14 are spaced apart in a planar view. In this embodiment, the first light-shielding layer 2a15 and the second light-shielding layer 2a14 are disposed in the same layer with an insulating film 41 interposed therebetween.

[0059] 1-6.Configuration of inspection area 17 FIG. 8 is an explanatory diagram of the inspection area 17 shown in FIG. 3. As shown in FIG. 8, the inspection area 17 shown in FIG. 3 includes inspection elements TD4, TD5, TD6, and TD7, which are formed simultaneously in the same layer as the diode element D of the sensor element 11 constituting the sensor circuit 1 shown in FIG. 5; inspection element Tr0, which is formed simultaneously in the same layer as the transistor Tr; inspection element R0, which is formed simultaneously in the same layer as the resistor element R3; inspection elements C10 and C20, which are formed simultaneously in the same layer as the first capacitor element C1 and the second capacitor element C2, respectively; and multiple inspection terminals T1 to T11 electrically connected to these inspection elements. Also provided are inspection terminals T12 and T13, which are electrically connected to the conductive layer 9s via contact holes CNT. The conductive layer 9s includes the light-shielding layer 2a, the semiconductor layer 31a (31h), the gate electrode 33g, the first electrode 4a, the second electrode 5a (the third electrode 5b), the fourth electrode 7a, the data line 6a, the capacitor line 8a, and the pixel electrode 9a. The resistive testing element R0 is formed, for example, in a curved planar shape corresponding to the planar shape of the resistive element R3. The resistive testing element R0 may be formed simultaneously in the same layer as the first resistive element R1 and the second resistive element R2. Here, the testing elements TD4, TD5, TD6, and TD7 are provided with a light-shielding layer 2a, similar to the diode element D of the sensor element 11. The effect of this configuration will be described in detail later.

[0060] With this inspection area 17, the electrical characteristics of the inspection elements TD4, TD5, TD6, and TD7 corresponding to the sensor element 11 can be inspected using the inspection terminals T1, T2, T3, and T4. The electrical characteristics of the inspection element Tr0 corresponding to the transistor Tr can be inspected using the inspection terminals T5, T6, and T8. The electrical characteristics of the inspection element R0 corresponding to the resistor element R3 can be inspected using the inspection terminals T7 and T8. The electrical characteristics of the inspection elements C10 and C20 corresponding to the first and second capacitive elements C1 and C2 can be inspected using the inspection terminals T9, T10, and T11. The electrical connections to each conductive film can be inspected using the inspection terminals T12 and T13.

[0061] Here, the inspection terminals T1 to T13 can be made wider and longer than the mounting terminals 102 shown in Fig. 3. This makes it easier to contact the inspection probes with the inspection terminals T1 to T13. Furthermore, the inspection terminals T1 to T13 are not electrically connected to the short-circuit wire 10g via the resistance element R. Therefore, the electrical characteristics of each circuit element constituting the sensor circuit 1 can be evaluated in the state of the large substrate 150 without being affected by the short-circuit current flowing through the resistance element R.

[0062] In the state of the large substrate 150, the anode terminal 102a and cathode terminal 102c of the sensor circuit 1 have a short-circuit path via the resistor element R and the short-circuit wire 10g. Therefore, when abnormal characteristics are observed, it is difficult to quickly determine the cause by simply applying a voltage between the anode terminal 102a and the cathode terminal 102c and observing the current. However, with the inspection area 17, it is possible to quickly estimate the location of the abnormal part.

[0063] Furthermore, the inspection area 17 is arranged along a side corresponding to the corner of the electro-optical device 100 where the sensor element 11 and the electrostatic protection circuit 12 are arranged. With this configuration, the inspection area 17 and the same circuit elements in the sensor element 11 and the electrostatic protection circuit 12 are processed using the same exposure range and are arranged in close proximity to each other. As a result, the electrical characteristics of the inspection area 17 and the same circuit elements in the sensor element 11 and the electrostatic protection circuit 12 can be made similar. As will be described in detail later, when the inspection area 17 and the sensor element 11 are arranged in close proximity, the thermal histories of the inspection area 17 and the sensor element 11 during the manufacturing process can be expected to be similar. If the thermal histories are similar, the effect of stress caused by the light-shielding layer 2a on the diode element D will be similar. Therefore, from the measured values ​​of the circuit elements in the inspection area 17, abnormalities in the formation of each circuit element can be detected, and the performance of the sensor circuit 1 can be estimated or managed.

[0064] Furthermore, in the inspection area 17, no short-circuit current occurs in any circuit element other than the circuit element being measured, making it easy to evaluate the electrical characteristics. Furthermore, when multiple diode elements TD4, TD5, and TD6 electrically connected in series are evaluated, the average electrical characteristics of the diode elements TD4, TD5, and TD6 are seen, which may make it difficult to properly evaluate the variations in the electrical characteristics of individual diode elements. However, in this embodiment, a single inspection element TD7 is provided, and thus the variations in the electrical characteristics of individual diode elements can be grasped in detail by evaluating the electrical characteristics of the diode element TD7 alone.

[0065] Furthermore, a light-shielding layer 2a is provided below the testing elements TD4, TD5, TD6, and TD7. This allows the testing elements TD4, TD5, TD6, and TD7 to have forward voltage temperature characteristics similar to those of the diode element D of the sensor element 11. As will be described in detail later, when the testing area 17 and the sensor element 11 are arranged closely to each other, the thermal histories of the testing area 17 and the sensor element 11 during the manufacturing process can be expected to be similar. If the thermal histories are similar, the effect of stress caused by the light-shielding layer 2a on the diode element D will be similar.

[0066] 1-7. Effects of the First Embodiment 5 and 6, in the electro-optical device 100 of this embodiment, the first light-shielding layer 2a15, which overlaps with the semiconductor layer 31h in a planar view, and the second light-shielding layer 2a14, which overlaps with the wiring 6m in a planar view, are separated by a slit s14, and a capacitance Cc exists between the first light-shielding layer 2a15 and the second light-shielding layer 2a14. Furthermore, a capacitance Cb exists between the first light-shielding layer 2a15 and the semiconductor layer 31h. That is, a capacitance Cb exists between the relay portion P1 and the first light-shielding layer 2a15. A capacitance Ca exists between the second light-shielding layer 2a14 and the wiring 6m. Therefore, a coupling capacitance exists between the wiring 6m and the semiconductor layer 31h, where the capacitances Ca, Cb, and Cc are electrically connected in series.

[0067] Here, the capacitance Cb is a parallel-plate capacitance formed by the first light-shielding layer 2a15 and the semiconductor layer 31h, and the capacitance Ca forms a parallel-plate capacitance by the second light-shielding layer 2a14 and the wiring 6m. Therefore, the capacitances Cb and Ca are relatively large. On the other hand, the capacitance Cc is a capacitance formed between the pattern end faces of the first light-shielding layer 2a15 and the second light-shielding layer 2a14, and can be made extremely small. That is, the relationship regarding the capacitance values is Cc << Ca, Cb. For this reason, the capacitance Cd (see FIG. 5) between the relay portion P1 (or P2) and the wiring 6m can be made extremely small.

[0068] Also, the distance between the first light-shielding layer 2a15 and the second light-shielding layer 2a14 is about 1 μm, whereas the distance between the first light-shielding layer 2a15 and the semiconductor layer 31h (the thickness of the insulating film 41) is about 0.4 μm. Therefore, most of the electric lines of force regarding the first light-shielding layer 2a15 extend to the semiconductor layer 31h, reducing the electric lines of force extending to the second light-shielding layer 2a14, thus reducing the capacitance Cc. Therefore, it is effective to make the width of the slit s14 larger than the widths of the other slits. For example, if the slit width of the standard light-shielding layer 2a is 1 μm, it is preferable to make the width of the slit s14 2 μm. If the slit width is 2 μm or less, it is hardly visible in the projection pattern.

[0069] On the other hand, in the comparative examples shown in FIGS. 9 and 10, light-shielding layers 2a1, 2a2,... 2a6 are provided on the lower layer side of the diode element D etc. and are separated via slits s1, s2,... s5, and the light-shielding layer 2a4 overlaps with both the semiconductor layer 31h and the wiring 6m in a plan view. Here, the light-shielding layers 2a1, 2a2,... 2a6 are electrically floating. For this reason, the coupling capacitance between the relay portion P1 and the wiring 6m, that is, the capacitance Cd (see FIG. 5) composed of the series connection of the capacitances Ca and Cb becomes a size that cannot be ignored.

[0070] Furthermore, the light-shielding layer 2a5, which overlaps in plan view with the relay portion P2 that electrically connects the diode element D2 and the diode element D3 in series, also overlaps in plan view with the wiring 6r to which the output control signal ENBY is supplied. Therefore, the coupling capacitance between the relay portion P2 and the wiring 6r becomes significant. Note that in FIG. 10, the capacitance symbols for the light-shielding layer 2a5 and the semiconductor layer 31h (relay portion P2) are omitted.

[0071] As described above, in the comparative example, a relatively large capacitance Cd (see FIG. 5) exists between the wiring 6m to which the common potential COM is applied and the relay portion P1 of the diode element D. Also, a relatively large capacitance Cd (see FIG. 5) exists between the wiring 6r to which the output control signal ENBY is supplied and the relay portion P2 of the diode element D. In contrast, in the first embodiment, the capacitance Cd (see FIG. 5) can be made small. Therefore, as will be described in detail below, in the comparative example, the capacitance Cd causes large fluctuations in the output voltage VF of the sensor circuit 1, but such fluctuations can be suppressed in the first embodiment.

[0072] In both the first embodiment and the comparative example, the wiring to which the common potential COM is supplied is often made wide to reduce resistance. Therefore, a capacitance Ce due to wiring intersections may exist between the wiring to which the common potential COM is supplied and the anode wiring La. Similarly, a capacitance Cf due to wiring intersections may exist between the wiring to which the common potential COM is supplied and the cathode wiring Lc. Because the anode wiring La and the cathode wiring Lc are located close to each other, it is reasonable to assume that the capacitances Ce and Cf have similar capacitance values. As will be described later, the effect of these capacitances Ce and Cf on the output voltage VF of the sensor circuit 1 is extremely small.

[0073] The following describes the effect that a change in the potential of the wiring 6m has on the output voltage VF of the sensor circuit 1. A common potential COM is applied to the wiring 6m, but when precharging is performed in the electro-optical device 100 of this embodiment, a change in the potential of the data line 6a due to precharging affects the potential of the capacitance line 8a via the parasitic capacitance between the capacitance line 8a and the data line 6a. As a result, large spike noise may occur in the common potential COM between the capacitance line 8a and the wiring 6m during precharging.

[0074] More specifically, a relatively large parasitic capacitance exists between the data line 6a and the capacitor line 8a. This parasitic capacitance is an essential element, maintaining a voltage corresponding to an image signal on the data line 6a. To improve display quality, the electro-optical device 100 is driven by a pre-writing process, generally referred to as pre-charging. This pre-charging process assists in writing the image signal voltage and reduces crosstalk, which occurs when a white window is displayed on a halftone background, causing the upper and lower portions of the white window to appear in a different grayscale than the surrounding area. The pre-charge voltage is often set near the minimum voltage of the image signal voltage range. For example, in a normally black mode electro-optical device 100, the common potential COM is set to a fixed potential of 7V, the image signal voltage for negative polarity display is set to 2V (white) to 7V (black), and the image signal voltage for positive polarity display is set to 7V (black) to 12V (white), with the pre-charge voltage set to approximately 2V to 4V. In reality, the common potential COM is adjusted taking into consideration the push-down voltages in the transistors 30e and 30f of the sample-and-hold circuit 101a and the pixel transistor 30, but this can be ignored in the explanation of the embodiment.

[0075] Precharge is typically performed simultaneously on all data lines 6a at the beginning of one horizontal period H. Therefore, during precharge, the potential of the data lines 6a simultaneously transitions to approximately 2V. This results in spike noise in the potential of the wiring 6m, moving from 7V to a lower potential. Based on observations using an external circuit, the inventors of the present invention estimated the magnitude of the spike noise to be ΔV = −1.5V, as shown in Figure 11. Furthermore, based on a rough estimation of the driving conditions of the electro-optical device 100, the horizontal period H was modeled as a 3 μs period t1, with a potential drop during the 100 ns period t2 and a potential rise during the 300 ns period t3. In reality, noise due to image signal writing also occurs, but because its magnitude is smaller than that of precharge, it was omitted from the model. Note that t1, t2, t3, and ΔV vary depending on the number of pixels and driving conditions of the electro-optical device 100.

[0076] In recent years, the number of data lines 6a in the display area 10a has increased due to the trend toward higher resolution, making it impossible to suppress this spike noise. Although it is difficult to actually measure the spike noise of the wiring 6m near the display area 10a, it is estimated that it may reach several volts. Moreover, the magnitude of the spike noise depends on the voltage of the image signal applied to the data lines 6a before precharging, and therefore varies depending on the image being displayed.

[0077] As a result of investigations by the inventors of the present invention, it was found that when the above modeled spike noise acts on the relay section of the series-connected diode element D via the capacitance Cd, there is a problem in that the output voltage VF of the sensor circuit 1 decreases.

[0078] Specifically, we considered a model in which six diode elements D were connected in series. That is, in the sensor circuit 1 shown in FIG. 5, we considered a model in which the sensor element 11 was composed of six diode elements D (D1 to D6). Therefore, each diode element D has five relay sections. Each relay section has a wiring to which a common potential COM is supplied and a capacitance Cd.

[0079] In calculations using the model under consideration, there was no spike noise associated with pre-charging from time 0 s to 0.1 s, and spike noise associated with pre-charging was generated after time 0.1 s. In practice, the stabilizing capacitance 152 is set to approximately 0.1 μF, but in the calculations it was set to 100 pF so that the impact of pre-charging could be calculated early. Therefore, the time constant related to the response of the output voltage VF differs between the calculation results and the actual circuit. For example, if the stabilizing capacitance 152 is set to 0.1 μF, it will take longer for the output voltage VF drop to saturate, as described below. Note that the calculations were performed at room temperature.

[0080] Calculation results showed that the output voltage VF gradually decreases after the start of pre-charging and eventually saturates. The output voltage VF shown in Figure 12 is the average value of the output voltage VF from 0.19 seconds to 0.2 seconds after the start of pre-charging. At this point, the decrease in the output voltage VF has saturated. After the decrease in the output voltage VF has saturated, the output voltage VF fluctuates in units of several millivolts to several tens of millivolts in sync with the spike noise. Therefore, the output voltage VF is the average voltage over a period much longer than the horizontal period.

[0081] After studying the capacitance Cd of the relay section and the drive current IF while changing them, we obtained the results shown in Figure 12. Figure 12 shows the relationship between the capacitance Cd of the relay section and the output voltage VF, and the results when the drive current IF was set to 100nA, 200nA, 400nA, and 800nA are shown by the solid lines L100, L200, L400, and L800, respectively.

[0082] As a result, it was found that even if the coupling capacitance (capacitances Ce, Cf) between the anode wiring La or the cathode wiring Lc and the wiring 6m is 0.5 pF, it is hardly a problem, but if a capacitance Cd of only 0.03 pF exists in the relay section, there is a possibility that the drop in the output voltage VF of the sensor circuit 1 may exceed 100 mV. Here, if the output voltage VF of the sensor circuit 1 drops by 100 mV, in the case of a sensor element 11 with a sensitivity of approximately -10 mV / °C, the temperature measurement error will reach 10°C or more, making it difficult to control the temperature of the electro-optical device 100. Note that 0.03 pF is, for example, a value of approximately 400 μm 2This corresponds to the parallel plate capacitance when the electrode patterns of these two elements face each other with a 0.4 μm silicon oxide film (dielectric constant 3.9) between them. In diode element D, the area of ​​the anode electrode (cathode electrode), which is the same node as the relay part, is about the same as that of the relay part, which can be a problem.

[0083] The inventors of the present invention conducted an experiment in which electrodes that overlap in a planar view were provided on the sensor element 11 in the electro-optical device 100, and a common potential was applied to these electrodes. As a result, the output voltage VF of the sensor circuit 1 when driven with precharge was lower than the output voltage VF of the sensor circuit 1 when driven without precharge. This qualitatively supported the calculation results. The behavior of the output voltage VF of the sensor circuit 1 decreasing over several seconds when switching from drive without precharge to drive with precharge was also consistent with the calculation results.

[0084] As can be seen from Figure 14, one possible way to avoid the above problem is to increase the drive current IF of the diode element D. However, increasing the drive current IF increases the fluctuation ΔVF in the forward voltage VF relative to the fluctuation ΔIF in the drive current at the operating point of the sensor element 11 due to the influence of series resistance, thereby reducing the reliability of the detected temperature. Therefore, simply increasing the drive current IF of the diode element D is not desirable.

[0085] Furthermore, increasing the drive current IF increases the operating point voltage of the sensor element 11, i.e., the output voltage VF. For example, if the drive current IF is 400 nA, the operating point voltage is approximately 3.8 V. A known constant current circuit is a discharge-type constant current circuit that uses a transistor, an operational amplifier, a shunt regulator, or the like. From a structural standpoint, it is preferable to use a 5 V power supply, such as that used in the upper circuit that drives a typical electro-optical device 100, as the power supply for the constant current circuit.

[0086] In this case, due to limitations in transistor characteristics, in order to maintain constant current operation, the operating point voltage must be maintained at approximately 3.7 V or less. In other words, there is a limit to the voltage range in which constant current operation can be maintained.

[0087] However, in Figure 12, when the drive current IF is 400 nA, the operating point voltage at room temperature is around 3.8 V, so constant current operation is not possible with a 5 V power supply. This requires the preparation of a new power supply circuit, which increases manufacturing costs. Alternatively, the operating point voltage can be lowered by reducing the number of diode elements D connected in series that make up the sensor element 11. In this case, the reduced number of diode elements D connected in series reduces the sensitivity of the output voltage VF to temperature changes.

[0088] 6, the first light-shielding layer 2a15 overlaps the diode elements D1 to D3 in plan view, but does not overlap the wiring 6r to which the output control signal ENBY, which is an AC signal, is applied in plan view. The light-shielding layer 2a also includes a third light-shielding layer 2a10 that overlaps the wiring 6r to which the output control signal ENBY is supplied in plan view, but the third light-shielding layer 2a10 is separated from the first light-shielding layer 2a15. A slit filled with an insulating film 41 is present between the third light-shielding layer 2a10 and the first light-shielding layer 2a15, separating the third light-shielding layer 2a10 and the first light-shielding layer 2a15 via the insulating film 41. Therefore, the coupling capacitance between the relay portions P1 and P2 of the diode elements D1 to D3 and the wiring 6r to which the output control signal ENBY is supplied is extremely small, so that voltage changes in the wiring 6r are unlikely to affect the output voltage VF of the sensor circuit 1.

[0089] 2. Embodiment 2 FIG. 13 is an explanatory diagram of an electro-optical device 100 according to a second embodiment of the present invention. FIG. 13 is a plan view that schematically shows the planar configuration of a sensor element 11 and the like. In FIG. 13, a portion of the capacitance line 8a has been removed, and the removed portion is indicated by a dashed line, so that the layout of the lower layer of the capacitance line 8a can be more clearly seen. FIG. 14 is a cross-sectional view that schematically shows a cross section of the sensor element 11 and the like shown in FIG. 13. FIG. 14 corresponds to the CC' cross section of FIG. 13. However, FIG. 14 also shows a cross section passing through a contact hole 45m.

[0090] FIG. 15 is an explanatory diagram of an inspection area 17 of an electro-optical device 100 according to a second embodiment of the present invention. FIG. 16 is an explanatory diagram of a diode element used to verify the effects of the second embodiment. FIG. 17 is a graph showing a comparison of the temperature characteristics of the forward voltage VF of the diode elements of type (a) and type (b) shown in FIG. 16. FIG. 18 is a graph showing an example of individual differences in the temperature characteristics of the forward voltage VF of the diode element of type (a) shown in FIG. 17. Note that the basic configuration of this embodiment is the same as that of the first embodiment, and therefore common parts are assigned the same reference numerals and their description will be omitted.

[0091] As shown in FIGS. 13 and 14 , the first substrate 10 includes a plurality of island-shaped semiconductor layers 31h, each of which includes an N-type region and a P-type region, similar to the first embodiment. A plurality of electrodes 6e1 and 6e2 are formed on the insulating film 45. The electrodes 6e1 and 6e2 are electrically connected to the high-concentration P-type region of one semiconductor layer 31h and the high-concentration N-type region of the adjacent semiconductor layer 31h via contact holes 45p and 45n that penetrate the gate insulating layer 32 and insulating films 42, 43, 44, and 45, respectively. Therefore, the electrode 6e1 forms a relay portion P1 that electrically connects the diode element D1 and the diode element D2, and the electrode 6e2 forms a relay portion P2 that electrically connects the diode element D2 and the diode element D3. A light-shielding layer 2a is provided between the substrate main body 10w and the insulating film 41.

[0092] The light-shielding layer 2a is made of tungsten silicide or the like, and is divided into a plurality of regions. For example, along line CC′ in FIG. 15 , the light-shielding layer 2a is divided into light-shielding layers 2a21, 2a22, ..., 2a29, and slits s21, S22, ..., S28 are provided between the light-shielding layers 2a21, 2a22, ..., 2a29. The width of the slits s21, S22, ..., S28 is, for example, 1 μm. In the second embodiment, the arrangement of these light-shielding layers and slits differs from that of the first embodiment. Unless otherwise specified, these light-shielding layers are electrically floating.

[0093] Here, the first light-shielding layers 2a25, 2a26, 2a27, and 2a28 overlap the semiconductor layer 31h between the substrate main body 10w and the semiconductor layer 31h in a planar view. The second light-shielding layer 2a24 overlaps the wiring 6m between the substrate main body 10w and the semiconductor layer 31h in a planar view. In this embodiment, the first light-shielding layers 2a25, 2a26, 2a27, and 2a28 are spaced apart from the second light-shielding layer 2a24 in a planar view. In this embodiment, the first light-shielding layers 2a25, 2a26, 2a27, and 2a28 and the second light-shielding layer 2a24 are arranged in the same layer with an insulating film 41 interposed therebetween. Therefore, the coupling capacitance between the wiring 6m and the relay portion P1 is extremely small because the coupling is via the extremely small capacitance Cc between the first light-shielding layer 2a25 and the second light-shielding layer 2a24 and the extremely small capacitance Cc2 between the first light-shielding layer 2a25 and the first light-shielding layer 2a26.

[0094] Furthermore, the first light-shielding layers 2a25, 2a26, 2a27, and 2a28 are divided by slits s25, s26, and s27. Therefore, when focusing on the semiconductor layer 31h constituting the diode element D2, the first light-shielding layers 2a26 and 2a27 are arranged such that a first portion made of the first light-shielding layer 2a26 overlaps the anode region of the semiconductor layer 31h in a planar view, and a second portion made of the first light-shielding layer 2a27 overlaps the cathode region of the semiconductor layer 31h in a planar view are separated by the slit s26. Here, because the slit s26 is filled with the insulating film 41, the first portion made of the first light-shielding layer 2a26 and the second portion made of the first light-shielding layer 2a27 are adjacent to each other via the insulating film 41.

[0095] In this embodiment, the first light-shielding layers 2a25, 2a26, 2a27, and 2a28 overlapping the diode elements D1 to D3 in plan view do not overlap the wiring 6r to which the output control signal ENBY, which is an AC signal, is applied in plan view. The light-shielding layer 2a also includes a third light-shielding layer 2a20 overlapping the wiring 6r to which the output control signal ENBY is supplied in plan view, but the third light-shielding layer 2a20 is separated from the first light-shielding layers 2a25, 2a26, 2a27, and 2a28. Slits filled with an insulating film 41 are present between the first light-shielding layers 2a25, 2a26, 2a27, and 2a28 and the third light-shielding layer 2a20, so the third light-shielding layer 2a20 is separated from the first light-shielding layers 2a25, 2a26, 2a27, and 2a28 via the insulating film 41. Therefore, the coupling capacitance between the wiring 6r to which the output control signal ENBY is applied and the relaying sections P1 and P2 is extremely small, so that the output voltage VF of the sensor circuit 1 is not easily affected by voltage changes in the wiring 6r.

[0096] Also in this embodiment, as in the first embodiment, the inspection area 17 shown in FIG. 15 includes inspection elements TD4, TD5, TD6, and TD7, which are formed simultaneously in the same layer as the diode element D of the sensor element 11 constituting the sensor circuit 1 shown in FIG. 5; inspection element Tr0, which is formed simultaneously in the same layer as the transistor Tr; inspection element R0, which is formed simultaneously in the same layer as the resistor element R3; inspection elements C10 and C20, which are formed simultaneously in the same layer as the first capacitive element C1 and the second capacitive element C2, respectively; and multiple inspection terminals T1 to T11 electrically connected to these inspection elements. Also provided are inspection terminals T12 and T13, which are electrically connected to the conductive layer 9s via contact holes CNT. This allows electrical inspection of each circuit element on the large substrate 150.

[0097] Here, a light-shielding layer 2a is formed below the testing elements TD4, TD5, TD6, and TD7, and the light-shielding layer 2a is divided by slits s, similar to the sensor element 11. Therefore, in the testing area 17, the testing elements TD4, TD5, TD6, and TD7 can have temperature characteristics similar to those of the sensor element 11 shown in Figures 13 and 14. Here, the width of the slits s is, for example, 1 µm, similar to the slits s25, s26, and s27 shown in Figure 14.

[0098] For the electro-optical device 100 configured as described above, the relationship between temperature and forward voltage VF was examined for a type (a) diode element D in which a slit s is provided in the light-shielding layer 2a overlapping the diode element D in a planar view, as shown in FIG. 16 , and a type (b) diode element D in which a slit s is not provided in the light-shielding layer 2a overlapping the diode element D in a planar view. As shown in FIG. 16 , the type (a) diode element D and the type (b) diode element D have the same dimensions in a planar view, such as the width W of the semiconductor layer 31h being 10 μm or less. Furthermore, the type (a) diode element D and the type (b) diode element D were formed on the same substrate, and the substrate was heated using a hot chuck mechanism of a prober, and the temperature characteristics of the forward voltage VF were measured. In FIG. 16 , the layer between the semiconductor layer 31h and the electrode 6e1, etc., is, for example, a silicon oxide film.

[0099] As a result, as shown in Figure 17, when the forward drive current IF was set to 20 nA, the temperature characteristic of the forward voltage VF was approximately -2 mV / °C for the type (a) diode element D, but approximately -1.5 mV / °C for the type (b) diode element D. Evaluation was also carried out by increasing the number of type (b) diode elements D, but in all cases the temperature characteristic of the forward voltage VF was approximately -1.5 mV / °C.

[0100] Furthermore, when the number of type (a) diode elements D was increased and evaluated, the average value of the temperature characteristic of the forward voltage VF was -1.94 mV / °C, and of the 48 elements evaluated, not a single one showed a temperature characteristic of the forward voltage VF of less than -1.8 mV / °C. In other words, even though the type (a) and type (b) diode elements were fabricated on the same substrate, the temperature characteristics of the forward voltage VF are different. Note that Figure 18 shows the results for type (a) diode elements a1 and a2 as representative examples.

[0101] These results can be explained as follows. As can be seen from Figure 16, the arrangement of the light-shielding layer 2a is different between the type (a) and type (b) diode elements D, which is thought to cause different stress effects on the semiconductor layer 31h. Because activation of polycrystalline silicon involves a high-temperature annealing process at 1000°C or higher, it is possible to assume that the difference in the effect of stress due to film shrinkage, etc.

[0102] Therefore, when connecting multiple diode elements D in series to form the sensor element 11 and disposing the light-shielding layer 2a below the semiconductor layer 31h constituting each diode element D, it is not recommended to freely arrange the layer as a design matter. In other words, it is not recommended to arrange the light-shielding layer 2a without any restrictions. The arrangement of the light-shielding layer 2a must be considered, taking into account the effects of stress. Therefore, when connecting multiple diode elements D in series to form the sensor element 11, it is preferable to align the arrangement of the slits s in the light-shielding layer 2a of each diode element D in the same manner in order to align the temperature characteristics of the forward voltage VF. Furthermore, as with the diode elements D constituting the sensor element 11, it is also preferable to align the arrangement of the slits s in the light-shielding layer 2a of the diode elements TD4, TD5, TD6, and TD7 arranged in the inspection area 17 in the same manner.

[0103] The arrangement of the slits s in the light-shielding layer 2a is uniformed to one of the following three types when the diode element D is viewed in plan view. Type (1): The light-shielding layer 2a is arranged so as to overlap all of the semiconductor layers 31h that constitute the diode element D in plan view (corresponding to the first embodiment). Type (2): In the light-shielding layer 2a, slits s are similarly provided for the plurality of semiconductor layers 31h that constitute the diode element D (corresponding to the second embodiment). Type (3): The light-shielding layer 2a is arranged so as not to overlap the plurality of semiconductor layers 31h that constitute the diode element D. (This corresponds to other embodiments described later.)

[0104] 3. Other embodiments of the electro-optical device In the first and second embodiments, the wiring 6m where the second light-shielding layers 2a14 and 2a24 overlap in a planar view is a constant potential line, but the present invention may be applied to a case where the wiring where the second light-shielding layers 2a14 and 2a24 overlap in a planar view is a signal line to which an AC signal is applied, such as the wiring 6r. Examples of such signal lines include a clock signal line, a start pulse signal line, a scanning direction designation signal line, an end pulse signal line, a scanning signal line, and the like related to the scanning line driving circuit 104. Similarly, various signal lines related to the data line driving circuit 101 are also included.

[0105] Furthermore, even if the wiring 6m shown in the first and second embodiments is not present, a coupling capacitance exists if there is a capacitance line 8a where the second light-shielding layers 2a14 and 2a24 overlap in plan view. In such a case, the present invention may be applied.

[0106] In addition, for example, depending on the driving mode of the electro-optical device 100, the non-selection potential of the scanning line 3a may be changed in accordance with the polarity of the image signal. In such cases, for example, the potential of the wiring 6s (VSSY) in the first and second embodiments is changed in accordance with the polarity of the image signal. The present invention may be applied to such wiring 6s. Alternatively, when the common potential COM is changed in accordance with the polarity of the image signal, the present invention may be applied to the common potential wiring.

[0107] Furthermore, if the sensor element 11 is not disposed near the display area, it is possible that the light-shielding layer 2a is not disposed below the semiconductor layer 31h that constitutes the diode element D. In this case, the type (3) is adopted, and the light-shielding layer 2a is disposed so as not to overlap the multiple semiconductor layers 31h that constitute the diode element D. Furthermore, the light-shielding layer 2a is not disposed for the diode elements TD4, TD5, TD6, and TD7 disposed in the inspection area 17 either. In this way, the temperature characteristics of the forward voltage VF of the diode elements TD4, TD5, TD6, and TD7 can be made uniform, and appropriate manufacturing control can be achieved using the diode elements TD4, TD5, TD6, and TD7 disposed in the inspection area 17.

[0108] 4. Electronic device configuration examples FIG. 19 is a block diagram showing an example of the configuration of a projection type display device 1000 to which the present invention is applied. The projection type display device 1000 shown in FIG. 19 is an example of an electronic device to which the present invention is applied. FIG. 20 is an explanatory diagram of the light path shift element 110 shown in FIG. 19. Note that polarizing plates and the like are omitted from FIG. 19. The projection type display device 1000 shown in FIG. 19 is an example of an electronic device to which the present invention is applied, and includes an illumination device 90, a separation optical system 70, three electro-optical devices 100R, 100G, and 100B, and a projection optical system 60. Each of the electro-optical devices 100R, 100G, and 100B is formed by the electro-optical device 100 described with reference to FIGS. 1 to 18.

[0109] The illumination device 90 is a white light source, and may be, for example, a laser light source or a halogen lamp. The separation optical system 70 includes three mirrors 71, 72, and 75 and dichroic mirrors 73 and 74. The separation optical system 70 separates the white light emitted from the illumination device 90 into three primary colors: red (R), green (G), and blue (B). Specifically, the dichroic mirror 74 transmits light in the red (R) wavelength range and reflects light in the green (G) and blue (B) wavelength ranges. The dichroic mirror 73 transmits light in the blue (B) wavelength range and reflects light in the green (G) wavelength range. The light corresponding to red (R), green (G), and blue (B) is guided to the electro-optical devices 100R, 100G, and 100B, respectively.

[0110] The light beams modulated by the electro-optical devices 100R, 100G, and 100B are incident on the dichroic prism 61 from three directions. The dichroic prism 61 constitutes a synthesis optical system that synthesizes red (R), green (G), and blue (B) images. Therefore, the projection lens system 62 enlarges and projects the synthesized image emitted from the light path shift element 110 onto a projection target such as a screen 80, thereby displaying a color image on the projection target such as the screen 80.

[0111] In this case, the control unit 160 can correct the image signals supplied to the electro-optical devices 100R, 100G, and 100B based on the temperature detection results of the sensor circuit 1. This allows for high-quality projection images to be displayed even when the ambient temperature fluctuates. Furthermore, if a light path shift element 110 (shown by a dashed line) is provided in the projection optical system 60 on the side from which light is emitted from the dichroic prism 61, shifting the position at which the projected pixel is viewed every predetermined period to enhance resolution, it becomes necessary to drive the liquid crystal layer at high speed. Even in this case, the electro-optical layer 50, which is made of a liquid crystal layer, can be driven at high speed by correcting the image signals supplied to the electro-optical devices 100R, 100G, and 100B based on the temperature detection results of the sensor circuit 1 or by adjusting the temperature of the liquid crystal panel 100p of the electro-optical devices 100R, 100G, and 100B.

[0112] As shown in Fig. 20, the light path shift element 110 is an optical element that shifts light emitted from the dichroic prism 61 in a predetermined direction. Fig. 20 illustrates an example in which the position of a projection pixel Pi, at which light emitted from each pixel 100a of the liquid crystal panel 100p is visible, is shifted by the light path shift element 110 by a distance equivalent to 0.5 pixel pitches (=P / 2) to one side X1 in the first direction X and by a distance equivalent to 0.5 pixel pitches (=P / 2) to one side Y1 in the second direction Y. The light path shift element 110 includes a light-transmitting plate, and the actuator swings the light-transmitting plate around an axis extending in the first direction X and / or around an axis extending in the second direction Y, thereby shifting the light path of the light emitted from each pixel 100a of the liquid crystal panel 100p to light path LA and light path LB.

[0113] 6. Other embodiments of electronic devices The projection display device may be configured to use an LED light source or the like that emits light of each color as the light source unit, and supply each color light emitted from the LED light source to a separate liquid crystal device.

[0114] Electronic devices equipped with the electro-optical device 100 to which the present invention is applied are not limited to the projection display device 1000 of the above embodiment. For example, the present invention may be used in electronic devices such as a HUD (head-up display), an HMD (head-mounted display), a personal computer, a digital still camera, and an LCD television. [Explanation of symbols]

[0115] 1...Sensor circuit, 2a, 2a1, 2a11, 2a2, 2a12, 2a21, 2a4, 2a22, 2a5...Light blocking layer, 2a10, 2a20...Third light blocking layer, 2a14, 2a24...Second light blocking layer, 2a15, 2a25, 2a26, 2a27, 2a28...First light blocking layer , 3a...scanning line, 4a...first electrode, 5a...second electrode, 5b...third electrode, 6a...data line, 6g, 6m, 6r, 6s, 6t...wiring, 7a...fourth electrode, 8a...capacitance line, 9a...pixel electrode, 9b...dummy pixel electrode, 10...first substrate, 10a...display area, 10b...frame shape region, 10c...peripheral region, 10e...scribe center line, 10f...inter-pixel region, 10g...short-circuit line, 10s, 20s...surface, 10w, 20w...substrate body, 11...sensor element, 11a...anode, 11c...cathode, 12...electrostatic protection circuit, 15...temperature detection drive circuit, 17...inspection region, 20...second substrate, 21...common electrode, 29...parting edge, 30...pixel transistor, 30n...N-type transistor, 30p...P-type transistor, 31a, 31h...semiconductor layer, 32...gate insulating layer, 33g, 33t...gate electrode, 41, 4 2, 43, 44, 45, 46, 47, 48, 49...insulating film, 50...electro-optical layer, 60...projection optical system, 61...dichroic prism, 62...projection lens system, 90...illumination device, 100, 100B, 100G, 100R...electro-optical device, 100a...pixel, 100p...liquid crystal panel, 101...data line driving circuit, 101a...sample and hold circuit, 102, 102g, 102r, 102s, 102t...terminal, 102a...anode terminal, 102c...cathode terminal, 104...scanning line driving circuit, 104a...inverter circuit, 105...precharge circuit, 110...light path shift element, 150...large substrate, 151...constant current circuit, 160...control unit, 1000...projection display device, D, D1, D2, D3...diode elements, C1...first capacitance element, C2...second capacitance element, P1, P2...relay unit, s11-s15, s21-s28...slits, Ca, Cb, Cc, Cc1, Cc2...capacitance, Cd, Ce, Cf...parasitic capacitance, La...anode wiring, Lc...cathode wiring, Tr, 30e, 30f...transistor, COM...common potential, VDDY, VSSY...constant potential

Claims

1. A substrate body, Outside the display area, a sensor element having a semiconductor layer; wiring provided so as not to overlap the semiconductor layer in a plan view; a first shielding layer disposed between the substrate body and the semiconductor layer and overlapping the semiconductor layer in a plan view; The optic layer and a second light-shielding layer disposed between the substrate body and the wiring and overlapping the wiring in a plan view; another light-shielding layer adjacent to the second light-shielding layer in a plan view; Equipped with The first light-shielding layer and the second light-shielding layer are disposed between the semiconductor layer and the wiring in a plan view. are spaced apart by a distance of 2 μm or less, The distance between the first light-shielding layer and the second light-shielding layer is The electro-optical device is characterized in that the distance therebetween is longer than the distance between the electrodes.

2. 2. The electro-optical device according to claim 1, The first light-shielding layer and the second light-shielding layer are disposed in the same layer with an insulating film interposed therebetween. An electro-optical device comprising:

3. 3. The electro-optical device according to claim 1, The sensor element includes a plurality of diode elements electrically connected in series. An electro-optical device characterized by:

4. 4. The electro-optical device according to claim 3, The first light-shielding layer is formed on the entire semiconductor layer that constitutes the plurality of diode elements. An electro-optical device characterized by being overlapped in a plan view.

5. A substrate body, Outside the display area, a sensor element including a diode element having a semiconductor layer; wiring provided so as not to overlap the semiconductor layer in a plan view; a first shielding layer disposed between the substrate body and the semiconductor layer and overlapping the semiconductor layer in a plan view; The optic layer and a second light-shielding layer disposed between the substrate body and the wiring and overlapping the wiring in a plan view; Equipped with The first light-shielding layer and the second light-shielding layer are disposed between the semiconductor layer and the wiring in a plan view. are spaced apart by a distance of 2 μm or less, The first light-shielding layer includes a first portion that overlaps the anode region of the semiconductor layer in a plan view, and a cathode region that overlaps the anode region of the semiconductor layer in a plan view. an electro-optical device, characterized in that the second portion overlapping the first region in a plan view is spaced apart from the first region in a plan view; Place.

6. 6. The electro-optical device according to claim 5, the first portion and the second portion are disposed via an insulating film. optical equipment.

7. A substrate body, Outside the display area, a sensor element having a semiconductor layer; a constant potential line that is provided so as not to overlap the semiconductor layer in a plan view and to which a constant potential is applied; a first shielding layer disposed between the substrate body and the semiconductor layer and overlapping the semiconductor layer in a plan view; The optic layer and a second shielding member disposed between the substrate body and the constant potential line and overlapping with the constant potential line in a plan view; The optic layer and another light-shielding layer adjacent to the second light-shielding layer in a plan view; Equipped with The first light-shielding layer and the second light-shielding layer are spaced apart from each other by a distance of 2 μm or less in a plan view. And, The distance between the first light-shielding layer and the second light-shielding layer is The electro-optical device is characterized in that the distance therebetween is longer than the distance between the electrodes.

8. A substrate body, Outside the display area, a sensor element having a semiconductor layer; a wiring provided so as not to overlap the semiconductor layer in a plan view, to which an AC signal is applied; a first shielding layer disposed between the substrate body and the semiconductor layer and overlapping the semiconductor layer in a plan view; The optic layer and a second light-shielding layer disposed between the substrate body and the wiring and overlapping the wiring in a plan view; another light-shielding layer adjacent to the second light-shielding layer in a plan view; Equipped with The first light-shielding layer and the second light-shielding layer are spaced apart from each other by a distance of 2 μm or less in a plan view. And, The distance between the first light-shielding layer and the second light-shielding layer is The electro-optical device is characterized in that the distance therebetween is longer than the distance between the electrodes.

9. A substrate body, Outside the display area, a sensor element having a semiconductor layer; The wiring and the signal wiring to which an AC signal is applied are provided so as not to overlap the semiconductor layer in a plan view. Route and a first shielding layer disposed between the substrate body and the semiconductor layer and overlapping the semiconductor layer in a plan view; The optic layer and a second light-shielding layer disposed between the substrate body and the wiring and overlapping the wiring in a plan view; a third light-shielding layer disposed between the substrate body and the signal line and overlapping the signal line in a plan view; and, another light-shielding layer disposed between the first light-shielding layer and the third light-shielding layer in a plan view; Equipped with The first light-shielding layer and the second light-shielding layer are spaced apart from each other by a distance of 2 μm or less in a plan view. And, The first light-shielding layer, the other light-shielding layer, and the third light-shielding layer are spaced apart from one another by 2 μm or less in plan view. are spaced apart at a distance, The distance between the first light-shielding layer and the second light-shielding layer is and the distance between the other light-shielding layer and the third light-shielding layer is longer than the distance between the other light-shielding layer and the third light-shielding layer. Place.

10. 10. The electro-optical device according to claim 9, The third light-shielding layer and the first light-shielding layer are disposed via an insulating film. Electro-optical device.

11. 11. The electro-optical device according to claim 1, The distance between the first light-shielding layer and the second light-shielding layer is The electro-optical device is characterized in that the distance between the electrodes is longer than the distance between the electrodes.

12. An electro-optical device comprising the electro-optical device according to any one of claims 1 to 11. Child equipment.

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