Multilayer ceramic capacitors

Abstract

The present invention provides a multilayer ceramic capacitor which has a good balance between improvement of reliability and improvement of temperature characteristics. With respect to this multilayer ceramic capacitor, a dielectric layer contains at least Ti; and if a region in the central part of the dielectric layer in the width direction and in the stacking direction, the region having a length of 800 nm in the width direction and a length of 1 nm in the stacking direction, is divided into 800 cells each having a length of 1 nm in the width direction and a length of 1 nm in the stacking direction, high-concentration cells, each of which has a molar ratio of rare earth elements of 5% by mole or more relative to 100 moles of Ti, are present at a proportion of not less than 75% but less than 100% among the 800 cells within the region.

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] BACKGROUND ART Multilayer ceramic capacitors are known that include a laminate in which a plurality of dielectric layers and internal electrode layers are alternately stacked, and external electrodes that are provided on the surface of the laminate and are electrically connected to the internal electrode layers that are extended to the surface of the laminate. While the applications of multilayer ceramic capacitors have expanded in recent years, their operating environments have become more severe, and they are increasingly being used in high-temperature environments. In high-temperature environments, the application of a high electric field can cause a problem of reduced insulation resistance. Patent Document 1 describes a multilayer ceramic capacitor whose dielectric layers contain a plurality of crystal grains that are primarily composed of barium titanate and in which magnesium, manganese, and rare earth elements are dissolved as oxides. As in the ceramic capacitor described in Patent Document 1, the crystal grains contained in the dielectric layers have a core-shell structure consisting of a core and a shell surrounding the core, which can suppress deterioration of insulation resistance in high-temperature environments. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-10530 Summary of the Invention [Problem to be solved by the invention]

[0004] However, even if the dielectric layers contain crystal grains with a core-shell structure, as in the multilayer ceramic capacitor described in Patent Document 1, it is still not possible to sufficiently suppress the deterioration of insulation resistance in a high-temperature environment, and there is room for improvement. Furthermore, there are cases where improving reliability and improving temperature characteristics are in conflict with each other. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic capacitor that achieves a good balance between improved reliability and improved temperature characteristics. [Means for solving the problem]

[0005] The multilayer ceramic capacitor comprises a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on the surface of the laminate and electrically connected to the internal electrode layers drawn out to the surface of the laminate, the dielectric layers containing at least Ti, and when a region having a length of 800 nm in the width direction and a length of 1 nm in the stacking direction at the center of the dielectric layers in the stacking direction and in the width direction perpendicular to the stacking direction is divided into 800 cells, each having a length of 1 nm in the width direction and a length of 1 nm in the stacking direction, and when a cell having a molar ratio of rare earth of 5 mol % or more relative to 100 mol of Ti is defined as a high-concentration cell, 75% or more but less than 100% of the 800 cells in the region are high-concentration cells.

[0006] Further, the multilayer ceramic capacitor comprises a laminate in which dielectric layers and internal electrode layers are alternately stacked multiple times, and external electrodes provided on the surface of the laminate and electrically connected to the internal electrode layers drawn out to the surface of the laminate, the dielectric layers containing at least Ti, and an area 800 nm long in the width direction and 800 nm long in the stacking direction at the center of the stacking direction of the dielectric layers and the width direction perpendicular to the stacking direction is divided into 800 cells in the width direction and 800 cells in the stacking direction, each cell having a length of 1 nm in the width direction and a length of 1 nm in the stacking direction, the arrangement of the cells in the width direction being defined as rows and the arrangement of the cells in the stacking direction being columns, and cells having a molar ratio of rare earth of 5 mol% or more relative to 100 mol of Ti are defined as high-concentration cells, and rows in which high-concentration cells account for 75% or more of the 800 cells in the same row are defined as high-concentration rows, where 9% to 43% of the 800 rows in the area are high-concentration rows. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that achieves a good balance between improved reliability and improved temperature characteristics. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view of a multilayer ceramic capacitor according to the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line II in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 4] FIG. 10 is a diagram showing how to divide into cells. [Figure 5] FIG. 10 is a diagram showing the distribution of high-concentration cells. [Figure 6] FIG. 10 is a diagram showing how to count the number of high-concentration cells. [Figure 7] FIG. 10 is a diagram showing another distribution of high-concentration cells. [Figure 8] FIG. 10 is a diagram showing another distribution of high-concentration cells. [Figure 9] FIG. 1 is a diagram showing characteristics of a multilayer ceramic capacitor. DETAILED DESCRIPTION OF THE INVENTION

[0009] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0010] <External view of multilayer ceramic capacitor> The outline of the appearance of the multilayer ceramic capacitor 1 will be described with reference to Fig. 1. Fig. 1 is a perspective view showing the multilayer ceramic capacitor 1 of this embodiment. The multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 20. The external electrodes 20 include a first external electrode 20a and a second external electrode 20b.

[0011] <Direction definition> 1 to 8 show an L direction, a W direction, and a T direction. The L direction is the length direction L of the multilayer ceramic capacitor 1. The W direction is the width direction W of the multilayer ceramic capacitor 1. The T direction is the stacking direction T of the multilayer ceramic capacitor 1. Therefore, the cross section shown in FIG. 2 is called the LT cross section, and the cross section shown in FIG. 3 is called the WT cross section. The length direction L, width direction W, and stacking direction T do not necessarily have to be perpendicular to each other, but may be intersecting each other.

[0012] <External shape of laminate> As shown in FIG. 1, the laminate 2 has a substantially rectangular parallelepiped shape. The laminate has two main surfaces M, two end surfaces E, and two side surfaces S. The main surfaces M are surfaces facing the stacking direction T. The end surfaces E are surfaces facing the length direction L. The side surfaces S are surfaces facing the width direction W. The two main surfaces M are referred to as a first main surface M1 and a second main surface M2. The two end surfaces E are referred to as a first end surface E1 and a second end surface E2. The two side surfaces S are referred to as a first side surface S1 and a second side surface S2.

[0013] It is preferable that the ridges and corners of the laminate 2 are rounded. A ridge is a portion where two surfaces of the laminate 2 intersect. A corner is a portion where three surfaces of the laminate 2 intersect.

[0014] <Size of laminate> The size of the laminate 2 is not particularly limited. For example, the length of the laminate 2 in the longitudinal direction L can be 0.05 mm or more and 1.00 mm or less. The length of the laminate 2 in the stacking direction T can be 0.10 mm or more and 0.50 mm or less. The length of the laminate 2 in the width direction W can be 0.10 mm or more and 0.50 mm or less. The length of each portion of the laminate 2 can be measured with a micrometer or an optical microscope. The length in the length direction L does not necessarily have to be longer than the length in the width direction W.

[0015] <Internal structure of laminate> The internal structure of the laminate 2 will be described with reference to Fig. 2. Fig. 2 is a cross-sectional view of the laminate ceramic capacitor shown in Fig. 1 taken along line II. The laminate 2 includes a plurality of dielectric layers 4 and a plurality of internal electrode layers 10. The plurality of dielectric layers 4 and the plurality of internal electrode layers 10 are stacked in a stacking direction T on top of each other.

[0016] <Inner and outer layers> The laminate 2 has inner layer portions IL and outer layer portions OL in the stacking direction T. The outer layer portions OL include a first outer layer portion OL1 and a second outer layer portion OL2. The first outer layer portion OL1 and the second outer layer portion OL2 are arranged to sandwich the inner layer portion IL in the stacking direction T.

[0017] The inner layer portion IL includes some of the plurality of dielectric layers 4 and a plurality of internal electrode layers 10. In the inner layer portion IL, the plurality of internal electrode layers 10 are arranged to face each other with the dielectric layer 4 interposed therebetween. The inner layer portion IL is a portion where capacitance is formed and essentially functions as a capacitor, and is therefore also called an effective portion.

[0018] The first outer layer portion OL1 is disposed on the first main surface M1 side of the laminate 2. The second outer layer portion OL2 is disposed on the second main surface M2 side of the laminate 2. Specifically, the first outer layer portion OL1 is disposed between the first main surface M1 and the internal electrode layer 10 that is closest to the first main surface M1 among the multiple internal electrode layers 10. The second outer layer portion OL2 is disposed between the second main surface M2 and the internal electrode layer 10 that is closest to the second main surface M2 among the multiple internal electrode layers 10. The first outer layer portion OL1 and the second outer layer portion OL2 do not include the internal electrode layer 10. The first outer layer portion OL1 and the second outer layer portion OL2 include the remaining dielectric layers 4 of the plurality of dielectric layers 4 excluding the dielectric layers 4 for the internal layer portion IL. The first outer layer portion OL1 and the second outer layer portion OL2 function as protective layers for the inner layer portion IL.

[0019] <Dielectric layer> The dielectric layer 4 includes an outer dielectric layer 5 and an inner dielectric layer 6 . <Outer dielectric layer> The outer dielectric layers 5 are the dielectric layers 4 that constitute the first outer layer portion OL1 and the second outer layer portion OL2 among the dielectric layers 4. The outer dielectric layers 5 are disposed between the first main surface M1 and the internal electrode layer 10 closest to the first main surface M1, and between the second main surface M2 and the internal electrode layer 10 closest to the second main surface M2.

[0020] <Inner dielectric layer> The inner dielectric layers 6 are dielectric layers 4 that are located between the internal electrode layers 10 and that, together with the internal electrode layers 10, constitute the inner layer portion IL. The inner dielectric layer 6 is disposed between a first inner electrode layer 10a and a second inner electrode layer 10b, which will be described below.

[0021] <Number of dielectric layers> The number of dielectric layers 4 stacked on the laminate 2 can be, for example, 10 to 2000.

[0022] <Thickness of dielectric layer> Of the dielectric layers 4, the outer dielectric layer 5 may have a thickness of, for example, 10 μm or more and 100 μm or less, and the inner dielectric layer 6 may have a thickness of, for example, 0.8 μm or more and 3.0 μm or less.

[0023] <Dielectric layer material> The material of the dielectric layer 4 is, for example, BaTiO3, CaTiO3, SrTiO 3、 It can be a dielectric ceramic containing CaZrO3 or TiO2 or the like. The material of the dielectric layer 4 may be the above-mentioned dielectric ceramic to which a Mn compound, Fe compound, Cr compound, Co compound, Ni compound or the like has been added in an amount less than that of the main component.

[0024] <Internal electrode layer> The internal electrode layers 10 include a first internal electrode layer 10a and a second internal electrode layer 10b. The first internal electrode layer 10a is an internal electrode layer 10 connected to the first external electrode 20a. The second internal electrode layer 10b is an internal electrode layer 10 connected to the second external electrode 20b. The first internal electrode layer 10a extends from the first end face E1 toward the second end face E2, and the second internal electrode layer 10b extends from the second end face E2 toward the first end face E1.

[0025] <Facing part and pull-out part> The first internal electrode layer 10a and the second internal electrode layer 10b each have a counter electrode portion 11 and an extraction electrode portion 12. The opposing electrode portion 11 is a portion of the internal electrode layer 10 where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. The extraction electrode portion 12 is a portion of the internal electrode layer 10 that is extracted from the opposing electrode portion 11 to the end face E1 or the end face E2 of the laminate 2.

[0026] The opposing electrode portion 11 of the first internal electrode layer 10a is referred to as the first opposing electrode portion 11a, and the extracted electrode portion 12 of the first internal electrode layer 10a is referred to as the first extracted electrode portion 12a. The first extracted electrode portion 12a is a portion extracted from the first opposing electrode portion 11a to the first end face E1 of the laminate 2. Similarly, the opposing electrode portion 11 of the second internal electrode layer 10b is referred to as the second opposing electrode portion 11b, and the extracted electrode portion 12 of the second internal electrode layer 10b is referred to as the second extracted electrode portion 12b. The second extracted electrode portion 12b is a portion extracted from the second opposing electrode portion 11b to the second end face E2 of the laminate 2.

[0027] <Number of internal electrode layers> The number of the internal electrode layers 10 can be, for example, 10 to 1000. The number of layers of the internal electrode layers 10 includes the number of first internal electrode layers 10a and second internal electrode layers 10b.

[0028] <Thickness of the internal electrode layer> The thickness of the internal electrode layer 10 can be set to, for example, 0.3 μm or more and 0.4 μm or less.

[0029] <Internal electrode layer material> The material of the internal electrode layers 10 can be, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys of Ni and Cu, alloys of Ag and Pd, etc. In addition, the material of the internal electrode layers 10 may contain dielectric particles of the same composition as the ceramic contained in the dielectric layers 4.

[0030] Sn may be disposed at the interface between the internal electrode layer 10 and the dielectric layer 4. This Sn may be in the form of a layer or may be scattered. Sn may be present in a solid solution on the internal electrode layer 10 side, or in a solid solution in the dielectric grains on the dielectric layer 4 side.

[0031] <Electrode facing part> The division of the laminate 2 in the length direction L will be described. The laminate 2 has an electrode opposing portion LF and an end gap portion EG in the longitudinal direction L. The end gap portion EG includes a first end gap portion EG1 and a second end gap portion EG2. The electrode facing portion LF is a portion where the first internal electrode layer 10a and the second internal electrode layer 10b face each other in the stacking direction T. In other words, the electrode facing portion LF is a portion where the first opposing electrode portion 11a and the second opposing electrode portion 11b face each other in the stacking direction T. The electrode facing portion LF is located at the center in the longitudinal direction L of the laminate 2. The electrode facing portion LF is a portion where electrostatic capacitance is formed and essentially functions as a capacitor, and is therefore also called an effective portion.

[0032] <End gap part> The end gap portion EG is a portion where the first internal electrode layer 10a and the second internal electrode layer 10b do not face each other in the stacking direction T. Specifically, in the stacking direction T, a portion where the first internal electrode layer 10a is arranged and the second internal electrode layer 10b is not arranged is the first end gap portion EG1. Similarly, a portion where the second internal electrode layer 10b is arranged and the first internal electrode layer 10a is not arranged is the second end gap portion EG2.

[0033] The first end gap EG1 corresponds to the portion where the first extraction electrode 12a is disposed, and the second end gap EG2 corresponds to the portion where the second extraction electrode 12b is disposed. The first end gap portion EG1 functions as an extraction electrode to the first end face E1 of the first internal electrode layer 10a, and the second end gap portion EG2 functions as an extraction electrode to the second end face E2 of the second internal electrode layer 10b. The end gap portion EG is a section in the length direction L, and is therefore also called an L gap.

[0034] The length of the end gap portion EG in the longitudinal direction L can be set to, for example, 5 μm or more and 30 μm or less.

[0035] <External electrode> The external electrodes include a first external electrode 20a and a second external electrode 20b. <First external electrode> The first external electrode 20a is an external electrode arranged on the first end face E1 of the laminate 2. The first external electrode 20a is electrically connected to the first internal electrode layer 10a.

[0036] <Second external electrode> The second external electrode 20b is an external electrode disposed on the second end face E2 of the laminate 2. The second external electrode 20b is electrically connected to the second internal electrode layer 10b.

[0037] <External electrodes on each side> The external electrode 20 extends from the end face E to parts of the two main faces M and to parts of the two side faces S. Of the external electrode 20, the portion arranged on the end face E is referred to as an end face external electrode 25. Of the external electrode 20, the portion arranged on a part of the main face M is referred to as a main face external electrode 26. Of the external electrode 20, the portion arranged on a part of the side face S is referred to as a side face external electrode 27.

[0038] Specifically, the portion of the first external electrode 20a that is arranged on the first end face E1 is referred to as the first end face external electrode 25a. The portion of the first external electrode 20a that is arranged on a part of the first main face M1 or a part of the second main face M2 is referred to as the first main face external electrode 26a. The portion of the first external electrode 20a that is arranged on a part of the first side face S1 or a part of the second side face S2 is referred to as the first side face external electrode 27a.

[0039] Similarly to the first external electrode 20a, the second external electrode 20b has a portion that is arranged on the second end face E2 referred to as a second end face external electrode 25b. The second external electrode 20b has a portion that is arranged on a part of the first main face M1 or a part of the second main face M2 referred to as a second main face external electrode 26b. The second external electrode 20b has a portion that is arranged on a part of the first side face S1 or a part of the second side face S2 referred to as a second side face external electrode 27b.

[0040] <Layer structure of external electrodes> The layer structure of the external electrode 20 will be described with reference to FIG. The external electrode 20 includes three layers: a base electrode layer 21, an inner plating layer 23, and a top plating layer 24. These layers are arranged in the following order from the end face E of the laminate 2: base electrode layer 21, inner plating layer 23, top plating layer 24. Specifically, the first external electrode 20a includes a first base electrode layer 21a, a first inner plating layer 23a, and a first surface plating layer 24a. Similarly, the second external electrode 20b includes a second base electrode layer 21b, a second inner plating layer 23b, and a second surface plating layer 24b. In the description of the external electrode 20, the direction away from the end face E of the laminate 2 may be referred to as the upside.

[0041] <Base electrode layer> The first base electrode layer 21a is disposed on and covers the first end face E1 of the laminate 2. The first base electrode layer 21a may extend from the first end face E1 to a portion of the first main face M1, a portion of the second main face M2, a portion of the first side face S1, and a portion of the second side face S2.

[0042] Similarly, the second base electrode layer 21b is disposed on and covers the second end face E2 of the laminate 2. The second base electrode layer 21b may extend from the second end face E2 to a part of the second main face M1, a part of the second main face M2, a part of the first side face S1, and a part of the second side face S2.

[0043] <Baked layer> The base electrode layer 21 can be a fired layer containing metal and glass. The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the applied paste. The fired layer may be a multi-layer structure.

[0044] The metal contained in the fired layer contains Cu as a main component, and may contain at least one selected from metals such as Ni, Ag, Pd, and Au, or alloys such as Ag-Pd alloys, as a main component, or may contain the same as a component other than the main component.

[0045] The glass contained in the fired layer may be a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. As a specific example, borosilicate glass may be used.

[0046] Alternatively, the base electrode layer 21 may be a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0047] The conductive resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the applied paste. The conductive resin layer may be a multi-layered layer.

[0048] The thickness of each of the base electrode layers 21 as the fired layer or conductive resin layer is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0049] The base electrode layer 21 may also be a thin film layer of 1 μm or less formed by a thin film formation method such as sputtering or vapor deposition, in which metal particles are deposited.

[0050] <Inner plating layer> The inner plating layer 23 is disposed on the base electrode layer 21 and covers at least a portion of the base electrode layer 21. The inner plating layer 23 includes at least one selected from metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag-Pd alloys.

[0051] <Surface plating layer> The surface plating layer 24 is disposed on the inner plating layer 23 and covers at least a portion of the inner plating layer 23. The surface plating layer 24 contains a metal such as Sn, for example.

[0052] The inner plating layer 23 is preferably a Ni plating layer, and the surface plating layer 24 is preferably a Sn plating layer. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component. The Sn plating layer can improve the wettability of the solder when mounting the ceramic electronic component, making mounting easier. By using a Sn plating layer as the top plating layer 24, the wettability of the solder to the external electrode 20 can be improved.

[0053] <Other configurations of external electrodes> The external electrode 20 can be a plated layer that is provided directly on the laminate 2 and directly connected to the internal electrode layer 10. A catalyst may also be provided on the laminate 2 as a pretreatment for plating. The plating layer preferably includes a first plating layer and a second plating layer provided on the first plating layer. The first plating layer and the second plating layer preferably include plating of one metal selected from the group consisting of Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn, or an alloy containing such a metal. For example, when Ni is used for the internal electrode layer 10, it is preferable to use Cu, which has good bonding properties with Ni, for the first plating layer. The second plating layer is preferably made of Sn or Au, which has good solder wettability, while the first plating layer is preferably made of Ni, which has solder barrier properties.

[0054] The second plating layer is formed as needed, so the external electrode 20 may be composed of only the first plating layer. The second plating layer may be provided as the outermost plating layer, or another plating layer may be provided on the second plating layer. The metal content per unit volume of the plating layer is preferably 99% by volume or more. The plating layer may have grains grown along the stacking direction T, and may be columnar.

[0055] <Internal structure of laminate (WT cross section)> The internal structure of the laminate 2, particularly the internal structure as seen from the second end face E2, will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II. The laminate 2 has an electrode facing portion WF and a side gap portion SG where the internal electrode layers 10 face each other in the width direction W. The side gap portion SG includes a first side gap portion SG1 and a second side gap portion SG2. The first side gap portion SG1 and the second side gap portion SG2 are arranged to sandwich the electrode facing portion WF. The first side gap SG1 is located between the electrode facing portion WF and the first side surface S1, and the second side gap SG2 is located between the electrode facing portion WF and the second side surface S2.

[0056] Specifically, the first side gap portion SG1 is located between the end of the internal electrode layer 10 on the first side surface S1 side and the first side surface S1, and the second side gap portion SG2 is located between the end of the internal electrode layer 10 on the second side surface S2 side and the second side surface S2. The first side gap SG1 and the second side gap SG2 do not include the internal electrode layer 10, but include only the dielectric layer 4. The first side gap SG1 and the second side gap SG2 function as protective layers for the internal electrode layers 10. The side gap portion SG is a section in the width direction W, and is therefore also called a W gap.

[0057] The length of the side gap portion SG in the width direction W can be set to, for example, one tenth of the length of the laminate 2 in the width direction W, or to 5 μm or more and 30 μm or less.

[0058] <Size of multilayer ceramic capacitor> The length in the longitudinal direction L of the entire multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 20, can be, for example, 0.2 mm or more and 2.0 mm or less. The length in the lamination direction T of the entire multilayer ceramic capacitor 1 can be, for example, 0.1 mm or more and 1.2 mm or less. The length in the width direction W of the entire multilayer ceramic capacitor 1 can be, for example, 0.1 mm or more and 1.2 mm or less.

[0059] In this embodiment, the multilayer ceramic capacitor 1 is a two-terminal capacitor, but the multilayer ceramic capacitor 1 is not limited to two terminals and can also be a multi-terminal capacitor with three or more terminals.

[0060] <Distribution of rare earth elements> The distribution of rare earth elements in the dielectric layer 4 will be described. The multilayer ceramic capacitor 1 of this embodiment is characterized by the distribution of rare earth elements in the dielectric layers 4. For example, in a dielectric layer 4 containing BaTiO3, when a high temperature and high electric field load is applied to the ceramic grain boundary, oxygen vacancies move and the insulation resistance deteriorates. Here, the migration of oxygen vacancies is suppressed by the solid solution of rare earth elements such as Re in BaTiO3. The more regions in the direction of the electric field where rare earth elements are solid-solved, the more the migration of oxygen vacancies is suppressed, resulting in higher reliability. In the multilayer ceramic capacitor 1 of this embodiment, rare earth elements are uniformly dissolved at a high concentration in the electrolysis direction. Specifically, by forming a region in which rare earth elements are uniformly dissolved in the electric field direction, i.e., the stacking direction T, the movement of oxygen vacancies is inhibited, thereby improving reliability. The following description will be given with reference to the drawings.

[0061] FIG. 4 is a WT cross-sectional view of the inner dielectric layer 6. 4 is a region having a length of 800 nm in the width direction W and a length of 800 nm in the stacking direction T at the center of the width direction W and the stacking direction T of the inner dielectric layer 6. Hereinafter, the predetermined region at the center of the width direction W and the stacking direction T of the inner dielectric layer 6 may be referred to as the evaluation region. The squares shown in Fig. 4 are squares with a length of 1 nm in the width direction W and a length of 1 nm in the stacking direction T. Each square corresponds to one cell. Also, an arrangement of cells extending in the width direction W is referred to as a row, and an arrangement of cells extending in the stacking direction T is referred to as a column. The area shown in FIG. 4 is divided into 800 rows and 800 columns, totaling 640,000 cells.

[0062] <High-concentration cells and low-concentration cells> Cell H in FIG. 4 indicates a high-concentration cell, and cell L in FIG. 4 indicates a low-concentration cell. Here, a high-concentration cell refers to a cell in which the molar ratio of rare earth elements is 5 mol% or more relative to 100 mol of Ti, while a low-concentration cell refers to a cell in which the molar ratio of rare earth elements is less than 5 mol% relative to 100 mol of Ti. The rare earth may be, for example, at least one of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y.

[0063] In the multilayer ceramic capacitor 1 of this embodiment, 600 or more but less than 800 high-concentration cells exist among 800 consecutive cells in the width direction W. In other words, 75% or more but less than 100% of the cells belonging to one row are high-concentration cells. This improves reliability in the electrolysis direction, in other words, in the stacking direction T.

[0064] On the other hand, if the proportion of high-concentration cells H is too high, the temperature characteristics will deteriorate. In the multilayer ceramic capacitor 1 of this embodiment, high-concentration cells H and low-concentration cells L coexist. Therefore, it is possible to provide a multilayer ceramic capacitor that has a good balance between improved reliability and improved temperature characteristics.

[0065] The dielectric layer 4 includes a plurality of dielectric grains. The dielectric grains are barium titanate-based ceramics such as perovskite-type compounds containing Ba and Ti, and are ceramic layers containing perovskite-type compounds containing Ba and Ti and rare earth elements. In high-concentration cells containing a predetermined amount or more of rare earth elements, the rare earth elements are likely to form a solid solution in barium titanate and the like. In the areas where the rare earth elements are solid-solved, the movement of oxygen vacancies is likely to be suppressed. Here, if a certain proportion or more of high-concentration cells exist in the width direction W, i.e., the row direction, which is perpendicular to the electrolysis direction, the movement of oxygen vacancies is efficiently suppressed, thereby improving the reliability of the multilayer ceramic capacitor 1.

[0066] A specific description will be given with reference to FIGS. FIG. 5 is a diagram showing the distribution of high-concentration regions H within the 800 nm×800 nm evaluation region described above. 501 in FIG. 5 shows the distribution of the molar ratio of rare earth elements in the cell, as measured by TEM (Transmission Electron Microscope)-EDX (Energy Dispersive X-ray Spectroscopy). 5 shows the distribution of the rare earth molar ratios of each cell, binarized as shown in 502. In the binarization, cells with a rare earth molar ratio of 5 mol% or more relative to 100 mol of Ti were designated as high-concentration cells H, and cells with a rare earth molar ratio of less than 5 mol% relative to 100 mol of Ti were designated as low-concentration cells L. 503 in FIG. 5 is a diagram showing the percentage of high-concentration cells H in each row.

[0067] As shown in FIG. 5, the proportion of high-concentration cells H in each row can be determined by binarizing the analysis results obtained by TEM-EDX.

[0068] A method for determining the proportion of high-concentration cells H in each row will be specifically described with reference to FIG. 601 in FIG. 6 is a diagram showing the distribution of the rare earth molar ratios of each cell after binarization, similar to 502 in FIG. 6 is an enlarged view of the rectangular area R in 601 in FIG. As mentioned above, the evaluation area is divided into 1 nm x 1 nm cells. TEM-EDX analysis and binarization of the results are performed for each cell. Therefore, as shown in 602 in Figure 6, the binarized results are output in a mosaic format in 1 nm units. Then, by counting the number of high-density cells H for each row, the proportion of high-density cells H in each row can be calculated, as shown in 503 of FIG. Similarly, how the proportion of high-concentration cells H is distributed in the stacking direction T can be found.

[0069] In the example shown in FIG. 5, there are rows in which the proportion of high-density cells H in the row direction is 75% or more and less than 100%.

[0070] 7 and 8 are diagrams corresponding to FIG. 5, showing other multilayer ceramic capacitors. 7 shows an example in which the proportion of high-concentration cells H is higher than that of the multilayer ceramic capacitor 1 shown in FIG. 5. Also, FIG. 8 shows an example in which the proportion of high-concentration cells H is lower than that of the multilayer ceramic capacitor 1 shown in FIG. 5. In the multilayer ceramic capacitor shown in Fig. 7, as shown by 702 in Fig. 7, the proportion of high-concentration cells H is higher than that of 502 in Fig. 5. Therefore, as shown by 703 in Fig. 7, the proportion of high-concentration cells H is 75% or more in all rows in the stacking direction T.

[0071] On the other hand, in the multilayer ceramic capacitor shown in Fig. 8, as shown in 802 in Fig. 8, the proportion of high-concentration cells H is lower than that of 502 in Fig. 5. Therefore, as shown in 803 in Fig. 8, there is no row where the proportion of high-concentration cells H is 75% or more.

[0072] <Distribution in stacking direction> Next, the distribution in the column direction of the high-concentration cells H, that is, in the stacking direction T, will be described. Here, a row in which 75% or more of the 800 cells in the same row are high-density cells is defined as a high-density row. It is preferable that high-density rows account for 9% to 43% of the total number of rows included in the evaluation area. If the total number of rows is 800, it is preferable that high-density rows be 72 to 344.

[0073] The presence of high-concentration cells H at a predetermined rate or more improves the reliability of the multilayer ceramic capacitor 1. It can improve the performance. However, if the proportion of high-concentration cells H is too high, the temperature characteristics will deteriorate. Therefore, by setting the proportion of high-density rows to between 9% and 43% of the total number of 800 rows included in the evaluation area, it is possible to improve reliability while suppressing deterioration in temperature characteristics.

[0074] In the multilayer ceramic capacitor shown in Fig. 5, 281 of the 800 rows are high-density rows, as indicated by 503 in Fig. 5. The proportion of high-density rows is 35%. Therefore, in the multilayer ceramic capacitor shown in FIG. 5, it is possible to suppress a decrease in temperature characteristics while improving reliability.

[0075] On the other hand, in the multilayer ceramic capacitor shown in Fig. 7, all of the 800 rows are high-density rows, as shown by 703 in Fig. 7. Therefore, the multilayer ceramic capacitor shown in Fig. 7 is inferior to the multilayer ceramic capacitor shown in Fig. 5 in terms of temperature characteristics.

[0076] <Low concentration cell> Next, the proportion of the low-concentration cells L will be described. As described above, the low-concentration cells L are cells in which the molar ratio of rare earth is less than 5 mol % relative to 100 mol of Ti. The number of these low-concentration cells L is preferably 71% or less of the total number of cells in the evaluation area. If the ratio of low-concentration cells L exceeds a certain range, reliability cannot be guaranteed. If the area occupied by low-concentration cells L increases, there is a possibility that a path for electrons will be created in the direction of the electric field. As a result, reliability cannot be guaranteed.

[0077] <Characteristics> Next, the characteristics of the example of the present invention and the comparative example will be shown based on Fig. 9. Fig. 9 is a table showing the characteristics of the example of the present invention and the comparative example. 9, the percentage of high-density regions in one line refers to the percentage of high-density cells among the cells belonging to one row. For example, if 200 of the 800 cells in one row are high-density cells, the percentage of high-density regions in one line is 25%.

[0078] MTTF stands for Mean Time To Failure.

[0079] The high-density area rate refers to the percentage of high-density rows among 800 rows, assuming that a row has 75% or more high-density cells among the 800 cells in the same row. For example, if there are 200 high-density rows among 800 rows, the high-density area rate is 25%.

[0080] The low-density area rate refers to the percentage of low-density cells among all cells in the evaluation area. For example, if there are 320,000 low-density cells among 640,000 cells in an 800-row x 800-column area, the low-density area rate is 50%.

[0081] <mttf> 9, Examples 1 to 6, in which the proportion of high-concentration regions in one line was 75% or more and less than 100%, exhibited better MTTF than Comparative Examples 2 and 3, in which the proportion of high-concentration regions in one line was less than 75%. Note that Comparative Example 1, in which the proportion of high-concentration regions in one line was 100%, exhibited good MTTF but poor temperature characteristics of relative dielectric constant. Similarly, in Examples 1 to 6 in which the high-density region rate was 9% or more and 43% or less, the MTTF was good as described above. Furthermore, in Examples 1 to 6, in which the low-concentration region rate was 71% or less, the temperature characteristics were good. In Comparative Example 1, in which the low-concentration region rate was 0%, other characteristics were outside the preferred ranges.

[0082] <Measurement method> As explained above, the sample to be subjected to TEM-EDX can be prepared by polishing the cross section of the laminate 2 at the center in the longitudinal direction L, exposing the surface in the width direction W and the stacking direction T. Then, the center of the cross section is imaged at 800 nm × 800 nm.

[0083] <Method for measuring dielectric constant> Next, a method for measuring the dielectric constant will be described. The dielectric constant is determined by applying a voltage of 1 kHz and 0.8 kV / mm, measuring the capacitance, and then calculating it using the following formula. Cap=εr·ε0×S / d where Cap is the dielectric constant, εr is the relative dielectric constant of the sample, ε0 is the dielectric constant of a vacuum, S is the area of ​​the electrode, and d is the thickness of the dielectric layer.

[0084] <Manufacturing method for multilayer ceramic capacitors> The multilayer ceramic capacitor 1 of this embodiment can be manufactured in the same manner as the conventional multilayer ceramic capacitor 1, in terms of the general flow of the manufacturing process.

[0085] To achieve a desired distribution of rare earth elements in the dielectric layer 4, for example, the following method can be used. That is, when preparing a laminated block, the distribution of rare earth elements in the dielectric sheets to be laminated is adjusted within the plane of the dielectric sheets, and when laminating the dielectric sheets, the distribution of rare earth elements in the dielectric sheets to be laminated is adjusted so that the distribution of rare earth elements in the lamination direction becomes a desired distribution. This allows the rare earth elements to be distributed in the width direction W, length direction L and stacking direction T in a desired manner.

[0086] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible. [Explanation of symbols]

[0087] 1. Multilayer ceramic capacitors 2. Laminate 4 Dielectric Layer 5. Outer dielectric layer 6 Inner dielectric layer 10 Internal electrode layer 11 Counter electrode section 12 Extraction electrode 20 External electrode 21 Base electrode layer 23 Inner plating layer 24 Surface plating layer 25 Edge external electrode 26 Main surface external electrode 27 Side external electrode IL Inner Layer OL outer layer LF electrode opposing part EG end gap WF electrode facing part SG Side gap part M main surface E End face S side T Stacking direction L lengthwise W width direction< / mttf>

Claims

1. a laminate in which a plurality of dielectric layers and internal electrode layers are alternately stacked; an external electrode provided on a surface of the laminate and electrically connected to the internal electrode layer extended to the surface of the laminate, the dielectric layer contains at least Ti; In the center portion of the dielectric layer in the stacking direction and in the width direction perpendicular to the stacking direction, A region with a width of 800 nm and a length of 1 nm in the stacking direction is The size of each cell is 1 nm in the width direction and 1 nm in the stacking direction, and the cell is divided into 800 cells. When a cell in which the molar ratio of rare earth is 5 mol % or more relative to 100 mol of Ti is defined as a high concentration cell, Among 800 cells in the region, high-concentration cells account for 75% or more but less than 100%. Multilayer ceramic capacitor.

2. a laminate in which a plurality of dielectric layers and internal electrode layers are alternately stacked; an external electrode provided on a surface of the laminate and electrically connected to the internal electrode layer extended to the surface of the laminate, the dielectric layer contains at least Ti; In the center portion of the dielectric layer in the stacking direction and in the width direction perpendicular to the stacking direction, A region having a width of 800 nm and a stacking direction of 800 nm is The size of each cell is 1 nm in the width direction and 1 nm in the stacking direction, and the cell is divided into 800 cells in the width direction and 800 cells in the stacking direction. The arrangement of cells in the width direction is defined as a row, and the arrangement of cells in the stacking direction is defined as a column. A cell in which the molar ratio of rare earth is 5 mol % or more relative to 100 mol of Ti is defined as a high-concentration cell. If a row has 75% or more high-density cells among 800 cells in the same row, the row is considered to be a high-density row. Among 800 lines in the region, high density lines are present in 9% to 43%. Multilayer ceramic capacitor.

3. When a cell in which the molar ratio of rare earth is less than 5 mol% relative to 100 mol of Ti is defined as a low concentration cell, the number of low-concentration cells is 71% or less of the total number of cells in the region; The multilayer ceramic capacitor according to claim 2 .

4. The thickness of the dielectric layer is 0.8 μm or more and 3.0 μm or less. The multilayer ceramic capacitor according to any one of claims 1 to 3.

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