Multilayer ceramic electronic components

Abstract

The present invention provides a multilayer ceramic electronic capacitor that has a high cracking resistance.　This multilayer ceramic capacitor 1 comprises: a laminate 10; a first external electrode 40A, which includes a first base electrode layer 50A; and a second external electrode 40B, which includes a second base electrode layer 50B, said external electrodes 40A and 40B being set apart from each other at each of both ends in the length direction L of the laminate 10. The first base electrode layer 50A and the second base electrode layer 50B have a metal part 70 and a plurality of non-metal parts 80 that are present in the metal part 70, and in the cross section view perpendicular to the width direction W, the average area of the non-metal parts 80 in a first population constituted of non-metal parts 80 having a circularity of 0.4 or less is 10 µm2 or greater, and in the cross section view perpendicular to the width direction W, the ratio at which the non-metal parts 80 are present in the first base electrode layer 50A and the second base electrode layer 50B is 8.2% or greater.

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component. [Background technology]

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on both end surfaces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, in which the external electrodes include base electrode layers formed by baking. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-243249 Summary of the Invention [Problem to be solved by the invention]

[0004] In the multilayer ceramic capacitor described in Patent Document 1, the external electrodes (external electrode layers) not only serve to electrically connect to the internal electrodes (internal electrode layers) but also to prevent moisture from penetrating into the end faces of the laminate from the outside. However, there is a risk that cracks will occur in the laminate of the multilayer ceramic capacitor when force is applied to these external electrodes.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a multilayer ceramic electronic component that is highly crack-resistant. [Means for solving the problem]

[0006] A multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of ceramic layers and a plurality of internal conductor layers alternately stacked in a stacking direction, and including a first main surface and a second main surface opposing each other in the stacking direction, a first end face and a second end face opposing each other in a longitudinal direction perpendicular to the stacking direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the stacking direction and the longitudinal direction, and a pair of external electrodes disposed spaced apart from each other at both longitudinal end portions of the laminate, wherein the internal conductor layers include a first internal conductor layer extended to the first end face, a second internal conductor layer extending to the second end face, wherein the external electrodes include a first external electrode including a first base electrode layer connected to the first internal conductor layer, and a second external electrode including a second base electrode layer connected to the second internal conductor layer, wherein the first base electrode layer and the second base electrode layer have a metal portion and a plurality of non-metal portions present in the metal portion, and the average area of ​​the non-metal portions in a first population constituted by the non-metal portions having a circularity of 0.4 or less is 10 μm or less in a cross section perpendicular to the width direction. 2 As described above, in a cross-sectional view perpendicular to the width direction, the abundance ratio of the non-metallic portion in the first base electrode layer and the second base electrode layer is 8.2% or more. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component having high crack resistance. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II of FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2. [Figure 4A] FIG. 3 is a cross-sectional view taken along the line IVA-IVA in FIG. 2. [Figure 4B] 4 is a cross-sectional view taken along line IVB-IVB of FIG. 2. [Figure 5] FIG. 3 is an enlarged cross-sectional view based on an SEM photograph of a portion indicated by R1 in FIG. 2. [Figure 6] FIG. 10 is a diagram showing an example of a non-metal part having a relatively low circularity. [Figure 7A] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a double structure. [Figure 7B] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a triple structure. [Figure 7C] FIG. 1 is a diagram showing a multilayer ceramic capacitor with a four-element structure. [Figure 8] FIG. 1 is a schematic diagram for explaining a weight drop test in the examples. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, a multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the embodiment. Fig. 2 is a cross-sectional view taken along II-II in Fig. 1. Fig. 3 is a cross-sectional view taken along III-III in Fig. 2. Fig. 4A is a cross-sectional view taken along IVA-IVA in Fig. 2. Fig. 4B is a cross-sectional view taken along IVB-IVB in Fig. 2.

[0010] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 while being spaced apart from each other.

[0011] In FIG. 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T also corresponds to the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In FIG. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In FIG. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the length direction L of the laminate 10.

[0012] 1 to 4B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0013] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T and the length direction L.

[0014] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 6 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, then the T dimension is preferably 0.05 mm or more and 5 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0017] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers stacked alternately in the stacking direction T, and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes, in the stacking direction T, the internal electrode layer 30 located closest to the first principal surface TS1 to the internal electrode layer 30 located closest to the second principal surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0018] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. The dielectric material may also be a material containing these main components plus a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound. It is particularly preferable that the dielectric material contain BaTiO3 as the main component.

[0019] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0020] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers and multiple second internal electrode layers 32 as multiple second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with the dielectric layer 20 sandwiched therebetween. The first internal electrode layers 31 extend to the first end face LS1. The second internal electrode layers 32 extend to the second end face LS2. In the following, when it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layers 30.

[0021] 4A, the first internal electrode layer 31 has a first opposing portion 31A and a first lead portion 31B. The first opposing portion 31A is a region facing the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first lead portion 31B is a portion that extends from the first opposing portion 31A to the first end face LS1 and is exposed at the first end face LS1.

[0022] 4B, the second internal electrode layer 32 has a second opposing portion 32A and a second lead portion 32B. The second opposing portion 32A is a region facing the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second lead portion 32B is a portion that extends from the second opposing portion 32A to the second end face LS2 and is exposed at the second end face LS2.

[0023] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first drawer portion 31B and the second drawer portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0025] The width direction W dimension of the first facing portion 31A and the width direction W dimension of the first lead portion 31B may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the second facing portion 32A and the width direction W dimension of the second lead portion 32B may be the same dimension, or one of the dimensions may be smaller.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 1000 or less.

[0028] As shown in FIGS. 2 and 3 , the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0029] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. FIGS. 4A and 4B show the ranges of the counter electrode portion 11E in the width direction W and length direction L. The counter electrode portion 11E is also referred to as the effective portion of the capacitor.

[0030] The laminate 10 has a side surface outer layer portion. The side surface outer layer portion includes a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second side surface WS2. Figures 3, 4A, and 4B show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portion is also referred to as a W gap or a side gap.

[0031] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion located between the counter electrode portion 11E and the first end face LS1, and includes the dielectric layer 20 and the first lead portion 31B. That is, the first end surface side outer layer portion LG1 is an assembly of the portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions 31B. The second end surface side outer layer portion LG2 is a portion located between the counter electrode portion 11E and the second end face LS2, and includes the dielectric layer 20 and the second lead portion 32B. That is, the second end surface side outer layer portion LG2 is an assembly of the portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of second lead portions 32B. 2, 4A, and 4B show the range of the first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 in the length direction L. The end-side outer layer portions are also called L gaps or end gaps.

[0032] As shown in Figures 1 and 2, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0033] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0034] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions 32B of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20, thereby forming capacitance. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0037] 2, 4A, and 4B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0038] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions 31B of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0039] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions 32B of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0040] The first and second base electrode layers 50A and 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, and Au. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, and Li. The ceramic component may be the same ceramic material as that of the dielectric layer 20, or a different ceramic material. The ceramic component may include at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, and CaZrO3.

[0041] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer can be formed by simultaneously baking a pre-fired laminate chip, which is the material for the laminate 10 having multiple internal electrodes and dielectric layers, and a conductive paste applied to the laminate chip. Alternatively, the baked layer can be formed by first firing the laminate chip to obtain the laminate 10, and then applying a conductive paste to the laminate 10 and baking it. In the above configuration, the baked layer is preferably formed by baking a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be multiple layers.

[0042] The thickness of the first base electrode layer 50A located on the first end face LS1 in the longitudinal direction L is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0043] The thickness of the second base electrode layer 50B located on the second end face LS2 in the longitudinal direction L is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0044] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on this portion, corresponding to the stacking direction T, is preferably, for example, approximately 3 μm or more and 40 μm or less, at the center of the first base electrode layer 50A provided on this portion in the length direction L and width direction W.

[0045] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided on this portion in the width direction W is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and stacking direction T.

[0046] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on this portion in the stacking direction T is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the second base electrode layer 50B provided on this portion in the length direction L and width direction W.

[0047] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided on this portion in the width direction W is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the second base electrode layer 50B provided on this portion in the length direction L and stacking direction T.

[0048] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0049] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0050] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0051] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A. In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0052] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B. In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0053] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0054] The external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer.

[0055] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0056] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The conductive particles preferably contain Ag. The conductive particles may be, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as the conductive particles.

[0057] The conductive particles may also be metal powders whose surfaces are coated with Ag. When using metal powders whose surfaces are coated with Ag, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag while making the base metal inexpensive, it is preferable to use Ag-coated metal powders.

[0058] Furthermore, the conductive particles may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive particles may be metal powder whose surface is coated with Sn, Ni, or Cu. When using metal powder whose surface is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0059] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0060] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, the conductive particles come into contact with each other to form electrical paths within the conductive resin layer.

[0061] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0062] The conductive resin layer may be formed of multiple layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0063] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 6 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 is defined as T, then the T dimension is preferably 0.05 mm or more and 5 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, then the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0064] Through repeated investigations and experiments, the inventors of the present application have found that in order to improve the crack resistance of a multilayer ceramic capacitor, it is desirable to make the non-metallic portions included in the base electrode layers that directly contact the laminate, i.e., the first base electrode layer 50A and the second base electrode layer 50B of this embodiment, into an appropriate state. This point will be explained below.

[0065] Fig. 5 is an enlarged cross-sectional view based on an SEM (scanning electron microscope) photograph of the portion indicated by R1 in Fig. 2. Fig. 5 shows a portion of the LT cross section perpendicular to the width direction W of the laminate 10 in the multilayer ceramic capacitor 1. Fig. 5 shows the first base electrode layer 50A, a portion of the first Ni plating layer 61A, and a portion of the laminate 10. Fig. 5 shows the dielectric layer 20 and multiple first internal electrode layers 31 in the laminate 10. The first base electrode layer 50A is in contact with the first internal electrode layer 31 exposed at the first end face LS1 of the laminate 10.

[0066] The second base electrode layer 50B of this embodiment also has a cross-sectional structure similar to that shown in Fig. 5. Therefore, the configuration of the first base electrode layer 50A described with reference to Fig. 5 is the configuration of the second base electrode layer 50B. Therefore, hereinafter, when it is not necessary to distinguish between the first base electrode layer 50A and the second base electrode layer 50B, the first base electrode layer 50A and the second base electrode layer 50B may be collectively referred to as the base electrode layer 50.

[0067] As shown in FIG. 5, the base electrode layer 50 has a metal portion 70 and a plurality of non-metal portions 80 present in this metal portion 70.

[0068] The metal portion 70 contains at least one metal component selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc., contained in the above-described baked layer that forms the base electrode layer 50. A plurality of non-metal portions 80 are dispersed within such metal portion 70.

[0069] The non-metallic portions 80 are primarily voids, but may not be entirely voids and may partially contain glass components containing Ba or Si. The non-metallic portions 80 may also be entirely composed of glass components containing Ba or Si. The multiple non-metallic portions 80 have different degrees of circularity and average areas. The non-metallic portions 80 function to relieve stress caused by force applied to the external electrode.

[0070] In the base electrode layer 50 of this embodiment, in the cross-sectional view of the LT perpendicular to the width direction W as shown in FIG. 5, the average area of ​​the non-metallic portions 80 in the first population constituted by the non-metallic portions 80 having a circularity of 0.4 or less is 10 μm 2 It is preferable that this is equal to or greater than this.

[0071] In the base electrode layer 50 of this embodiment, in the LT cross section perpendicular to the width direction W as shown in FIG. 5, the abundance ratio of the non-metallic portion 80 is preferably 8.2% or more.

[0072] In the multilayer ceramic capacitor 1 of this embodiment, of the non-metallic portions 80 present in the base electrode layer 50, the non-metallic portions 80 with low circularity have a relatively large area.

[0073] 6 shows an example of a non-metallic portion 80 with a relatively low circularity. The circularity of this non-metallic portion 80 is 0.169. When there are multiple non-metallic portions 80 with such low circularity and the non-metallic portions 80 are large in size, it is possible to effectively achieve stress relaxation without increasing the size of all of the non-metallic portions 80 or significantly increasing the proportion of the non-metallic portions 80 present.

[0074] In this embodiment, when a population constituted by non-metallic portions 80 having a circularity of 0.4 or less in the LT cross section of the base electrode layer 50 is defined as a first population, the average area of ​​the plurality of non-metallic portions 80 constituting the first population is 10 μm 2 In the region shown in Figure 5, the 2 In this embodiment, the proportion of the non-metallic portion 80 in the base electrode layer 50 is 8.2% or more, specifically 18% in the region shown in FIG. 5. This ensures the effect of alleviating stress against force applied to the external electrode even when the base electrode layer 50 contains the non-metallic portion 80. This improves crack resistance and increases reliability.

[0075] In this embodiment, the average area of ​​the plurality of non-metallic portions 80 constituting the first population is preferably 10 μm 2 More than 23μm 2 More preferably, 10.5 μm or less. 2 More than 23μm 2 This provides the effect of more appropriately improving crack resistance.

[0076] In the multilayer ceramic capacitor 1 of this embodiment, in the LT cross section, the abundance ratio of the non-metallic portion 80 in the base electrode layer 50 is preferably 8.2% or more, and more preferably, for example, 8.2% or more and 30% or less. Furthermore, the abundance ratio of the non-metallic portion 80 in the base electrode layer 50 is preferably, for example, 8.2% or more and 25% or less, and more preferably, for example, 11% or more and 25% or less. Even if the base electrode layer 50 contains the non-metallic portion 80 and the abundance ratio of the non-metallic portion 80 in the base electrode layer 50 is within this range, the effect of this embodiment, i.e., the effect of improving crack resistance, can be obtained.

[0077] Next, methods for measuring various parameters in this embodiment, such as the circularity of the non-metallic portions 80, the average area of ​​the non-metallic portions 80, and the proportion of the non-metallic portions 80 in the base electrode layer 50, will be described.

[0078] First, the multilayer ceramic capacitor 1 is polished from the first side surface WS1 or the second side surface WS2 to a position halfway along the width direction W. This exposes the LT cross section at the center of the multilayer ceramic capacitor 1 in the width direction W. Next, the LT cross section exposed by polishing is observed using an SEM. Specifically, a backscattered electron image is taken of the portion of the LT cross section including the base electrode layer 50. In the backscattered electron image, the difference in resistance value is reflected as contrast, with the metal portion 70 appearing relatively white and the non-metal portion 80 appearing darker than the metal portion 70. The magnification is 2000x, and the portion of the base electrode layer 50 in the backscattered electron image is the range of analysis.

[0079] Backscattered electron images are acquired at four locations: two locations on the first base electrode layer 50A and two locations on the second base electrode layer 50B. In FIG. 2, the four locations where the backscattered electron images are acquired are indicated by R1, R2, R3, and R4. R1 is the portion of the first base electrode layer 50A that contacts the inner layer portion 11 of the laminate 10 closest to the first principal surface TS1. R2 is the portion of the first base electrode layer 50A that contacts the inner layer portion 11 of the laminate 10 closest to the second principal surface TS2. R3 is the portion of the second base electrode layer 50B that contacts the inner layer portion 11 of the laminate 10 closest to the first principal surface TS1. R4 is the portion of the second base electrode layer 50B that contacts the inner layer portion 11 of the laminate 10 closest to the second principal surface TS2. The length of R1, R2, R3, and R4 in the stacking direction T was all 80 μm.

[0080] In the base electrode layer 50, four regions corresponding to the backscattered electron image acquisition positions R1, R2, R3, and R4 are likely to become structural singular points and have a large impact on crack resistance. Therefore, the state of the base electrode layer 50 in these portions is important from the viewpoint of crack resistance.

[0081] The acquired backscattered electron image is binarized using image analysis software "WinROOF (manufactured by Mitani Shoji Co., Ltd.)" to distinguish between the metal portion 70 and the multiple non-metal portions 80 present within the metal portion 70. This binarized image is used to calculate various parameters such as the area of ​​each non-metal portion 80 present within the base electrode layer 50. In addition, the proportion of the non-metal portions 80 present in the base electrode layer 50 is calculated.

[0082] The area of ​​the non-metallic portion 80 is calculated based on a binarized image obtained by binarizing a backscattered electron image. 2 If the value is less than 2.0 μm, it may be noise rather than the non-metallic portion 80. Therefore, in order to eliminate the influence of noise, 2 Non-metallic parts less than 80 were excluded from the analysis.

[0083] For each non-metal portion 80, the circularity of the non-metal portion 80 is calculated based on the area of ​​the non-metal portion 80 and the circumference (length of the contour line) of the non-metal portion 80 using the following formula (1). Circularity = 4π × (area) / (perimeter) 2 …(1)

[0084] All non-metallic parts 80 (with an area of ​​2.0 μm as described above) identified in the analysis range of the backscattered electron images acquired at the four backscattered electron image acquisition positions R1, R2, R3, and R4 were analyzed. 2 A set of non-metallic portions 80 with a circularity of 0.4 or less among the non-metallic portions 80 with a circularity of 0.4 or less (excluding those with a value less than 0.4) is set as a first population. Based on the area of ​​each non-metallic portion 80 that makes up this first population, the average area of ​​the non-metallic portions 80 in the first population is calculated.

[0085] Based on the area of ​​the analysis range and the area of ​​the non-metallic portion 80, the proportion of the non-metallic portion 80 in the base electrode layer 50 is calculated using the following formula (2). Presence ratio of non-metallic parts (%) = (area of ​​non-metallic parts / area of ​​analysis range) × 100…(2)

[0086] The proportion of non-metallic portions 80 is calculated for each of the four analysis ranges (R1, R2, R3, R4), and the average value is calculated as the proportion of non-metallic portions 80 in this embodiment.

[0087] As described above, the measurement range for calculating the average area of ​​non-metallic portions 80 in the first population constituted by non-metallic portions 80 with a circularity of 0.4 or less is a collection of the above-mentioned four analysis ranges (R1, R2, R3, R4). Specifically, the measurement range is the portion on the first main surface TS1 side and the portion on the second main surface TS2 side of the first base electrode layer 50A and the second base electrode layer 50B that contact the inner layer portion 11 of the laminate 10. More specifically, the measurement range is the portion of the first base electrode layer 50A and the second base electrode layer 50B from the position in the stacking direction of the boundary between the inner layer portion 11 and the first main surface side outer layer portion 12 of the laminate 10 to a position 80 μm toward the center of the stacking direction of the laminate 10, and the portion from the position in the stacking direction of the boundary between the inner layer portion 11 and the second main surface side outer layer portion 13 of the laminate 10 to a position 80 μm toward the center of the stacking direction of the laminate 10.

[0088] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0089] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. Both the dielectric sheet for the dielectric layer 20 and the conductive paste for the internal electrode layer 30 contain a binder and a solvent. The binder and solvent may be known. The paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent have been added.

[0090] A conductive paste for the internal electrode layer 30 is printed on the dielectric sheet by, for example, screen printing or gravure printing using a printing plate patterned to have the shape of the internal electrode layer 30 of this embodiment. As a result, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0091] A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked to form a portion that will become the first main surface side outer layer portion 12 on the first main surface TS1 side. Dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed are stacked alternately in sequence on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed are stacked on top of this portion that will become the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is obtained.

[0092] Next, the laminated sheet is pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0093] The laminated block is then cut into individual pieces of a predetermined size to obtain a plurality of laminated chips, which may then be polished by barrel polishing or the like to round off corners and ridges.

[0094] Next, the laminated chip is fired to obtain the laminate 10. The firing temperature at this time depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably, for example, 900°C or higher and 1400°C or lower.

[0095] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. The baked layer can be formed by applying a conductive paste containing a glass component and a metal to the laminate 10 by a method such as dipping, and then performing a baking process. The temperature for the baking process at this time is preferably 700°C or higher and 900°C or lower.

[0096] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 10 with the fired layer.

[0097] The circularity of the non-metallic portion 80 present inside the base electrode layer 50 can be controlled by changing the shape and particle size distribution of the copper powder added to the conductive paste. The circularity of the non-metallic portion 80 improves when spherical copper powder is used and the particle size distribution of the copper powder is sharp. Conversely, the circularity of the non-metallic portion 80 decreases when flat copper powder is used and the particle size distribution of the copper powder is broad.

[0098] The average area of ​​the non-metallic portion 80 present inside the base electrode layer 50 can be controlled by changing the particle size and firing temperature of the copper powder and the glass component. The smaller the particle size of the copper powder and the glass component and the higher the firing temperature, the smaller the average area of ​​the non-metallic portion 80. Conversely, the larger the particle size of the copper powder and the glass component and the lower the firing temperature, the larger the average area of ​​the non-metallic portion 80.

[0099] The proportion of the non-metallic portion 80 in the base electrode layer 50 can be controlled by changing the amount of glass component added and the firing temperature. The greater the amount of glass component added and the lower the firing temperature, the higher the proportion of the non-metallic portion 80. Conversely, the less the amount of glass component added and the higher the firing temperature, the lower the proportion of the non-metallic portion 80. The conductive paste is composed of 50 vol% to 80 vol% copper powder, 5 vol% to 20 vol% glass component, and other solvents and resin components.

[0100] Thereafter, a plating layer is formed on the surface of the base electrode layer 50, which is made of a baked layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and an Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0101] When a conductive resin layer is provided, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably 100 ppm or less.

[0102] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0103] The configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 4B. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure as shown in Figures 7A, 7B, and 7C.

[0104] The multilayer ceramic capacitor 1 shown in FIG. 7A is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33, a second internal electrode layer 34, and a floating internal electrode layer 35 that is not extended to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in FIG. 7B is a triple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in FIG. 7C is a quadruple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as the floating internal electrode layers 35. By providing the floating internal electrode layers 35 as the internal electrode layers 30, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby achieving a high withstand voltage for the multilayer ceramic capacitor 1. It goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multi-row structure of four or more rows.

[0105] The multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or may be a multi-terminal type having many external electrodes.

[0106] In the above-described embodiment, a multilayer ceramic capacitor in which the dielectric layers 20 made of a dielectric ceramic are used as ceramic layers has been exemplified as the multilayer ceramic electronic component. However, the multilayer ceramic electronic component of the present disclosure is not limited to this. For example, the ceramic electronic component of the present disclosure can also be applied to various multilayer ceramic electronic components, such as piezoelectric components using piezoelectric ceramic as the ceramic layers and thermistors using semiconductor ceramic as the ceramic layers. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, and examples of semiconductor ceramics include spinel ceramics.

[0107] The multilayer ceramic capacitor 1 according to the embodiment described above provides the following advantages.

[0108] The multilayer ceramic capacitor 1 according to the embodiment includes a laminate 10 including dielectric layers 20 as a plurality of ceramic layers alternately stacked in a stacking direction T and internal electrode layers 30 as a plurality of internal conductor layers, and including a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first end face LS1 and a second end face LS2 facing a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing a width direction W perpendicular to the stacking direction T and the length direction L, and a pair of external electrodes 40 arranged spaced apart from each other at both ends in the length direction L of the laminate 10, and the internal electrode layer 30 serves as a first internal conductor layer drawn to the first end face LS1. and a second internal electrode layer 32 as a second internal conductor layer drawn to a second end face LS2, and the external electrode 40 has a first external electrode 40A including a first base electrode layer 50A connected to the first internal electrode layer 31, and a second external electrode 40B including a second base electrode layer 50B connected to the second internal electrode layer 32, wherein the first base electrode layer 50A and the second base electrode layer 50B have a metal portion 70 and a plurality of non-metal portions 80 present in the metal portion 70, and in a cross-sectional view perpendicular to the width direction W, the average area of ​​the non-metal portions 80 in a first population constituted by the non-metal portions 80 having a circularity of 0.4 or less is 10 μm 2 As described above, in a cross-sectional view perpendicular to the width direction, the abundance ratio of the non-metallic portion in the first base electrode layer and the second base electrode layer is 8.2% or more.

[0109] This provides the effect of alleviating stress from forces applied to the external electrodes, making it possible to provide a multilayer ceramic capacitor with high crack resistance.

[0110] In the multilayer ceramic capacitor 1 according to the embodiment, the first base electrode layer 50A and the second base electrode layer 50B are preferably baked layers.

[0111] This allows the first base electrode layer 50A and the second base electrode layer 50B to be formed by a relatively simple method compared to when they are formed by thin film formation methods such as sputtering, vapor deposition, etc. Furthermore, by forming the baked layer simultaneously with firing the laminate 10, the manufacturing process can be simplified.

[0112] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments. [Example]

[0113] Examples are described below. Multiple lots of multilayer ceramic capacitors were fabricated using the manufacturing method described in the above embodiment, with the average area of ​​the non-metallic portions in the first population in the base electrode layer being different values, as samples of Examples 1 to 6 and a comparative example. Examples 1 to 6 are multilayer ceramic capacitors that satisfy the present invention, while the comparative example is a multilayer ceramic capacitor outside the present invention. Samples from the same lot were fabricated under the same manufacturing conditions, and the specifications of the base electrode layer were the same. 72 samples were fabricated for each lot (Examples 1 to 6 and the comparative example). Next, the fabricated samples of Examples 1 to 6 and the comparative example were subjected to a weight drop test. The weight drop test was performed using a configuration as shown in FIG. 8, and was a test to determine whether or not they could withstand mechanical stress. FIG. 8 is a schematic diagram for explaining the weight drop test in the examples. The weight drop test will be described later. Furthermore, 10 samples prepared separately from the samples for the weight drop test and manufactured in the same lot as the samples of Examples 1 to 6 and the Comparative Example were polished, and parameters such as the average area of ​​the non-metallic parts in the first population were measured using the above-mentioned measurement method.

[0114] In manufacturing, each sample was prepared according to the following specifications.

[0115] - Dimensions of multilayer ceramic capacitor: L×W×T=1.6mm×0.8mm×0.8mm Dielectric layer: BaTiO3 ·Capacity: 10μF Rated voltage: 25V Base electrode layer: Electrode containing conductive metal (Cu) and glass components (thickness of the base electrode layer placed on each of the first and second end faces: 36 μm) Plated layer: Two layers formed: Ni plated layer (2 μm) and Sn plated layer (4 μm) ·Internal electrode layer: Ni

[0116] The measurement results for the average area of ​​the non-metallic portions in the first population and the proportion of the non-metallic portions in the base electrode layer for the samples of Examples 1 to 6 and the Comparative Example are shown in Table 1. Note that these measurement results are the average values ​​for 10 samples prepared in addition to the 72 samples tested above.

[0117] First, as shown in Figure 8, a sample multilayer ceramic capacitor 1 is fixed with a fixture G on a steel stand D, and a weight W is dropped onto the multilayer ceramic capacitor under the following conditions: The weight W is dropped onto the external electrodes on the end faces of the laminate. After the test, the capacitor is checked for internal cracks. Weight: 6g (3.1mm diameter x 100.4mm length cylindrical stainless steel rod) Weight drop height: 4.8mm Crack observations were performed by starting polishing from the first or second side of the multilayer ceramic capacitor, exposing the LT cross section each time, and observing under a microscope from the point where the internal electrode layers began to be exposed until they finished. The number of cracks was counted, distinguishing between those with cracks in the effective portion and those with cracks but no cracks extending to the effective portion. The results are shown in Table 1.

[0118] [Table 1]

[0119] According to Table 1, as is clear from the comparative example, the average area of ​​the non-metallic portion in the first population is 10 μm 2 On the other hand, as in Examples 1 to 6, when the average area of ​​the non-metallic part in the first population is 10 μm 2 If the average area of ​​the non-metallic portion in the first population is 10 μm or more, there will be no cracks reaching the effective portion and the crack resistance will be good. 2 In order to ensure crack resistance, it is preferable that the proportion of non-metallic parts in the first population is 8.2% or more, similarly to the average area, in order to ensure crack resistance.

[0120] In Example 1, no samples were found to have cracks that reached the effective portion and were found to have NG crack resistance, but cracks that did not reach the effective portion were found. Therefore, the average area of ​​the non-metallic portion in the first population was 10.5 μm 2 It can be said that the presence ratio of the non-metallic portion in the first population is more preferably 11% or more.

[0121] For example, the average area of ​​the non-metallic portions constituting the first population is preferably 10 μm 2 More than 23μm 2 More preferably, 10.5 μm or less. 2 More than 23μm 2 This improves crack resistance.

[0122] The content of the non-metallic portion in the base electrode layer is preferably 8.2% to 25%. For example, the content of the non-metallic portion in the base electrode layer is preferably 11% to 25%.

[0123] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments. [Explanation of symbols]

[0124] 1. Multilayer ceramic capacitors (multilayer ceramic electronic components) 10 Laminate 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 31 First internal electrode layer (first internal conductor layer) 32 Second internal electrode layer (second internal conductor layer) 40 External electrode 40A First outer electrode 40B Second external electrode 50 Base electrode layer 50A First base electrode layer 50B Second base electrode layer 70 Metal Parts 80 Non-metallic parts L lengthwise T Stacking direction W width direction LS1 First end face LS2 Second end face TS1 First principal surface TS2 Second principal surface WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate including a plurality of ceramic layers and a plurality of internal conductor layers alternately stacked in a stacking direction, and including a first main surface and a second main surface opposing each other in the stacking direction, a first end face and a second end face opposing each other in a length direction perpendicular to the stacking direction, and a first side face and a second side face opposing each other in a width direction perpendicular to the stacking direction and the length direction; a pair of external electrodes disposed at a distance from each other at both longitudinal ends of the laminate, The internal conductor layer is a first internal conductor layer extending to the first end face; a second internal conductor layer extending to the second end surface, The external electrode is a first external electrode including a first base electrode layer connected to the first internal conductor layer; a second external electrode including a second base electrode layer connected to the second internal conductor layer, the first base electrode layer and the second base electrode layer each have a metal portion and a plurality of non-metal portions present in the metal portion; In a cross-sectional view perpendicular to the width direction, The average area of ​​the non-metallic portions in the first population constituted by the non-metallic portions having a circularity of 0.4 or less is 10 μm ２ That's all, In a cross-sectional view perpendicular to the width direction, the proportion of the non-metallic portion in the first base electrode layer and the second base electrode layer is 8.2% or more.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein the first and second base electrode layers are baked layers.

Images