Cache device, storage device, control method and program

Abstract

To operate a cache memory effectively. [Solution] The cache device comprises a cache memory that temporarily stores data, a host control unit that controls the input and output of data between a host and the cache memory, a storage control unit that controls the input and output of data between a storage that permanently stores data and the cache memory, and a cache control unit that controls the storage operation of the cache memory, and the cache control unit estimates the total free space of each of multiple partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period, and if data is written that exceeds the upper limit of the partition, it raises the upper limit within the range of the estimated free space.

Description

[Technical Field]

[0001] The present disclosure relates to a cache device, a storage device, a control method, and a program. [Background technology]

[0002] Patent Document 1 describes the following cache device that aims to quickly restore free space in a segment that has become low on free space. That is, the cache device described in Patent Document 1 maintains a list of dirty data stored in cache segments that are obtained by dividing the cache memory, and performs write-back processing preferentially on dirty data stored in segments with little remaining usable capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-153030 Summary of the Invention [Problem to be solved by the invention]

[0004] The cache device described in Patent Document 1 is effective in quickly recovering free space when, for example, logical disks in a physical disk group are allocated across multiple segments. However, this is not effective when logical disks are allocated to the same segment. In other words, there is a problem in that the cache memory may not operate effectively.

[0005] An object of the present disclosure is to provide a cache device, a storage device, a control method, and a program that solve the above-mentioned problems. [Means for solving the problem]

[0006] A cache device according to one aspect of the present disclosure comprises a cache memory that temporarily stores data, a host control unit that controls the input and output of data between a host and the cache memory, a storage control unit that controls the input and output of data between a storage that permanently stores data and the cache memory, and a cache control unit that controls the storage operation of the cache memory, wherein the cache control unit estimates the combined free space of each of multiple partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period, and when data is written that exceeds the upper limit of the partition, raises the upper limit within the range of the estimated free space.

[0007] A storage device according to one aspect of the present disclosure comprises a cache memory for temporarily storing data, a host control unit for controlling the input and output of data between a host and the cache memory, a storage for permanently storing data, a storage control unit for controlling the input and output of data between the storage and the cache memory, and a cache control unit for controlling the storage operation of the cache memory, wherein the cache control unit estimates the total free space of each of multiple partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period, and when data is written that exceeds the upper limit of the partition, raises the upper limit within the range of the estimated free space.

[0008] A control method according to one aspect of the present disclosure is a control method for a cache device comprising: a cache memory for temporarily storing data; a host control unit for controlling input / output of data between a host and the cache memory; a storage control unit for controlling input / output of data between a storage for permanently storing data and the cache memory; and a cache control unit for controlling the storage operation of the cache memory, and includes a step of estimating the total free space of each of a plurality of partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period; and a step of, when data is written that exceeds the upper limit amount of the partition, raising the upper limit amount within the range of the estimated free space.

[0009] A program according to one aspect of the present disclosure is a control program for a cache device that includes a cache memory that temporarily stores data, a host control unit that controls the input and output of data between a host and the cache memory, a storage control unit that controls the input and output of data between a storage that permanently stores data and the cache memory, and a cache control unit that controls the storage operation of the cache memory, and causes a computer to execute the steps of estimating the total free space of each of multiple partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period, and, when data is written that exceeds the upper limit of the partition, raising the upper limit within the range of the estimated free space. [Effects of the Invention]

[0010] According to the above aspect, the cache memory can be operated effectively. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a configuration diagram of a storage device according to the present disclosure. [Figure 2] FIG. 1 is a schematic diagram illustrating a storage device according to the present disclosure. [Figure 3] FIG. 10 is a schematic diagram illustrating an example of the operation of the storage device according to the present disclosure. [Figure 4] FIG. 10 is a diagram illustrating an example of the configuration of a time-slot data management table according to the present disclosure. [Figure 5] FIG. 10 is a diagram illustrating an example of a time-zone data management table according to the present disclosure. [Figure 6] FIG. 10 is a schematic diagram illustrating an example of the operation of a cache memory according to the present disclosure. [Figure 7] FIG. 10 is a schematic diagram illustrating an example of the operation of a cache memory according to the present disclosure. [Figure 8] FIG. 10 is a schematic diagram illustrating an example of the operation of a cache memory according to the present disclosure. [Figure 9]10 is a flowchart illustrating an example of the operation of the storage device according to the present disclosure. [Figure 10] 10 is a flowchart illustrating an example of the operation of the storage device according to the present disclosure. [Figure 11] FIG. 1 is a configuration diagram of a cache device according to the present disclosure. [Figure 12] 10 is a flowchart illustrating an example of the operation of a cache device according to the present disclosure. [Figure 13] FIG. 1 is a block diagram illustrating an example of a schematic configuration of a computer according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] Each embodiment will be described below with reference to the drawings. In all drawings, the same or corresponding components are designated by the same reference numerals, and common descriptions will be omitted.

[0013] Fig. 1 shows an example of the configuration of an embodiment of a storage device according to the present disclosure. Fig. 1 shows a storage device 2 accessed by one or more host computers 1. The host computer 1 and storage device 2 are connected via a predetermined communication line, and the host computer 1 writes data to the storage device 2 and reads data from the storage device 2. The storage device 2 is also connected to a management server 10 via the predetermined communication line, and the configuration and settings of the storage device 2 can be changed by the management server 10.

[0014] The storage device 2 includes a disk enclosure 9 and a storage controller 3. The disk enclosure 9 controls multiple physical disks 20 and permanently stores data. The storage controller 3 operates under program control and controls the storage operation of the cache memory 5. The disk enclosure 9 houses multiple physical disks 20 and also includes an interface and control circuitry that connects a disk interface 6 to the multiple physical disks 20. The physical disks 20 are nonvolatile storage devices such as hard disk drives (HDDs) and solid-state drives (SSDs). Data input / output between the disk enclosure 9 (or multiple physical disks 20) and the disk interface 6 is controlled in units of physical disk groups (RANKs) that make up a redundant array of inexpensive disks (RAID). In the following explanation, data input / output is also referred to as I / O (Input / Output).

[0015] The storage controller 3 includes a host interface 4, a cache memory 5, a disk interface 6, a microprocessor 7, and a control memory 8. The host interface 4 controls I / O between the host computer 1 and the cache memory 5 under the control of the microprocessor 7. The cache memory 5 has a storage area for temporarily storing data. The microprocessor 7 divides the storage area of ​​the cache memory 5 into multiple segments and controls data for each segment. The disk interface 6 controls I / O between the disk enclosure 9 and the cache memory 5 under the control of the microprocessor 7. The control memory 8 is used by the microprocessor 7 to, for example, present multiple physical disks 20 to the host computer 1 as one or multiple logical disks. The control memory 8 also divides the cache memory 5 into multiple segments (cache segments) for management and stores segment management memory 8a for accumulating load information. In this embodiment, the load information represents the load on the storage device 2, and includes, for example, information representing the capacity of unused space in each segment for each specified time period and information representing the capacity of dirty data in each segment for each specified time period.

[0016] In this embodiment, the microprocessor 7 includes functional blocks configured by a combination of software and hardware, such as a segment setting unit 71, a usage status monitoring unit 72, a free space monitoring unit 73, and an estimated free space calculation unit 74. In this embodiment, the microprocessor 7 estimates the total free space of each segment, which is obtained by dividing the cache memory 5, based on the past usage status of each segment during the same time period. Also, in this embodiment, if data is written that exceeds the upper limit of the segment, the microprocessor 7 increases the upper limit within the range of the estimated free space. Note that, hereinafter, it is assumed that the control of the storage operation of the cache memory 5 (control by existing methods) other than the control and operations performed by the segment setting unit 71, usage status monitoring unit 72, free space monitoring unit 73, and estimated free space calculation unit 74 is mainly performed by the microprocessor 7.

[0017] The segment setting unit 71 sets the segments by dividing the storage area of ​​the cache memory 5 as follows. Figure 2 shows an example of the configuration of the cache memory 5, in which the cache memory 5 is divided into three segments SG1, SG2, and SG3. Segments are collectively referred to as segments SG. One or more logical disks 11 can be assigned to each segment SG. In this embodiment, by associating a logical disk 11 with a segment SG, when a write from the host computer 1 occurs to a specific logical disk 11, the use of the entire cache memory 5 is restricted, preventing interference with logical disks 11 associated with other segments SG. Each segment SG can also be assigned a maximum usable capacity. To avoid interference, the total maximum capacity of the segments SG must typically be less than the total capacity of the cache memory 5. Note that the segments SG are not completely separated by physical addresses; rather, they are managed by their maximum usage capacity and share the same physical addresses. While an example with three segments SG is shown here, the number of segments SG may be two, four, or more. The segment setting unit 71 dynamically changes the upper limit of each segment SG based on, for example, the amount of dirty data in each segment SG and the estimated capacity of unused space calculated by the estimated free space calculation unit 74. For example, when data exceeding the upper limit of a segment SG is written, the segment setting unit 71 raises the upper limit within the range of free space estimated by the estimated free space calculation unit 74.

[0018] Here, we will explain how the data on the segment SG shown in Fig. 3 increases and decreases, and the data stored in the time slot data management table SCT shown in Fig. 4. In Fig. 3, state (ST0) indicates the state before data is written to the segment SG in state (ST1).

[0019] State (ST1) shows how data is written from the host computer 1. Data written to the cache 5 that has not been synchronized to the physical disk 20 is called dirty data. As the number of writes (write receptions) from the host computer 1 increases, the amount of dirty data on the segment SG increases.

[0020] State (ST2) shows how dirty data is written back to the physical disk 20. The write back is performed asynchronously with the writing from the host computer 1, and the dirty data written back to the physical disk 20 can be deleted from the cache 5.

[0021] State (ST3) is the state of segment SG when the capacity of unused space in a specified time period is at its minimum. The usage status monitoring unit 72 shown in FIG. 1 stores the capacity of segment SG when the capacity of unused space in a specified time period is at its minimum as load information for each segment SG in the segment management memory 8a, for example, in the form of a time period data management table SCT as shown in FIG. 4. The amount of dirty data increases or decreases depending on the amount of data written from the host computer 1 and the amount of data flushed to the physical disk 20. The usage status monitoring unit 72 continuously records the capacity of unused space in a certain time period at its minimum for each segment.

[0022] The time-slot data management table SCT shown in Fig. 4 stores the minimum unused capacity for each segment SG for each time slot. The usage status monitoring unit 72 stores data, for example, permanently, as this time-slot data management table SCT. In the example shown in Fig. 4, the time-slot data management table SCT is stored every hour, but it is also possible to record data at other time intervals, such as every minute.

[0023] The free space monitoring unit 73 monitors the free space (the capacity of unused areas) in the cache memory 5 and in each segment SG.

[0024] The estimated free space calculation unit 74 refers to the time-slot data management table SCT and estimates the total free space of each segment SG based on the past usage status during the same time slot for each of the multiple segments SG into which the cache memory 5 is divided. Furthermore, the estimated free space calculation unit 74 increases or decreases the free space when the free space changes due to data writing or write-back.

[0025] 5 to 8, an image of using the cache memory 5 by increasing the upper limit capacity of the segment SG based on the time period data management table SCT shown in Fig. 5 is shown. The time period data management table SCT shown in Fig. 5 shows an example in which the unused area capacities of the four segments SG0 to SG4 are 200, 700, 400, and 300 MB (total of 1600 MB) from time 00:00 to 00:59.

[0026] Figure 6 shows the cache capacity that was unused during a time period based on the information in the past time-slot-based data management table SCT shown in Figure 5. If the same operation were performed, it is expected that at least 1600 MB of unused space would be unused, calculated by adding up all unused space. This capacity is the estimated free space. Furthermore, for each segment SG, the value obtained by subtracting the estimated capacity of the unused space from the upper limit is the maximum estimated value for the capacity of dirty data.

[0027] Figure 7 shows a situation where a write operation that exceeds the upper limit has occurred in segment #0 (SG0). When the upper limit is exceeded, it is estimated that there is 1,400 MB (= 1,600 MB - 200 MB) of unused space in segment #1 (SG1), segment #2 (SG2), and segment #3 (SG3), and this space can be used. The past data used for estimation can be selected from data such as the previous day, the same day of the week last week, or the Xth day of the week last month (where X is an integer between 1 and 5). This allows the past time zone data management table SCT to be used in accordance with the system's date and time processing, weekly processing, and monthly processing.

[0028] Figure 8 shows a state in which free space has been used in segment #1 (SG1) other than segment #0 (SG0) beyond the estimated maximum amount of dirty data. When the maximum amount of dirty data estimated for each segment is exceeded, the excess amount is managed and subtracted from the estimated free space. This provides a guard against further use of free space if the actual estimated free space is small.

[0029] FIG. 9 shows a flow when a write is made from the host computer 1. The process shown in FIG. 9 starts when a write is made from the host computer 1. When the microprocessor 7 receives a write request from the host computer 1 to the logical disk 11 (step S1), the estimated free space calculation unit 74 determines whether the free space update condition is met (step S2). The estimated free space update condition is a condition that the time-slot-specific data management table SCT being referenced needs to be updated. The update condition is met when the time slot changes. When the estimated free space update condition is met (step S2: Yes), the estimated free space calculation unit 74 calculates the estimated free space as follows (step S3). In step S3, the estimated free space calculation unit 74 first references the time-slot-specific data management table SCT corresponding to the current time slot or multiple time-slot-specific data management tables SCT corresponding to the current time slot. Next, the estimated free space calculation unit 74 calculates the estimated minimum unused space capacity for each segment SG in the current time slot using the referenced value or the minimum or average value in the multiple time-slot-specific data management tables SCT. Next, the estimated free space calculation unit 74 calculates the estimated free space by adding up the estimated capacities of the smallest unused areas for each segment. Next, the estimated free space calculation unit 74 acquires information indicating the current free space of each segment SG from the free space monitoring unit 73, compares the sum of the current free spaces of each segment SG with the estimated free space, and sets the smaller value as the estimated free space. In this way, the estimated free space is calculated in step S3.

[0030] If the condition in step S2 is not met (step S2: No), or after step S3, the segment setting unit 71 determines whether the write has exceeded the upper limit of the segment SG allocated to the logical disk 11 (step S4). If the upper limit has not been exceeded (step S4: No), the segment setting unit 71 further determines whether the write will use the estimated free space (step S10). If the write will not use the estimated free space (step S10: No), the microprocessor 7 receives the write data as is (step S9). If the write will use the estimated free space (step S10: Yes), the estimated free space calculation unit 74 subtracts the write capacity from the estimated free space (step S8), and then the microprocessor 7 receives the write data (step S9).

[0031] If the upper limit is exceeded (step S4: Yes), and if there is free space in the cache 5 and there is also estimated free space (step S5: Yes), the segment setting unit 71 changes the upper limit of the segment SG (step S7), the estimated free space calculation unit 74 subtracts the amount exceeding the upper limit from the estimated free space (step S8), and the microprocessor 7 receives the write data (step S9). If there is no free space in the cache 5 or there is no estimated free space (step S5: No), the microprocessor 7 waits for free space (step S6).

[0032] 10 shows a flow when write-back to the physical disk 20 is completed and data is discarded. In the process shown in FIG. 10, when the microprocessor 7 discards the data (step S21), if there is no dirty data remaining in the target segment SG in the estimated free space (step S22: No), the microprocessor 7 simply ends the process. If there is dirty data remaining (step S22: Yes), the estimated free space calculation unit 74 increases the estimated free space by the amount of data that was written back (step S23).

[0033] As described above, according to this embodiment, by utilizing the past usage status of each segment (cache segment) SG, if it is estimated that there is room in the cache 5, writing beyond the cache usage upper limit is permitted. This makes it possible to process without I / O delays or write-back wait times even if there is a sudden increase in write I / O to a segment SG with little remaining available capacity. Furthermore, by using data from the same past time period, it is possible to allocate the cache 5 in a way that is suited to the business operations of each time period.

[0034] The storage controller 3 of this embodiment includes a host interface 4, a cache memory 5, a disk interface 6, and a microprocessor 7. The cache memory 5 temporarily stores data. The host interface 4 controls the input and output of data between the host computer 1 and the cache memory 5. The disk interface 6 controls the input and output of data between the cache memory 5 and a disk enclosure 9 that permanently stores data. The microprocessor 7 controls the storage operation of the cache memory 5. The microprocessor 7 also estimates the total free space of each segment SG, into which the cache memory 5 is divided, based on the past usage status of each segment SG during the same time period. If data is written that exceeds the upper limit of a segment SG, the microprocessor 7 raises the upper limit within the range of the estimated free space. This configuration allows the cache memory 5 to operate effectively.

[0035] The usage status indicates the minimum unused capacity for each predetermined time period. With this configuration, the estimated free space can be estimated based on the minimum unused capacity for each segment for each predetermined time period.

[0036] Furthermore, the segment SG is used in units of one or more logical disks 11 set in the disk enclosure 9 (or physical disk 20). According to this configuration, the segment SG can be set, managed, and operated in units of logical disks 11.

[0037] Furthermore, each segment SG shares the same physical address of the cache memory 5 and is divided by setting an upper limit amount for each segment SG. According to this configuration, the cache memory 5 can be divided by sharing the same physical address of the cache memory 5 and setting an upper limit amount for each segment SG.

[0038] The storage device 2 of this embodiment includes a disk enclosure 9 (or a physical disk 20) ​​and a storage controller 3. This configuration allows the cache memory 5 to operate effectively.

[0039] Next, another embodiment of the present disclosure will be described with reference to FIGS. 11 and 12. FIG. 11 is a configuration diagram of a cache device according to the present disclosure. The cache device 100 shown in FIG. 11 includes a cache memory 101, a host control unit 102, a storage control unit 103, and a cache control unit 104. The cache memory 101 temporarily stores data. The host control unit 102 controls data input / output between the host and the cache memory 101. The storage control unit 103 controls data input / output between the cache memory 101 and storage that permanently stores data. The cache control unit 104 controls the storage operation of the cache memory 101. The cache control unit 104 also estimates the total free space of each partition based on the past usage status of each partition during the same time period, which is obtained by dividing the cache memory 101. If data is written that exceeds the upper limit of the partition, the cache control unit 104 raises the upper limit within the range of the estimated free space.

[0040] The correspondence between the components in this embodiment and the embodiment shown in FIG. 1 is as follows: The cache device 100 of this embodiment corresponds to the storage controller 3 shown in FIG. 1. The cache memory 101 of this embodiment corresponds to the cache memory 5 shown in FIG. 1. The host control unit 102 of this embodiment corresponds to the host interface 4 shown in FIG. 1. The storage control unit 103 of this embodiment corresponds to the disk interface 6 shown in FIG. 1. The cache control unit 104 of this embodiment corresponds to the microprocessor 7 shown in FIG. 1. The host of this embodiment corresponds to the host computer 1 shown in FIG. 1. The storage of this embodiment corresponds to the disk enclosure 9 (or one or more physical disks 20) shown in FIG. 1. The partition of this embodiment corresponds to the segment (cache segment) SG shown in FIG. 1. The estimated free space of this embodiment corresponds to the estimated free space calculated by the estimated free space calculation unit 74 shown in FIG. 1.

[0041] Fig. 12 is a flowchart showing an example of the operation of the cache device 100 shown in Fig. 11. In the process (control method of the cache device 100) shown in Fig. 12, first, the total free space of each partition, into which the cache memory 101 is divided, is estimated based on the past usage status of each partition during the same time period (step S101). Next, if data is written that exceeds the upper limit of the partition, the upper limit is raised within the range of the estimated free space (step S102).

[0042] <Computer configuration> 13 is a block diagram showing a schematic configuration example of a computer according to an embodiment of the present disclosure. The computer 700 includes a CPU (Central Processing Unit) 710, a main memory device 720, an auxiliary memory device 730, and an interface 740. A non-volatile memory medium 750, for example, is connected to the interface 740. The microprocessor 7 described above is implemented in the computer 700. The operation of each of the processing units (functional blocks) described above is stored in the auxiliary memory device 730 in the form of a program. The CPU 710 reads the program from the auxiliary memory device 730, loads it into the main memory device 720, and executes the above-described processing in accordance with the program. The CPU 710 also allocates storage areas in the main memory device 720 corresponding to each of the storage units described above in accordance with the program.

[0043] The program may be for realizing some of the functions to be performed by the computer 700. For example, the program may be combined with other programs already stored in the auxiliary storage device 730 or other programs implemented in other devices to perform the functions. In other embodiments, the computer may include a custom LSI (Large Scale Integrated Circuit) such as a PLD (Programmable Logic Device) in addition to or instead of the above configuration. Examples of PLDs include PAL (Programmable Array Logic), GAL (Generic Array Logic), CPLD (Complex Programmable Logic Device), and FPGA (Field Programmable Gate Array). In this case, some or all of the functions realized by the CPU 710 may be realized by the integrated circuit.

[0044] Examples of auxiliary storage device 730 include a hard disk drive (HDD), a solid state drive (SSD), a magnetic disk, a magneto-optical disk, a compact disc read-only memory (CD-ROM), a digital versatile disc read-only memory (DVD-ROM), and semiconductor memory. Auxiliary storage device 730 may be internal media directly connected to the bus of computer 700, or may be external media connected to computer 700 via interface 740 or a communication line. Furthermore, if this program is distributed to computer 700 via a communication line, computer 700 that receives the program may load the program into main storage device 720 and execute the above-described processing. In at least one embodiment, auxiliary storage device 730 is a non-transitory tangible storage medium.

[0045] Although the present disclosure has been described above with reference to the embodiments, the present disclosure is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration and details of the present disclosure within the scope of the present disclosure.

[0046] Some or all of the above embodiments can be described as, but are not limited to, the following supplementary notes.

[0047] (Appendix 1) a cache memory for temporarily storing data; a host control unit that controls input and output of data between a host and the cache memory; a storage control unit that controls input and output of data between a storage that permanently stores data and the cache memory; a cache control unit that controls a storage operation of the cache memory; Equipped with The cache control unit estimates the total free space of each of a plurality of partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period, and when data is written that exceeds the upper limit of the partition, raises the upper limit within the range of the estimated free space. Cache device.

[0048] (Appendix 2) The usage status indicates the minimum unused area capacity per predetermined time. 2. The cache device of claim 1.

[0049] (Appendix 3) The partition is used in units of one or more logical disks set in the storage. 3. The cache device of claim 1 or 2.

[0050] (Appendix 4) The partitions share the same physical address of the cache memory, and are divided by setting an upper limit amount for each partition. 4. The cache device according to claim 1, wherein the cache device is a

[0051] (Appendix 5) a cache memory for temporarily storing data; a host control unit that controls input and output of data between a host and the cache memory; storage for persistently storing data; a storage control unit that controls input and output of data between the storage and the cache memory; a cache control unit that controls a storage operation of the cache memory; Equipped with The cache control unit estimates the total free space of each of a plurality of partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period, and when data is written that exceeds the upper limit of the partition, raises the upper limit within the range of the estimated free space. Storage device.

[0052] (Appendix 6) The usage status indicates the minimum unused area capacity per predetermined time. 6. The storage device of claim 5.

[0053] (Appendix 7) The partition is used in units of one or more logical disks set in the storage. 7. The storage device according to claim 5 or 6.

[0054] (Appendix 8) The partitions share the same physical address of the cache memory, and are divided by setting an upper limit amount for each partition. 8. The storage device according to any one of appendices 5 to 7.

[0055] (Appendix 9) a cache memory for temporarily storing data; a host control unit that controls input and output of data between a host and the cache memory; a storage control unit that controls input and output of data between a storage that permanently stores data and the cache memory; a cache control unit that controls a storage operation of the cache memory; A method for controlling a cache device comprising: a step of estimating a total free space of each of a plurality of partitions obtained by dividing the cache memory based on a past usage status of each of the partitions during the same time period; a step of raising the upper limit amount within the range of the estimated free space when data is written that exceeds the upper limit amount of the partition; A control method comprising:

[0056] (Appendix 10) The usage status indicates the minimum unused area capacity per predetermined time. 10. The control method of claim 9.

[0057] (Appendix 11) The partition is used in units of one or more logical disks set in the storage. 11. The control method according to claim 9 or 10.

[0058] (Appendix 12) The partitions share the same physical address of the cache memory, and are divided by setting an upper limit amount for each partition. A control method according to any one of Supplementary Notes 9 to 11.

[0059] (Appendix 13) a cache memory for temporarily storing data; a host control unit that controls input and output of data between a host and the cache memory; a storage control unit that controls input and output of data between a storage that permanently stores data and the cache memory; a cache control unit that controls a storage operation of the cache memory; A control program for a cache device comprising: a step of estimating a total free space of each of a plurality of partitions obtained by dividing the cache memory based on a past usage status of each of the partitions during the same time period; a step of raising the upper limit amount within the range of the estimated free space when data is written that exceeds the upper limit amount of the partition; A program that causes a computer to execute the following.

[0060] (Appendix 14) The usage status indicates the minimum unused area capacity per predetermined time. 13. The program described in Appendix 13.

[0061] (Appendix 15) The partition is used in units of one or more logical disks set in the storage. 15. The program of claim 13 or 14.

[0062] (Appendix 16) The partitions share the same physical address of the cache memory, and are divided by setting an upper limit amount for each partition. A program according to any one of Appendices 13 to 15. [Explanation of symbols]

[0063] 1. Host Computer 2. Storage devices 3 Storage Controllers 4 Host Interface 5, 101 cache memory 6 Disk Interface 7 Microprocessors 8 Control Memory 9 Disk Enclosures 10 physical disks 11 Logical Disks SG Segment 100 Cache Device 102 Host control unit 103 Storage control section 104 Cache control unit

Claims

1. a cache memory for temporarily storing data; a host control unit that controls input and output of data between a host and the cache memory; a storage control unit that controls input and output of data between a storage that permanently stores data and the cache memory; a cache control unit that controls a storage operation of the cache memory; Equipped with The cache control unit estimates the total free space of each of a plurality of partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period, and when data is written that exceeds the upper limit of the partition, raises the upper limit within the range of the estimated free space. Cache device.

2. The usage status indicates the minimum unused area capacity per predetermined time. The cache device according to claim 1 .

3. The partition is used in units of one or more logical disks set in the storage.

3. The cache device according to claim 2.

4. The partitions share the same physical address of the cache memory, and are divided by setting an upper limit amount for each partition. The cache device according to any one of claims 1 to 3.

5. a cache memory for temporarily storing data; a host control unit that controls input and output of data between a host and the cache memory; storage for persistently storing data; a storage control unit that controls input and output of data between the storage and the cache memory; a cache control unit that controls a storage operation of the cache memory; Equipped with The cache control unit estimates the total free space of each of a plurality of partitions into which the cache memory is divided based on the past usage status of each of the partitions during the same time period, and when data is written that exceeds the upper limit of the partition, raises the upper limit within the range of the estimated free space. Storage device.

6. a cache memory for temporarily storing data; a host control unit that controls input and output of data between a host and the cache memory; a storage control unit that controls input and output of data between a storage that permanently stores data and the cache memory; a cache control unit that controls a storage operation of the cache memory; A method for controlling a cache device comprising: a step of estimating a total free space of each of a plurality of partitions obtained by dividing the cache memory based on a past usage status of each of the partitions during the same time period; a step of raising the upper limit amount within the range of the estimated free space when data is written that exceeds the upper limit amount of the partition; A control method comprising:

7. a cache memory for temporarily storing data; a host control unit that controls input and output of data between a host and the cache memory; a storage control unit that controls input and output of data between a storage that permanently stores data and the cache memory; a cache control unit that controls a storage operation of the cache memory; A control program for a cache device comprising: a step of estimating a total free space of each of a plurality of partitions obtained by dividing the cache memory based on a past usage status of each of the partitions during the same time period; a step of raising the upper limit amount within the range of the estimated free space when data is written that exceeds the upper limit amount of the partition; A program that causes a computer to execute the following.

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