Semiconductor Devices

Abstract

To provide a disconnection detection circuit capable of suitably inspecting the connection state of a wire without increasing parasitic capacitance.SOLUTION: A semiconductor device 100 includes a first integrated circuit 110 including a transformer including a primary coil 111 and a secondary coil 112, and a second integrated circuit 120 connected to the secondary coil 112 in one package. The second integrated circuit 120 has a reference line 123 and a detection circuit 130. The reference line 123 connects a midpoint P10 of the secondary coil 112 and a preset reference potential portion G1. The detection circuit 130 detects whether the connection state of the wire connected from the first power supply line 131 to the reference line 123 via the secondary coil 112 is normal or abnormal on the basis of a first power line 131 that connects the first constant current source 133 and the end of the secondary coil 112 and the potential at a predetermined reference point P11 of the first power line 131.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In integrated circuits, there are circuits that detect broken wire bonds.

[0003] For example, Patent Document 1 discloses a wire break detection circuit having a switch that sets a detection signal to be supplied to a signal line and a resistor that supplies the detection signal set by the switch to the signal line. This wire break detection circuit has control means that controls the switch to set the detection signal to be supplied to the signal line and determines whether or not the signal line is broken based on a change in the detection signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-240810 Summary of the Invention [Problem to be solved by the invention]

[0005] There are semiconductor devices that have a configuration in which multiple semiconductor chips are connected to each other by bonding wires within a package. In the case of semiconductor devices with such a configuration, it can be difficult to check the connection status of the bonding wires after assembly is complete. Furthermore, for example, in order to sensitively detect the connection status around the bonding using the above-mentioned technology, a large current must be passed through the detection circuit. However, if a circuit that can pass a large current is constructed, parasitic capacitance increases, making it incompatible with the original circuit specifications. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present disclosure includes a first integrated circuit including a transformer including a primary coil and a secondary coil, and a second integrated circuit connected to the secondary coil, all in a single package. The second integrated circuit includes a reference line and a detection circuit. The reference line connects the midpoint of the secondary coil to a preset reference potential. The detection circuit detects whether the connection state of a wire connecting a first power supply line connecting a constant current source to an end of the secondary coil and a wire connecting the first power supply line through the secondary coil to the reference line is normal or abnormal based on a reference potential at a predetermined reference point on the first power supply line. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to provide a disconnection detection circuit that can suitably inspect the connection state of a wire without increasing parasitic capacitance. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment; [Figure 2] FIG. 2 is a diagram illustrating an example of use of the semiconductor device according to the first embodiment. [Figure 3] FIG. 10 is a diagram illustrating a configuration of a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a diagram illustrating a configuration of a semiconductor device according to a third embodiment. [Figure 5] FIG. 10 is a diagram illustrating a configuration of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present invention will be described below through embodiments of the invention, but the invention according to the claims is not limited to the following embodiments. Furthermore, not all of the configurations described in the embodiments are necessarily essential means for solving the problems. For clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are assigned the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] <First Embodiment> Hereinafter, a first embodiment of the present disclosure will be described with reference to the drawings. Fig. 1 is a diagram showing a configuration of a semiconductor device 100 according to the first embodiment. Fig. 1 shows a state in which the semiconductor device 100 and an inspection system 20 are connected to each other and an inspection of the internal circuit of the semiconductor device 100 is performed.

[0011] The inspection system 20 inspects the connection state of a predetermined circuit in the semiconductor device 100. More specifically, for example, the inspection system 20 inspects the connection state between the first integrated circuit 110 and the second integrated circuit 120 in the semiconductor device 100. The inspection system 20 mainly comprises an external power supply 21 and a receiving unit 22.

[0012] The external power supply 21 supplies current to the second integrated circuit 120 of the semiconductor device 100. The receiving unit 22 is connected to the output line 137 of the detection circuit 130 of the semiconductor device 100, and receives the open circuit detection signal output by the detection circuit 130.

[0013] In addition to the above-described configuration, the inspection system 20 may include, for example, a circuit or a display device for outputting the inspection result in response to the signal received by the receiving unit 22. The inspection system 20 may also have a configuration for performing an inspection different from the above-described inspection. For example, the inspection system 20 may have a configuration for performing an inspection other than the above-described inspection related to the transformer included in the semiconductor device 100.

[0014] The semiconductor device 100 is a gate driver with an isolation function. The semiconductor device 100 includes, in a single package, a first integrated circuit 110 including an isolation transformer including a primary coil 111 and a secondary coil 112, and a second integrated circuit connected to the secondary coil 112. That is, the semiconductor device 100 mainly includes the first integrated circuit 110 and the second integrated circuit 120. The first integrated circuit 110 and the second integrated circuit 120 are connected by wire bonding within the package of the semiconductor device 100 via a first wire 101, a second wire 102, and a third wire 103.

[0015] The first wire 101 connects one end of the secondary coil 112 to a first signal line 121 of the second integrated circuit 120. The second wire 102 connects a branch line connected to a midpoint P10 of the secondary coil 112 to a second signal line 122 of the second integrated circuit 120. The third wire 103 connects the other end of the secondary coil 112 to a third signal line 124 of the second integrated circuit 120.

[0016] The first integrated circuit 110 has a transmitting circuit 113 connected to the primary coil 111, and a secondary coil 112 that forms a transformer (isolation transformer) adjacent to the primary coil 111. The transmitting circuit 113 receives a signal from outside the semiconductor device 100 and supplies a transmitting signal corresponding to the received signal to the primary coil 111. The secondary coil 112 has one end connected to the first wire 101, the other end connected to the third wire 103, and a midpoint P10 connected to the second wire 102.

[0017] The second integrated circuit 120 is connected to the first integrated circuit 110 via a first wire 101, a second wire 102, and a third wire 103. The second integrated circuit 120 generates and outputs a drive signal for driving, for example, an IGBT (Insulated Gate Bipolar Transistor) from a signal received from the first integrated circuit 110. The second integrated circuit 120 mainly includes a first signal line 121, a second signal line 122, a reference line 123, a third signal line 124, a receiving circuit 125, a gate driver circuit 126, and a detection circuit 130.

[0018] The first signal line 121 connects the first wire 101 and the receiving circuit 125. The first signal line 121 also has a contact A1 that connects to the first power supply line 131 of the detection circuit 130. The second signal line 122 connects the second wire 102 and the receiving circuit 125. The second signal line 122 also has a contact A2 with the reference line 123 and a contact A3 with the second power supply line 132 of the detection circuit 130. The third signal line 124 connects the third wire 103 and the receiving circuit 125. One end of the reference line 123 is connected to the second signal line 122 at contact A2, and the other end is connected to a reference potential portion G1. The reference potential portion G1 is set to a reference potential. The potential of the reference potential portion G1 is, for example, 0 V. Alternatively, the reference potential portion G1 can be said to be ground.

[0019] The receiving circuit 125 performs predetermined processing on the signal received from the secondary coil 112 and supplies the processed signal to the gate driver circuit 126. At this time, the receiving circuit 125 handles a differential signal of the signals supplied from the first wire 101 and the third wire 103, with the potential of the second wire 102 as a reference potential. This allows the semiconductor device 100 to process the transmission signal appropriately. The gate driver circuit 126 is configured to be able to output a predetermined drive signal to the outside of the semiconductor device 100 based on the processed signal received from the receiving circuit 125.

[0020] The detection circuit 130 detects whether the connection state of the wire connecting the first power supply line 131 to the reference line 123 via the secondary coil 112 is normal or abnormal. The detection circuit 130 mainly includes the first power supply line 131, the second power supply line 132, the first constant current source 133, the second constant current source 134, the reference resistor 135, the comparator 136, and the output line 137.

[0021] The first power supply line 131 receives a preset current from a first constant current source 133 and supplies this current to the first wire 101 via a contact A1 and a first signal line 121. The first power supply line 131 also has a reference point P11. A branch line extends from the reference point P11, and this branch line supplies a first input signal to a comparator 136.

[0022] The second power supply line 132 receives a preset current supply from a second constant current source 134 at one end, and is connected to the second signal line 122 at the other end, contact point A3, via a reference resistor 135. The contact point A3 is connected to the reference potential section G1 via the second signal line 122 and the reference line 123. Therefore, the potential at the contact point A3 of the second signal line 122 becomes the reference potential.

[0023] The second power supply line 132 is connected to the reference potential unit G1 via the second signal line 122 and the reference line 123. However, the configuration of the side of the second power supply line 132 opposite to the side connected to the second constant current source 134 is not limited to the above configuration as long as it is a configuration that provides the reference potential.

[0024] The reference resistor 135 is interposed between the second constant current source 134 and a contact point A3 on the second power supply line 132. The second power supply line 132 also has a reference point P12 between the second constant current source 134 and the reference resistor 135. A branch line extends from the reference point P12, and this branch line supplies a second input signal to the comparator 136.

[0025] The first constant current source 133 is a circuit that receives a current supplied from an external power source 21 provided outside the semiconductor device 100 and supplies a constant current to the first power supply line 131. The second constant current source 134 is a circuit that receives a current supplied from the external power source 21 provided outside the semiconductor device 100 and supplies a constant current to the second power supply line 132.

[0026] The comparator 136 receives as inputs a branch line of the first power supply line 131 branching at a reference point P11 and a branch line of the second power supply line 132 branching at a reference point P12, and compares the potential of the reference point P11, which is a first input signal, with the potential of the reference point P12, which is a second input signal. For example, the comparator 136 outputs an L level when the potential of the reference point P11 is less than the potential of the reference point P12. On the other hand, the comparator 136 outputs an H level when the potential of the reference point P11 is equal to or greater than the potential of the reference point P12. The output line 137 is a signal line for outputting the output signal of the comparator 136 to the outside. The output line 137 is connected to the receiving unit 22 of the inspection system 20.

[0027] In the above-described configuration, the detection circuit 130 has the following functions. When the inspection system 20 and the semiconductor device 100 are connected, the first constant current source 133 supplies a constant current to the first power supply line 131. This generates a predetermined voltage in the wire extending from the first power supply line 131 to the reference line 123. Here, the connection between the end of the secondary coil 112 and the first signal line 121, and the connection between the midpoint P10 and the second signal line 122 are each made via a bonding wire.

[0028] If the connection between the second wire 102 and the wire bonding connecting the second wire 102 is in a disconnected state, the resistance value of this portion will be relatively high. In such a disconnected state, the potential at the reference point P11 will be higher than the potential at the reference point P11 when the wire is not in a disconnected state. Therefore, the detection circuit 130 detects whether the connection of the wire connecting the first power supply line 131, through the secondary coil 112, to the reference line 123 is normal or abnormal based on the potential at the reference point P11 of the first power supply line 131.

[0029] In the following description, expressions such as "connection state," "disconnection," and "disconnection state" refer to the continuity state of the second wire 102 and the wire bonding that connects the second wire 102. Furthermore, "the connection state is normal" means that the above-mentioned continuity state is good, and "the connection state is abnormal" means that the above-mentioned continuity state is not good.

[0030] The detection circuit 130 will be further described below with specific examples. The first constant current source 133 supplies a current I1 to the first power line 131. The second constant current source 134 supplies a current I2 to the second power line 132. Let the resistance value of the second wire 102 be R1. In this case, if the potential at the reference point P11 is V11, then V11 is R1*I1. Similarly, if the resistance value of the reference resistor 135 on the second power line 132 is R2, then V12, which is the potential at the reference point P12, is R2*I2. When the second wire 102 is not broken, the resistance value R1 is sufficiently low. That is, in this case, R1 < R2*I2 / I1, and V11 is smaller than V12. Therefore, the comparator 136 outputs an L level.

[0031] On the other hand, when the second wire 102 is broken, the resistance value R1 becomes high. In this case, for example, R1 ≥ R2*I2 / I1, and V11 becomes greater than or equal to V12. Then the comparator 136 outputs an H level.

[0032] In this way, the detection circuit 130 compares the potential difference between the potential V11 at the reference point P11 and the potential V12 at the reference point P12, which is a predetermined position on the second power line 132. Thereby, when the connection state is normal, the detection circuit 130 outputs an L level, and when the connection state is abnormal, it outputs an H level. Also, the output line 137 outputs the output of the comparator 136 to the outside and transmits it to the receiving unit 22.

[0033] As described above, the semiconductor device 100 detects the disconnection of the second wire 102 by comparing the voltage at the reference point P11 and the voltage at the reference point P12. At this time, the threshold value for detecting the disconnection of the second wire 102 can be set by adjusting the voltage V12 at the reference point P12. For example, by setting the voltage V12 to a relatively small value, the sensitivity of disconnection detection relatively increases. In this way, the semiconductor device 100 does not need to increase the current amount when increasing the detection sensitivity. Therefore, the semiconductor device 100 can increase the detection sensitivity without increasing the parasitic capacitance of the circuit related to disconnection detection.

[0034] It is preferable to perform the above-described detection of a break in the second wire 102 after confirming that the first wire 101 and the third wire 103 are not broken. The break in the first wire 101 and the break in the third wire 103 can be confirmed by a normal functional test of the semiconductor device 100. The normal functional test here is something that would be conceivable to a person skilled in the art. Therefore, a detailed description is omitted here. On the other hand, if the second wire 102 is broken, no change sufficient to reveal an abnormality in the characteristics occurs in a functional test in a low-noise environment, such as a normal test environment. The semiconductor device 100 includes the detection circuit 130, which enables it to detect a break in the second wire 102 in the above-described test. After the above-described test is completed, the semiconductor device 100 is disconnected from the test system 20.

[0035] Next, a usage state of the semiconductor device 100 will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of usage of the semiconductor device according to the first embodiment.

[0036] The semiconductor device 100 is a gate driver with an insulating function. A first integrated circuit 110 of the semiconductor device 100 is connected to a microcomputer 901 and receives a predetermined control signal from the microcomputer 901. A transmission circuit 113 of the first integrated circuit 110 supplies a predetermined transmission signal based on the control signal received from the microcomputer 901 to a primary coil 111. The primary coil 111 and secondary coil 112 form a transformer. Therefore, the secondary coil 112 connected to a second integrated circuit 120 supplies a signal corresponding to the signal from the primary coil 111 to the second integrated circuit 120.

[0037] The second integrated circuit 120 has a receiving circuit 125 and a gate driver circuit 126. The receiving circuit 125 of the second integrated circuit 120 processes the differential signal received from the secondary coil 112 using a differential circuit. This allows the receiving circuit 125 to improve its resistance to common-mode noise. To match the reference potentials of the transformer and the receiving circuit 125, the midpoint P10 and the second signal line 122 are connected by wire bonding via the second wire 102. The gate driver circuit 126 is connected to an IGBT 902 provided outside the semiconductor device 100 and outputs a drive signal to the IGBT 902.

[0038] 2, in the environment in which the semiconductor device 100 is used, the detection circuit 130 is not connected to the inspection system 20. In other words, the detection circuit 130 is configured not to affect the function of the semiconductor device 100 in the environment in which the semiconductor device 100 performs its function.

[0039] 2 may be used for circuits (not shown) having other functions of the semiconductor device 100. In this case, the detection circuit 130 may be disconnected from the external terminals by a switch or the like. More specifically, the semiconductor device 100 may be configured to switch between a test mode in which the detection circuit 130 is used to inspect the connection state and a use mode in which the semiconductor device 100 performs its normal function, in response to an external signal.

[0040] As described above, the first integrated circuit 110 includes the transmitting circuit 113 that emits a transmission signal for transmitting a predetermined signal. The second integrated circuit 120 is a gate driver that outputs a predetermined drive signal based on a differential signal received from the transmitting circuit 113 via a transformer.

[0041] The semiconductor device 100 is not limited to a gate driver. The semiconductor device 100 may be any device that includes a transformer and has multiple integrated circuits connected by wire bonding within a package. For example, the semiconductor device 100 may be an amplifier IC or a DC / DC converter that includes a transformer. For ease of understanding, the above description appropriately omits configurations that are not described in the description. However, the present disclosure may include other configurations for achieving the above-described functions.

[0042] As described above, according to this embodiment, it is possible to provide a disconnection detection circuit that can suitably inspect the connection state of a wire without increasing parasitic capacitance.

[0043] <Embodiment 2> Next, a description will be given of a second embodiment. The second embodiment differs from the first embodiment in that a detection circuit 230 including an inverter is provided instead of a comparator. Fig. 3 is a diagram showing the configuration of a semiconductor device 200 according to the second embodiment.

[0044] The second integrated circuit 120 according to this embodiment has a detection circuit 230. The detection circuit 230 has a first power supply line 131, a second power supply line 132, an inverter 231, a transistor 232, and an output line 233 as its main components.

[0045] The first power supply line 131 according to this embodiment receives a preset current from a first constant current source 133 and supplies this current to the first wire 101 via a contact A1 and a first signal line 121. The first power supply line 131 also has a reference point P21. A branch line extends from the reference point P21 and is connected to the gate of a transistor 232.

[0046] The second power supply line 132 receives a preset current supply from a second constant current source 134 at one end, and is connected to the reference potential unit G1 via a transistor 232. Note that, as shown in the first embodiment, the second power supply line 132 may become the reference potential by being connected to the second signal line 122. This also applies to the configurations of the following embodiments.

[0047] The source of the transistor 232 is connected to the side of the second power supply line 132 that is closer to the reference potential portion. The drain of the transistor 232 is connected to the side of the second power supply line 132 that is closer to the second constant current source 134. The second power supply line 132 has a reference point P22 between the second constant current source 134 and the transistor 232. A branch line extends from the reference point P22 and is connected to the input side of the inverter 231.

[0048] The inverter 231 is provided so as to be able to detect voltage fluctuations at a reference point P22 which is a predetermined position on the second power supply line 222. The inverter 231 also transmits an output signal to the receiving unit 22 via an output line 233.

[0049] The transistor 232 is an NMOS transistor, and its gate is connected to a branch line branching from the reference point P21. The transistor 232 has its drain connected to the reference point P22 side and its source connected to the reference potential unit G1 side. The transistor 232 is configured so that a current flows through the second power line 132 when the reference point P21 has a potential higher than the threshold potential.

[0050] In the above configuration, when the first constant current source 133 supplies a constant current I1 to the first power line 131, a voltage V21 is generated at the reference point P21. Here, the second wire 102 has a resistance value R1, and the voltage V21 is R1*I1. If the second wire 102 is not broken, the resistance value R1 is sufficiently low. In this case, the voltage V21 does not turn on the transistor 232.

[0051] On the other hand, if the second wire 102 is broken, the resistance value R1 increases, which increases the gate voltage and turns on the transistor 232. As a result, the voltage at the reference point P22 becomes the L level of the inverter 231. Therefore, the inverter 231 outputs an H level signal to the output line 233.

[0052] The semiconductor device 200 according to this embodiment has been described above. The semiconductor device 200 can preferably detect a wire break with a configuration that includes a small number of components. The threshold value for the detection circuit 230 to detect a wire break can be adjusted by adjusting the current I1 of the first constant current source 133. Therefore, this embodiment can provide a wire break detection circuit that can preferably inspect the connection state of a wire with a simple configuration.

[0053] <Third Embodiment> Next, a third embodiment will be described. Fig. 4 is a diagram showing a configuration of a semiconductor device 300 according to the third embodiment. Fig. 4 shows a state in which an inspection system 30 and the semiconductor device 300 are connected to each other.

[0054] The inspection system 30 according to this embodiment mainly comprises an external power supply 21 and a detection unit 24. The external power supply 21 supplies a current to the second integrated circuit 120 of the semiconductor device 300. The detection unit 24 measures the current supplied by the external power supply 21 and is configured to be able to detect whether the connection state of the semiconductor device 300 is normal or abnormal depending on the measured current.

[0055] The semiconductor device 300 has a detection circuit 330 instead of the detection circuit 130 or the detection circuit 230 according to the above-described embodiments. The detection circuit 330 mainly includes a first power supply line 131, a first constant current source 133, a second power supply line 332, a resistor 331, and a transistor 232. The configurations of the first power supply line 131, the first constant current source 133, and the reference point P21 of the first power supply line 131 according to the present embodiment are the same as those described in the second embodiment.

[0056] The second power supply line 322 receives a current from the external power supply 21 at one end and is connected to the reference potential section G1 via a resistor 331 and a transistor 232. The second power supply line 332 has the resistor 331 on the side closer to the power supply than the transistor 232. The second power supply line 332 also has the transistor 232 between the resistor 331 and the reference potential section G1.

[0057] The transistor 232 is an NMOS, and its gate is connected to a branch line branching off from the reference point P21. The transistor 232 has its drain connected to the side connected to the resistor 331 and its source connected to the reference potential unit G1. By connecting its gate to the branch line branching off from the reference point P21, the transistor 232 is set to allow or prevent a current from flowing depending on the threshold potential at the reference point P21. The transistor 232 according to this embodiment is set so that a current flows to the second power line 332 when the reference point P21 has a potential higher than the threshold potential.

[0058] In the above configuration, when the first constant current source 133 supplies a constant current I1 to the first power line 131, a voltage V21 is generated at the reference point P21. Here, the second wire 102 has a resistance value R1, and the voltage V21 is R1*I1. If the second wire 102 is not broken, the resistance value R1 is sufficiently low. In this case, the voltage V21 does not turn on the transistor 232.

[0059] On the other hand, if the second wire 102 is broken, the resistance value R1 increases, and accordingly the gate voltage increases relatively. When the potential at the reference point P21 exceeds the threshold, the transistor 232 turns on. As a result, a current corresponding to the resistance 331 flows through the second power supply line 332. When the detection unit 24 measures the current when a current flows through the second power supply line 332, it detects that the connection state of the semiconductor device 300 is abnormal.

[0060] The third embodiment has been described above. In the semiconductor device 300 according to this embodiment, the detection circuit 330 generates a change in the power supply current instead of outputting a disconnection detection signal. Therefore, the semiconductor device 300 according to this embodiment can detect a disconnection without providing a complex logic circuit for disconnection detection. As described above, this embodiment can provide a disconnection detection circuit that can suitably inspect the connection state of a wire without increasing parasitic capacitance.

[0061] <Fourth Embodiment> Next, a fourth embodiment will be described. Fig. 5 is a diagram showing the configuration of a semiconductor device 400 according to the fourth embodiment. Like the first embodiment, the semiconductor device 400 has a comparator 136 in the detection circuit. However, the semiconductor device 400 differs from the first embodiment in that it has a plurality of transformers, and the second integrated circuit 120 has switches for switchably connecting constant current sources separately to the ends of each of the plurality of transformers.

[0062] The semiconductor device 400 according to this embodiment differs from the semiconductor device 100 according to the embodiment in that the semiconductor device 400 includes a first integrated circuit 110A and a first integrated circuit 110B. Similarly, the second integrated circuit 120 also includes a receiving circuit 125A and a receiving circuit 125B.

[0063] The first integrated circuit 110A and the first integrated circuit 110B basically have the same configuration. In FIG. 5, the components of the first integrated circuit 110A are designated by a reference numeral suffix "A." On the other hand, in FIG. 5, the components of the first integrated circuit 110B are designated by a reference numeral suffix "B." Similarly, the reference numerals of the wires (first wire 101, second wire 102, and third wire 103) to which the secondary coil 112A and the secondary coil 112B are respectively connected are also designated by a corresponding reference numeral suffix "A" or "B." Furthermore, the reference numerals of the first signal line 121 to the third signal line 124 of the second integrated circuit 120 are also designated by a corresponding reference numeral suffix "A" or "B."

[0064] The semiconductor device 400 according to the present embodiment includes a detection circuit 430. The detection circuit 430 mainly includes a first power supply line 131, a second power supply line 132, a first constant current source 133, a second constant current source 134, a reference resistor 135, a comparator 136, an output line 137, a first switch SW1, and a second switch SW2. A detailed description of the configuration described in the first embodiment will be omitted here.

[0065] The first power supply line 131 has a signal line that connects from the reference point P11 to the first signal line 121A. The first power supply line 131 also has a signal line that branches off from the reference point P11 and connects to the first signal line 121B. The first power supply line 131 has a first switch SW1 between the reference point P11 and the first signal line 121A. Similarly, the first power supply line 131 has a second switch SW2 on the signal line that branches off from the reference point P11 and connects to the first signal line 121B. The first power supply line 131 also has a branch line that branches off from the reference point P11 and supplies a first input signal to the comparator 136.

[0066] In the above configuration, the detection circuit 430 switches between the first switch SW1 and the second switch SW2 to sequentially supply current to each of them. Note that the above-mentioned switches can be switched by supplying a control signal (not shown) from the inspection system 20.

[0067] For example, the detection circuit 430 first checks the connection status of the second wire 102A. In this case, the first switch SW1 is turned on and the second switch SW2 is turned off. As a result, when the first constant current source 133 supplies a current I1 to the first power supply line 131, the current flows through the first signal line 121A and the first wire 101A to the secondary coil 112A. The current also flows through the midpoint P10A to the second wire 102A, the second signal line 122A, and the reference line 123A. Therefore, in this case, the output of the comparator 136 indicates the connection status of the second wire 102A.

[0068] Next, the detection circuit 430 checks the connection status of the second wire 102B. In this case, the first switch SW1 is turned off and the second switch SW2 is turned on. As a result, when the first constant current source 133 supplies a current I1 to the first power supply line 131, the current flows through the first signal line 121B and the first wire 101B to the secondary coil 112B. The current also flows through the midpoint P10B to the second wire 102B, the second signal line 122B, and the reference line 123B. Therefore, in this case, the output of the comparator 136 indicates the connection status of the second wire 102B.

[0069] The fourth embodiment has been described above. The detection circuit 430 according to this embodiment detects whether the connection state is normal or abnormal for each connected transformer. Note that while the present embodiment has been described with reference to a case where there are two transformers, there may be three or more transformers. In this case, the detection circuit 430 has switches corresponding to the number of transformers and inspects each transformer individually. As described above, this embodiment can provide an open-circuit detection circuit that can suitably inspect the connection state of multiple wires without increasing parasitic capacitance.

[0070] Although the embodiments have been described above, the configurations of the above-described embodiments may be combined with each other, or some of the configurations may be replaced with other configurations. Furthermore, the configurations of the above-described embodiments may be modified in various ways without departing from the spirit of the invention. [Explanation of symbols]

[0071] 20 Inspection System 21 External power supply 22 Receiving unit 24 Detector 30 Inspection Systems 100 Semiconductor device 101 First Wire 102 Second Wire 103 Third Wire 110 First Integrated Circuit 111 Primary coil 112 Secondary coil 113 Transmitting circuit 120 Second Integrated Circuit 121 First signal line 122 Second signal line 123 Reference Line 124 Third signal line 125 receiving circuit 126 Gate driver circuit 130 Detection circuit 131 1st power line 132 2nd power line 133 1st constant current source 134 Second constant current source 135 Reference Resistor 136 Comparator 137 Output Line 200 Semiconductor device 230 Detection circuit 231 Inverter 232 transistors 233 output line 300 Semiconductor device 330 Detection circuit 331 Resistance 332 2nd power line 400 Semiconductor Devices 430 Detection Circuit 901 Microcomputer 902 IGBT G1 Reference potential section P10 midpoint P11 Reference point P12 Reference point P21 Reference point P22 Reference point SW1 First switch SW2 Second switch

Claims

1. A semiconductor device having, in one package, a first integrated circuit including a transformer including a primary coil and a secondary coil, and a second integrated circuit connected to the secondary coil, The second integrated circuit comprises: a reference line connecting a midpoint of the secondary coil and a reference potential portion set to a reference potential; a first power supply line connecting a first constant current source and an end of the secondary coil; and a detection circuit for detecting whether a connection state of a wire connecting from the first power supply line through the secondary coil to the reference line is normal or abnormal based on a potential at a predetermined reference point on the first power supply line; A semiconductor device comprising:

2. the end of the secondary coil is connected to the first power supply line, and the midpoint is connected to the reference line via bonding wires, respectively; The semiconductor device according to claim 1 .

3. a second power supply line connecting a second constant current source and the reference potential unit; the detection circuit detects whether the connection state is normal or abnormal based on a potential difference between the potential at the reference point and a potential at a predetermined reference point on the second power line. The semiconductor device according to claim 1 .

4. the detection circuit has a comparator that receives the branch of the first power supply line and the branch of the second power supply line as inputs, and has a signal line for outputting an output signal of the comparator to an external device. The semiconductor device according to claim 3 .

5. the detection circuit further includes a second power supply line connected to a power supply and a ground via a transistor, and an inverter provided to be able to detect a voltage fluctuation at a predetermined position on the second power supply line; The transistor has a gate connected to a branch line branching from the reference point, and whether or not a current flows is determined based on a threshold potential at the reference point. The semiconductor device according to claim 1 .

6. the transistor is an NMOS transistor configured to allow a current to flow to the second power line when the reference point has a potential higher than the threshold potential, The inverter has a signal line for outputting an output signal to the outside. The semiconductor device according to claim 5 .

7. the detection circuit further includes a second power supply line connected to an external power supply and ground via a transistor; the transistor is configured such that a gate is connected to a branch line branching from the reference point, and whether or not a current flows is determined based on a threshold potential at the reference point, thereby making it possible to detect whether the connection state is normal or abnormal by measuring the state of the current of the external power supply; The semiconductor device according to claim 1 .

8. the transistor is an NMOS transistor configured to allow a current to flow through the second power line when the reference point has a potential higher than the threshold potential; The semiconductor device according to claim 7 .

9. the semiconductor device includes a plurality of the transformers, the second integrated circuit includes a switch for switchably and separately connecting the first constant current source to each end of the plurality of transformers; the detection circuit detects whether the connection state is normal or abnormal for each of the transformers to be connected. The semiconductor device according to claim 1 .

10. the first integrated circuit includes a transmitting circuit that emits a transmission signal for transmitting a predetermined signal; the second integrated circuit is a gate driver that outputs a predetermined drive signal based on a differential signal received from the transmission circuit via a transformer; The semiconductor device according to claim 1 .

Images