Decoder-side motion vector refinement tool on / off control

Abstract

To provide a technique for enabling very precise on / off control of two or more different decoder-side refinement tools.SOLUTION: Rather than just enabling or enabling these tools for an entire video sequence of video data, this disclosure describes a technique for enabling or disabling different decoder-side refinement tools for a subset (or portion) of a video sequence.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] This application claims priority to U.S. Provisional Application No. 16 / 892,714, filed June 4, 2020, which claims the benefit of U.S. Provisional Application No. 62 / 858,094, filed June 6, 2019, and U.S. Provisional Application No. 62 / 863,080, filed June 18, 2019, the entire contents of each of which are incorporated herein by reference.

[0002] TECHNICAL FIELD This disclosure relates to video encoding and decoding. [Background technology]

[0003] Digital video capabilities may be incorporated into a wide range of devices, including digital televisions, digital direct broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite radiotelephones, so-called "smartphones," video teleconferencing devices, video streaming devices, etc. Digital video devices implement video coding techniques, such as those described in standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4, Part 10 Advanced Video Coding (AVC), ITU-T H.265 / High Efficiency Video Coding (HEVC), and extensions to such standards. By implementing such video coding techniques, video devices may more efficiently transmit, receive, encode, decode, and / or store digital video information.

[0004] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video picture or a portion of a video picture) may be partitioned into video blocks, which are also sometimes referred to as coding tree units (CTUs), coding units (CUs), and / or coding nodes. Video blocks in an intra-coded (I) slice of a picture are encoded using spatial prediction with respect to reference samples in neighboring blocks in the same picture. Video blocks in an inter-coded (P or B) slice of a picture may use spatial prediction with respect to reference samples in neighboring blocks in the same picture or temporal prediction with respect to reference samples in other reference pictures. A picture may be referred to as a frame, and a reference picture may be referred to as a reference frame. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Bross et al., "Versatile Video Coding (Draft 5)", Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11, 14th Meeting: Geneva, CH, 19-27, March 2019, JVET-N1001-v3 Summary of the Invention [Means for solving the problem]

[0006] In the development of the Versatile Video Coding (VVC) standard, several decoder-side motion refinement tools have been proposed and / or adopted into the standard to improve compression efficiency. One example is bidirectional optical flow (BDOF), and another exemplary tool is decoder-side motion vector refinement (DMVR). Generally, this disclosure describes several different video encoding and decoding techniques, including techniques for decoder-side refinement tool on / off control.

[0007] More specifically, this disclosure describes techniques for enabling highly precise on / off control of two or more different decoder-side refinement tools. Rather than simply enabling or enabling these tools for an entire video sequence of video data, this disclosure describes techniques for enabling or disabling different decoder-side refinement tools for a subset (or portion) of the video sequence. In this way, the present techniques can provide greater flexibility between the conflicting goals of reduced decoding complexity and increased compression efficiency in different video applications or settings.

[0008] In some examples, this disclosure describes a method for decoding a sequence of video data including a plurality of pictures. The method may include decoding a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in the sequence of video data, and determining, based on the value of the first syntax element, whether the first decoder-side refinement tool is enabled or disabled for the first subset of video data. Furthermore, the method may include decoding a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data in the sequence of video data, and determining, based on the value of the first syntax element, whether the second decoder-side refinement tool is enabled or disabled for the first subset of video data. As an example, the first subset of video data may include a slice, a picture, a subpicture, a frame, or a block of video data in the video sequence. Decoding the first subset of the video data may include decoding the first subset of the video data using a first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the first subset; decoding the first subset of the video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the first subset; decoding the first subset of the video data using a second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the first subset; and decoding the subset of the video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the first subset.

[0009] In another example, this disclosure describes a method for encoding a sequence of video data including a plurality of pictures. The method may include: encoding a first instance of a first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in the sequence of video data, the second subset being different from the first subset; encoding a first instance of a second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data in the sequence of video data; and encoding a second instance of the second syntax element to identify whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data in the sequence of video data.

[0010] In some examples, the present disclosure describes a video decoding device comprising: a memory configured to store a sequence of video data including a plurality of pictures; and processing circuitry configured to: decode a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data within the sequence of video data; determine, based on the value of the first syntax element, whether the first decoder-side refinement tool is enabled or disabled for the first subset of video data; decode a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data within the sequence of video data; and determine, based on the value of the first syntax element, whether the second decoder-side refinement tool is enabled or disabled for the first subset of video data. The processing circuitry may be further configured to: decode the first subset of the video data using the first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the first subset; decode the first subset of the video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the first subset; decode the first subset of the video data using the second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the first subset; and decode the subset of the video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the first subset.

[0011] In some examples, this disclosure describes a video encoding device comprising: a memory configured to store a sequence of video data including a plurality of pictures; and processing circuitry; the processing circuitry configured to: encode a first instance of a first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data within the sequence of video data; and configure the first syntax element to identify whether the first decoder-side refinement tool is enabled or disabled for a second subset of video data within the sequence of video data. the first instance of the second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data in the sequence of video data, wherein the second subset is different from the first subset; and encoding the second instance of the second syntax element to identify whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data in the sequence of video data.

[0012] In yet another example, the present disclosure describes a computer-readable storage medium storing instructions that, when executed, cause one or more processors of a video device to perform an encoding or decoding method of the present disclosure.

[0013] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram illustrating an example video encoding and decoding system that may implement techniques of this disclosure. [Figure 2A]FIG. 1 is a conceptual diagram illustrating an exemplary quad-tree binary tree (QTBT) structure and corresponding coding tree unit (CTU). [Figure 2B] FIG. 1 is a conceptual diagram illustrating an exemplary quad-tree binary tree (QTBT) structure and corresponding coding tree unit (CTU). [Figure 3] FIG. 2 is a block diagram illustrating an example video encoder that may implement the techniques of this disclosure. [Figure 4] FIG. 2 is a block diagram illustrating an example video decoder that may implement the techniques of this disclosure. [Figure 5] FIG. 1 is a conceptual diagram illustrating an extended coding unit region used in bidirectional optical flow. [Figure 6] FIG. 10 is a conceptual diagram illustrating an example of decoder-side motion vector refinement. [Figure 7] FIG. 10 is a conceptual diagram illustrating an exemplary merge mode using motion vector difference search points. [Figure 8] 1 is a flowchart illustrating an exemplary encoding method of the present disclosure. [Figure 9] 1 is a flowchart illustrating an exemplary decoding method of the present disclosure. [Figure 10] 10 is a flowchart illustrating another decoding method consistent with this disclosure. [Figure 11] 10 is a flowchart illustrating another encoding method consistent with this disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0015] This disclosure describes techniques for enabling highly precise on / off control of two or more different decoder-side refinement tools. With some video compression standards, such as the current Versatile Video Coding (VVC) standard under development, several decoder-side motion refinement tools are employed to improve compression efficiency. However, while decoder-side motion refinement tools may improve compression efficiency, they may also increase decoding complexity, which is undesirable in some situations. The techniques of this disclosure can provide greater flexibility in the ability to enable or disable decoder-side refinement tools, thereby providing flexibility between the conflicting goals of reducing decoding complexity and increasing compression efficiency in different video applications or settings.

[0016] One exemplary decoder-side refinement tool is a bidirectional optical flow (BDOF) tool, and another exemplary decoder-side refinement tool is a decoder-side motion vector refinement (DMVR) tool. Generally, this disclosure describes techniques for decoder-side motion refinement on / off control of these or other decoder-side refinement tools. In particular, the described techniques may enable very precise on / off control of subsets of video data in a video sequence. For example, rather than simply enabling or enabling these tools for a video sequence, this disclosure describes techniques for enabling or disabling different decoder-side refinement tools for subsets (or portions) of a video sequence.

[0017] In some examples, separate on / off controls for different decoder-side refinement tools may be enabled or disabled for different subsets or portions of a video sequence, such as a slice of video data within a video sequence, a frame of video data within a video sequence, a picture of video data within a video sequence, a sub-picture of video data within a video sequence, a block of video data within a video sequence, or another portion (some, but not all) of the video data of a video sequence. In this manner, greater flexibility is gained between the conflicting goals of reducing decoding complexity and increasing compression efficiency in different video applications or settings. The subset of a video sequence may, for example, include at least a portion of a first picture among multiple pictures of a sequence of video data.

[0018] According to this disclosure, one or more decoder-side refinement tools may be enabled to improve compression efficiency, or alternatively, one or more decoder-side refinement tools may be disabled to promote decoder simplicity. Control may be more adaptive by allowing such control for a subset of video data (e.g., for only a portion or part of the entire video sequence). On / off control may be signaled by one or more syntax elements of the coded bitstream for a frame of video data, a picture of video data, a slice of video data, a sub-picture of video data, a block of video data, or other subset or sub-portion of a larger video sequence.

[0019] The following acronyms are used in this disclosure: Coding Unit: CU Coding Tree Unit: CTU Motion Vector: MV Motion Vector Differential: MVD Motion Vector Predictor: MVP

[0020] 1 is a block diagram illustrating an example video encoding and decoding system 100 that may implement techniques of this disclosure. The techniques of this disclosure are generally directed to coding (encoding and / or decoding) video data. Generally, video data includes any data for processing video. Thus, video data may include raw uncoded video, coded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0021] 1, system 100 includes a source device 102 that, in this example, provides encoded video data to be decoded and displayed by a destination device 116. Specifically, source device 102 provides the video data to destination device 116 via a computer-readable medium 110. Source device 102 and destination device 116 may comprise any of a wide range of devices, including desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, telephone handsets such as smartphones, televisions, cameras, display devices, digital media players, video gaming consoles, video streaming devices, etc. In some cases, source device 102 and destination device 116 may be equipped for wireless communication and therefore may be referred to as wireless communication devices.

[0022] In the example of FIG. 1, source device 102 includes a video source 104, memory 106, a video encoder 200, and an output interface 108. Destination device 116 includes an input interface 122, a video decoder 300, memory 120, and a display device 118. According to this disclosure, the video encoder 200 of source device 102 and the video decoder 300 of destination device 116 may be configured to apply techniques for decoder-side motion refinement on / off control. Thus, source device 102 represents an example of a video encoding device, and destination device 116 represents an example of a video decoding device. In other examples, the source device and destination device may include other components or arrangements. For example, source device 102 may receive video data from an external video source, such as an external camera. Similarly, destination device 116 may interface with an external display device rather than including an integrated display device.

[0023] System 100 as shown in FIG. 1 is merely an example. In general, any digital video encoding and / or decoding device may implement techniques for decoder-side motion refinement on / off control. Source device 102 and destination device 116 are merely examples of coding devices, such that source device 102 generates coded video data for transmission to destination device 116. This disclosure refers to a “coding” device as a device that performs coding (encoding and / or decoding) of data. Accordingly, video encoder 200 and video decoder 300 represent examples of coding devices, specifically, video encoders and video decoders, respectively. In some examples, devices 102, 116 may operate in a substantially symmetric manner, such that each of devices 102, 116 includes video encoding and decoding components. Thus, system 100 may support unidirectional or bidirectional video transmission between video devices 102, 116, e.g., for video streaming, video playback, video broadcasting, or video telephony.

[0024] Generally, video source 104 represents a source of video data (i.e., raw, unencoded video data) and provides a sequential series of pictures (also called “frames”) of the video data to video encoder 200, which encodes the data for the pictures. Video source 104 of source device 102 may include a video capture device, such as a video camera, a video archive containing previously captured raw video, and / or a video feed interface for receiving video from a video content provider. As a further alternative, video source 104 may generate computer-graphics-based data as source video, or a combination of live, archived, and computer-generated video. In each case, video encoder 200 encodes the captured, pre-captured, or computer-generated video data. Video encoder 200 may reorder the pictures from the order in which they were received (sometimes referred to as “display order”) into a coding order for coding. Video encoder 200 may generate a bitstream including the encoded video data. Source device 102 may then output the encoded video data via output interface 108 onto computer-readable medium 110 for receipt and / or retrieval by input interface 122 of destination device 116, for example.

[0025] Memory 106 of source device 102 and memory 120 of destination device 116 represent general-purpose memory. In some examples, memory 106, 120 may store raw video data, e.g., raw video from video source 104 and raw decoded video data from video decoder 300. Additionally or alternatively, memory 106, 120 may store software instructions executable by, e.g., video encoder 200 and video decoder 300, respectively. While shown separately from video encoder 200 and video decoder 300 in this example, it should be understood that video encoder 200 and video decoder 300 may also include internal memory for functionally similar or equivalent purposes. Additionally, memory 106, 120 may store encoded video data, e.g., output from video encoder 200 and input to video decoder 300. In some examples, a portion of memory 106, 120 may be allocated as one or more video buffers, e.g., for storing raw decoded and / or encoded video data.

[0026] The computer-readable medium 110 may represent any type of medium or device capable of transporting encoded video data from the source device 102 to the destination device 116. In one example, the computer-readable medium 110 represents a communication medium that enables the source device 102 to transmit encoded video data directly to the destination device 116 in real time, for example, via a radio frequency network or a computer-based network. The output interface 108 may modulate a transmission signal containing the encoded video data, and the input interface 122 may demodulate a received transmission signal, in accordance with a communication standard such as a wireless communication protocol. The communication medium may comprise any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network, such as a local area network, a wide area network, or a global network such as the Internet. The communication medium may include routers, switches, base stations, or any other equipment that may be useful for facilitating communication from the source device 102 to the destination device 116.

[0027] In some examples, source device 102 may output encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, a Blu-ray disc, a DVD, a CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data.

[0028] In some examples, source device 102 may output the encoded video data to a file server 114 or another intermediate storage device, which may store the encoded video generated by source device 102. Destination device 116 may access the stored video data from file server 114 via streaming or download. File server 114 may be any type of server device capable of storing encoded video data and transmitting the encoded video data to destination device 116. File server 114 may represent a web server (e.g., for a website), a file transfer protocol (FTP) server, a content delivery network device, or a network-attached storage (NAS) device. Destination device 116 may access the encoded video data from file server 114 through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both suitable for accessing the encoded video data stored on file server 114. The file server 114 and the input interface 122 may be configured to operate according to a streaming transmission protocol, a download transmission protocol, or a combination thereof.

[0029] Output interface 108 and input interface 122 may represent a wireless transmitter / receiver, a modem, a wired networking component (e.g., an Ethernet card), a wireless communication component operating according to any of the various IEEE 802.11 standards, or other physical components. In examples in which output interface 108 and input interface 122 comprise wireless components, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to a cellular communication standard, such as 4G, 4G-LTE (Long Term Evolution), LTE-Advanced, 5G, etc. In some examples in which output interface 108 comprises a wireless transmitter, output interface 108 and input interface 122 may be configured to transfer data, such as encoded video data, according to other wireless standards, such as the IEEE 802.11 specification, the IEEE 802.15 specification (e.g., ZigBee™), the Bluetooth™ standard, etc. In some examples, source device 102 and / or destination device 116 may include respective system-on-chip (SoC) devices. For example, the source device 102 may include an SoC device for implementing functionality attributed to the video encoder 200 and / or the output interface 108, and the destination device 116 may include an SoC device for implementing functionality attributed to the video decoder 300 and / or the input interface 122.

[0030] The techniques of this disclosure may be applied to video coding supporting any of a variety of multimedia applications, such as over-the-air television broadcast, cable television transmission, satellite television transmission, Internet streaming video transmission such as Dynamic Adaptive Streaming over HTTP (DASH), digital video encoded on a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0031] The input interface 122 of the destination device 116 receives the encoded video bitstream from the computer-readable medium 110 (e.g., the storage device 112, the file server 114, etc.). The encoded video bitstream may include signaling information defined by the video encoder 200 and also used by the video decoder 300, such as syntax elements having values ​​that describe the characteristics and / or processing of video blocks or other coded units (e.g., slices, pictures, groups of pictures, sequences, etc.). The display device 118 displays decoded pictures of the decoded video data to a user. The display device 118 may represent any of a variety of display devices, such as a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, an organic light-emitting diode (OLED) display, or another type of display device.

[0032] 1, in some examples, video encoder 200 and video decoder 300 may each be integrated with an audio encoder and / or decoder and may include an appropriate MUX-DEMUX unit or other hardware and / or software to process multiplexed streams containing both audio and video in a common data stream. Where applicable, the MUX-DEMUX unit may conform to the ITU H.223 multiplexer protocol or other protocols such as the User Datagram Protocol (UDP).

[0033] The video encoder 200 and the video decoder 300 may each be implemented as any of a variety of suitable encoder and / or decoder circuit configurations, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When the techniques are implemented partially in software, a device may store instructions for the software on a suitable non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to implement the techniques of this disclosure. Each of the video encoder 200 and the video decoder 300 may be included in one or more encoders or decoders, any of which may be integrated as part of a combined encoder / decoder (codec) within the respective device. A device including the video encoder 200 and / or the video decoder 300 may comprise an integrated circuit, a microprocessor, and / or a wireless communication device such as a cellular phone.

[0034] Video encoder 200 and video decoder 300 may operate according to a video coding standard such as ITU-T H.265, also known as High Efficiency Video Coding (HEVC), or extensions thereof, such as multiview and / or scalable video coding extensions. Alternatively, video encoder 200 and video decoder 300 may operate according to other proprietary or industry standards, such as the Joint Search and Test Model (JEM) or ITU-T H.266, also known as Versatile Video Coding (VVC). The latest draft of the VVC standard is set forth in Bross et al., "Versatile Video Coding (Draft 5)," Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11, 14th Meeting: Geneva, CH, March 19-27, 2019, JVET-N1001-v3 (hereinafter, "VVC Draft 5"). However, the techniques of this disclosure are not limited to any particular coding standard.

[0035] Generally, the video encoder 200 and the video decoder 300 may perform block-based coding of pictures. The term “block” generally refers to a structure containing data to be processed (e.g., encoded, decoded, or otherwise used in an encoding and / or decoding process). For example, a block may include a two-dimensional matrix of luma and / or chroma data samples. Generally, the video encoder 200 and the video decoder 300 may code video data represented in YUV (e.g., Y, Cb, Cr) format. That is, rather than coding red, green, and blue (RGB) data for samples of a picture, the video encoder 200 and the video decoder 300 may code luma and chroma components, which may include both red and blue hues. In some examples, the video encoder 200 converts received RGB-formatted data to a YUV representation prior to encoding, and the video decoder 300 converts the YUV representation to an RGB format. Alternatively, pre-processing and post-processing units (not shown) may perform these conversions.

[0036] This disclosure may generally refer to coding (e.g., encoding and decoding) a picture to include the process of encoding or decoding data for the picture. Similarly, this disclosure may refer to coding of a block of a picture, e.g., predictive and / or residual coding, to include the process of encoding or decoding data for the block. A coded video bitstream generally includes a series of values ​​for syntax elements that represent coding decisions (e.g., coding modes) and the partitioning of a picture into blocks. Thus, references to coding a picture or a block should generally be understood as coding values ​​for the syntax elements that form the picture or block.

[0037] HEVC defines various blocks, including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video coder (such as video encoder 200) partitions coding tree units (CTUs) into CUs according to a quadtree structure. That is, the video coder partitions CTUs and CUs into four equal, non-overlapping squares, and each node in the quadtree has either zero or four child nodes. A node with no child nodes may be called a "leaf node," and a CU of such a leaf node may include one or more PUs and / or one or more TUs. The video coder may further partition PUs and TUs. For example, in HEVC, a residual quadtree (RQT) represents the partitioning of TUs. In HEVC, a PU represents inter-predicted data, and a TU represents residual data. An intra-predicted CU includes intra-prediction information, such as an intra-mode indication.

[0038] As another example, video encoder 200 and video decoder 300 may be configured to operate according to JEM or VVC. According to JEM or VVC, a video coder (such as video encoder 200) partitions a picture into multiple coding tree units (CTUs). Video encoder 200 may partition the CTUs according to a tree structure such as a quadtree-binary tree (QTBT) structure or a multi-type tree (MTT) structure. The QTBT structure eliminates the concept of multiple partition types, such as the distinction between CUs, PUs, and TUs in HEVC. The QTBT structure includes two levels: a first level partitioned according to quadtree partitioning and a second level partitioned according to binary tree partitioning. The root node of the QTBT structure corresponds to a CTU. The leaf nodes of the binary tree correspond to coding units (CUs).

[0039] In the MTT partitioning structure, blocks may be partitioned using quadtree (QT) partitioning, binary tree (BT) partitioning, and one or more types of triple tree (TT) partitioning. Triple tree partitioning is a partitioning in which a block is divided into three sub-blocks. In some examples, triple tree partitioning divides a block into three sub-blocks without splitting the original block through the center. The partition types in MTT (e.g., QT, BT, and TT) can be symmetric or asymmetric.

[0040] In some examples, the video encoder 200 and the video decoder 300 may use a single QTBT or MTT structure to represent each of the luma and chroma components, and in other examples, the video encoder 200 and the video decoder 300 may use two or more QTBT or MTT structures, such as one QTBT / MTT structure for the luma component and another QTBT / MTT structure for both chroma components (or two QTBT / MTT structures for each chroma component).

[0041] Video encoder 200 and video decoder 300 may be configured to use HEVC-specific quadtree partitioning, QTBT partitioning, MTT partitioning, or other partition structures. For illustrative purposes, the description of the techniques of this disclosure is presented with respect to QTBT partitioning. However, it should be understood that the techniques of this disclosure may also be applied to video coders configured to use quadtree partitioning or other types of partitioning.

[0042] This disclosure may use "N x N" and "N by N" interchangeably to refer to the sample dimensions of a block (such as a CU or other video block) in terms of the vertical and horizontal dimensions, e.g., 16 x 16 samples or 16 by 16 samples. Generally, a 16 x 16 CU has 16 samples in the vertical direction (y = 16) and 16 samples in the horizontal direction (x = 16). Similarly, an N x N CU generally has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. Samples in a CU may be arranged in rows and columns. Furthermore, a CU does not necessarily have to have the same number of samples horizontally as vertically. For example, a CU may comprise N x M samples, where M is not necessarily equal to N.

[0043] Video encoder 200 encodes video data for a CU that represents prediction and / or residual information, as well as other information. The prediction information indicates how the CU will be predicted to form a predictive block for the CU. The residual information generally represents sample-by-sample differences between the samples of the CU and the samples of the predictive block prior to encoding.

[0044] To predict a CU, the video encoder 200 may generally form a predictive block for the CU through inter prediction or intra prediction. Inter prediction generally refers to predicting a CU from data of a previously coded picture, while intra prediction generally refers to predicting a CU from previously coded data of the same picture. To perform inter prediction, the video encoder 200 may generate a predictive block using one or more motion vectors. The video encoder 200 may generally perform motion search to identify a reference block that closely matches the CU, for example, with respect to the difference between the CU and the reference block. The video encoder 200 may calculate a difference metric using a sum of absolute differences (SAD), a sum of squared differences (SSD), a mean absolute difference (MAD), a mean squared difference (MSD), or other such difference calculation to determine whether the reference block closely matches the current CU. In some examples, the video encoder 200 may predict the current CU using unidirectional prediction or bidirectional prediction.

[0045] Some examples of JEM and VVC also provide an affine motion compensation mode, which may be considered an inter-prediction mode. In an affine motion compensation mode, video encoder 200 may determine two or more motion vectors that represent non-translational motion, such as zooming in or out, rotation, perspective motion, or other irregular motion types.

[0046] To perform intra prediction, video encoder 200 may select an intra prediction mode to generate a predictive block. Some examples of JEM and VVC provide 67 intra prediction modes, including various directional modes, as well as a planar mode and a DC mode. Generally, video encoder 200 selects an intra prediction mode that describes neighboring samples relative to a current block (e.g., a block of a CU) from which to predict samples of the current block. Such samples may generally be above, above and to the left of, or to the left of the current block in the same picture as the current block, assuming that video encoder 200 codes CTUs and CUs in raster scan order (left to right, top to bottom).

[0047] The video encoder 200 encodes data representing a prediction mode for the current block. For example, in the case of an inter prediction mode, the video encoder 200 may encode data representing which of various available inter prediction modes is used, as well as motion information for the corresponding mode. In the case of unidirectional or bidirectional inter prediction, for example, the video encoder 200 may encode motion vectors using advanced motion vector prediction (AMVP) or merge mode. The video encoder 200 may use a similar mode to encode motion vectors for an affine motion compensation mode.

[0048] Following prediction, such as intra-prediction or inter-prediction, of a block, the video encoder 200 may calculate residual data for the block. The residual data, such as a residual block, represents sample-by-sample differences between the block and a predictive block for that block formed using a corresponding prediction mode. The video encoder 200 may apply one or more transforms to the residual block to generate transform data in a transform domain rather than a sample domain. For example, the video encoder 200 may apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform to the residual video data. In addition, the video encoder 200 may apply a secondary transform, such as a mode-dependent non-separable secondary transform (MDNSST), a signal-dependent transform, or a Karhunen-Loeve transform (KLT), following the initial transform. The video encoder 200 generates transform coefficients following application of the one or more transforms.

[0049] As described above, following any transformation to generate transform coefficients, the video encoder 200 may perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the coefficients, thereby providing further compression. By performing the quantization process, the video encoder 200 may reduce the bit depth associated with some or all of the coefficients. For example, the video encoder 200 may round an n-bit value to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, the video encoder 200 may perform a bitwise right shift of the value to be quantized.

[0050] Following quantization, the video encoder 200 may scan the transform coefficients and generate a one-dimensional vector from the two-dimensional matrix including the quantized transform coefficients. The scan may be designed to place higher energy (and therefore lower frequency) transform coefficients at the front of the vector and lower energy (and therefore higher frequency) transform coefficients at the back of the vector. In some examples, the video encoder 200 may use a predefined scan order for scanning the quantized transform coefficients to generate a serialized vector and then entropy encode the quantized transform coefficients of the vector. In other examples, the video encoder 200 may perform adaptive scanning. After scanning the quantized transform coefficients to form the one-dimensional vector, the video encoder 200 may entropy encode the one-dimensional vector, for example, according to context-adaptive binary arithmetic coding (CABAC). The video encoder 200 may also entropy encode values ​​for syntax elements describing metadata associated with the encoded video data for use by the video decoder 300 in decoding the video data.

[0051] To implement CABAC, video encoder 200 may assign a context within a context model to a symbol to be transmitted. The context may relate, for example, to whether neighboring values ​​of the symbol are zeroed. A probability decision may be based on the context assigned to the symbol.

[0052] Video encoder 200 may further generate syntax data, such as block-based syntax data, picture-based syntax data, and sequence-based syntax data to video decoder 300, e.g., in a picture header, block header, slice header, or other syntax data, such as a sequence parameter set (SPS), picture parameter set (PPS), or video parameter set (VPS). Video decoder 300 may similarly decode such syntax data to determine how to decode the corresponding video data. Indeed, this disclosure contemplates decoder-side refinement control signaling that occurs in a parameter set associated with a portion or subset (e.g., some, but not all) of a video sequence. Such signaling may apply, for example, to a picture, frame, slice, sub-picture, video block, or another subset of video data within a larger sequence of video data. Thus, the decoder-side refinement control signaling may be controlled so that a first subset of video data associated with a video sequence (e.g., a first picture, slice, frame, sub-picture, block, or other subset of video data) is decoded with a different decoder-side refinement tool than a second subset of video data within the same video sequence (e.g., a different picture, slice, frame, block, sub-picture, or other subset of video data) that is different from the first subset of video data.

[0053] In this manner, video encoder 200 may generate coded video data, e.g., a bitstream including syntax elements that describe partitions of a picture into blocks (e.g., CUs) and prediction and / or residual information for the blocks. Finally, video decoder 300 may receive the bitstream and decode the coded video data. On / off signaling of decoder-side refinement tools can ensure that the decoder is properly configured to apply any desired decoder-side refinement, and the control may be more refined than conventional control.

[0054] In general, video decoder 300 performs a process that is the reverse of that performed by video encoder 200 to decode encoded video data of a bitstream. For example, video decoder 300 may decode values ​​for syntax elements of a bitstream using CABAC in a manner that is the reverse of, but substantially similar to, the CABAC encoding process of video encoder 200. The syntax elements may define picture partition information into CTUs and the partition of each CTU according to a corresponding partition structure, such as a QTBT structure, to define the CUs of the CTU. Furthermore, the syntax elements may enable precise (subsequence-level) control of whether decoder-side refinement tools are on or off for different portions of a video sequence. The syntax elements may further define prediction and residual information for blocks of video data (e.g., CUs).

[0055] The residual information may be represented, for example, by quantized transform coefficients. The video decoder 300 may dequantize and inverse transform the quantized transform coefficients of the block to reconstruct a residual block for the block. The video decoder 300 uses the signaled prediction mode (intra-prediction or inter-prediction) and associated prediction information (e.g., motion information for inter-prediction) to form a predictive block for the block. The video decoder 300 may then combine the predictive block and the residual block (sample by sample) to reconstruct the original block. The video decoder 300 may perform additional processing, such as performing a deblocking process to reduce visual artifacts along block boundaries.

[0056] According to the techniques of this disclosure, video encoder 200 and video decoder 300 may be configured to code a syntax element that indicates whether a decoder-side motion refinement mode is on or off for a subset of video data in a video sequence (e.g., a slice, a picture, a frame, a sub-picture, a block, or other subset), and video encoder 200 and video decoder 300 may be configured to code blocks of the video data subset based on the syntax element associated with that subset (e.g., a slice, a picture, a frame, a sub-picture, a block, or other subset).

[0057] This disclosure generally refers to “signaling” certain information, such as syntax elements. The term “signaling” may generally refer to communication of values ​​for syntax elements and / or other data used to decode encoded video data. That is, video encoder 200 may signal values ​​for syntax elements in a bitstream. Generally, signaling refers to generating values ​​in the bitstream. As mentioned above, source device 102 may transport the bitstream to destination device 116 substantially in real time or not in real time, such as may occur when storing syntax elements to storage device 112 for later retrieval by destination device 116. According to this disclosure, different syntax elements may be used to signal whether different decoder-side refinement tools are enabled, and syntax elements may be signaled multiple times for a video sequence to allow decoder-side refinement tools to be enabled or disabled for different subsets or portions of the video sequence (e.g., for different slices, pictures, frames, subpictures, or blocks of video data within a larger video sequence of video data).

[0058] 2A and 2B are conceptual diagrams illustrating an exemplary quadtree-binary tree (QTBT) structure 130 and a corresponding coding tree unit (CTU) 132. Solid lines represent quadtree splits, and dotted lines represent binary tree splits. At each split (i.e., non-leaf) node of the binary tree, one flag is signaled to indicate which split type (i.e., horizontal or vertical) is used, where, in this example, 0 indicates horizontal split and 1 indicates vertical split. In the case of quadtree splits, the quadtree node splits a block horizontally and vertically into four equal-sized sub-blocks, so there is no need to indicate the split type. Thus, the video encoder 200 can encode syntax elements (e.g., split information) for the region tree level (i.e., solid lines) of the QTBT structure 130 and syntax elements (e.g., split information) for the prediction tree level (i.e., dashed lines) of the QTBT structure 130, and the video decoder 300 can decode these syntax elements. The video encoder 200 may encode, and the video decoder 300 may decode, video data, such as prediction data and transform data, for the CUs represented by the terminal leaf nodes of the QTBT structure 130.

[0059] 2B may be associated with parameters that define the sizes of blocks corresponding to nodes of the QTBT structure 130 at the first and second levels. These parameters may include a CTU size (representing the size of the CTU 132 in the sample), a minimum quadtree size (MinQTSize, representing the minimum allowed quadtree leaf node size), a maximum binary tree size (MaxBTSize, representing the maximum allowed binary tree root node size), a maximum binary tree depth (MaxBTDepth, representing the maximum allowed binary tree depth), and a minimum binary tree size (MinBTSize, representing the minimum allowed binary tree leaf node size).

[0060] The root node of a QTBT structure corresponding to a CTU may have four child nodes at the first level of the QTBT structure, and each child node may be partitioned according to a quadtree partition. That is, a first-level node is either a leaf node (with no child nodes) or has four child nodes. The example QTBT structure 130 represents a node as including a parent node and child nodes with solid lines for branching. If a first-level node is not larger than the maximum allowed binary tree root node size (MaxBTSize), the node may be further partitioned by its respective binary tree. The binary tree split of a node may be repeated until the resulting node reaches the minimum allowed binary tree leaf node size (MinBTSize) or the maximum allowed binary tree depth (MaxBTDepth). The example QTBT structure 130 represents a node as including dashed lines for branching. The binary tree leaf nodes are called coding units (CUs), which are used for prediction (e.g., intra-picture prediction or inter-picture prediction) and transformation without further division. As discussed above, CUs may also be called "video blocks" or "blocks."

[0061] In one example of a QTBT partitioning structure, the CTU size is set as 128x128 (luma samples and two corresponding 64x64 chroma samples), MinQTSize is set as 16x16, MaxBTSize is set as 64x64, MinBTSize (for both width and height) is set as 4, and MaxBTDepth is set as 4. To generate a quadtree leaf node, quadtree partitioning is first applied to the CTU. The quadtree leaf node can have a size from 16x16 (i.e., MinQTSize) to 128x128 (i.e., CTU size). If the leaf quadtree node is 128x128, it is not further divided by the binary tree because its size exceeds MaxBTSize (i.e., 64x64 in this example). Otherwise, the leaf quadtree node is further partitioned by the binary tree. Therefore, the quadtree leaf node is also the root node of the binary tree and has the binary tree depth as 0. When the binary tree depth reaches MaxBTDepth (4 in this example), no further splits are allowed. When a binary tree node has a width equal to MinBTSize (4 in this example), it indicates that no further horizontal splits are allowed. Similarly, a binary tree node with a height equal to MinBTSize indicates that no further vertical splits are allowed for that binary tree node. As mentioned above, the leaf nodes of the binary tree are called CUs and are further processed according to the prediction and transformation without further partitioning.

[0062] 3 is a block diagram illustrating an example video encoder 200 that may implement the techniques of this disclosure. Figure 3 is provided for purposes of explanation and should not be considered a limitation of the techniques as broadly illustrated and described in this disclosure. For purposes of explanation, this disclosure describes video encoder 200 in the context of video coding standards such as the HEVC video coding standard and the developing H.266 video coding standard. However, the techniques of this disclosure are not limited to these video coding standards and are applicable to video encoding and decoding generally.

[0063] 3, video encoder 200 includes video data memory 230, mode select unit 202, residual generation unit 204, transform processing unit 206, quantization unit 208, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, filter unit 216, decoded picture buffer (DPB) 218, and entropy coding unit 220. Any or all of video data memory 230, mode select unit 202, residual generation unit 204, transform processing unit 206, quantization unit 208, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, filter unit 216, DPB 218, and entropy coding unit 220 may be implemented in one or more processors or processing circuitry. Furthermore, video encoder 200 may include additional or alternative processors or processing circuitry for performing these and other functions.

[0064] Video data memory 230 may store video data to be encoded by components of video encoder 200. Video encoder 200 may receive video data stored in video data memory 230, for example, from video source 104 (FIG. 1). DPB 218 may act as a reference picture memory that stores reference video data for use in predicting subsequent video data by video encoder 200. Video data memory 230 and DPB 218 may be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. Video data memory 230 and DPB 218 may be provided by the same memory device or separate memory devices. In various examples, video data memory 230 may be on-chip with other components of video encoder 200, as shown, or may be off-chip relative to those components.

[0065] In this disclosure, references to video data memory 230 should not be construed as limited to memory internal to video encoder 200, unless specifically described as such, or to memory external to video encoder 200, unless specifically described as such. Rather, references to video data memory 230 should be understood as a reference memory that stores video data that video encoder 200 receives for encoding (e.g., video data for the current block to be encoded). Memory 106 of FIG. 1 may also provide temporary storage of outputs from various units of video encoder 200.

[0066] The various units in FIG. 3 are illustrated to aid in understanding the operations performed by video encoder 200. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. A fixed-function circuit refers to a circuit that provides specific functionality and is preset for the operations that may be performed. A programmable circuit refers to a circuit that can be programmed to perform various tasks and provides flexible functionality in the operations that may be performed. For example, a programmable circuit may execute software or firmware that causes the programmable circuit to operate in a manner defined by the software or firmware instructions. A fixed-function circuit may execute software instructions (e.g., to receive or output parameters), but the types of operations that the fixed-function circuit performs are generally invariant. In some examples, one or more of the units may be separate circuit blocks (fixed function or programmable), and in some examples, one or more units may be integrated circuits.

[0067] Video encoder 200 may include an arithmetic logic unit (ALU), an elementary function unit (EFU), digital circuits, analog circuits, and / or a programmable core formed from programmable circuits. In examples in which the operations of video encoder 200 are implemented using software executed by programmable circuits, memory 106 (FIG. 1) may store object code for the software that video encoder 200 receives and executes, or another memory (not shown) within video encoder 200 may store such instructions.

[0068] The video data memory 230 is configured to store received video data. The video encoder 200 may retrieve pictures of the video data from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 may be raw video data to be encoded.

[0069] The mode select unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra prediction unit 226. The mode select unit 202 may include additional functional units for performing video prediction according to other prediction modes. By way of example, the mode select unit 202 may include a palette unit, an intra block copy unit (which may be part of the motion estimation unit 222 and / or the motion compensation unit 224), an affine unit, a linear model (LM) unit, etc.

[0070] Mode selection unit 202 typically coordinates multiple encoding passes to test combinations of encoding parameters and the resulting rate-distortion values ​​for such combinations. The encoding parameters may include partitioning of CTUs into CUs, prediction modes for CUs, transform types for residual data of CUs, quantization parameters for residual data of CUs, etc. Mode selection unit 202 may ultimately select a combination of encoding parameters that has a better rate-distortion value than the other tested combinations.

[0071] Video encoder 200 may partition a picture retrieved from video data memory 230 into a series of CTUs and encapsulate one or more CTUs within a slice. Mode select unit 202 may partition the CTUs of the picture according to a tree structure, such as the QTBT structure or quadtree structure of HEVC described above. As described above, video encoder 200 may form one or more CUs from partitioning the CTUs according to the tree structure. Such CUs may also be generally referred to as "video blocks" or "blocks."

[0072] Generally, the mode select unit 202 also controls its components (e.g., the motion estimation unit 222, the motion compensation unit 224, and the intra prediction unit 226) to generate a predictive block for a current block (e.g., the current CU, or in HEVC, the overlapping portion of the PU and TU). In the case of inter prediction of the current block, the motion estimation unit 222 may perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously coded pictures stored in the DPB 218). Specifically, the motion estimation unit 222 may calculate a value representing how similar a potential reference block is to the current block according to, for example, the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), etc. The motion estimation unit 222 may generally perform these calculations using the sample-by-sample differences between the current block and the reference block under consideration. Motion estimation unit 222 may identify the reference block having the lowest value resulting from these calculations, which indicates the reference block that most closely matches the current block.

[0073] The motion estimation unit 222 may form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to the position of the current block in the current picture. The motion estimation unit 222 may then provide the motion vectors to the motion compensation unit 224. For example, in the case of unidirectional inter prediction, the motion estimation unit 222 may provide a single motion vector, while in the case of bidirectional inter prediction, the motion estimation unit 222 may provide two motion vectors. The motion compensation unit 224 may then generate a predictive block using the motion vectors. For example, the motion compensation unit 224 may use the motion vectors to retrieve data of the reference block. As another example, if the motion vectors have fractional sample precision, the motion compensation unit 224 may interpolate values ​​for the predictive block according to one or more interpolation filters. Furthermore, in the case of bidirectional inter prediction, the motion compensation unit 224 may retrieve data for the two reference blocks identified by the respective motion vectors and combine the retrieved data, for example, by sample-wise averaging or weighted averaging.

[0074] As another example, in the case of intra prediction or intra predictive coding, the intra prediction unit 226 may generate a predictive block from samples neighboring the current block. For example, in the case of a directional mode, the intra prediction unit 226 may generally mathematically combine the values ​​of neighboring samples and apply these calculated values ​​in a defined direction across the current block to generate a predictive block. As another example, in the case of a DC mode, the intra prediction unit 226 may calculate an average of neighboring samples for the current block and generate a predictive block to include this resulting average for each sample of the predictive block.

[0075] The mode select unit 202 provides the predictive block to the residual generation unit 204. The residual generation unit 204 receives a raw, uncoded version of the current block from the video data memory 230 and receives the predictive block from the mode select unit 202. The residual generation unit 204 calculates sample-by-sample differences between the current block and the predictive block. The resulting sample-by-sample differences define a residual block for the current block. In some examples, the residual generation unit 204 may also determine differences between sample values ​​in the residual block to generate the residual block using residual differential pulse code modulation (RDPCM). In some examples, the residual generation unit 204 may be formed using one or more subtractor circuits that perform binary subtraction.

[0076] In examples in which mode select unit 202 partitions CUs into PUs, each PU may be associated with a luma prediction unit and a corresponding chroma prediction unit. Video encoder 200 and video decoder 300 may support PUs with various sizes. As indicated above, the size of a CU may refer to the size of the luma coding block of the CU, and the size of a PU may refer to the size of the luma prediction unit of the PU. Assuming that the size of a particular CU is 2N×2N, video encoder 200 may support a PU size of 2N×2N or N×N for intra prediction, and a symmetric PU size of 2N×2N, 2N×N, N×2N, N×N, or similar for inter prediction. Video encoder 200 and video decoder 300 may also support asymmetric partitioning for PU sizes of 2N×nU, 2N×nD, nL×2N, and nR×2N for inter prediction.

[0077] In examples where the mode select unit does not further partition CUs into PUs, each CU may be associated with a luma coding block and a corresponding chroma coding block. As described above, the size of a CU may refer to the size of the luma coding block of the CU. Video encoder 200 and video decoder 120 may support CU sizes of 2N×2N, 2N×N, or N×2N.

[0078] In other video coding techniques, such as intra-block copy mode coding, affine mode coding, and linear model (LM) mode coding, as a few examples, mode select unit 202 generates a predictive block for the current block being coded via a respective unit associated with the coding technique. In some examples, such as palette mode coding, mode select unit 202 may not generate a predictive block, but instead may generate syntax elements that indicate how to reconstruct the block based on a selected palette. In such modes, mode select unit 202 may provide these syntax elements to entropy coding unit 220 to be coded.

[0079] As described above, the residual generation unit 204 receives video data for a current block and a corresponding predictive block. The residual generation unit 204 then generates a residual block for the current block. To generate the residual block, the residual generation unit 204 calculates sample-by-sample differences between the predictive block and the current block.

[0080] Transform processing unit 206 applies one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a "transform coefficient block"). Transform processing unit 206 may apply various transforms to the residual block to form the transform coefficient block. For example, transform processing unit 206 may apply a discrete cosine transform (DCT), a directional transform, a Karhunen-Loeve transform (KLT), or a conceptually similar transform to the residual block. In some examples, transform processing unit 206 may perform multiple transforms, e.g., a linear transform and a quadratic transform, such as a rotation transform, on the residual block. In some examples, transform processing unit 206 does not apply a transform to the residual block.

[0081] The quantization unit 208 may quantize the transform coefficients in the transform coefficient block to generate a quantized transform coefficient block. The quantization unit 208 may quantize the transform coefficients of the transform coefficient block according to a quantization parameter (QP) value associated with the current block. The video encoder 200 (e.g., via the mode select unit 202) may adjust the degree of quantization applied to the transform coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization may result in loss of information, and therefore, the quantized transform coefficients may be less accurate than the original transform coefficients generated by the transform processing unit 206.

[0082] The inverse quantization unit 210 and the inverse transform processing unit 212 may apply inverse quantization and inverse transform, respectively, to the quantized transform coefficient block to reconstruct a residual block from the transform coefficient block. The reconstruction unit 214 may generate a reconstructed block that corresponds to the current block (possibly with some distortion) based on the reconstructed residual block and the predictive block generated by the mode select unit 202. For example, the reconstruction unit 214 may add samples of the reconstructed residual block to corresponding samples from the predictive block generated by the mode select unit 202 to generate the reconstructed block.

[0083] Filter unit 216 may perform one or more filter operations on the reconstructed block. For example, filter unit 216 may perform a deblocking operation to reduce blockiness artifacts along the edges of a CU. The operations of filter unit 216 may be skipped in some examples.

[0084] Video encoder 200 stores the reconstructed blocks in DPB 218. For example, in examples where the operation of filter unit 216 is not required, reconstruction unit 214 may store the reconstructed blocks in DPB 218. In examples where the operation of filter unit 216 is required, filter unit 216 may store the filtered reconstructed blocks in DPB 218. Motion estimation unit 222 and motion compensation unit 224 may retrieve reference pictures from DPB 218, formed from the reconstructed (and possibly filtered) blocks, to inter-predict blocks of a later-encoded picture. Additionally, intra-prediction unit 226 may use reconstructed blocks in DPB 218 of the current picture to intra-predict other blocks in the current picture.

[0085] In general, entropy encoding unit 220 may entropy encode syntax elements received from other functional components of video encoder 200. For example, entropy encoding unit 220 may entropy encode quantized transform coefficient blocks from quantization unit 208. As another example, entropy encoding unit 220 may entropy encode predictive syntax elements (e.g., motion information for inter-prediction or intra-mode information for intra-prediction) from mode select unit 202. Entropy encoding unit 220 may perform one or more entropy encoding operations on syntax elements, which are another example of video data, to generate entropy-encoded data. For example, entropy encoding unit 220 may perform a context-adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable-to-variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a probability interval partitioned entropy (PIPE) coding operation, an exponential-Golomb coding operation, or another type of entropy coding operation on the data. In some examples, entropy encoding unit 220 may operate in a bypass mode in which syntax elements are not entropy coded.

[0086] Video encoder 200 may output a bitstream that includes entropy coding syntax elements needed to reconstruct blocks of a slice or picture. Specifically, entropy coding unit 220 may output the bitstream.

[0087] The operations described above are described with respect to blocks. Such descriptions should be understood as operations for luma coding blocks and / or chroma coding blocks. As described above, in some examples, the luma coding blocks and chroma coding blocks are luma and chroma components of a CU. In some examples, the luma coding blocks and chroma coding blocks are luma and chroma components of a PU.

[0088] In some examples, operations performed with respect to luma coding blocks need not be repeated for chroma coding blocks. As one example, operations for identifying motion vectors (MVs) and reference pictures for luma coding blocks need not be repeated to identify MVs and reference pictures for chroma blocks. Rather, MVs for luma coding blocks may be scaled to determine MVs for chroma blocks, and the reference pictures may be the same. As another example, the intra prediction process may be the same for luma coding blocks and chroma coding blocks.

[0089] Video encoder 200 represents an example of a device configured to encode video data, including a memory configured to store video data and one or more processing units implemented in circuitry and configured to code a syntax element (e.g., at the slice level, picture level, sub-picture level, frame level, or block level) that indicates whether a decoder-side motion refinement mode is on or off for a subset of video data in a video sequence, and to code blocks of video data in the subset of video data based on the syntax element.

[0090] According to some examples, decoder-side refinement signaling (e.g., on / off control for a subset of a video sequence) may be performed by mode select unit 202 and applied as part of the decoding loop during the encoding process, possibly by motion estimation unit 222 and motion compensation unit 224. For example, enabling or disabling of a DMVR tool may be signaled by mode select unit 202 by outputting a value indicating DMVR on or off to entropy encoding unit 220. Similarly, enabling or disabling of a BDOF tool may be signaled by mode select unit 202 by outputting a value indicating BDOF on or off to entropy encoding unit 220. However, other types of decoder-side refinement that may be enabled or disabled as described herein may be enabled by other units, such as intra prediction unit 226 and / or filter unit 216.

[0091] In some examples, video encoder 200 may be configured to encode a sequence of video data including a plurality of pictures. In doing so, video encoder 200 (specifically, motion compensation unit 224 and entropy coding unit 220) may be configured to: encode a first instance of a first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data within the sequence of video data; and encode a second instance of the first syntax element to identify whether the first decoder-side refinement tool is enabled or disabled for a second subset of video data within the sequence of video data, the second subset being different from the first subset. Furthermore, video encoder 200 (specifically, motion compensation unit 224 and entropy coding unit 220) may be further configured to encode a first instance of a second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for a first subset of video data within the sequence of video data, and to encode a second instance of the second syntax element to identify whether the second decoder-side refinement tool is enabled or disabled for a second subset of video data within the sequence of video data. In this manner, on / off control of two different decoder-side refinement tools may be enabled or disabled in the coded bitstream for different subsets of the coded video sequence. Video data memory 230 may include a memory configured to store a sequence of video data including a plurality of pictures, and motion compensation unit 224 and entropy coding unit 220 may comprise processing circuitry configured to perform encoding and determinations associated with the decoder-side refinement tools.

[0092] 4 is a block diagram illustrating an example video decoder 300 that may implement the techniques of this disclosure. Figure 4 is provided for purposes of explanation and does not limit the techniques as broadly illustrated and described in this disclosure. For purposes of explanation, this disclosure describes a video decoder 300 in accordance with JEM, VVC, and HEVC techniques. However, the techniques of this disclosure may be implemented by video coding devices configured according to other video coding standards.

[0093] 4, the video decoder 300 includes a coded picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filter unit 312, and a decoded picture buffer (DPB) 314. Any or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the filter unit 312, and the DPB 314 may be implemented in one or more processors or processing circuitry. Furthermore, the video decoder 300 may include additional or alternative processors or processing circuitry for performing these and other functions.

[0094] Prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. Prediction processing unit 304 may include additional units for performing prediction according to other prediction modes. By way of example, prediction processing unit 304 may include a palette unit, an intra block copy unit (which may form part of motion compensation unit 316), an affine unit, a linear model (LM) unit, etc. In other examples, video decoder 300 may include more, fewer, or different functional components.

[0095] CPB memory 320 may store video data, such as an encoded video bitstream, to be decoded by components of video decoder 300. The video data stored in CPB memory 320 may be retrieved, for example, from computer-readable medium 110 (FIG. 1). CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from the encoded video bitstream. CPB memory 320 may also store video data other than syntax elements of coded pictures, such as temporary data representing output from various units of video decoder 300. DPB 314 generally stores decoded pictures that video decoder 300 may output and / or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. CPB memory 320 and DPB 314 may be formed by any of a variety of memory devices, such as DRAM, including SDRAM, MRAM, RRAM, or other types of memory devices. CPB memory 320 and DPB 314 may be provided by the same memory device or separate memory devices. In various examples, the CPB memory 320 may be on-chip with other components of the video decoder 300, or may be off-chip relative to those components.

[0096] Additionally or alternatively, in some examples, video decoder 300 may retrieve coded video data from memory 120 (FIG. 1). That is, memory 120 may store data such as those described above with respect to CPB memory 320. Similarly, memory 120 may store instructions to be executed by video decoder 300 when some or all of the functionality of video decoder 300 is implemented in software to be executed by processing circuitry of video decoder 300. In some examples, decoder-side refinement (when enabled) is performed by a unit within video decoder 300, such as prediction processing unit 304, motion compensation unit 316, intra-prediction unit 318, and / or filter unit 312. For example, DMVR, when enabled, may be performed by motion compensation unit 316, and BDOF, when enabled, may be performed by the motion compensation unit. In other examples, other types of decoder-side refinement, which may be enabled or disabled as described herein, may be performed by the motion compensation unit 316 or by other units, such as the intra prediction unit 318 and / or the filter unit 312.

[0097] The various units shown in FIG. 4 are illustrated to aid in understanding the operations performed by video decoder 300. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. As with FIG. 3, fixed-function circuits refer to circuits that provide specific functionality and are preset for the operations that may be performed. Programmable circuits refer to circuits that may be programmed to perform various tasks and provide flexible functionality in the operations that may be performed. For example, a programmable circuit may execute software or firmware that causes the programmable circuit to operate in a manner defined by the software or firmware instructions. While a fixed-function circuit may execute software instructions (e.g., to receive or output parameters), the types of operations that the fixed-function circuit performs are generally invariant. In some examples, one or more of the units may be separate circuit blocks (fixed function or programmable), and in some examples, one or more units may be integrated circuits.

[0098] The video decoder 300 may include a programmable core formed from an ALU, an EFU, digital circuits, analog circuits, and / or programmable circuits. In examples in which the operations of the video decoder 300 are performed by software executing on programmable circuits, on-chip or off-chip memory may store instructions (e.g., object code) of the software that the video decoder 300 receives and executes.

[0099] The entropy decoding unit 302 may receive the encoded video data from the CPB and entropy decode the video data to recover the syntax elements. The prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, and the filter unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0100] In general, video decoder 300 reconstructs a picture on a block-by-block basis. Video decoder 300 may perform a reconstruction operation on each block individually (here, the block currently being reconstructed, i.e., decoded, may be referred to as the “current block”).

[0101] The entropy decoding unit 302 may entropy decode the quantized transform coefficients of the quantized transform coefficient block as well as syntax elements defining transform information, such as a quantization parameter (QP) and / or a transform mode indication. The inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine the degree of quantization and, similarly, the degree of inverse quantization to apply. The inverse quantization unit 306 may, for example, perform a bitwise left-shift operation to inverse quantize the quantized transform coefficients. The inverse quantization unit 306 may thereby form a transform coefficient block including the transform coefficients.

[0102] After the inverse quantization unit 306 forms the transform coefficient block, the inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, the inverse transform processing unit 308 may apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve transform (KLT), an inverse rotational transform, an inverse transform, or another inverse transform to the coefficient block.

[0103] Further, prediction processing unit 304 generates a predictive block according to the prediction information syntax element entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax element indicates that the current block is inter-predicted, motion compensation unit 316 may generate a predictive block. In this case, the prediction information syntax element may indicate a reference picture in DPB 314 from which to retrieve a reference block, as well as a motion vector that identifies the location of the reference block in the reference picture relative to the location of the current block in the current picture. Motion compensation unit 316 may generally perform the inter-prediction process in a manner substantially similar to that described with respect to motion compensation unit 224 (FIG. 3).

[0104] As another example, if the prediction information syntax element indicates that the current block is intra-predicted, intra prediction unit 318 may generate a predictive block according to the intra-prediction mode indicated by the prediction information syntax element. Again, intra prediction unit 318 may generally perform the intra-prediction process in a manner substantially similar to that described with respect to intra prediction unit 226 (FIG. 3). Intra prediction unit 318 may retrieve data of neighboring samples for the current block from DPB 314.

[0105] The reconstruction unit 310 may reconstruct the current block using the predictive block and the residual block. For example, the reconstruction unit 310 may add samples of the residual block to corresponding samples of the predictive block to reconstruct the current block.

[0106] Filter unit 312 may perform one or more filter operations on the reconstructed blocks. For example, filter unit 312 may perform a deblocking operation to reduce blockiness artifacts along the edges of the reconstructed blocks. The operations of filter unit 312 may not be performed in all instances.

[0107] Video decoder 300 may store the reconstructed blocks in DPB 314. As described above, DPB 314 may provide reference information to prediction processing unit 304, such as samples of the current picture for intra prediction and previously decoded pictures for subsequent motion compensation. Additionally, video decoder 300 may output decoded pictures from DPB 314 for later presentation on a display device, such as display device 118 of FIG. 1.

[0108] Thus, the video decoder 300 represents an example of a video decoding device that includes a memory configured to store video data and one or more processing units implemented in a circuit configuration and configured to code a syntax element (e.g., at the slice level, picture level, sub-picture level, frame level, or block level) that indicates whether a decoder-side motion refinement mode is on or off for a subset of video data within a video sequence, and to code blocks of video data in the subset of video data based on the syntax element.

[0109] For example, the video decoder 300 (specifically, the entropy decoding unit 302 and the motion compensation unit 316) may be configured to: decode a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in a sequence of video data; determine, based on the value of the first syntax element, whether the first decoder-side refinement tool is enabled or disabled for the first subset of video data; decode a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data in the sequence of video data; and determine, based on the value of the first syntax element, whether the second decoder-side refinement tool is enabled or disabled for the first subset of video data. The video decoder 300 (specifically, the entropy decoding unit 302 and the motion compensation unit 316) may decode a first subset of the video data using a first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the first subset, decode the first subset of the video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the first subset, decode the first subset of the video data using a second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the first subset, and decode the first subset of the video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the first subset. The CPB memory 320 may include memory configured to store a sequence of video data including a plurality of pictures, and the entropy decoding unit 302 and the motion compensation unit 316 may include processing circuitry configured to perform decoding and decisions associated with decoder-side refinement tools.

[0110] Bidirectional Optical Flow (BDOF) Bidirectional Optical Flow (BDOF) mode, formerly known as BIO, is a tool that can be used to refine the bi-predictive signal of a coding unit (CU) at the 4x4 sub-block level. As the name suggests, BDOF mode is based on the optical flow concept, which assumes that object motion is smooth. For each 4x4 sub-block, video encoder 200 and video decoder 300 perform motion refinement (vDOF) by minimizing the difference between the L0 and L1 prediction samples. x ,v y ) Video encoder 200 and video decoder 300 may then use motion refinement to adjust the bi-predictive sample values ​​in the 4x4 sub-blocks.

[0111] The following steps may be applied in the BDOF process: First, the video encoder 200 and the video decoder 300 calculate the horizontal and vertical gradients of the two prediction signals with k=0,1, i.e.

[0112]

number

[0113] Let,be two adjacent samples, i.e.,,

[0114]

number

[0115] It can be calculated by directly calculating the difference between (k) (i,j) is the sample value at coordinate (i,j) of the predicted signal in list k, where k=0,1.

[0116] Then, the video encoder 200 and the video decoder 300 calculate the gradients, i.e., the auto- and cross-correlations of S1, S2, S3, S5 and S6, as

[0117]

number

[0118] It can be calculated as follows:

[0119]

number

[0120] where Ω is a 6×6 window around the 4×4 sub-block.

[0121] The video encoder 200 and the video decoder 300 then use the cross- and autocorrelation terms to refine the motion (v x ,v y ) into the formula

[0122]

number

[0123] can be derived using the above formula,

[0124]

number

[0125] is the floor function.

[0126] Based on the motion refinement and gradients, video encoder 200 and video decoder 300 may calculate the following adjustments for each sample in the 4x4 sub-block:

[0127]

number

[0128] Finally, video encoder 200 and video decoder 300 may calculate the BDOF samples of the CU by adjusting the bi-predictive samples as follows: pred BDOF (x,y)=(I (0) (x,y)+I (1) (x,y)+b(x,y)+ο offset )≫shift

[0129] These values ​​are chosen so that the multipliers in the BDOF process do not exceed 15 bits and the maximum bit width of the intermediate parameters in the BDOF process is kept within 32 bits.

[0130] To derive the gradient values, video encoder 200 and video decoder 300 select a number of prediction samples I in list k (k=0, 1) outside the current CU boundary. (k) (i,j). Figure 5 is a conceptual diagram showing an extended coding unit region 501 used in bidirectional optical flow. As shown in Figure 5, BDOF in VVC Test Model 4.0 (VTM4) uses one extended row / column around the boundary of a CU. To control the computational complexity of generating out-of-bounds predicted samples, the video encoder 200 and video decoder 300 may generate predicted samples in the extended area (white positions) by directly taking reference samples at nearby integer positions (using the floor() operation on the coordinates) without interpolation, and a standard 8-tap motion compensation interpolation filter is used to generate predicted samples within the CU (gray positions). In some examples, the video encoder 200 and video decoder 300 may only use these extended sample values ​​in gradient calculations. For the remaining steps in the BDOF process, if any samples and gradient values ​​outside the CU boundary are needed, the video encoder 200 and video decoder 300 may pad (e.g., repeat) the samples and gradient values ​​from their nearest neighbors.

[0131] In one example of a VTM, video encoder 200 and video decoder 300 may be configured to apply BDOF for a CU being coded under the following conditions: ·Bi-predictive MV Bi-prediction is equal weighting for both directions For the current picture, one reference picture is in the past and another is in the future. The CU has an additional 64 luma samples, and the height of the CU is at least 8 luma samples.

[0132] Decoder-side Motion Vector Refinement (DMVR) To increase the accuracy of the merge mode MV, the video encoder 200 and the video decoder 300 may be configured to apply bidirectional matching-based decoder-side motion vector refinement. In some examples, the video encoder 200 may apply the decoder-side motion vector refinement technique in the reconstruction loop. In a bi-predictive operation, the video decoder 300 may be configured to search for a refined MV around an initial MV in the reference picture list L0 and the reference picture list L1. The video decoder 300 may use a block matching method to calculate the distortion between two candidate blocks in the reference picture list L0 and the list L1. Figure 6 is a conceptual diagram illustrating an example of decoder-side motion vector refinement.

[0133] 6, the video decoder 300 can calculate the sum of absolute differences (SAD) between blocks labeled 601 and 602 based on each MV candidate around the initial MV. The MV candidate with the lowest SAD becomes the refined MV and is used by the video decoder 300 to generate the bi-predictive signal.

[0134] In one example of a VTM, DMVR is applied for CUs coded with the following conditions: CU level merge mode with bi-predictive MV Bi-prediction is equal weighting for both directions For the current picture, one reference picture is in the past and another is in the future. The distance from both reference pictures to the current picture (i.e., the POC difference) is the same A CU has an additional 64 luma samples, and the height of the CU is greater than 8 luma samples

[0135] Merge Mode by Motion Vector Difference (MMVD) In addition to the merge mode in which implicitly derived motion information is directly used for predictive sample generation of the current CU, a merge mode by motion vector difference (MMVD) is introduced in VVC. Video encoder 200 may be configured to signal an MMVD flag after sending a skip flag and a merge flag to specify whether the MMVD mode is used for a CU.

[0136] In MMVD, after a merge candidate is selected, video encoder 200 and video decoder 300 may further refine the merge candidate using the signaled MVD information. The additional information includes a merge candidate flag, an index for specifying the motion magnitude, and an index for indicating the motion direction. In MMVD mode, video encoder 200 and video decoder 300 may select one of the first two candidates in the merge list to be used as the MV basis. Video encoder 200 signals a merge candidate flag to specify which one to use. Video decoder 300 decodes the flag to determine which merge candidate to use.

[0137] The distance index (IDX) specifies motion magnitude information and indicates a predefined offset from the starting point. Figure 7 is a conceptual diagram illustrating an example merge mode using a motion vector difference search point. The search point may be defined at a center point shown in L0 reference 701 and / or at a center point shown in L1 reference 702. As shown in Figure 7, the offset is added to either the horizontal or vertical component of the starting MV. The relationship between the distance index and the predefined offset is specified in Table 1-1.

[0138] [Table 1]

[0139] The direction index (IDX) represents the direction of the MVD relative to the starting point. The direction index can represent four directions as shown in Table 1-2. The meaning of the MVD code can change depending on the information of the starting MV. When the starting MV is a uni-predictive MV or a bi-predictive MV with both lists pointing to the same side of the current picture (i.e., the POCs of the two references are both greater than the POC of the current picture or both less than the POC of the current picture), the code in Table 1-2 specifies the sign of the MV offset added to the starting MV. When the starting MV is a bi-predictive MV with two MVs pointing to different sides of the current picture (i.e., the POC of one reference is greater than the POC of the current picture and the POC of the other reference is less than the POC of the current picture), the code in Table 1-2 specifies the sign of the MV offset added to the list0 MV component of the starting MV, and the code for the list1 MV has the opposite value.

[0140] [Table 2]

[0141] The decoder-side motion refinement tools described above may improve compression efficiency. However, the use of decoder-side motion refinement tools also increases encoding / decoding complexity. In this disclosure, techniques for on / off control of decoder-side motion refinement tools are disclosed to provide options for implementers to select the best trade-off between complexity and compression efficiency in different applications.

[0142] This disclosure generally describes on / off controls applied to subsets of video data within a video sequence. Thus, according to this disclosure, controls of different decoder-side refinement tools may be enabled or disabled for different subsets or portions of a video sequence, such as slices of video data, frames of video data, pictures of video data, sub-pictures of video data, or blocks of video data within a video sequence. In this manner, greater flexibility is provided between the conflicting goals of reducing decoding complexity and increasing compression efficiency in different video applications or settings. The subset of a video sequence may, for example, include at least a portion of a first picture among multiple pictures of a sequence of video data.

[0143] A slice may refer to a portion or subset of video data. A slice may include an entire picture of a video sequence or a portion thereof. A video sequence may include multiple pictures. A subset of a video sequence may include, for example, at least a portion of a first picture among multiple pictures of a sequence of video data, e.g., an entire picture or frame, some but not all of a picture of a sequence, a portion of a picture of a sequence, a slice (which may include some or all of a picture), a set of blocks, or an individual video block. Control may be provided at any of these different levels in accordance with this disclosure, so long as the control may enable different portions of a video sequence to apply different decoder-side refinements.

[0144] Slice Level Control In one example of this disclosure, the video encoder 200 and the video decoder 300 may be configured to code slice-level on / off control. That is, the video encoder 200 and the video decoder 300 may be configured to apply (i.e., turn on) or not apply (i.e., turn off) one or more decoder-side motion refinement techniques (e.g., DMVR, BDOF, etc.) at the slice level. Similar techniques for slice-level control may be applied to other subportions of a sequence.

[0145] In one example, the video encoder 200 and the video decoder 300 may code a first syntax element (e.g., a flag) in the slice header to indicate the on / off status of the DMVR in the slice, and the video encoder 200 and the video decoder 300 may code a second syntax element (e.g., a flag) in the slice header to indicate the on / off status of the BDOF in the slice, or vice versa.

[0146] In another example, video encoder 200 and video decoder 300 may code one syntax element (eg, a flag) in the slice header to indicate the on / off status of both DMVR and BDOF in the slice.

[0147] In yet another example, video encoder 200 and video decoder 300 may code only one syntax element (e.g., a flag) in the slice header to indicate the on / off status of DMVR in the slice. BDOF on / off control at the slice level is not available. That is, BDOF is not turned on / off at the slice level in this example.

[0148] In yet another example, video encoder 200 and video decoder 300 may code only one syntax element (e.g., a flag) in the slice header to indicate the on / off status of BDOF in the slice. DMVR on / off control at the slice level is not available. That is, DMVR is not turned on / off at the slice level in this example. A slice may refer to an entire picture or a subset or portion of a picture.

[0149] Block-Level Control In yet another example, video encoder 200 and video decoder 300 may code syntax elements at the block level for more precise control. As outlined below, several different methods may be used.

[0150] Block-level on / off flags In one example, video encoder 200 and video decoder 300 may code a flag for a merge mode CU (ie, a CU coded using merge mode) to indicate the on / off status of the DMVR.

[0151] In one variation of the above technique, video encoder 200 and video decoder 300 may code a flag for a merge mode CU to indicate the on / off status of both DMVR and BDOF.

[0152] In another variation of the above technique, video encoder 200 and video decoder 300 may code a flag to indicate DMVR (or BDOF) on / off status only if the merge candidate index is within some certain range. In one example, the range may be from 0 to N, where N may be 1, 2, 3, 4, etc. In another example, the range may be N to the maximum allowed index, where N may be 1, 2, 3, 4, etc.

[0153] In another example, the DMVR on / off flag (also referred to as an enable flag) and the BDOF on / off (enable) flag may be part of the motion information and are borrowed (e.g., reused) as motion vector candidates from neighboring blocks. When artificial motion vector candidates are derived, the video encoder 200 and the video decoder 300 may, in one example, set these flags to 0.

[0154] In other examples, rather than block-level or slice-level control, control may be provided for other defined subsets of video data within a larger video sequence, for example, for a set of pictures (but only a portion of a video sequence), for an individual picture, for a frame of video data, for a sub-picture or portion of a picture, for a slice, for a block, or for another subset of video data within a larger video sequence.

[0155] Zero MVD for MMVD mode In another example, video encoder 200 and video decoder 300 may implement block-level on / off control by enabling zero MVD for MMVD mode. Currently, DMVR is not applied when a block is coded in MMVD mode. Therefore, when MVD for MMVD mode is zero, it is equivalent to standard merge mode without DMVR. The same idea may be applied to the BDOF case. That is, BDOF is not used with zero MVD in MMVD mode.

[0156] When zero MVD for MMVD mode is applied, video encoder 200 and video decoder 300 may modify the relationship between the distance index and the predetermined offset so that the first index indicates a zero offset, and the indexes of other offset values ​​are increased by 1 accordingly. An example of the modified table is shown in Table 2-1 (Table 3). Note that the signaling of the distance index does not need to be changed. However, when zero MVD is applied and the signaled distance index is 0, video encoder 200 and video decoder 300 may not need to code a direction index because zero MVD has no direction.

[0157] [Table 3]

[0158] Adaptive Zero MVD for MMVD Mode In another example of this disclosure, video encoder 200 and video decoder 300 may adaptively apply zero MVD in MMVD mode according to block size and / or slice type.

[0159] For P or low delay coding slices where DMVR cannot be applied, video encoder 200 and video decoder 300 may not apply zero MVD to the MMVD mode. Similarly, if the size of the block does not satisfy the size constraint, DMVR is not applied to the block. In this example, video encoder 200 and video decoder 300 may not apply zero MVD to the MMVD mode for the block.

[0160] The same techniques described above may be applied for the BDOF mode.

[0161] BDOF In some examples, the zero MVD may also be used to control BDOF. For example, when the zero MVD is applied, the video encoder 200 and the video decoder 300 may not implement BDOF.

[0162] redundancy removal In another example of this disclosure, video encoder 200 and video decoder 300 may apply zero MVD on a selected base merge candidate. Even if the current slice is a B slice and the current block satisfies the size constraint, the base merge candidate may not satisfy all DMVR conditions. Therefore, DMVR is not guaranteed for the corresponding merge candidate. When zero MVD is applied to a base merge candidate, it may be identical to the merge candidate in the normal merge mode. It is proposed to remove those redundant MMVD candidates by modifying them. For example, video encoder 200 and video decoder 300 may be configured to change the prediction direction, reference picture / index, and motion vector.

[0163] Redundancy may also exist in the method described above with respect to the block-level on / off flag. For example, when a CU-level flag is on, the flag indicates that DMVR and / or BDOF may be applied to the current CU. However, some merge candidates may not satisfy all DMVR / BDOF conditions. Therefore, if that candidate is chosen, you will end up with the same result regardless of whether the CU-level flag is on or off.

[0164] Accordingly, additional examples of redundancy removal are described below. The following techniques may be applied with any combination of the block-level on / off flag techniques described above, the zero MVD techniques for MMVD modes described above, or with any other block-level DMVR / BDOF on / off control techniques.

[0165] Uni-predictive to bi-predictive conversion In another example of this disclosure, if the selected base merge candidate is uni-predictive, the video encoder 200 and the video decoder 300 may convert the selected base merge candidate to bi-predictive for redundancy removal.

[0166] In one example, video encoder 200 and video decoder 300 may perform conversion by mirroring unidirectional motion. In one example, if the unidirectional motion vector is MV0, the reference list is L0, and the reference index is refIdx0, then the mirrored motion vector in the other list is MV1=-MV0, the reference list is L1, and the reference index is refIdx1=refIdx0. In another example, the mirrored reference index is always 0, and the mirrored motion vector is scaled according to the POC distance between the current picture and the reference picture indicated by refIdx0 in L0 and reference index 0 in L1.

[0167] Adding a new distance offset value In some examples, if the selected base merge candidate is bi-predicted but does not meet the DMVR condition, video encoder 200 and video decoder 300 may interpret distance index 0 as a new distance offset value that is not present in the MMVD offset table, such as 1 / 8, 1 / 16, etc.

[0168] Instead of converting uni-prediction to bi-prediction, the method of adding a new offset value may be applied to base merge candidates that are uni-prediction.

[0169] Bi-predictive to uni-predictive conversion In another example of removing redundancy for bi-predictive base merge candidates, video encoder 200 and video decoder 300 may convert the bi-predictive base merge candidate to uni-prediction, for example, L0 / L1 motion is discarded if the selected base merge candidate is bi-predictive but does not satisfy the DMVR condition.

[0170] Conversion between unequal weight biprediction and equal weight biprediction In some cases, video encoder 200 and video decoder 300 may not perform DMVR on bi-predictive merge candidates if the weighting parameters for the two directions are unequal. When unequal weight bi-prediction is allowed in MMVD and zero MVD is applied, video encoder 200 and video decoder 300 may convert unequal weight bi-predictive based merge candidates to equal weight bi-predictive based merge candidates, and video encoder 200 and video decoder 300 may convert equal weight bi-predictive based merge candidates to unequal weight bi-predictive based merge candidates.

[0171] In some cases, sequence-level control may determine whether one or more decoder-side refinement tools are available for a large video sequence, and lower-level control (e.g., for subsets of the sequence) may allow decoder-side refinement tools to be controlled on or off for different subsets within the video sequence.

[0172] 8 is a flowchart illustrating an example method for encoding a current block. The current block may include a current CU. Although described with respect to video encoder 200 (FIGS. 1 and 3), it should be understood that other devices may be configured to implement a method similar to that of FIG.

[0173] In this example, video encoder 200 first predicts the current block (350). For example, video encoder 200 may form a predictive block for the current block. Then, video encoder 200 may calculate a residual block for the current block (352). To calculate the residual block, video encoder 200 may calculate a difference between the original uncoded block and the predictive block for the current block. Then, video encoder 200 may transform and quantize the coefficients of the residual block (354). Next, video encoder 200 may scan the quantized transform coefficients of the residual block (356). During or following the scan, video encoder 200 may entropy code the coefficients (358). For example, video encoder 200 may code the coefficients using CAVLC or CABAC. Then, video encoder 200 may output entropy-coded data for the block (360).

[0174] 8, the encoding process (such as predicting the current block (350)) may include steps for enabling or disabling decoder-side refinement. Accordingly, the encoding process may include steps for encoding syntax elements, as described herein, to enable or disable such decoder-side refinement tools for different subsets or portions of a larger video sequence.

[0175] 9 is a flowchart illustrating an example method for decoding a current block of video data. The current block may include a current CU. Although described with respect to video decoder 300 (FIGS. 1 and 4), it should be understood that other devices may be configured to implement methods similar to that of FIG.

[0176] The video decoder 300 may receive entropy-coded data for the current block, such as entropy-coded prediction information and entropy-coded data for the coefficients of the residual block corresponding to the current block (370). The video decoder 300 may entropy decode the entropy-coded data to determine prediction information for the current block and to reconstruct the coefficients of the residual block (372). The video decoder 300 may predict the current block using, for example, an intra-prediction mode or an inter-prediction mode as indicated by the prediction information for the current block, to calculate a predictive block for the current block (374). The video decoder 300 may then inverse scan the reconstructed coefficients to create a block of quantized transform coefficients (376). The video decoder 300 may then inverse quantize and inverse transform the coefficients to produce a residual block (378). The video decoder 300 may finally decode the current block by combining the predictive block and the residual block (380).

[0177] In some examples consistent with Figure 9, the decoding process (such as predicting the current block (374)) may include application of one or more decoder-side refinement tools. Accordingly, the decoding process may include steps for decoding syntax elements as described herein that allow for enabling or disabling decoder-side refinement tools for different subsets or portions of a larger video sequence. Figures 10 and 11 provide some additional detail on examples for decoding and encoding different subsets of video data within a larger video sequence, where the different subsets (e.g., different slices, different pictures, different sub-pictures, different frames, different sets of pictures, different blocks, or other different subsets) have decoder-side refinement tools separately enabled or disabled.

[0178] As shown in FIG. 10, the video decoder 300 may include processing circuitry configured to decode a first syntax element (402) and determine whether a first decoder-side refinement tool is enabled or disabled for the subset of video data based on a value of the first syntax element (404). For example, the first syntax element may include a flag or bit associated with a DMVR tool, and the subset of video data may include a portion (some, but not all) of a video sequence including multiple pictures of the video data. In particular, the subset described herein may include a slice of video data, a picture of video data, a sub-picture of video data, a frame of video data, a block of video data, or another subportion of video data within a video sequence. The video decoder 300 may be configured to decode a second syntax element (406) and determine whether a second decoder-side refinement tool is enabled or disabled for the subset of video data based on a value of the second syntax element (404). For example, the second syntax element may include a flag or bit associated with a BDOF tool. The video decoder 300 then decodes the subset (i.e., slice, picture, subpicture, frame, block, or other subset of the larger sequence) based on the determination (410).For example, the decoder 300 may be configured to: decode a subset of the video data (e.g., the first subset of the video data) using a first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the first subset; decode the subset of the video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the first subset; decode the subset of the video data using a second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the first subset; and decode the subset of the video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the first subset.

[0179] The video decoder 300 may be configured to determine (412) whether there is another subset of the video data to decode, e.g., another slice, picture, subpicture, frame, block, or other subset. If so (the “yes” branch of 412), the process repeats for the second subset of video data, e.g., a different slice, picture, subpicture, frame, block, or other subset within the same video sequence that included the first subset of video data. In this example, the first step of decoding a first syntax element (402) may include decoding a first instance of the first syntax element, and the first step of decoding a second syntax element (406) may include decoding a first instance of the second syntax element. Thus, upon identifying another subset, the video decoder 300 may decode (402) a second instance of the first syntax element that identifies whether the first decoder-side refinement tool is enabled or disabled for a second subset of video data in the sequence of video data, the second subset being different from the first subset (i.e., the “yes” branch of 412). The video decoder 300 may then determine whether the first decoder-side refinement tool is enabled or disabled for the second subset of video data based on the value of the second instance of the first syntax element (404), decode the second instance of the second syntax element to determine whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data in the sequence of video data (406), and determine whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data based on the value of the second instance of the second syntax element (408).The decoder 300 may be configured to decode (410) a second subset of the video data, which may include: decoding the second subset of the video data using a first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the second subset; decoding the second subset of the video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the second subset; decoding the second subset of the video data using a second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the second subset; and decoding the second subset of the video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the second subset.

[0180] The video decoder 300 may be configured to again determine (412) whether there is another subset of the video data to decode, e.g., another slice, picture, subpicture, frame, block, or other subset. If so (the "yes" branch of 412), the process repeats for a third subset of the video data, e.g., a different slice, picture, subpicture, frame, block, or other subset within the same video sequence that included the first subset of the video data. In fact, the process may repeat for many subsets of the video data within a larger video sequence.

[0181] For a third subset of the video data, for example, the video decoder 300 may include processing circuitry configured to decode (402) a third instance of a first syntax element indicating whether the first decoder-side refinement tool is enabled or disabled for the third subset of the video data in the sequence of video data, where the third subset is different from the first subset and the third subset is different from the second subset. The video decoder may be further configured to determine whether a first decoder-side refinement tool is enabled or disabled for the third subset of video data based on a value of the third instance of the first syntax element (404); decode a third instance of a second syntax element that identifies whether a second decoder-side refinement tool is enabled or disabled for the third subset of video data in the sequence of video data (406); and determine whether the second decoder-side refinement tool is enabled or disabled for the third subset of video data based on the value of the third instance of the second syntax element (408), wherein the decoder 300 decodes the third subset of video data (410). and may include decoding the third subset of the video data using a first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the third subset; decoding the third subset of the video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the third subset; decoding the third subset of the video data using a second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the third subset; and decoding the third subset of the video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the third subset.

[0182] In this manner, a decoder-side refinement tool may be enabled or disabled multiple times for different subsets of data in a video sequence. For example, the video decoder 300 may be configured to: determine, based on the value of the first instance of a first syntax element, that a first decoder-side refinement tool is enabled for a first subset of video data; determine, based on the value of the first instance of a second syntax element, that a second decoder-side refinement tool is disabled for the first subset of video data; and decode the first subset of video data with the first decoder-side refinement tool and without the second decoder-side refinement tool. Then, for the same video sequence, the video decoder 300 may be configured to determine, based on the value of the second instance of the first syntax element, that the first decoder-side refinement tool is disabled for a second subset of the video data, based on the value of the second instance of the second syntax element, that the second decoder-side refinement tool is enabled for the second subset of the video data, and decode the second subset of the video data using the second decoder-side refinement tool and without using the first decoder-side refinement tool.

[0183] The first and second decoder-side refinement tools may generally be available for decoding any of a plurality of pictures of a sequence of video data, but one or both of the first and second decoder-side refinement tools may be enabled for some subsets of video data within the sequence of video data, and one or both of the first and second decoder-side refinement tools may be disabled for other subsets of video data within the sequence of video data.

[0184] In some examples, general availability of decoder-side refinement tools may be defined at a sequence level, with more refined on / off control being available for subsets of the sequence (e.g., slices, blocks, pictures, subpictures, frames, or other subsets). For example, video decoder 300 may include processing circuitry configured to decode one or more syntax elements associated with a sequence of video data and determine, based on the one or more syntax elements associated with the sequence of video data, that first and second decoder-side refinement tools are enabled to be available for decoding a plurality of pictures of the sequence of video data. Video decoder 300 may then perform the process of FIG. 10 for each subset of video data in the sequence, such that on / off control of decoder-side refinement tools may be at the subsequence level. In some examples, each subset of video data for which on / off control is signaled may include at least a portion of a picture among a plurality of pictures of the sequence of video data. Again, by way of example, the subset may include a slice of video data within a sequence, a frame of video data within a sequence, a picture among multiple pictures of a sequence of video data, a sub-picture of video data, or a block of video data within a sequence.

[0185] 11 is an example flow diagram illustrating an encoding technique consistent with this disclosure for enabling or disabling two or more decoder-side refinement tools for different portions or subsets of a video sequence including multiple pictures. As shown in FIG. 11, video encoder 200 may be configured to determine whether decoder-side refinement tools are available for a video sequence (502). In some cases, the availability of decoder-side refinement tools is implied (not signaled), and in some cases, video encoder 200 may be configured to encode one or more sequence-level syntax elements to identify one or more decoder-side refinement tools available for use with the sequence. In either case, upon determining that one or more decoder-side refinement tools are available (the “yes” branch of 502), video encoder 200 may encode a first syntax element (504) to identify whether a first decoder-side refinement tool is enabled for the subset of the video sequence. Further, video encoder 200 may be configured to encode a second syntax element (506) to identify whether a second decoder-side refinement tool is enabled for the subset of the video sequence. Video encoder 200 may then determine whether there is another subset of video data for the sequence to encode, and if so (“yes” branch of 508), video encoder 200 may repeat the steps of encoding the first and second syntax elements (504 and 506) for the next subset.

[0186] Accordingly, the video encoder 200 may comprise processing circuitry configured to: encode a first instance of a first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data within the sequence of video data (504); encode a second instance of the first syntax element to identify whether the first decoder-side refinement tool is enabled or disabled for a second subset of video data within the sequence of video data (506), where the second subset is different from the first subset; encode a first instance of a second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data within the sequence of video data (504); and encode a second instance of the second syntax element to identify whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data within the sequence of video data. Again, by way of example, the first decoder-side refinement tool may include a DMVR tool and the second decoder-side refinement tool may include a BDOF tool.

[0187] Similarly, the process may be repeated for other subsets of data within the video sequence, e.g., other frames, slices, pictures, subpictures, blocks, or other subportions (some, but not all) of the video sequence. Thus, in some examples, video encoder 200 may encode a third instance of the first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a third subset of video data within the sequence of video data (504), where the third subset is different from the first subset and the third subset is different from the second subset, and encode a third instance of the second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the third subset of video data within the sequence of video data.

[0188] Thus, one or both of the first and second decoder-side refinement tools may be enabled for some subsets of video data within a sequence of video data, and one or both of the first and second decoder-side refinement tools may be disabled for other subsets of video data within the sequence of video data.

[0189] In some examples, general availability of decoder-side refinement tools may be defined at the sequence level, with more refined on / off control being available for subsets of the sequence (e.g., slices, blocks, pictures, subpictures, frames, or other subsets). For example, video encoder 200 may include processing circuitry configured to encode one or more syntax elements associated with a sequence of video data to indicate that first and second decoder-side refinement tools are available for decoding multiple pictures of the sequence of video data. In these or other examples, as described herein, one or both of the first and second decoder-side refinement tools may be enabled for some subsets of video data within the sequence of video data, and one or both of the first and second decoder-side refinement tools are disabled for other subsets of video data within the sequence of video data.

[0190] Again, a subset of video data may refer to at least a portion of a first picture among multiple pictures of a sequence of video data. The subset of video data may include, for example, one or more of a slice, a frame, a picture, a subpicture, a block, or another portion (some, but not all) of the video data in a video sequence.

[0191] It should be appreciated that, depending on the example, some acts or events of any of the techniques described herein may be performed in a different sequence, added, combined, or omitted entirely (e.g., not all described acts or events may be necessary to practice the techniques). Furthermore, in some examples, acts or events may be performed simultaneously rather than sequentially, for example, through multithreaded processing, interrupt processing, or multiple processors.

[0192] EXAMPLES: The following examples may demonstrate one or more features or aspects consistent with the present disclosure.

[0193] Example 1: A method includes the steps of coding a slice level syntax element that indicates whether a decoder-side motion refinement mode is on or off for a slice of video data, and coding blocks of video data in the slice of video data based on the slice level syntax element.

[0194] Example 2: A device includes a memory and one or more processors in communication with the memory, the one or more processors configured to code a slice level syntax element indicating whether a decoder-side motion refinement mode is on or off for a slice of video data, and to code blocks of video data in the slice of video data based on the slice level syntax element.

[0195] Example 3: A device includes means for coding a slice level syntax element that indicates whether a decoder-side motion refinement mode is on or off for a slice of video data, and means for coding a block of video data in the slice of video data based on the slice level syntax element.

[0196] Example 4: A computer-readable storage medium is encoded with instructions that, when executed, cause a programmable processor to code a slice-level syntax element that indicates whether a decoder-side motion refinement mode is on or off for a slice of video data, and to code a block of video data in the slice of video data based on the slice-level syntax element.

[0197] Example 5: A method of coding video data, comprising: coding a slice level syntax element that indicates whether a decoder-side motion refinement mode is on or off for a slice of the video data; and coding blocks of video data in the slice of the video data based on the slice level syntax element.

[0198] Example 6: The method of Example 5, wherein the decoder-side motion refinement mode is one of decoder-side motion vector refinement or bidirectional optical flow.

[0199] Example 7: The method of Example 5 or 6, wherein coding a slice level syntax element indicating whether a decoder-side motion refinement mode is on or off for a slice of the video data includes coding a first slice level syntax element indicating whether a decoder-side motion vector refinement mode is on or off for a slice of the video data, and coding a second slice level syntax element indicating whether a bidirectional optical flow mode is on or off for the slice of the video data.

[0200] Example 8: A method for coding video data, comprising: coding a block level syntax element that indicates whether a decoder-side motion refinement mode is on or off for a block of the video data; and coding the block of the video data based on the block level syntax element.

[0201] Example 9: The method of Example 8, wherein the decoder-side motion refinement mode is one of decoder-side motion vector refinement or bidirectional optical flow.

[0202] Example 10: The method of example 8, wherein the decoder-side motion refinement mode is both decoder-side motion vector refinement and bidirectional optical flow.

[0203] Example 11: The method of example 8, wherein the block of video data is a merge mode coding unit.

[0204] Example 12: The method of Example 8, wherein coding a block level syntax element indicating whether a decoder-side motion refinement mode is on or off for a block of video data includes coding a block level syntax element indicating whether a decoder-side motion refinement mode is on or off for a block of video data when a merge candidate index for the block of video data is within a predefined range.

[0205] Example 13: The method of Example 8, wherein coding a block level syntax element indicating whether a decoder-side motion refinement mode is on or off for a block of video data includes reusing a neighboring block level syntax element indicating whether a decoder-side motion refinement mode is on or off for a neighboring block of video data for the block of video data.

[0206] Example 14: A method of coding video data, comprising disabling a decoder-side motion refinement mode by applying a zero motion vector differential to a block of video data, and coding the block of video data using the zero motion vector.

[0207] Example 15: The method of example 14, wherein the blocks of video data are coded using merge mode with motion vector differential (MMVD).

[0208] Example 16: The method of Example 14, wherein the decoder-side motion refinement mode is one of decoder-side motion vector refinement or bidirectional optical flow.

[0209] Example 17: The method of Example 14, wherein disabling a decoder-side motion refinement mode by applying a zero motion vector differential to a block of video data includes disabling a decoder-side motion refinement mode by applying a zero motion vector differential to a block of video data based on one or more of a block size or a slice type.

[0210] Example 18: The method of Example 14, further comprising removing redundant candidates in a merge mode using a motion vector difference candidate list (MMVD).

[0211] Example 19: The method of any of Examples 5 to 18, wherein the coding includes decoding.

[0212] Example 20: The method of any of Examples 5-18, wherein coding includes encoding.

[0213] Example 21: A device for coding video data, comprising one or more means for implementing the method of any of Examples 5 to 18.

[0214] Example 22: The device of Example 21, wherein the one or more means comprise one or more processors implemented in circuitry.

[0215] Example 23: The device of Example 21 or 22, further comprising a memory for storing video data.

[0216] Example 24: The device of any of Examples 21-23, further comprising a display configured to display the decoded video data.

[0217] Example 25: The device of any of Examples 21-24, comprising one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0218] Example 26: The device of any one of Examples 21 to 25, wherein the device includes a video decoder.

[0219] Example 27: The device of any of Examples 21 to 25, wherein the device includes a video encoder.

[0220] Example 28: A computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors to perform the method of any of Examples 5-18.

[0221] Example 29: Any combination of the techniques of Examples 5-18.

[0222] Example 30: A method of decoding a plurality of pictures of a sequence of video data, comprising: decoding a first syntax element to determine whether a first decoder-side refinement tool is enabled for a first portion of a first picture among the plurality of pictures of the sequence of video data, the first decoder-side refinement tool being enabled for decoding the plurality of pictures of the sequence of video data; determining, based on a value of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the first picture; and decoding a second decoder-side refinement tool to determine whether a first decoder-side refinement tool is enabled for the first portion of the first picture among the plurality of pictures of the sequence of video data, the first decoder-side refinement tool being enabled for decoding the plurality of pictures of the sequence of video data. 1. A method comprising: decoding a second syntax element to determine whether the second decoder-side refinement tool is enabled for a first portion of a first picture in a plurality of pictures of a sequence, the second decoder-side refinement tool being enabled for decoding a plurality of pictures of the sequence of video data; determining, based on a value of a first instance of the second syntax element, that the second decoder-side refinement tool is disabled for the first portion of the first picture; and decoding the first portion of the first picture with the first decoder-side refinement tool and without the second decoder-side refinement tool.

[0223] Example 31: A method of decoding a sequence of video data including a plurality of pictures, comprising: decoding a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in the sequence of video data; determining whether the first decoder-side refinement tool is enabled or disabled for the first subset of video data based on a value of the first syntax element; decoding a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data based on the value of the first syntax element; decoding the first subset of video data using a first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the first subset; decoding the first subset of video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the first subset; decoding the first subset of video data using a second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the first subset; and decoding the first subset of video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the first subset.

[0224] Example 32: The method of Example 31, wherein the first decoder-side refinement tool includes a DMVR tool and the second decoder-side refinement tool includes a BDOF tool.

[0225] Example 33: decoding the first syntax element includes decoding a first instance of the first syntax element, and decoding the second syntax element includes decoding a first instance of the second syntax element, the method including: decoding a second instance of the first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a second subset of video data in the sequence of video data, the second subset being different from the first subset; determining whether the first decoder-side refinement tool is enabled or disabled for the second subset of video data based on a value of the second instance of the first syntax element; decoding a second instance of the second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the second subset of video data in the sequence of video data; 32. The method of any combination of Examples 30 and 31, further comprising: determining whether a second decoder-side refinement tool is enabled or disabled for the second subset of the video data based on the value of the second instance of the metric element; decoding the second subset of the video data using the first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the second subset; decoding the second subset of the video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the second subset; decoding the second subset of the video data using the second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the second subset; and decoding the second subset of the video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the second subset.

[0226] Example 34: decoding a third instance of a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a third subset of video data in a sequence of video data, the third subset being different from the first subset, and the third subset being different from the second subset; determining whether the first decoder-side refinement tool is enabled or disabled for the third subset of video data based on a value of the third instance of the first syntax element; decoding a third instance of a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the third subset of video data in the sequence of video data; 34. The method of any combination of Examples 31-33, further comprising: determining whether a first decoder-side refinement tool is enabled or disabled for a third subset of video data; decoding the third subset of video data using the first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the third subset; decoding the third subset of video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the third subset; decoding the third subset of video data using the second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the third subset; and decoding the third subset of video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the third subset.

[0227] Example 35: The method of any combination of Examples 31 to 34, further comprising: determining, based on a value of the first instance of the first syntax element, that a first decoder-side refinement tool is enabled for the first subset of the video data; determining, based on a value of the first instance of the second syntax element, that a second decoder-side refinement tool is disabled for the first subset of the video data; decoding the first subset of the video data with the first decoder-side refinement tool and without the second decoder-side refinement tool; determining, based on a value of the second instance of the first syntax element, that the first decoder-side refinement tool is disabled for the second subset of the video data; determining, based on a value of the second instance of the second syntax element, that the second decoder-side refinement tool is enabled for the second subset of the video data; and decoding the second subset of the video data with the second decoder-side refinement tool and without the first decoder-side refinement tool.

[0228] Example 36: A method of any combination of Examples 31 to 35, wherein the first and second decoder-side refinement tools are available for decoding any of a plurality of pictures of a sequence of video data, and one or both of the first and second decoder-side refinement tools are enabled for some subsets of video data in the sequence of video data, and one or both of the first and second decoder-side refinement tools are disabled for other subsets of video data in the sequence of video data.

[0229] Example 37: A method of any combination of Examples 31 to 36, further comprising the steps of decoding one or more syntax elements associated with the sequence of video data, and determining, based on the one or more syntax elements associated with the sequence of video data, that first and second decoder-side refinement tools are enabled so as to be available for decoding multiple pictures of the sequence of video data.

[0230] Example 38: The method of any combination of Examples 31 to 37, wherein the first subset includes at least a portion of a first picture among a plurality of pictures of the sequence of video data.

[0231] Example 39: A method of any combination of Examples 31 to 38, wherein the first subset of video data in the sequence of video data includes one or more of a slice of video data, a frame of video data, a picture among a plurality of pictures of the sequence of video data, a sub-picture, and a block of video data.

[0232] Example 40: A method for encoding a sequence of video data including a plurality of pictures, the method comprising: encoding a first instance of a first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data within the sequence of video data; encoding a second instance of the first syntax element to identify whether the first decoder-side refinement tool is enabled or disabled for a second subset of video data within the sequence of video data, the second subset being different from the first subset; encoding a first instance of a second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data within the sequence of video data; and encoding a second instance of the second syntax element to identify whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data within the sequence of video data.

[0233] Example 41: The method of Example 40, wherein the first decoder-side refinement tool includes a DMVR tool and the second decoder-side refinement tool includes a BDOF tool.

[0234] Example 42: A method of any combination of Examples 40 to 41, further comprising: encoding a third instance of the first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a third subset of video data in the sequence of video data, the third subset being different from the first subset and the third subset being different from the second subset; and encoding a third instance of the second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the third subset of video data in the sequence of video data.

[0235] Example 43: A method of any combination of Examples 40 to 42, wherein one or both of the first and second decoder-side refinement tools are enabled for some subsets of video data within the sequence of video data, and one or both of the first and second decoder-side refinement tools are disabled for other subsets of video data within the sequence of video data.

[0236] Example 44: A method of any combination of Examples 40 to 43, further comprising encoding one or more syntax elements associated with the sequence of video data to indicate that the first and second decoder-side refinement tools are available for decoding multiple pictures of the sequence of video data, wherein one or both of the first and second decoder-side refinement tools are enabled for some subsets of video data in the sequence of video data, and one or both of the first and second decoder-side refinement tools are disabled for other subsets of video data in the sequence of video data.

[0237] Example 45: The method of any combination of Examples 40 to 44, wherein the first subset includes at least a portion of a first picture among a plurality of pictures of the sequence of video data.

[0238] Example 46: The method of any combination of Examples 40 to 45, wherein the first subset of video data in the sequence of video data includes one or more of a slice, a frame, a picture, a subpicture, and a block.

[0239] Example 47: A video decoding device comprising: a memory configured to store a sequence of video data including a plurality of pictures; and processing circuitry, wherein the processing circuitry is configured to: decode a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in the sequence of video data; determine whether the first decoder-side refinement tool is enabled or disabled for the first subset of video data based on a value of the first syntax element; decode a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data in the sequence of video data; and determine whether the second decoder-side refinement tool is enabled or disabled for the first subset of video data based on the value of the first syntax element. and determining whether a first decoder-side refinement tool is enabled or disabled for the first subset; decoding the first subset of video data with the first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the first subset; decoding the first subset of video data without the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the first subset; decoding the first subset of video data with the second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the first subset; and decoding the first subset of video data without the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the first subset.

[0240] Example 48: The video decoding device of Example 47, wherein the first decoder-side refinement tool includes a DMVR tool and the second decoder-side refinement tool includes a BDOF tool.

[0241] Example 49: Processing circuitry is configured to decode a first syntax element by decoding a first instance of the first syntax element and to decode a second syntax element by decoding a first instance of the second syntax element, wherein the processing circuitry is configured to: decode a second instance of the first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a second subset of video data in a sequence of video data, the second subset being different from the first subset; determine whether the first decoder-side refinement tool is enabled or disabled for the second subset of video data based on a value of the second instance of the first syntax element; decode a second instance of the second syntax element indicating whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data in the sequence of video data; 49. The video decoding device of Example 47 or 48, further configured to: determine whether a second decoder-side refinement tool is enabled or disabled for the second subset of the video data based on the value of the second instance of the syntax element #2; decode the second subset of the video data with the first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the second subset; decode the second subset of the video data without using the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the second subset; decode the second subset of the video data with the second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the second subset; and decode the second subset of the video data without using the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the second subset.

[0242] Example 50: A processing circuit configuration is configured to: decode a third instance of a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a third subset of video data in a sequence of video data, the third subset being different from the first subset and the third subset being different from the second subset; determine whether the first decoder-side refinement tool is enabled or disabled for the third subset of video data based on a value of the third instance of the first syntax element; decode a third instance of a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the third subset of video data in the sequence of video data; and determine whether the second decoder-side refinement tool is enabled or disabled for the third subset of video data based on the value of the third instance of the second syntax element. 50. The video coding device of any combination of Examples 47-49, further configured to: determine whether a first decoder-side refinement tool is enabled or disabled for the third subset of the video data; decode the third subset of the video data with the first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the third subset; decode the third subset of the video data without the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the third subset; decode the third subset of the video data with the second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the third subset; and decode the third subset of the video data without the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the third subset.

[0243] Example 51: A video coding device of any combination of Examples 47 to 50, wherein the processing circuitry is configured to: determine, based on a value of a first instance of a first syntax element, that a first decoder-side refinement tool is enabled for a first subset of the video data; determine, based on a value of a first instance of a second syntax element, that a second decoder-side refinement tool is disabled for the first subset of the video data; decode the first subset of the video data with the first decoder-side refinement tool and without the second decoder-side refinement tool; determine, based on a value of a second instance of the first syntax element, that the first decoder-side refinement tool is disabled for a second subset of the video data; determine, based on a value of a second instance of the second syntax element, that the second decoder-side refinement tool is enabled for the second subset of the video data; and decode the second subset of the video data with the second decoder-side refinement tool and without the first decoder-side refinement tool.

[0244] Example 52: A video coding device of any combination of Examples 47 to 51, wherein the first and second decoder-side refinement tools are available for decoding any of a plurality of pictures of a sequence of video data, and one or both of the first and second decoder-side refinement tools are enabled for some subsets of video data in the sequence of video data, and one or both of the first and second decoder-side refinement tools are disabled for other subsets of video data in the sequence of video data.

[0245] Example 53: A video coding device of any combination of Examples 47 to 52, wherein the processing circuit configuration is further configured to: decode one or more syntax elements associated with the sequence of video data; and determine, based on the one or more syntax elements associated with the sequence of video data, that first and second decoder-side refinement tools are enabled so as to be available for decoding multiple pictures of the sequence of video data.

[0246] Example 54: The video coding device of any combination of Examples 47 to 53, wherein the first subset includes at least a portion of a first picture among a plurality of pictures of the sequence of video data.

[0247] Example 55: A video coding device of any combination of Examples 47 to 54, wherein the first subset of video data in the sequence of video data includes one or more of a slice of video data, a frame of video data, a picture among a plurality of pictures of the sequence of video data, a subpicture, and a block of video data.

[0248] Example 56: A video encoding device comprising: a memory configured to store a sequence of video data including a plurality of pictures; and processing circuitry; the processing circuitry: encoding a first instance of a first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in the sequence of video data; and encoding a second instance of the first syntax element to identify whether the first decoder-side refinement tool is enabled or disabled for a second subset of video data in the sequence of video data. a first instance of a second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data in the sequence of video data, wherein the second subset is different from the first subset; and a second instance of the second syntax element to identify whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data in the sequence of video data.

[0249] Example 57: The video encoding device of Example 56, wherein the first decoder-side refinement tool includes a DMVR tool and the second decoder-side refinement tool includes a BDOF tool.

[0250] Example 58: The video encoding device of Example 56 or 57, wherein the processing circuitry is further configured to: encode a third instance of the first syntax element to identify whether the first decoder-side refinement tool is enabled or disabled for a third subset of video data in the sequence of video data, the third subset being different from the first subset and the third subset being different from the second subset; and encode a third instance of the second syntax element to identify whether the second decoder-side refinement tool is enabled or disabled for the third subset of video data in the sequence of video data.

[0251] Example 59: A video encoding device of any combination of Examples 56 to 58, wherein one or both of the first and second decoder-side refinement tools are enabled for some subsets of video data within the sequence of video data, and one or both of the first and second decoder-side refinement tools are disabled for other subsets of video data within the sequence of video data.

[0252] Example 60: A video encoding device of any combination of Examples 56 to 59, wherein the processing circuit configuration is further configured to encode one or more syntax elements associated with the sequence of video data to indicate that the first and second decoder-side refinement tools are available for decoding multiple pictures of the sequence of video data, and one or both of the first and second decoder-side refinement tools are enabled for some subsets of video data in the sequence of video data, and one or both of the first and second decoder-side refinement tools are disabled for other subsets of video data in the sequence of video data.

[0253] Example 61: The video encoding device of any combination of Examples 56 to 60, wherein the first subset includes at least a portion of a first picture among a plurality of pictures of the sequence of video data.

[0254] Example 62: The video encoding device of any combination of Examples 56 to 61, wherein the first subset of video data in the sequence of video data includes one or more of a slice, a frame, a picture, a subpicture, and a block.

[0255] Example 63: A video decoding device configured to decode a sequence of video data including a plurality of pictures, comprising: means for decoding a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in the sequence of video data; means for determining whether the first decoder-side refinement tool is enabled or disabled for the first subset of video data based on a value of the first syntax element; means for decoding a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data based on the value of the first syntax element; means for determining whether a first decoder-side refinement tool is enabled or disabled for the first subset; means for decoding the first subset of video data with a first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the first subset; means for decoding the first subset of video data without the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the first subset; means for decoding the first subset of video data with a second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the first subset; and means for decoding the subset of video data without the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the first subset.

[0256] Example 64: A video encoding device configured to encode a sequence of video data including a plurality of pictures, comprising: means for encoding a first instance of a first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data within the sequence of video data; means for encoding a second instance of the first syntax element to identify whether the first decoder-side refinement tool is enabled or disabled for a second subset of video data within the sequence of video data, the second subset being different from the first subset; means for encoding a first instance of a second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data within the sequence of video data; and means for encoding a second instance of the second syntax element to identify whether the second decoder-side refinement tool is enabled or disabled for the second subset of video data within the sequence of video data.

[0257] Example 65: A computer-readable storage medium storing instructions that, when executed, cause one or more processors of a video decoding device to: decode a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in a sequence of video data, the sequence of video data including a plurality of pictures; determine whether the first decoder-side refinement tool is enabled or disabled for the first subset of video data based on a value of the first syntax element; decode a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data in the sequence of video data based on the value of the first syntax element; 11. A computer-readable storage medium that causes a processor to: determine whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data; decode the first subset of video data with the first decoder-side refinement tool in response to the first decoder-side refinement tool being enabled for the first subset; decode the first subset of video data without the first decoder-side refinement tool in response to the first decoder-side refinement tool being disabled for the first subset; decode the first subset of video data with a second decoder-side refinement tool in response to the second decoder-side refinement tool being enabled for the first subset; and decode the subset of video data without the second decoder-side refinement tool in response to the second decoder-side refinement tool being disabled for the first subset.

[0258] Example 66: A computer-readable storage medium storing instructions that, when executed, cause one or more processors of a video encoding device to encode a first instance of a first syntax element to identify whether a first decoder-side refinement tool is enabled or disabled for a first subset of video data in a sequence of video data, the sequence of video data including a plurality of pictures; and encode a first instance of a first syntax element to identify whether the first decoder-side refinement tool is enabled or disabled for a second subset of video data in the sequence of video data. a first instance of a second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the first subset of video data in the sequence of video data, the second subset being different from the first subset; and a second instance of a second syntax element to identify whether a second decoder-side refinement tool is enabled or disabled for the second subset of video data in the sequence of video data.

[0259] In one or more examples, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which correspond to tangible media such as data storage media, or communication media, including any medium that facilitates transfer of a computer program from one place to another, for example, according to a communications protocol. As such, computer-readable media may generally correspond to (1) non-transitory tangible computer-readable storage media or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementing the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0260] By way of example, and not limitation, such computer-readable storage media may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but instead cover non-transitory tangible storage media. As used herein, disk and disc include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically and discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0261] The instructions may be executed by one or more processors, such as one or more DSPs, general-purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. Accordingly, the terms "processor" and "processing circuitry," as used herein, may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. Additionally, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or may be incorporated into a combined codec. Also, the techniques may be implemented entirely in one or more circuits or logic elements.

[0262] The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in this disclosure to highlight functional aspects of devices configured to implement the disclosed techniques, but they do not necessarily require realization by different hardware units. Rather, as explained above, the various units may be combined in a codec hardware unit or may be provided by a collection of interoperable hardware units, including one or more processors as described above, along with appropriate software and / or firmware.

[0263] Various examples have been described. These and other examples are within the scope of the following claims. [Explanation of symbols]

[0264] 100 Video encoding and decoding system, system 102 Source Device, Device, Video Device 104 Video Sources 106 memory 108 Output Interface 110 Computer-Readable Medium 112 Storage Devices 114 File Server 116 Destination Device, Device, Video Device 118 Display Devices 120 memory 122 input interface 200 Video Encoder 202 Mode Selection Unit 204 Residual Generation Unit 206 Conversion Processing Unit 208 quantization units 210 Inverse Quantization Unit 212 Inverse Transformation Processing Unit 214 Reconstruction Unit 216 Filter Unit 218 Decoded Picture Buffer (DPB) 220 Entropy Coding Unit 222 Motion Estimation Unit 224 Motion Compensation Unit 226 intra prediction units 230 video data memory 300 Video Decoder 302 Entropy Decoding Unit 304 Prediction Processing Unit 306 Inverse Quantization Unit 308 Inverse Transformation Processing Unit 310 Reconstruction Unit 312 Filter Unit 314 Decoded Picture Buffer (DPB) 316 Motion Compensation Unit 318 Intra Prediction Units 320 Coded Picture Buffer (CPB) memory

Claims

1. 1. A method of decoding a sequence of video data comprising a plurality of pictures, comprising: decoding a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first portion of a first picture in the plurality of pictures in a video data sequence; determining, based on a value of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the first picture; decoding a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first portion of the first picture, wherein the first decoder-side refinement tool and the second decoder-side refinement tool are enabled to refine motion information associated with the plurality of pictures; determining, based on a value of the second syntax element, that the second decoder-side refinement tool is disabled for the first portion of the first picture; in response to determining that the first decoder-side refinement tool is enabled for the first portion of the first picture and in response to determining that the second decoder-side refinement tool is disabled for the first portion of the first picture, decoding the first portion of the first picture using the first decoder-side refinement tool; A method comprising:

2. the first decoder-side refinement tool comprises a decoder-side motion vector refinement (DMVR) tool; The method of claim 1 , wherein the second decoder-side refinement tool comprises a bidirectional optical flow (BDOF) tool.

3. decoding the first syntax element includes decoding a first instance of the first syntax element; decoding the second syntax element includes decoding a first instance of the second syntax element; The method comprises: decoding a second instance of the first syntax element indicating whether the first decoder-side refinement tool is enabled or disabled for a first portion of a second picture in the plurality of pictures in the video data sequence, the second picture in the plurality of pictures being different from the first picture in the plurality of pictures; determining, based on a value of the second instance of the first syntax element, that the first decoder-side refinement tool is disabled for the first portion of the second picture; decoding a second instance of the second syntax element indicating whether the second decoder-side refinement tool is enabled or disabled for the first portion of the second picture in the plurality of pictures in the video data sequence; determining, based on a value of the second instance of the second syntax element, that the second decoder-side refinement tool is enabled for the first portion of the second picture; in response to determining that the first decoder-side refinement tool is disabled and that the second decoder-side refinement tool is enabled for the first portion of the second picture in the plurality of pictures, decoding the first portion of the second picture using the second decoder-side refinement tool; The method of claim 1 further comprising:

4. the first decoder-side refinement tool decoding a third instance of the first syntax element indicating whether to be enabled or disabled for a first portion of a third picture in the plurality of pictures in the video data sequence, the third picture being different from the first picture and the third picture being different from the second picture; determining, based on a value of the third instance of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the third picture; decoding a third instance of the second syntax element indicating whether the second decoder-side refinement tool is enabled or disabled for the first portion of the third picture in the plurality of pictures in the video data sequence; determining, based on a value of the third instance of the second syntax element, that the second decoder-side refinement tool is enabled for the first portion of the third picture; in response to determining that the first decoder-side refinement tool is enabled for the first portion of the third picture and that the second decoder-side refinement tool is enabled for the first portion of the third picture, decoding the first portion of the third picture using the first decoder-side refinement tool and the second decoder-side refinement tool; 4. The method of claim 3, further comprising:

5. determining, based on a value of a first instance of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the first picture in the plurality of pictures; determining, based on a value of a first instance of the second syntax element, that the second decoder-side refinement tool is disabled for the first portion of the first picture in the plurality of pictures; The method of claim 1 further comprising:

6. the first and second decoder-side refinement tools are operable to decode any of the plurality of pictures of the video data sequence; one or both of the first and second decoder-side refinement tools are enabled for a portion of pictures in the plurality of pictures in the video data sequence; The method of claim 1 , wherein one or both of the first and second decoder-side refinement tools are disabled for other portions of pictures in the plurality of pictures in the video data sequence.

7. decoding one or more syntax elements associated with the sequence of video data; determining, based on the one or more syntax elements associated with the video data sequence, that the first and second decoder-side refinement tools are enabled for the video data sequence so as to be available for decoding the plurality of pictures of the video data sequence; The method of claim 1 further comprising:

8. The first portion of the first picture Slicing video data, a frame of video data, a picture among the plurality of pictures of the video data sequence; Subpictures of the video data, and Blocks of video data The method of claim 1 , comprising one of:

9. 1. A method of encoding a sequence of video data comprising a plurality of pictures, comprising: encoding a first instance of a first syntax element to identify a first decoder-side refinement tool as being enabled for a first portion of a first picture in the plurality of pictures in a video data sequence; encoding a second instance of the first syntax element to identify the first decoder-side refinement tool as being disabled for a first portion of a second picture among the plurality of pictures in the video data sequence, the second picture being different from the first picture, and the first decoder-side refinement tool and a second decoder-side refinement tool being enabled to refine motion information associated with the plurality of pictures; encoding a first instance of a second syntax element to identify the second decoder-side refinement tool as being disabled for the first portion of the first picture in the plurality of pictures in the video data sequence; encoding a second instance of the second syntax element to identify the second decoder-side refinement tool as being enabled for the first portion of the second picture in the plurality of pictures in the video data sequence; A method comprising:

10. the first decoder-side refinement tool comprises a decoder-side motion vector refinement (DMVR) tool; The method of claim 9 , wherein the second decoder-side refinement tool comprises a bidirectional optical flow (BDOF) tool.

11. encoding a third instance of the first syntax element to identify the first decoder-side refinement tool as being enabled for a first portion of a third picture in the plurality of pictures in the video data sequence, the third picture being different from the first picture and the third picture being different from the second picture; encoding a third instance of the second syntax element to identify the second decoder-side refinement tool as being enabled for the first portion of the third picture in the plurality of pictures in the video data sequence; 10. The method of claim 9, further comprising:

12. one or both of the first and second decoder-side refinement tools are enabled for a portion of pictures in the plurality of pictures in the video data sequence; 10. The method of claim 9, wherein one or both of the first and second decoder-side refinement tools are disabled for other portions of pictures in the plurality of pictures in the video data sequence.

13. encoding one or more syntax elements associated with the video data sequence to indicate that the first and second decoder-side refinement tools are enabled for the video data sequence; one or both of the first and second decoder-side refinement tools are enabled for a portion of pictures in the plurality of pictures in the video data sequence; 10. The method of claim 9, wherein one or both of the first and second decoder-side refinement tools are disabled for other portions of pictures in the plurality of pictures in the video data sequence.

14. The first portion of the first picture in the plurality of pictures comprises: slice, Frame, Picture, Subpicture, and block 10. The method of claim 9, comprising one or more of:

15. a memory configured to store a sequence of video data including a plurality of pictures; Processing circuit configuration and 1. A video decoding device comprising: decoding a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first portion of a first picture in the plurality of pictures in a video data sequence; determining, based on a value of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the first picture; decoding a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first portion of the first picture among the plurality of pictures in the video data sequence, wherein the first decoder-side refinement tool and the second decoder-side refinement tool are enabled to refine motion information associated with the plurality of pictures; determining, based on a value of the second syntax element, that the second decoder-side refinement tool is disabled for the first portion of the first picture; in response to determining that the first decoder-side refinement tool is enabled and in response to determining that the second decoder-side refinement tool is disabled for the first portion of the first picture, decoding the first portion of the first picture using the first decoder-side refinement tool; a video decoding device configured to:

16. the first decoder-side refinement tool comprises a decoder-side motion vector refinement (DMVR) tool; The video decoding device of claim 15 , wherein the second decoder-side refinement tool includes a bidirectional optical flow (BDOF) tool.

17. The processing circuitry includes: decoding the first syntax element by decoding a first instance of the first syntax element; decoding the second syntax element by decoding a first instance of the second syntax element; configured to: The processing circuitry includes: decoding a second instance of the first syntax element indicating whether the first decoder-side refinement tool is enabled or disabled for a first portion of a second picture among the plurality of pictures in the video data sequence, the second picture being different from the first picture; and determining, based on a value of the second instance of the first syntax element, that the first decoder-side refinement tool is disabled for the first portion of the second picture; decoding a second instance of the second syntax element indicating whether the second decoder-side refinement tool is enabled or disabled for the first portion of the second picture in the plurality of pictures in the video data sequence; determining, based on a value of the second instance of the second syntax element, that the second decoder-side refinement tool is enabled for the first portion of the second picture; in response to determining that the first decoder-side refinement tool is disabled and that the second decoder-side refinement tool is enabled for the first portion of the second picture, decoding the first portion of the second picture using the second decoder-side refinement tool; The video decoding device of claim 15, further configured to:

18. The processing circuitry includes: decoding a third instance of the first syntax element indicating whether the first decoder-side refinement tool is enabled or disabled for a first portion of a third picture among the plurality of pictures in the video data sequence, the third picture being different from the first picture and the third picture being different from the second picture; and determining, based on a value of the third instance of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the third picture; decoding a third instance of the second syntax element indicating whether the second decoder-side refinement tool is enabled or disabled for the first portion of the third picture in the plurality of pictures in the video data sequence; determining, based on a value of the third instance of the second syntax element, that the second decoder-side refinement tool is enabled for the first portion of the third picture; in response to determining that the first decoder-side refinement tool is enabled for the first portion of the third picture and in response to determining that the second decoder-side refinement tool is enabled for the first portion of the third picture, decoding the first portion of the third picture using the first decoder-side refinement tool and the second decoder-side refinement tool; 20. The video decoding device of claim 17, further configured to:

19. The processing circuitry includes: determining, based on a value of a first instance of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the first picture in the plurality of pictures; determining, based on a value of a first instance of the second syntax element, that the second decoder-side refinement tool is disabled for the first portion of the first picture in the plurality of pictures; The video decoding device of claim 15, further configured to:

20. the first and second decoder-side refinement tools are operable to decode any of the plurality of pictures of the video data sequence; one or both of the first and second decoder-side refinement tools are enabled for a portion of the pictures in the plurality of pictures in the video data sequence; 16. The video decoding device of claim 15, wherein one or both of the first and second decoder-side refinement tools are disabled for other portions of pictures among the plurality of pictures in the video data sequence.

21. The processing circuitry includes: decoding one or more syntax elements associated with the video data sequence; determining, based on the one or more syntax elements associated with the video data sequence, that the first and second decoder-side refinement tools are enabled for the video data sequence so as to be available for decoding the plurality of pictures of the video data sequence; The video decoding device of claim 15, further configured to:

22. The first portion of the first picture Slicing video data, a frame of video data, a picture among the plurality of pictures of the video data sequence; Subpictures of the video data, and Blocks of video data 20. The video decoding device of claim 17, comprising one of:

23. a memory configured to store a sequence of video data including a plurality of pictures; Processing circuit configuration and 1. A video encoding device comprising: encoding a first instance of a first syntax element to identify a first decoder-side refinement tool as being enabled for a first portion of a first picture in the plurality of pictures in a video data sequence; encoding a second instance of the first syntax element to identify the first decoder-side refinement tool as being disabled for a first portion of a second picture among the plurality of pictures in the video data sequence, the second picture being different from the first picture, and the first decoder-side refinement tool and a second decoder-side refinement tool being enabled to refine motion information associated with the plurality of pictures; encoding a first instance of a second syntax element to identify the second decoder-side refinement tool as being disabled for the first portion of the first picture in the plurality of pictures in the video data sequence; encoding a second instance of the second syntax element to identify the second decoder-side refinement tool as being enabled for the first portion of the second picture in the plurality of pictures in the video data sequence; a video encoding device configured to:

24. the first decoder-side refinement tool comprises a decoder-side motion vector refinement (DMVR) tool; 24. The video encoding device of claim 23, wherein the second decoder-side refinement tool includes a bidirectional optical flow (BDOF) tool.

25. The processing circuitry includes: encoding a third instance of the first syntax element to identify the first decoder-side refinement tool as being enabled for a first portion of a third picture among the plurality of pictures in the video data sequence, the third picture being different from the first picture and the third picture being different from the second picture; and encoding a third instance of the second syntax element to identify the second decoder-side refinement tool as being enabled for the first portion of the third picture in the plurality of pictures in the video data sequence; and 24. The video encoding device of claim 23, further configured to:

26. one or both of the first and second decoder-side refinement tools are enabled for a portion of pictures in the plurality of pictures in the video data sequence; 24. The video encoding device of claim 23, wherein one or both of the first and second decoder-side refinement tools are disabled for other portions of pictures in the plurality of pictures in the video data sequence.

27. The processing circuitry includes: the first and second decoder-side refinement tools are further configured to encode one or more syntax elements associated with the video data sequence to indicate that the first and second decoder-side refinement tools are enabled for the video data sequence; one or both of the first and second decoder-side refinement tools are enabled for a portion of pictures in the plurality of pictures in the video data sequence; 24. The video encoding device of claim 23, wherein one or both of the first and second decoder-side refinement tools are disabled for other portions of pictures in the plurality of pictures in the video data sequence.

28. The first portion of the first picture slice, Frame, Picture, Subpicture, and block 24. The video encoding device of claim 23, comprising one of:

29. 1. A video decoding device configured to decode a sequence of video data comprising a plurality of pictures, the video decoding device comprising: means for decoding a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first portion of a first picture in the plurality of pictures in a video data sequence; means for determining, based on a value of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the first picture; means for decoding a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first portion of the first picture in the plurality of pictures in the video data sequence, wherein the first decoder-side refinement tool and the second decoder-side refinement tool are enabled to refine motion information associated with the plurality of pictures; means for determining, based on a value of the second syntax element, that the second decoder-side refinement tool is disabled for the first portion of the first picture; means for decoding the first portion of the first picture using the first decoder-side refinement tool in response to determining that the first decoder-side refinement tool is enabled for the first portion of the first picture in the plurality of pictures and in response to determining that the second decoder-side refinement tool is disabled; 1. A video decoding device comprising:

30. 1. A video encoding device configured to encode a sequence of video data comprising a plurality of pictures, the video encoding device comprising: means for encoding a first instance of a first syntax element to identify a first decoder-side refinement tool as being enabled for a first portion of a first picture in the plurality of pictures in a video data sequence; means for encoding a second instance of the first syntax element to identify the first decoder-side refinement tool as being disabled for a first portion of a second picture among the plurality of pictures in the video data sequence, the second picture being different from the first picture, and the first decoder-side refinement tool and a second decoder-side refinement tool being enabled to refine motion information associated with the plurality of pictures; means for encoding a first instance of a second syntax element to identify the second decoder-side refinement tool as being disabled for the first portion of the first picture in the plurality of pictures in the video data sequence; means for encoding a second instance of the second syntax element to identify the second decoder-side refinement tool as being enabled for the first portion of the second picture in the plurality of pictures in the video data sequence; and 1. A video encoding device comprising:

31. 1. A computer-readable storage medium storing instructions that, when executed, cause one or more processors of a video decoding device to: decoding a first syntax element indicating whether a first decoder-side refinement tool is enabled or disabled for a first portion of a first picture in a plurality of pictures in a video data sequence; determining, based on a value of the first syntax element, that the first decoder-side refinement tool is enabled for the first portion of the first picture; decoding a second syntax element indicating whether a second decoder-side refinement tool is enabled or disabled for the first portion of the first picture among the plurality of pictures in the video data sequence, wherein the first decoder-side refinement tool and the second decoder-side refinement tool are enabled to refine motion information associated with the plurality of pictures; determining, based on a value of the second syntax element, that the second decoder-side refinement tool is disabled for the first portion of the first picture; in response to determining that the first decoder-side refinement tool is enabled for the first portion of the first picture among the plurality of pictures and in response to determining that the second decoder-side refinement tool is disabled, decoding the first portion of the first picture using the first decoder-side refinement tool; A computer-readable storage medium that causes the

32. 1. A computer-readable storage medium storing instructions that, when executed, cause one or more processors of a video encoding device to: encoding a first instance of a first syntax element to identify a first decoder-side refinement tool as being enabled for a first portion of a first picture among a plurality of pictures in a video data sequence; encoding a second instance of the first syntax element to identify the first decoder-side refinement tool as being disabled for a first portion of a second picture among the plurality of pictures in the video data sequence, the second picture being different from the first picture, and the first decoder-side refinement tool and a second decoder-side refinement tool being enabled to refine motion information associated with the plurality of pictures; encoding a first instance of a second syntax element to identify the second decoder-side refinement tool as being disabled for the first portion of the first picture in the plurality of pictures in the video data sequence; encoding a second instance of the second syntax element to identify the second decoder-side refinement tool as being enabled for the first portion of the second picture in the plurality of pictures in the video data sequence; A computer-readable storage medium that causes the

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