Method and apparatus for time-transfer signal conversion, computer-readable medium

Abstract

The present disclosure provides a method for time transfer signal conversion, the method includes: a conversion unit obtains a second initial time transfer signal corresponding to the same time according to a first time transfer signal, and outputs the second initial time transfer signal; a logic OR gate receives a trigger signal of the first time transfer signal and a second initial time transfer signal, and outputs a second time transfer signal, the first time transfer signal has a first format, the second initial time transfer signal and the second time transfer signal have a second format, and the fixed time points of the trigger signal of the first time transfer signal, the second initial time transfer signal and the second time transfer signal are all rising edges. The present disclosure provides an apparatus for time transfer signal conversion, a computer readable medium.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This disclosure claims priority to Patent Application No. 202111403539.8 filed with the China Patent Office on November 24, 2021, the entire contents of which are incorporated herein by reference. [Technical Field]

[0002] The present disclosure relates to, but is not limited to, the field of time-granting technology. [Background technology]

[0003] In many cases, it is necessary to convert the format of the time signal. For example, the time signal output of the modem chip in 5G (fifth generation mobile communication technology) CPE (customer premises equipment) equipment is usually in 1 pulse per second + time of day (1PPS + TOD) format, but the time signal used in power terminals is generally in Telecommunications Working Group B (IRIG-B) format, so in this case, the 1PPS + TOD time signal needs to be converted to an IRIG-B time signal for use in power terminal time signaling. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a method and apparatus for time-transfer signal conversion, and a computer-readable medium. [Means for solving the problem]

[0005] In a first aspect, the present disclosure provides a method for converting a time transfer signal, the method comprising: a conversion unit obtaining a second initial time transfer signal corresponding to the same time based on a first time transfer signal, and outputting the second initial time transfer signal; a logic OR gate receiving a trigger signal of the first time transfer signal and the second initial time transfer signal, and outputting a second time transfer signal; wherein the first time transfer signal has a first format, the second initial time transfer signal and the second time transfer signal have second formats, and the predetermined time points of the trigger signal of the first time transfer signal, the second initial time transfer signal and the second time transfer signal are all rising edges.

[0006] In a second aspect, the present disclosure provides a time granularity signal conversion device, including: a conversion unit configured to obtain a second initial time granularity signal corresponding to the same time based on a first time granularity signal, and output the second initial time granularity signal; and a logic OR gate configured to receive a trigger signal of the first time granularity signal and the second initial time granularity signal, and output the second time granularity signal, wherein the first time granularity signal has a first format, the second initial time granularity signal and the second time granularity signal have second formats, and the fixed time points of the trigger signal of the first time granularity signal, the second initial time granularity signal and the second time granularity signal are all rising edges.

[0007] In a third aspect, the present disclosure provides a computer-readable medium having a computer program stored thereon, the computer program, when executed by a processor, causing the processor to perform any of the time-transfer signal conversion methods of the present disclosure. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a conceptual diagram of different symbol formats in IRIG-B time transfer signals. [Figure 2] 1 is a flowchart of a method for time-transfer signal conversion provided by the present disclosure. [Figure 3] 1 is a flowchart of another method for time-transfer signal conversion provided by the present disclosure. [Figure 4] 1 is a conceptual diagram of a signal processing process of the method of time-transfer signal conversion provided by the present disclosure. [Figure 5] FIG. 10 is a schematic diagram of a process for obtaining a second initial signal in another method for time-transfer signal conversion provided by the present disclosure. [Figure 6] 1 is a block diagram of a time transfer signal conversion device provided by the present disclosure. [Figure 7] 1 is a block diagram of a computer-readable medium provided by the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the following detailed description will be given in conjunction with the accompanying drawings of the time transmission and reception signal conversion method and apparatus, and computer-readable medium provided by the present disclosure embodiments.

[0010] The present disclosure will now be described more fully with reference to the drawings, although the illustrated embodiments may be embodied in different forms and the disclosure should not be construed as limited to the embodiments described below. On the contrary, the purpose of providing these embodiments is to make this disclosure thorough and complete, and to fully convey the scope of the disclosure to those skilled in the art.

[0011] The drawings of the embodiments of the present disclosure are intended to provide a further understanding of the embodiments of the present disclosure, constitute a part of the specification, and are intended to explain the present disclosure together with the detailed embodiments, and are not intended to constitute limitations on the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing the detailed embodiments with reference to the drawings.

[0012] The present disclosure may be described with reference to plan views and / or cross-sectional views using idealized schematic diagrams of the present disclosure. Therefore, the exemplary drawings may be modified based on manufacturing techniques and / or tolerances.

[0013] Unless inconsistent, the embodiments and features of the embodiments of the present disclosure may be combined with each other.

[0014] The terms used in this disclosure are used only to describe particular embodiments and are not intended to limit the disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used in this disclosure, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising," "comprising," and "consisting of" refer to the presence of said features, wholes, steps, operations, elements, and / or assemblies, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, assemblies, and / or groups thereof.

[0015] Unless otherwise limited, the meanings of all terms (including technical and scientific terms) used in this disclosure are the same as those commonly understood by those skilled in the art. It will also be understood that terms as defined in common dictionaries will be interpreted to have a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted to have an ideal or overly formal meaning unless expressly so limited in this disclosure.

[0016] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic attributes, and the shapes of the regions illustrated in the drawings are illustrative of the specific shapes of the regions of the elements, but are not limiting.

[0017] In some related technologies, conversion of the time transfer signal format is required, for example, in the process of transferring time to a power terminal, it may be necessary to convert a 1PPS+TOD time transfer signal into an IRIG-B time transfer signal.

[0018] Here, 1PPS+TOD (1 Pulse Per Second+Time of Day) is a "1 Pulse Per Second+Time of Day" format that includes a trigger signal that is the basis for on time (On Time) and a time-of-day (TOD) signal that characterizes a specific time. Here, the transmission period of the trigger signal is 1 second (1PPS), its rising edge (starting edge) is the on time point, and the TOD signal starts transmission 1 ms after the on time point of the trigger signal and is used to characterize the specific time.

[0019] Here, the "fixed time" is also called a "fixed time edge," and in a time transfer signal (for example, a trigger signal of a time transfer signal), the moment when the fixed time arrives is the time indicated by the time transfer signal. For example, if the time corresponding to a certain time transfer signal is 15:00:00 and the fixed time is the rising edge of the trigger signal, the device receiving the time transfer signal will determine that the time is 15:00:00 at the moment when the rising edge of the trigger signal arrives.

[0020] The IRIG-B (Inter Range Instrumentation Group-B) time signal is in the "Telecommunications Workgroup B Code" format, abbreviated as "B Code." It transmits one time signal per second. Each time signal (one frame signal) contains 100 pulses (100 PPS). The rising edge of the first pulse indicates the fixed time. Different pulses represent seconds, tens of seconds, minutes, hours, days, days, and hundredths of a day, as well as P-codes. Each symbol has a total time length of 10 ms, and its meaning is determined by its pulse width (i.e., its duty cycle). As shown in Figure 1, a 2-ms pulse width represents a "0," a 5-ms pulse width represents a "1," and an 8-ms pulse width represents a P-code.

[0021] However, since signal conversion inevitably takes a certain amount of time, the converted time transfer signal will have a delay with respect to the original time transfer signal, that is, the time is not accurate and has low precision, which cannot meet the practical application needs of many scenarios (such as power differential protection scenarios).

[0022] In a first aspect, the present disclosure provides a method for time-to-signal conversion.

[0023] The disclosed method for converting time-transfer signals is used to convert a time-transfer signal of an input format into a time-transfer signal of another format, and then output the converted time-transfer signal. This allows the method to be used in situations where the format of the original time-transfer signal available does not match the format of the time-transfer signal required by the target device (e.g., a power terminal).

[0024] Here, the time transfer signal conversion method disclosed herein can be performed by a time transfer signal conversion device, which may be a separate device dedicated to performing the conversion, or may be integrated with a device that generates the original time transfer signal (e.g., a power 5G CPE product that supports 5G time transfer function, a device that supports GPS time transfer, etc.), or may be integrated with a target device (e.g., a power terminal) that requires the converted time transfer signal.

[0025] As shown in FIGS. 2, 4, and 6, in some embodiments, the method of the present disclosure may include step S101 and step S102.

[0026] In step S101, the conversion unit obtains a second initial time transfer signal corresponding to the same time according to the first time transfer signal, and outputs the second initial time transfer signal.

[0027] In step S102, a logical OR gate receives the trigger signal of the first time transfer signal and the second initial time transfer signal, and outputs a second time transfer signal.

[0028] Here, the first time exchange signal has a first format, the second initial time exchange signal and the second time exchange signal have a second format, and the trigger signal of the first time exchange signal, the second initial time exchange signal and the second time exchange signal all have their rising edges at their fixed points in time.

[0029] The conversion unit of the time transfer signal conversion device receives a time transfer signal in a format (first format) and converts it into a time transfer signal (second initial time transfer signal) in another format (second format) representing the same time, and then inputs the second initial time transfer signal together with the trigger signal of the original first time transfer signal into a logic OR gate, and the output of the logic OR gate is the final converted second time transfer signal.

[0030] As shown in Figure 4, the conversion takes time, so the second initial time transfer signal (IRIG-B (initial) in Figure 4) obtained after conversion will inevitably be delayed compared to the first time transfer signal (1PPS+TOD time transfer signal in Figure 4). That is, the fixed point (On Time, rising edge) of the second initial time transfer signal is slightly delayed compared to the fixed point (rising edge) of the trigger signal of the first time transfer signal. However, by using an OR operation, the fixed point (rising edge) of the final output second time transfer signal (IRIG15 B (output) in Figure 4) can be synchronized with the fixed point of the trigger signal of the first time transfer signal. This ensures that the fixed point of the final converted second time transfer signal is the same as the fixed point of the original first time transfer signal. At the same time, the time characterized by the second time transfer signal is the same as that of the first time transfer signal, so the second time transfer signal can achieve accurate time transfer and high precision.

[0031] Here, the pulse (symbol) width in the time transfer signal is at least milliseconds (ms), and the conversion time does not exceed tens of microseconds (μs) at most. That is, the delay due to conversion is always much shorter than the symbol length of the time transfer signal. Therefore, although the above "OR" operation changes the pulse width (duty ratio) of the first pulse of the second time transfer signal, this only affects the fixed time point and does not affect the information actually represented by the symbol.

[0032] In the present disclosure, the first time transfer signal in the first format is converted to obtain the second initial time transfer signal in the second format. However, instead of directly outputting the second initial time transfer signal, the second initial time transfer signal and the trigger signal of the first time transfer signal are input together into a logic OR gate. The "OR" operation ensures that the fixed time point output by the logic OR gate is the same as the fixed time point of the trigger signal of the first time transfer signal. This is equivalent to "advancing" the second time transfer signal obtained by conversion based on the first time transfer signal until it is synchronized with the first time transfer signal. This eliminates the delay of the second time transfer signal caused by the conversion time and ensures that the first time transfer signal and the second time transfer signal are time-aligned. This ensures that the converted signal has high accuracy (<1 μs) and meets the practical application needs of various scenarios (e.g., power differential protection scenarios).

[0033] In some embodiments, the conversion unit includes a microcontroller unit MCU.

[0034] As an embodiment of the present disclosure, as shown in FIG. 4, the conversion unit may include a microcontroller unit (MCU), for example, the conversion unit may be a "single chip."

[0035] Some related technologies use field programmable gate arrays (FPGAs) to convert time-transmitted signals, but the size, cost, and power consumption of these FPGA printed circuit boards make them difficult to implement in practical applications.

[0036] Compared with FPGA, MCU has advantages such as lower cost, lower power consumption, smaller size, and practical convenience, but its conversion accuracy is generally lower.

[0037] On the other hand, in the present disclosure, the time transfer signal is aligned using a logical OR gate, so the conversion accuracy of the MCU itself (the accuracy of the second initial time transfer signal) does not actually affect the accuracy of the final output second transfer signal. Therefore, by using the MCU as a conversion unit, it is possible to achieve conversion of time transfer signals with low cost, low power consumption, small size, and high accuracy.

[0038] Of course, the specific form of the conversion unit in the present disclosure is not limited to an MCU, and for example, an FPGA can be used as the conversion unit.

[0039] In some embodiments, the first format is 1PPS+TOD, the second format is IRIG1-B, and the trigger signal of the first time transfer signal is a 1PPS signal.

[0040] As an embodiment of the present disclosure, for example, the method can be used to convert a 1PPS+TOD time-to-date signal into an IRIG-B time-to-date signal, whereby the first time-to-date signal is a 1PPS+TOD time-to-date signal, of which the trigger signal is a 1PPS signal, the second initial time-to-date signal is IRIG-B (initial), and the second time-to-date signal is IRIG-B (output).

[0041] In the following part of the content, we will use 1PPS+TOD time transfer signal and IRIG-B time transfer signal as examples.

[0042] Of course, the specific format of the time transfer signal in this disclosure is not limited to this, and can also be used to convert time transfer signals of other formats (including but not limited to DCLS time transfer signals, NTP time transfer signals, PTP time transfer signals, etc.), as long as the fixed point in time of the time transfer signal is the rising edge.

[0043] In some embodiments, as shown in Figures 3 and 5, the step (S101) of the conversion unit obtaining a second initial time transfer signal corresponding to the same time based on the first time transfer signal and outputting the second initial time transfer signal may include steps S1011 to S1013.

[0044] In step S1011, the conversion unit obtains the date and time TOD signal and the 1PPS signal of the first time signal.

[0045] In step S1012, the conversion unit generates information of a second initial time-to-date signal based on the time corresponding to the TOD signal plus a preset time length, and stores the information in the cache.

[0046] In step S1013, in response to the rising edge of the 1PPS signal of one of the first time exchange signals, the conversion unit obtains from the cache information of the second initial time exchange signal generated based on the first time exchange signal of a preset time length, and generates and outputs the second initial time exchange signal.

[0047] As shown in FIG. 5, the conversion unit can receive the TOD signal in the 1PPS+TOD time transfer signal (first time transfer signal) (for example, by the TOD time information receiving module), then analyze the time of the TOD signal (for example, by the B code format conversion module), add a preset time length (for example, 1 s) to the time, and then re-encode (for example, BCD encode) the obtained time (for example, if the time of the TOD signal is 15:00:00, the time after adding 1 s is 15:00:01) to generate the IRIG-B time transfer signal (second initial time transfer signal). The information of the IRIG-B time transfer signal (for example, the type of each symbol of the IRIG-B time transfer signal) is obtained, and the information of the IRIG-B time transfer signal is stored in a cache. When a 1PPS signal (trigger signal) of the 1PPS+TOD time transfer signal after a preset time length (for example, the next) arrives, the information of the current IRIG-B time transfer signal is triggered to be read from the cache (for example, by the 1PPS trigger module), and a second initial time transfer signal generated based on the information is output (for example, by the B code output module), i.e., IRIG-B (initial) in Figures 4 and 5. Here, the above trigger can be understood as actually triggering the output of information corresponding to the TOD signal before (for example, the previous) a preset time length for each 1PPS signal.

[0048] Here, the TOD signal itself, which is the same time transfer signal, is 1 ms slower than the 1PPS signal, and the second initial time transfer signal obtained by converting it also requires a certain time. That is, the time when the second initial time transfer signal (IRIG-B(initial)) is actually generated inevitably has a larger delay than the time represented by the directly corresponding TOD signal. Therefore, to avoid an error due to the large time difference between the second initial time transfer signal and the 1PPS signal, which would cause excessive distortion of the first symbol of the second time transfer signal obtained by the logical OR gate, the time corresponding to the TOD signal can be added to a preset time length (e.g., 1 second) before conversion, and the output can be waited for the trigger of the 1PPS signal after the preset time length (such as the 1PPS signal of 1 second). (Because the 1PPS signal always has one 1 second, this output is still accurate.)

[0049] Of course, in order to make the time difference as short as possible, the above preset time length may be 1 second, and the signals before / after the corresponding preset time length are the signals one before / one after.

[0050] In some embodiments, the information of the second initial time exchange signal is pulse width modulated PWM information for each pulse thereof.

[0051] In an embodiment of the present disclosure, the number and positions (at 10 ms intervals) of IRIG-B time transfer signal pulses (symbols) are all fixed, and the meaning of the corresponding symbol is simply distinguished by the pulse width of each pulse (e.g., 8 ms, 5 ms, 2 ms). Therefore, by storing the PWM (Pulse Width Modulation) information (e.g., duty ratio or pulse width) of each pulse (symbol), all signals of the IRIG-B time transfer signal can be represented, thereby reducing the amount of information to be stored and simplifying the information format.

[0052] For example, for each IRIG-B time transfer signal, 100 duty ratio values ​​corresponding to the 100 pulses can be stored in the cache in sequence, and the sequence of the 100 values ​​can be used as the corresponding information.

[0053] Therefore, when the generation of the IRIG-B time transfer signal (i.e., the second initial time transfer signal of the B code) starts based on this information (for example, when the next 1PPS signal is received), a 10 ms timer can be started, so that one numerical value can be read from the cached array every 10 ms, and one pulse of the corresponding pulse width can be generated and output based on this value.

[0054] Of course, it is also possible that the information of the second initial time signal is in other formats or is stored in other ways.

[0055] In some embodiments, the preset amount of time is 1 second and the cache is a ping-pong cache.

[0056] In an embodiment of the present disclosure, the cache for storing the information of the second initial time exchange signal may be a "ping-pong cache." As shown in Fig. 5, the ping-pong cache actually includes two cache areas, i.e., buffer1 and buffer2. When writing the information of the second initial time exchange signal to buffer1, the previously stored information of the second initial time exchange signal can be read from buffer2 to generate the second initial time exchange signal. When writing the information of the second initial time exchange signal to buffer2, the previously stored information of the second initial time exchange signal can be read from buffer1 to generate the second initial time exchange signal.

[0057] For example, as shown in FIG. 5, one read pointer and one write pointer can be provided, and the two pointers point to buffer1 and buffer2 in turn, and perform read and write operations on buffer1 and buffer2 in turn.

[0058] The ping-pong cache allows only a small amount of cache space to be used, and when operations such as information copying are not performed, information can be read and written simultaneously at any time. Therefore, when the structure is simple and the cost is low (e.g., in an MCU), the method disclosed herein can operate well and can continue to reliably output the second initial time transmission / reception signal.

[0059] Of course, the specific form of the cache in the embodiment of the present disclosure is not limited to this, and it is sufficient if the cache can write and read information of the second initial time transmission / reception signal in a timely manner.

[0060] In a second aspect, the present disclosure provides an apparatus for time-transfer signal conversion.

[0061] The time transfer signal conversion device of the present disclosure is used to realize the above time transfer signal conversion method.

[0062] Here, the time transfer signal conversion device disclosed herein may be an independent device dedicated to performing the conversion, or may be integrated with equipment that generates the original time transfer signal (e.g., a power 5G CPE product that supports 5G time transfer function, a device that supports GPS time transfer, etc.), or may be integrated with a target device that requires the converted time transfer signal (e.g., a power terminal, etc.). As shown in FIG. 6, in one embodiment, the time transfer signal conversion device of the present disclosure includes: a conversion unit configured to obtain a second initial time transfer signal corresponding to the same time based on a first time transfer signal, and output the second initial time transfer signal; and a logic OR gate configured to receive a trigger signal of the first time transfer signal and the second initial time transfer signal, and output the second time transfer signal, wherein the first time transfer signal has a first format, the second initial time transfer signal and the second time transfer signal have second formats, and the fixed time points of the trigger signal of the first time transfer signal, the second initial time transfer signal and the second time transfer signal are all rising edges.

[0063] In some embodiments, the conversion unit includes an MCU.

[0064] In some embodiments, the first format is 1PPS+TOD, the second format is IRIG-B, and the trigger signal of the first time-transfer signal is a 1PPS signal.

[0065] In a third aspect, the present disclosure provides a computer-readable medium having a computer program stored thereon, the computer program causing the processor to perform the method for time-transfer signal conversion of any of the embodiments of the present disclosure, as shown in FIG. 8, when the computer program is executed by a processor.

[0066] Those skilled in the art will understand that all or some of the steps, systems, and functional modules / units in the devices disclosed above can be implemented as software, firmware, hardware, or a suitable combination thereof.

[0067] In hardware embodiments, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by multiple physical components working together.

[0068] Some or all of the physical components may be implemented as software executed by a processor, such as a central processor (CPU), digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as a dedicated integrated circuit. Such software may be distributed on computer-readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (e.g., computer-readable instructions, data structures, program modules, or other data). Computer storage media may be used for any medium that stores the desired information and is accessible by a computer, including, but not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk memory, read-only optical disks (CD-ROMs), digital versatile disks (DVDs) or other optical disk memory, magnetic cassettes, magnetic tapes, magnetic disk storage devices, or other magnetic storage devices. Additionally, communication media typically includes computer-readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery media as known to those skilled in the art.

[0069] In this disclosure, exemplary embodiments are disclosed, and specific terms are used; however, they are to be used and interpreted in a general, illustrative sense only, and not for purposes of limitation. It will be apparent to those skilled in the art that, in some embodiments, features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or may be used in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specified. Accordingly, those skilled in the art will recognize that various changes in form and detail may be made without departing from the scope of the present disclosure, as defined by the appended claims.

Claims

1. A conversion unit obtains a second initial time transfer signal corresponding to the same time according to the first time transfer signal, and outputs the second initial time transfer signal; a logic OR gate receiving a trigger signal of the first time transfer signal and a second initial time transfer signal and outputting a second time transfer signal; the first time transfer signal has a first format, the second initial time transfer signal and the second time transfer signal have a second format; The fixed time point of the trigger signal of the first time exchange signal is a rising edge of the trigger signal of the first time exchange signal, the fixed time point of the second initial time exchange signal is a rising edge of the second initial time exchange signal, and the fixed time point of the second time exchange signal is a rising edge of the second time exchange signal; the first format is 1 pulse per second + time of day 1PPS + TOD, said second format is the Remote Communications Workgroup B code IRIG-B; The trigger signal of the first time transmission / reception signal is a 1 pulse per second (1PPS) signal; A method for converting time-transfer signals.

2. The conversion unit includes a microcontroller unit MCU The method of claim 1.

3. The step of the conversion unit obtaining a second initial time transfer signal corresponding to the same time based on the first time transfer signal and outputting the second initial time transfer signal comprises: The conversion unit obtains a date and time TOD signal and a 1PPS signal from the first time transmission and reception signal; The conversion unit generates information of the second initial time-to-date signal based on the time corresponding to the TOD signal plus a preset time length, and stores the information in a cache; The conversion unit, in response to a rising edge of the 1 PPS signal of one of the first time transfer signals, retrieves information of a second initial time transfer signal generated based on the first time transfer signal of a preset time length from a cache, and generates and outputs the second initial time transfer signal. The method of claim 1.

4. The preset time length is 1 s, The cache is a ping-pong cache The method of claim 3.

5. The information of the second initial time transmission signal is pulse width modulation (PWM) information of each pulse thereof. The method of claim 3.

6. a conversion unit configured to obtain a second initial time transfer signal corresponding to the same time based on the first time transfer signal, and output the second initial time transfer signal; a logic OR gate configured to receive a trigger signal of the first time delivery signal and a second initial time delivery signal and to output a second time delivery signal; the first time transfer signal has a first format, the second initial time transfer signal and the second time transfer signal have a second format; The fixed time point of the trigger signal of the first time exchange signal is a rising edge of the trigger signal of the first time exchange signal, the fixed time point of the second initial time exchange signal is a rising edge of the second initial time exchange signal, and the fixed time point of the second time exchange signal is a rising edge of the second time exchange signal; the first format is 1 pulse per second + time of day 1PPS + TOD, said second format is the Remote Communications Workgroup B code IRIG-B; The trigger signal of the first time transmission / reception signal is a 1 pulse per second (1PPS) signal; A device for converting time signals.

7. The conversion unit includes a microcontroller unit MCU.

7. The apparatus of claim 6.

8. A computer program is stored, and when the computer program is executed by a processor, the method for time transfer signal conversion according to any one of claims 1 to 5 is realized by the processor. A computer-readable storage medium.

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