Semiconductor device and control method

Abstract

To perform a high-speed data transfer between a host and a memory chip.SOLUTION: A semiconductor device comprises a first chip, a second chip group which are a plurality of second chips electrically connected to the first chip, and a third chip group which are a plurality of third chips electrically connected to the first chip in parallel with the second chip group. The first chip has a command queue which stores a plurality of read commands received from a host, and a read buffer memory which buffers read data. The first chip sequentially issues the plurality of read commands stored in the command queue to the second chip group or the third chip group, stores the read data corresponding to the plurality of read commands in the read buffer memory from the second chip group or the third chip group, and transmits any read data among the pieces of read data stored in the buffer memory to the host, on the basis of an execution state of any read command among the plurality of read commands.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device and a control method. [Background technology]

[0002] There is a semiconductor device that can be connected to a host. Such a semiconductor device has multiple memory chips. The semiconductor device also has multiple channels connected to the multiple memory chips. Commands and data intended for the memory chips are transferred between the host and the semiconductor device. It is desirable to transfer signals corresponding to the commands and data between the host and the memory chips at high speed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-149729 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of one embodiment is to provide a semiconductor device that transfers data between a host and a memory chip at high speed. [Means for solving the problem]

[0005] According to one embodiment, a semiconductor device comprises a first chip, a second chip group consisting of a plurality of second chips electrically connected to the first chip, and a third chip group consisting of a plurality of third chips electrically connected to the first chip in parallel to the second chip group, wherein the first chip has a command queue that stores a plurality of read commands received from a host and a read buffer memory that buffers the read data, sequentially issues the plurality of read commands stored in the command queue to the second chip group or the third chip group, stores read data corresponding to the plurality of read commands from the second chip group or the third chip group in the read buffer memory, and transmits any of the read data stored in the read buffer memory to the host based on the execution status of any of the plurality of read commands. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a diagram showing the configuration of a storage system to which a semiconductor device according to a first embodiment is applied; [Figure 2] FIG. 1 is a diagram showing a configuration of a semiconductor device according to a first embodiment. [Figure 3] FIG. 3 is a diagram showing the operation of the semiconductor device according to the first embodiment. [Figure 4] FIG. 10 is a diagram showing the operation of the semiconductor device according to the second embodiment. [Figure 5] FIG. 10 is a diagram showing the operation of the semiconductor device according to the third embodiment. [Figure 6] FIG. 10 is a diagram showing the operation of the semiconductor device according to the fourth embodiment. [Figure 7] FIG. 10 is a diagram showing another operation of the semiconductor device according to the fourth embodiment. [Figure 8] FIG. 10 is a diagram showing the operation of the semiconductor device according to the fifth embodiment. [Figure 9] FIG. 10 is a diagram showing the operation of the semiconductor device according to the sixth embodiment. [Figure 10] FIG. 13 is a diagram showing the operation of the semiconductor device according to the seventh embodiment. [Figure 11]FIG. 13 is a diagram showing another operation of the semiconductor device according to the seventh embodiment. [Figure 12] FIG. 13 is a diagram showing the configuration of a semiconductor device according to an eighth embodiment. [Figure 13] FIG. 13 is a diagram showing the operation of the semiconductor device according to the eighth embodiment. [Figure 14] FIG. 13 is a diagram showing the operation of the semiconductor device according to the ninth embodiment. [Figure 15A] FIG. 23 is a diagram showing an example of data read by a StatusRead command according to the ninth embodiment. [Figure 15B] FIG. 23 is a diagram showing an example of formatted read data according to the ninth embodiment. [Figure 16A] FIG. 23 is a diagram showing another example of data read by the StatusRead command according to the ninth embodiment. [Figure 16B] FIG. 23 is a diagram showing another example of data obtained by formatting read data according to the ninth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the embodiment.

[0008] (First embodiment) A semiconductor device according to an embodiment includes an external terminal connectable to a host, a bridge chip, and multiple chips. The multiple chips are connected to the external terminal via the bridge chip. The external terminal of the semiconductor device is connected to the host via a wired communication path. In this semiconductor device, access from the host to the multiple chips via the wired communication path is performed via the bridge chip. Each chip is, for example, a memory chip of a nonvolatile memory such as a NAND flash memory.

[0009] When each chip is a memory chip, the number of chips mounted on a semiconductor device is increasing to improve packaging density. For example, stacking chips can improve packaging density. In this case, to reduce the load on connections to each chip and increase speed, a bridge chip called an FBI (Frequency Boosting Interface) chip is connected to an external terminal, and multiple channels are used to connect the bridge chip to multiple chips. Multiple chips can be connected to each channel. The bandwidth of the wired communication path is equal to the bandwidth of each channel but smaller than the total bandwidth of the channels. Because one channel is used selectively among multiple channels, the communication speed between the bridge chip and each chip tends to be slow. Therefore, when a semiconductor device receives a command from a host and processes the command on each channel according to the received command, a waiting time tends to occur on the host side.

[0010] Therefore, in this embodiment, a command queue capable of storing multiple commands is provided in the semiconductor device, and commands are executed in parallel on multiple channels, thereby improving the data transfer speed between the host and multiple chips via the bridge chip.

[0011] Specifically, the storage system SYS to which the semiconductor device 1 is applied is configured as shown in Fig. 1. Fig. 1 is a diagram showing the configuration of the storage system SYS to which the semiconductor device 1 is applied.

[0012] The storage system SYS includes a host HA and a semiconductor device 1. The semiconductor device 1 includes a bridge chip BC and a plurality of chips LUN0 to LUN7. The bridge chip BC is an example of a first chip. The chips LUN0 to LUN3 are an example of a second chip. The chips LUN4 to LUN7 are an example of a third chip. The semiconductor device 1 can be implemented as an MCP (Multi Chip Package) in which the chips LUN0 to LUN7 are stacked. When the semiconductor device 1 is implemented as an MCP, the periphery of the bridge chip BC and the plurality of chips LUN0 to LUN7 in the semiconductor device 1 may be sealed with molding resin. FIG. 1 illustrates a configuration in which four chips LUN0 to LUN3 are connected to the bridge chip BC via a channel CH1, and four chips LUN4 to LUN7 are connected to the bridge chip BC via a channel CH2. That is, the semiconductor device 1 can be configured as a multi-chip module including a plurality of (here, eight) chips LUN0 to LUN7. Each of chip LUN0 to chip LUN7 is a memory chip of a nonvolatile memory such as a NAND flash memory.

[0013] The host HA may be a device such as a controller, or may be a processor provided in an electronic device such as a computer or a mobile terminal and controlling the semiconductor device 1. The semiconductor device 1 can be connected to the host HA via a wired communication channel (e.g., a serial bus) CH0. The semiconductor device 1 and the host HA are connected via the wired communication channel CH0 configured based on a predetermined standard. When each of chips LUN0 to LUN7 is a NAND flash memory, the predetermined standard is, for example, the toggle DDR standard or the ONFi standard. For example, the wired communication channel CH0 functions as a toggle DDR interface.

[0014] The bridge chip BC is electrically connected between the external terminal group 1a and a plurality of (here, two) channels CH1 and CH2. The external terminal group 1a can be electrically connected to the host HA via a wired communication path CH0. A plurality of chips LUN0 to LUN7 are connected to the bridge chip BC via a plurality of channels CH1 and CH2. The bridge chip BC and each of the chips LUN0 to LUN7 are connected via channels CH1 and CH2 configured based on a predetermined standard. If each of the chips LUN0 to LUN7 is a NAND-type flash memory, the predetermined standard is, for example, the toggle DDR standard or the ONFi standard. For example, the channels CH1 and CH2 function as a toggle DDR interface. Furthermore, the chip group CP1 is a chip group consisting of chips LUN0 to LUN3. The chip group CP2 is a chip group consisting of chips LUN4 to LUN7. The chip group CP1 is an example of a second chip group. The chip group CP2 is an example of a third chip group.

[0015] Fig. 2 is a diagram showing a detailed configuration of the semiconductor device 1. For example, as shown in Fig. 2, the external terminal group includes a terminal for a chip enable signal CEZ, a terminal for a data signal DQ[7:0], a terminal for a read enable signal RE / RE, a terminal for a data strobe signal DQS / DQS, and a terminal for an R / B signal.

[0016] As access speeds become increasingly faster, the semiconductor device 1 can perform command-related operations in synchronization with the rising and falling edges of a timing signal for capturing transferred data. The R / B signal indicates whether the semiconductor device 1 is accessible. An example of a chip control signal is the chip enable signal CEZ. An example of transferred data is the data signal DQ[7:0]. An example of a timing signal is the data strobe signal DQS / DQS_. The read enable signal RE_ and the read enable signal RE form a pair of differential signals. The data strobe signal DQS and the data strobe signal DQS_ form a pair of differential signals. The read enable signal RE_ / RE is a timing signal supplied from the host HA. The data strobe signal DQS / DQS_ is a timing signal output to the host HA in response to a data read request from the host HA. For this reason, the timing signals can be configured as differential signals.

[0017] The bridge chip BC includes a controller 101 , a read buffer memory 102 , a write buffer memory 103 , and a channel interface 104 .

[0018] The controller 101 is arranged between a terminal for the chip enable signal CEZ, a terminal for the data signal DQ[7:0], a terminal for the read enable signal RE_ / RE, a terminal for the data strobe signal DQS / DQS_, and a terminal for the R / B_ signal and the channel interface 104. The controller 101 uses a read buffer memory 102 and a write buffer memory 103 to control the exchange of information between the above-mentioned terminals and the channel interface 104.

[0019] The controller 101 includes a command queue 101a, a command decoder 101b, a command queue status management unit 101c, a command priority control unit 101d, a command issue timing control unit 101e, an RE - / RE generation unit 101f, and a buffer control unit 101g.

[0020] The command queue 101a queues commands (for example, write commands, read commands, etc.) received from the host HA.

[0021] The command decoder 101b analyzes commands received from the host HA via a terminal for the data signal DQ[7:0] and issues commands to the chip groups CP1 and CP2 according to the analysis results. The issued commands are supplied to either of the chip groups CP1 and CP2 from the channel interface 104 via either of the channels CH1 and CH2. For example, the command decoder 101b may receive a data setup command or a data output command from the host HA as a read command. The data output command is an example of a read command. The data setup command is a command that instructs data transfer from the memory cell array 111 of the target chip LUN included in the chip groups CP1 and CP2 to the buffer memory 113. The data output command is a command that instructs data stored in the buffer memory 113 of the target chip LUN included in the chip groups CP1 and CP2 to be output from the chip groups CP1 and CP2. In response to receiving each command from the host HA, the command decoder 101b supplies the corresponding command to either the chip group CP1 or CP2 via either the channel CH1 or CH2 from the channel interface 104. The command decoder 101b also executes decoding processing for write commands and erase commands.

[0022] The command queue status management unit 101c refers to the execution status of the command stored in the command queue 101a and transmits information about the execution status of the command to the host HA. Here, the execution status of the command indicates the processing status of read / write, etc., related to the command in the chip LUN0, etc., that issued the command.

[0023] The command priority control unit 101d changes the execution order of commands stored in the command queue 101a in accordance with instructions from the host HA.

[0024] The command issue timing control unit 101e controls the timing of issuing instructions to the chip groups CP1 and CP2 to process commands.

[0025] If the command is a data output command according to the analysis result of the command decoder 101b, the RE - / RE generator 103b autonomously generates a read enable signal RE - / RE. The generated read enable signal RE - / RE is supplied to either the chip group CP1 or CP2 from the channel interface 104 via either the channel CH1 or CH2.

[0026] When the controller 101 receives the read enable signals RE - / RE from the host HA, it generates data strobe signals DQS / DQS - from the received read enable signals RE - / RE and outputs them to the host HA.

[0027] The buffer control unit 101 g controls the reading and writing of data from and to the read buffer memory 102 and the write buffer memory 103 .

[0028] The read buffer memory 102 is provided to store data read from the chip group CP1 or the chip group CP2. The read buffer memory 102 can be configured, for example, by an SRAM.

[0029] The write buffer memory 103 is provided to store data to be written to the chip group CP1 or the chip group CP2. The write buffer memory 103 can be configured, for example, by an SRAM.

[0030] The channel interface 104 connects with the chip groups CP1 and CP2 via the channels CH1 and CH2. The channel interface 104 transfers commands, addresses, data, etc. supplied from the controller 101 to the chip groups CP1 and CP2 via the channels CH1 and CH2, stores data supplied from the chip groups CP1 and CP2 in the read buffer memory 102 and write buffer memory 103, and supplies the data to the controller 101.

[0031] Each of the chip LUNs has terminal groups TM1 to TM4, a memory cell array 111, a peripheral circuit 112, and a buffer memory 113. The terminal groups TM1 to TM4 are electrically connected to the channel interface 104 via one channel CH1. The terminal groups TM1, TM2, TM3, and TM4 of each of the multiple chip LUN0 to chip LUN3 are electrically connected to one another. The terminal groups TM1 to TM4 are electrically connected to the peripheral circuit 112 and one end of the channel CH1. The other end of the channel CH1 is electrically connected to the channel interface 104.

[0032] The terminal group TM1 is a terminal group for the chip enable signal CEZ, and includes terminals the number of which corresponds to the bit width of the chip enable signal CEZ.

[0033] The terminal group TM2 is a terminal group for the data signal DQ[7:0]. The terminal group TM1 includes terminals the number of which corresponds to the bit width (for example, 8 bits) of the data signal DQ[7:0].

[0034] The terminal group TM3 is a terminal group for the read enable signal RE_ / RE. The terminal group TM2 includes terminals the number of which corresponds to the bit width of the read enable signal RE_ / RE.

[0035] The terminal group TM4 is a terminal group for the data strobe signals DQS / DQS − . The terminal group TM3 includes terminals the number of which corresponds to the bit width of the data strobe signals DQS / DQS − .

[0036] The memory cell array 111 has a structure in which a plurality of memory cells are arranged two-dimensionally or three-dimensionally. The memory cell array 111 is connected to a peripheral circuit 112. The peripheral circuit 112 is arranged on the periphery of the memory cell array 111 and is electrically connected to terminal groups TM1 to TM4, a buffer memory 113, and the memory cell array 111. The peripheral circuit 112 controls access operations (e.g., read operations, write operations) to each memory cell of the memory cell array 111 using the buffer memory 113 in response to commands received from the bridge chip BC via the terminal group TM2.

[0037] The buffer memory 113 is a buffer for input / output via terminal groups TM1 to TM4 in each of chips LUN0 to LUN3 of the chip group CP1, and is also called an input / output data latch or a page buffer. The peripheral circuit 112 temporarily stores data read from the memory cell array 111 in the buffer memory 113 in response to a read data command received from the bridge chip BC. Therefore, the capacity (or size) of the buffer memory 113 has a data size (e.g., 16 kB) that is the data read unit in the chip group CP1.

[0038] In response to a data output command received from the bridge chip BC, the peripheral circuit 112 supplies the data stored in the buffer memory 113 to the bridge chip BC via the terminal group TM1 to the terminal group TM4 and the channel CH1. At this time, the controller 101 of the bridge chip BC temporarily stores the data received from any one of the chip LUNs of the chip group CP1 in the read buffer memory 102.

[0039] Here, the capacity (or size) of the Read buffer memory 102 of the bridge chip BC is an integer multiple (for example, 16×N [kB], where N is any positive integer) of the data size that is the read unit of data from the chip group CP1. This allows the buffer memory to store the read data continuously when the read data is continuously output from the chip group CP1.

[0040] Similarly, the chip LUN of the chip group CP2 connected to the channel CH2 also has terminal groups TM1 to TM4, a memory cell array 111, a peripheral circuit 112, and a buffer memory 113. Each configuration is the same as the chip LUN of the chip group CP1 connected to the channel CH1, so a description thereof will be omitted.

[0041] Next, the operation of the semiconductor device 1 will be described with reference to Fig. 3. HOST Ch0 shown in Fig. 3 indicates a signal exchanged between the host HA and the bridge chip BC via the wired communication channel CH0. NAND Ch1 shown in Fig. 3 indicates a signal exchanged between the bridge chip BC and the chip group CP1 via the channel CH1. NAND Ch2 shown in Fig. 3 indicates a signal exchanged between the bridge chip BC and the chip group CP2 via the channel CH2.

[0042] The "CMDQ Status" table shown in FIG. 3 shows information indicating the execution status of commands stored in the command queue 101a. "ST" in the "CMDQ Status" table indicates the processing status of each command. When "ST" is "0", it indicates that command processing is incomplete. When "ST" is "1", it indicates that command processing has been completed. The Read buffer shown in FIG. 3 shows information stored in the Read buffer memory 102.

[0043] The bridge chip BC receives a data setup command CM*s (* corresponds to the LUN number) from the host HA, and then receives a data output command CM*r after data transfer from the memory cell array 111 of the target LUN to the buffer memory 113 is complete (the data setup command CM*s will be omitted from the following operation examples). The data setup command CM*s is a preparation command for read processing. The operation example of FIG. 3 shows an example in which a data output command CM0r for chip LUN0, a data output command CM1r for chip LUN1, a data output command CM4r for LUN4, and a data output command CM5r for LUN5 are received in this order from the host HA. In this example, the command decoder 101b decodes each of the data output commands CM0r, CM1r, CM4r, and CM5r and stores them in the command queue 101a.

[0044] The command issuance timing control unit 101e issues a data output command CM*r depending on the availability of channel Ch1 or channel Ch2. Specifically, when the data output command CM0r is stored in the command queue 101a, the command issuance timing control unit 101e issues the data output command CM0r to channel Ch1. Note that the state of the "CMDQ Status" table at this timing t1 is that the data output command CM0r is set, and "ST" is set to "0," indicating that reading from channel Ch1 is not complete. In addition, the memory cell array 111 sends the data to be read that is stored in the buffer memory 113 to the bridge chip BC.

[0045] Furthermore, when the data output command CM1r is stored in the command queue 101a, the command issuance timing control unit 101e does not issue the data output command CM1r to channel Ch1 because the channel Ch1 to which the data output command CM1r is to be issued is currently executing a command. Note that the buffer control unit 101g sequentially stores the read data sent from chip LUN0 during the DOUT period in the "CM0r DOUT" area of ​​the Read buffer memory 102.

[0046] Next, when the data output command CM4r is stored in the command queue 101a, the command issuance timing control unit 101e issues the data output command CM4r stored in the command queue 101a to channel Ch2. In this way, the command issuance timing control unit 101e sequentially issues the data output commands stored in the command queue 101a to channel Ch1 or channel Ch2.

[0047] At timing t2, the "CMDQ Status" table contains the data output command CM1r and the data output command CM4r, and the "ST" of these commands is set to "0" indicating that these commands have not been completed. Also, with regard to the data output command CM0r, since not all of the read data sent from chip LUN0 has been stored in the Read buffer memory 102, the flag information of the data output command CM0r is also set to "0."

[0048] Furthermore, when the output of read data from chip LUN0 is completed, the command issuance timing control unit 101e issues a data output command CM1r to chip LUN1. Furthermore, the command queue status management unit 101c updates "ST" of "CM0r" in the "CMDQ Status" table to "1". When the host HA has issued a predetermined number of commands, it issues a command CQ0 indicating a status check. The command queue status management unit 101c sends the information in the "CMDQ Status" table to the host HA.

[0049] The host HA refers to the information in the "CMDQ Status" table and reads the read data of the data output command for which "ST" is "1." At timing t3, "ST" of "CM0r" is "1," so the host HA makes a read request for the read data of chip LUN0 corresponding to the data output command CM0r. In response to this, the buffer control unit 101g sends the data in the "CM0r DOUT" area of ​​the read buffer memory 102 to the host HA. In response to the completion of sending the read data of the data output command CM0r to the host HA, the command queue status management unit 101c deletes the record for "CM0r" from the "CMDQ Status" table.

[0050] At timing t4, "ST" of "CM4r" in the "CMDQ Status" table becomes "1." Because not all of the read data sent from chip LUN5 in response to data output command CM5r issued before timing t4 has been stored in the read buffer memory 102, "ST" of data output command CM5r becomes "0." At timing t5, "ST" of "CM1r" and "CM5r," which have not yet completed reading, becomes "1."

[0051] In this way, the bridge chip BC stores read data corresponding to the read command stored in the command queue 101a as a data output command from the first chip group CP1 or the second chip group CP2 in the read buffer memory 102, and transmits the read data to the host HA according to the execution status of the command in the command queue 101a. The bridge chip BC can store multiple commands in the command queue 101a, executes the commands sequentially, and transmits the read data to the host HA according to the status of the read data stored in the read buffer memory 102, so that processing can be executed between the host HA and the bridge chip BC without any waiting time.

[0052] (Second embodiment) In the first embodiment, the next data output command is issued to the chip after all read data corresponding to the data output command is stored in the read buffer memory 102. In the second embodiment, the next data output command is issued to the chip after some read data corresponding to the data output command is stored in the read buffer memory 102.

[0053] An example of operation according to the second embodiment will be described with reference to FIG. 4. Explanation of points common to those shown in FIG. 3 will be omitted. The timing t11 is the same as the timing t1 in FIG. 3. A data output command CM0r is issued to chip LUN0. After timing t11, the buffer control unit 101g stores a predetermined size of read data in the Read buffer memory 102. At this point, reception of read data from chip LUN0 is interrupted. In response, the command issuance timing control unit 101e issues a data output command CM1r to LUN1. The data output command CM0r is an example of a first read command, and the data output command CM1r is an example of a second read command. Furthermore, the command queue status management unit 101c updates the "ST" of "CM0r" in the "CMDQ Status" table to "1." As a result, at timing t12, the "ST" of "CM0r" in the "CMDQ Status" table becomes "1."

[0054] Furthermore, for other data output commands as well, the bridge chip BC updates "ST" of "CM*r" in the "CMDQ Status" table to "1" when part of the read data has been stored in the Read buffer memory 102. That is, the same process is executed for the data output command CM1r and the data output command CM4r. Then, at timing t13 when the host HA issues the command CQ0 indicating a status check after finishing issuing the data output command, "ST" of "CM0r", "CM1r", and "CM4r" in the "CMDQ Status" table becomes "1".

[0055] Furthermore, when the host HA starts reading the read data, the buffer control unit 101g stores the remaining read data from the target chip LUN in the read buffer memory 102. For example, when the host HA makes a read request for read data of chip LUN0 corresponding to the data output command CM0r, the buffer control unit 101g stores the remaining read data from the target chip LUN in the read buffer memory 102.

[0056] In this way, the bridge chip BC according to the second embodiment stores a portion of the read data corresponding to the data output command in the read buffer memory 102. After that, the bridge chip BC according to the second embodiment stores the remaining read data corresponding to the data output command from the first chip group CP1 or the second chip group CP2 in the read buffer memory 102 based on the state of the other data output command. This enables the host HA to read the read data at an earlier timing than in the case of the bridge chip BC according to the first embodiment. Also, the capacity of the read buffer memory 102 can be reduced.

[0057] (Third embodiment) In the first and second embodiments, the bridge chip BC executes command processing based on the order of commands sent from the host HA. In this embodiment, the order of command processing is changed based on a specification from the host HA.

[0058] An operation example according to the third embodiment will be described with reference to FIG. 5. Explanation of points common to FIG. 4 will be omitted. The processing from timing t21 to timing t23 is common to the processing from timing t11 to timing t13 in FIG. 4. After issuing a command CQ0 indicating a status check, the host HA issues a command S1 indicating that a data output command CM1r is to be given priority. The command issuance timing control unit 101e of the bridge chip BC instructs the buffer control unit 101g to send the read data of LUN1. In response to this, the buffer control unit 101g reads the read data of chip LUN1, not chip LUN0.

[0059] In this way, the bridge chip BC can flexibly change the timing at which the host HA sends the read data it extracts by changing the data extraction order in accordance with an instruction from the host HA.

[0060] (Fourth embodiment) In the fourth embodiment, the processing when a write processing command is received from the host HA will be described. In the data write processing, write data is received a predetermined period of time after the data write command is received from the host. This causes a waiting time between the host and the data write process, which can lead to the problem of inefficient execution. Therefore, in this embodiment, the write processing is executed via the write buffer memory 103, thereby enabling efficient execution of the write processing.

[0061] An operation example according to the fourth embodiment will be described with reference to Fig. 6. While Figs. 3 to 5 show a read buffer, Fig. 6 shows a write buffer instead. The host HA issues a write command CM0w indicating a command for write processing to chip LUN0. The command decoder 101b then decodes the write command CM0w and stores it in the command queue 101a. Note that in the "CMDQ Status" table at this timing t31, the write command CM0w is set, and "0" indicating that the write is not completed is set in "ST".

[0062] The host HA issues a write command CM0w and transmits write data for chip LUN0 to the bridge chip BC as DIN for chip LUN0. The buffer control unit 101g of the bridge chip BC writes the write data for LUN0 to the write buffer memory 103. The buffer control unit 101g provides an area for write data for chip LUN0 in the write buffer memory 103.

[0063] Then, after transmitting write data (DIN) to chip LUN0, the host HA issues a write command CM4w indicating a command for write processing to chip LUN4. Because the write data has been written to the write buffer memory 103, the host HA does not need to consider the wait time for write processing of the write data between the bridge chip BC and chip LUN0. Therefore, at timing t32, before the write processing from the bridge chip BC to chip LUN0 is completed as shown in NAND Ch1, the host HA issues a write command CM4w as shown in NAND Ch2.

[0064] At timing t33, the write process of the write data between the bridge chip BC and chip LUN0 is completed, so "ST" of "CM0w" in the "CMDQ Status" table is updated to "1".

[0065] Another operation example according to the fourth embodiment will be described with reference to Fig. 7. In Fig. 6, the write buffer memory 103 has only an area for write data corresponding to one command. In this operation example, the write buffer memory 103 has areas for write data corresponding to multiple commands.

[0066] In this case, as shown in FIG. 7, when "CM1w" and "CM2w" are set in the "CMDQ Status" table at timing t43, the buffer control unit 101g provides areas for write data to chip LUN1 and chip LUN2 in the write buffer memory 103. Also, when "CM1w" is set as completed ("ST" is "1") and "CM4w" is newly set as incomplete ("ST" is "0") in the "CMDQ Status" table as at timing t45, the buffer control unit 101g provides a new area for write data to chip LUN4 in the write buffer memory 103 at timing t46. At this time, the buffer control unit 101g deletes the area for write data to chip LUN1 from the write buffer memory 103. This allows the bridge chip BC to process the write process for the chip group CP1 and the write process for the chip group CP2 in parallel.

[0067] In this way, the bridge chip BC is provided with a write buffer memory 103, and when it receives a write command (for example, a write command CM0w) from the host HA, it writes the write data of the command into the write buffer memory 103. Then, the bridge chip BC writes the write data stored in the write buffer memory 103 to the chip LUN. In this case, since the bridge chip BC has written the write data into the write buffer memory 103, the host HA can issue a command without considering the processing time between the bridge chip BC and the chip LUN.

[0068] (Fifth embodiment) The fifth embodiment is an embodiment regarding processing when a plurality of types of commands are mixed, and in the fifth embodiment, it is assumed that a data output command, a write command, and an erase command are mixed.

[0069] An example of operation in the fifth embodiment will be described with reference to Fig. 8. The host HA issues a data output command CM0r indicating a command for a read process to chip LUN0. Next, the host HA issues a data output command CM1r indicating a command for a read process to chip LUN1. Next, the host HA issues a data output command CM4r indicating a command for a read process to chip LUN4. Next, the host HA issues an erase command CM5e indicating a command for an erase process to chip LUN5. Next, the host HA issues a write command CM6w indicating a command for a write process to chip LUN6.

[0070] When the bridge chip BC receives these commands, it stores each command in the command queue 101a. The bridge chip BC also registers a record indicating the status of the command in the "CMDQ Status" table. For records of data output commands and erase commands, the bridge chip BC deletes the record after completing the issuance of the command and after transmitting the command status to the host HA.

[0071] After storing the commands in the command queue 101a, the bridge chip BC executes the same processing as in the first embodiment for the data output commands CM0r, CM1r, and CM4r, and executes the same processing as in the fourth embodiment for the write command CM6w. After extracting the erase command CM5e from the command queue 101a, the bridge chip BC issues the erase command to the target chip LUN5.

[0072] When the bridge chip BC receives the command CQ0 for checking the status, it sends the information of the "CMDQ Status" table to the host HA at timing t54, and the host HA makes a read request for the chip (for example, chip LUN0) in response.

[0073] As described above, the bridge chip BC can store not only data output commands but also write processing commands and erase processing commands in the command queue 101a, executes commands sequentially, and sends read data to the host HA according to the state of the read data stored in the buffer memory. Therefore, even if write processing commands and erase processing commands are mixed, processing can be executed between the host HA and the bridge chip BC without any waiting time.

[0074] (Sixth embodiment) In the sixth embodiment, when there is a priority command, which is a command whose execution order is prioritized, the priority command is executed with priority regardless of the order of commands issued by the host HA.

[0075] An operation example according to the sixth embodiment will be described with reference to Fig. 9. CM*r is a data output command. CM*s is a data setup command. It is assumed that the command priority control unit 101d gives priority to the data setup command.

[0076] The host HA issues commands in the following order: data output command CM0r, data output command CM1r, data setup command CM0s, data setup command CM1s, . . . , data setup command CM5s.

[0077] At timing t61, only the data output command CM0r is stored in the command queue 101a. After timing t61, the bridge chip BC issues commands to channel Ch1 in the following order: data setup command CM0s, data setup command CM1s, and data output command CM1r. At timing t62, the data output command CM0r, data output command CM1r, and data setup command CM0s are stored in the command queue 101a. After the output of read data from chip LUN0 is completed, the data output command CM1r is issued in order by the host HA, but the data setup command CM0s is executed with priority.

[0078] This is because a data setup command takes longer to process than a data output command. In this way, the bridge chip BC can improve the performance of the entire system by prioritizing the processing of commands that take longer to process.

[0079] Seventh embodiment In the seventh embodiment, peak current suppression control is performed on the chip group CP1 or the chip group CP2. Here, the description will be divided into read processing and write processing.

[0080] An operation example of a read process according to the seventh embodiment is shown in Fig. 10. In the example of Fig. 10, the host HA issues a data setup command CM*s and a data output command CM*r. The bridge chip BC issues data setup commands CM0s, CM4s, CM1s, CM5s, CM2s, and CM6s.

[0081] In this state, if the bridge chip BC plans to issue further data setup commands CM3s and CM7s, it suppresses or waits to issue the data setup commands CM3s and CM7s until some of the six data setup commands are completed. During the period (tR) when the read target data is being transferred from the memory cell array 111 to the buffer memory 113, the processing load on the chip increases, so it is desirable to be able to adjust the number of chips that fall within the period tR.

[0082] As described above, the bridge chip BC can reduce the peak current of chip group CP1 or chip group CP2 by adjusting the number of chip LUNs that are performing the process of transferring read data from the memory cell array 111 to the buffer memory 113.

[0083] An operation example of a write process according to the seventh embodiment is shown in Fig. 11. In the example of Fig. 11, the host HA issues a write command CM*w. The bridge chip BC issues write commands CM0w, CM4w, CM1w, CM5w, CM2w, and CM6w.

[0084] In this state, if the bridge chip BC is to issue further write commands CM3w and CM7w, it suppresses or waits until some of the six write commands are completed before issuing the write commands CM3w and CM7w.

[0085] During the period (tPROG) when data to be written is transferred from the buffer memory 113 to the memory cell array 111, the processing load on the chip increases, so it is desirable to be able to adjust the number of chips that fall within the period tPROG.

[0086] As described above, the bridge chip BC adjusts the number of chip LUNs that are performing the process of transferring data from the buffer memory 113 to the memory cell array 111, thereby reducing the peak current of the chip group CP1 or the chip group CP2.

[0087] (Eighth embodiment) In the eighth embodiment, the RBZ signals of the chips in the chip group CP1 or the chip group CP2 are monitored, and a command is issued based on the results.

[0088] The configuration of a semiconductor device 1A according to the eighth embodiment will be described with reference to Fig. 12. Explanation of parts that overlap with the contents shown in Fig. 2 will be omitted. The semiconductor device 1A according to the eighth embodiment further includes an RBZ control unit 101h and an SR format conversion circuit 101i.

[0089] The RBZ control unit 101h monitors and controls the RBZ signal. Here, the RBZ signal is a signal that indicates whether the chip LUN of the chip group CP1 or the chip group CP2 is in a state where it can receive commands from the bridge chip BC. The SR format conversion circuit 101i converts the format of the status read data. Here, the status read data is status information of the chip LUN of the chip group CP1 or the chip group CP2. The Status Read buffer memory 105 is a buffer memory for storing the results of the Status Read command. Each chip LUN further has a terminal group TM5. The terminal group TM5 is a terminal group for the RBZ signal.

[0090] Next, an operation example of the semiconductor device 1 in the eighth embodiment will be described with reference to Fig. 13. HOST Ch0 shown in Fig. 13 indicates a signal exchanged between the host HA and the bridge chip BC via the wired communication channel CH0. NAND Ch1 shown in Fig. 13 indicates a signal exchanged between the bridge chip BC and the chip group CP1 via the channel CH1.

[0091] NAND LUN0 RBZ shown in Fig. 13 indicates the level of the RBZ signal in chip LUN0. NAND LUN01 RBZ shown in Fig. 13 indicates the RBZ signal in chip LUN0, and NAND LUN1 RBZ indicates the RBZ signal in chip LUN1. HOST RBZ0 shown in Fig. 13 indicates the RBZ signal in the bridge chip BC.

[0092] 13 shows information indicating the execution status of commands stored in the command queue 101a. The read buffer shown in FIG.

[0093] CM*r is a data output command. CM*s is a data setup command. The host HA issues commands in the following order: data setup command CM0s, data setup command CM1s, data output command CM0r, and data output command CM1r.

[0094] The bridge chip BC issues a data setup command CM0s to chip LUN0, and issues a data setup command CM1s to chip LUN1. This causes the RBZ signal in chip LUN0 and the RBZ signal in chip LUN1 to become Busy. The RBZ control unit 101h monitors these RBZ signals. At timing t71 when the Busy state of the RBZ signal in chip LUN0 is released, the command issuance timing control unit 101e issues a data output command CM0r to LUN0.

[0095] In this way, the bridge chip BC monitors the chip's RBZ signal and issues a data output command to the chip depending on the state of the RBZ signal, thereby enabling the data output command to be executed efficiently without the host HA having to issue a command to refer to the state of the LUN.

[0096] (Ninth embodiment) The semiconductor device 1B in the ninth embodiment converts the format of the result of the StatusRead command and outputs it. Each of the chips LUN0 to LUN7 has a plurality of parallel operation elements (planes). Each of the chips LUN0 to LUN7 has four planes.

[0097] Next, an example of operation of the semiconductor device 1B in the ninth embodiment will be described with reference to Fig. 14. HOST Ch0 shown in Fig. 14 indicates a signal exchanged between the host HA and the bridge chip BC via the wired communication path CH0. NAND Ch1 indicates a signal exchanged between the bridge chip BC and the chip group CP1 via the channel CH1. NAND Ch2 indicates a signal exchanged between the bridge chip BC and the chip group CP2 via the channel CH2.

[0098] The "CMDQ Status" table shown in Fig. 14 shows information indicating the status of the command queue 101a. The StatusRead buffer (LUN0) shown in Fig. 14 shows information for chip LUN0 stored in the StatusRead buffer memory 105. The StatusRead buffer (LUN4) shown in Fig. 14 shows information for chip LUN4 stored in the StatusRead buffer memory 105.

[0099] SR*P# is a StatusRead command. * corresponds to the LUN number. # corresponds to the plane number. DO immediately after SR*P# in NAND Ch1 and Ch2 indicates a data read corresponding to the StatusRead command.

[0100] The host HA issues StatusRead commands SR0P0, SR0P1, SR0P2, SR0P3, SR4P0, SR4P1, SR4P2, and SR4P3.

[0101] The bridge chip BC issues a StatusRead command SR0P0 or the like to the chip LUN0 or LUN4, reads data corresponding to the StatusRead command from the chip LUN0 or LUN4, and stores it in the buffer memory 105 for StatusRead.

[0102] At timing t81 when all StatusRead commands have been completed, the host HA issues a status confirmation command CQ, and the bridge chip BC transmits the result to the host HA. The status confirmation command CQ is a command for confirming the execution status of the StatusRead command. The host HA issues a merge process command MSR in response to this result. The merge process command MSR is a command that instructs the execution of the StatusRead merge process. The DO immediately after the MSR in HOST Ch0 indicates the transmission of data corresponding to the StatusRead command and the merge process command MSR. In response to these commands, the SR format conversion circuit 101i of the bridge chip BC converts the information in the StatusRead buffer memory 105 and transmits it to the host HA.

[0103] The host HA specifies a template number when issuing the merge process command MSR. An example of conversion of information in the StatusRead command will now be described with reference to Fig. 15A and Fig. 15B.

[0104] FIG. 15A shows data read by a StatusRead command for planes PL0 to PL3. As shown in FIG. 15A, the read data includes eight items of information. FIG. 15B shows a conversion example. As shown in FIG. 15B, for example, when template number 1 is specified, the SR format conversion circuit 101i generates information by extracting information for items 5 and 6 of planes PL0 to PL3 (areas surrounded by thick solid lines in FIG. 15A). Also, when template number 2 is specified, the SR format conversion circuit 101i generates information by extracting information for items 0 and 1 of planes PL0 to PL3 (areas surrounded by thick dotted lines in FIG. 15A).

[0105] As shown in Fig. 16A, when data of the StatusRead command of the chip LUN is read, data corresponding to a preset template number is stored, but other read data may be discarded as shown in Fig. 16B. In this case, the capacity of the StatusRead buffer memory 105 can be reduced.

[0106] In this way, the bridge chip BC converts the information in the StatusRead buffer memory 105 and transmits it to the host HA. This eliminates the need for the host HA to read out the information for the number of planes, thereby reducing the processing load.

[0107] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0108] 1 semiconductor device, 101 controller, 102 read buffer memory, 103 write buffer memory, 104 channel interface, BC bridge chip group, CP1 chip group, CP2 chip group.

Claims

1. a first chip having a terminal to which a signal from a host is input; a second chip group consisting of a plurality of second chips electrically connected to the first chip; a third chip group consisting of a plurality of third chips electrically connected to the first chip in parallel with the second chip group; Equipped with The first chip includes: a command queue for storing a plurality of read commands received from the host; a read buffer memory for buffering read data; sequentially issuing the plurality of read commands stored in the command queue to the second chip group or the third chip group; storing read data corresponding to the plurality of read commands from the second chip group or the third chip group in the read buffer memory; transmitting any one of the read data stored in the read buffer memory to the host based on an execution status of any one of the plurality of read commands; Semiconductor device.

2. The first chip comprises: storing a portion of read data corresponding to a first read command among the plurality of read commands from the second chip group or the third chip group in the read buffer memory; 2. The semiconductor device according to claim 1, wherein the remaining read data corresponding to the first read command is stored in the read buffer memory from the second chip group or the third chip group based on an execution state of a second read command other than the first read command.

3. 2. The semiconductor device according to claim 1, wherein an execution order of said plurality of read commands stored in said command queue is variable.

4. the first chip further includes a write buffer memory; 2. The semiconductor device according to claim 1, wherein the semiconductor device receives a write command from the host, stores write data related to the write command in the write buffer memory, and writes the stored write data to the second chip group or the third chip group.

5. the first chip receives a command different from the read command from the host and further stores the different command in the command queue; The semiconductor device according to claim 1 .

6. 2. The semiconductor device according to claim 1, wherein, when the first chip receives a priority command from the host specifying a command whose execution is to be prioritized, the first chip executes the command whose execution is to be prioritized that is stored in a command queue in accordance with the received priority command.

7. The second chip and the third chip each have a plurality of planes defined therein, which are parallel operating elements; 2. The semiconductor device according to claim 1, wherein said first chip transmits compiled information on the states of each plane to a host.

8. a first chip that is a semiconductor device connectable to a host and has a command queue that stores a plurality of read commands received from the host and a read buffer memory that buffers read data; a second chip group consisting of a plurality of second chips electrically connected to the first chip; a third chip group consisting of a plurality of third chips electrically connected to the first chip in parallel with the second chip group; A control method for controlling a semiconductor device comprising: sequentially issuing the plurality of read commands stored in the command queue to the second chip group or the third chip group; storing read data corresponding to the plurality of read commands from the second chip group or the third chip group in the read buffer memory; a control method for transmitting one of the read data stored in the read buffer memory to the host based on an execution status of one of the plurality of read commands;

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