Analog neural memory array for storing synaptic weights for differential cell pairs in artificial neural networks.

Abstract

To provide an analog neural memory array in which synapsis weights are stored in differential cell pairs in an array; power consumption is substantially constant from a bit line to a bit line within the array when cells are being read; and weight mapping is performed adaptively for optimal performance in power and noise.SOLUTION: An analog neural memory system comprises an array of non-volatile memory cells which can be used in a vector by matrix multiplication (VMM) array, the cells arranged in rows and columns, the columns arranged in physically adjacent pairs of columns, within each adjacent pair, one column in the adjacent pair comprising cells storing W+ values, and one column in the adjacent pair comprising cells storing W- values. The adjacent cells in the adjacent pair store a differential weight W, according to the formula W=(W+)-(W-). In another embodiment, a system comprises a first array of non-volatile memory cells storing W+ values and a second array storing W- values.SELECTED DRAWING: Figure 21A

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. Provisional Patent Application No. 62 / 985,826, filed March 5, 2020, entitled "Analog Neural Memory Array in Artificial Neural Network With Accurate Array Source Impedance With Adaptive Weight Mapping and Distributed Power," and U.S. Patent Application No. 16 / 987,101, filed August 6, 2020, entitled "Analog Neural Memory Array Storing Synapsis Weights In Differential Cell Pairs in Artificial Neural Network."

[0002] FIELD OF THE INVENTION Numerous embodiments of an analog neural memory array are disclosed. In particular embodiments, synaptic weights are stored in differential cell pairs within the array. In particular embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are read. In particular embodiments, weight mapping is performed adaptively for optimal performance in power and noise. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages.

[0004] Figure 1 shows an artificial neural network, where circles represent layers of inputs or neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the artificial neural network to adapt to the inputs and learn. Typically, an artificial neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons, and an output layer of neurons that provide the neural network's output. At each level, neurons make decisions, individually or collectively, based on the data they receive from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. In practice, practical artificial neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computational processes. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] The applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application No. 15 / 594,439, published as U.S. Patent Publication No. 2017 / 0337466, which is incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. As used herein, the term neuromorphic refers to a circuit that implements a model of a nervous system. The analog neuromorphic memory includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses include a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply a first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs. An array of memory cells arranged in this manner may be referred to as a vector by matrix multiplication (VMM) array.

[0007] We now consider examples of different non-volatile memory cells that can be used in a VMM. <<Nonvolatile memory cells>>

[0008] Various types of known nonvolatile memory cells can be used in a VMM array. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed above and insulated from (and controls the conductivity of) a first portion of the channel region 18 and extends over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed above and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0009] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to tunnel from the floating gate 20 to the word line terminal 22 through the insulator between them via Fowler-Nordheim tunneling.

[0010] The memory cell 210 is programmed (electrons are applied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electron current flows from the drain region 16 toward the source region 14 (source line terminal). The electrons accelerate and become energized (heated) when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0011] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased of electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0012] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 2 [Table 1] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0013] Figure 3 shows a memory cell 310 similar to memory cell 210 of Figure 2, with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0V / -8V) during erasure, and a low or medium voltage (e.g., 0V / 2.5V) during reading. The other terminals are biased similarly to the terminals of Figure 2.

[0014] FIG. 4 shows a four-gate memory cell 410 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0015] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 2: Operation of flash memory cell 410 of FIG. 4 [Table 2] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0016] 5 shows a memory cell 510 similar to memory cell 410 of FIG. 4, except that memory cell 510 does not include an erase gate (EG) terminal. Erasing is accomplished by biasing substrate 18 to a high voltage and control gate CG terminal 28 to a low or negative voltage. Alternatively, erasure is accomplished by biasing word line terminal 22 to a positive voltage and control gate terminal 28 to a negative voltage. Programming and reading are similar to those of FIG. 4.

[0017] Figure 6 shows another type of flash memory cell, a three-gate memory cell 610. Memory cell 610 is identical to memory cell 410 of Figure 4, except that memory cell 610 does not have a separate control gate terminal. Erase and read operations (erasure occurs through use of the erase gate terminal) are similar to those of Figure 4, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminal during a program operation to compensate for the lack of control gate bias.

[0018] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 610 of FIG. 6 [Table 3] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0019] FIG. 7 illustrates another type of flash memory cell, a stacked-gate memory cell 710. Memory cell 710 is similar to memory cell 210 of FIG. 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate terminal 22 (coupled to a word line) extends above the floating gate 20, separated by an insulating layer (not shown). Programming is performed using hot electron injection from the channel 18 into the floating gate 20 in the channel region next to the drain region 16, and erasure is performed by Fowler-Nordheim electron tunneling from the floating gate 20 to the substrate 12. Read operations operate in a manner similar to that described above for memory cell 210.

[0020] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 710 of FIG. 7 [Table 4]

[0021] "Read 1" is a read mode in which the cell current is output to a bit line. "Read 2" is a read mode in which the cell current is output to a source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, a source line may be coupled to one row of memory cells or two adjacent rows of memory cells. That is, a source line terminal may be shared by adjacent rows of memory cells.

[0022] 8 shows a twin split gate memory cell 810. The twin split gate memory cell 810 comprises a pair of memory cells (A on the left and B on the right), each of which has a floating gate (FGA, FGB) 20 disposed above and insulated from the substrate 12, a control gate 28 (CGA, CGB) disposed above and insulated from the floating gate 20, and an erase gate 30 (EG) disposed adjacent to and insulated from the floating gate and control gate 20 / 28 and above and insulated from the substrate 12, the erase gate being formed in a T-shape, so that each Floating Gate F G.A., F The upper corners of the GB face the respective inner corners of the T-shaped erase gate to improve the erase efficiency. The erase gate 30 (EG) and the drain region 16 (DRA, DRB) in the substrate adjacent to the floating gate 20 (respective drain N territoryThe memory cells are formed as pairs of memory cells sharing a common erase gate 30. This cell design differs from the memory cells discussed above with reference to FIGS. 2-7 in that it lacks at least a source region under the erase gate EG, a select gate (also called a word line), and a channel region in each memory cell. Instead, a single continuous channel region 18 extends under both memory cells (i.e., from the drain region 16 of one memory cell to the drain region 16 of the other memory cell). To read or program one memory cell, the control gate 28 of the other memory cell is raised to a sufficient voltage to activate a portion of the underlying channel region via voltage coupling to the floating gate 20 between them (e.g., to read or program cell A, a voltage on the FGB is raised via voltage coupling from the CGB to activate the channel region under the FGB). Erasing is performed using Fowler-Nordheim electron tunneling from floating gate 20A and / or floating gate 20B to erase gate 30. Programming is performed using hot electron injection from channel 18 into floating gate 20.

[0023] Table 5 shows typical voltage ranges that may be applied to the terminals of memory cell 810 to perform read, erase, and program operations. Cell A (FG, CGA, BLA) is selected for read, program, and erase operations. Table 5: Operation of Flash Memory Cell 810 of FIG. 8 [Table 5]

[0024] To utilize a memory array comprising one of the above non-volatile memory cell types in an artificial neural network, in one embodiment, two modifications are made: First, as further described below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; and Second, continuous (analog) programming of the memory cells is provided.

[0025] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be continuously changed from a fully programmed state to a fully erased state, or from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog, or at a minimum, can store one of a number of discrete values ​​(such as 16 or 256 different values), which allows very precise and individual tuning of every cell in the memory array, making it ideal for storing and creating fine-tuned synaptic weights for neural networks.

[0026] The methods and means described herein can be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive random access memory), PCM (phase change memory), MRAM (magnetoresistive random access memory), FeRAM (ferroelectric random access memory), OTP (bi-level or multi-level one-time programmable), and CeRAM (strongly correlated electron memory). The methods and means described herein can be applied to, but not limited to, volatile memory technologies used in neural networks, such as SRAM, DRAM, and other volatile synapse cells. <<Neural Network Using Nonvolatile Memory Cell Arrays>>

[0027] 9 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0028] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, where each pixel has 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and sums the outputs of the multiplications to determine a single output value, which is provided by the first synapse of CB1 to generate one pixel of the feature map of layer C1. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for C1 until all of the feature maps for layer C1 have been calculated.

[0029] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, while a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0030] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. The purpose of pooling function P1 is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. An activation function (pooling) is applied at synapse CB3 going from layer S2 to layer C3, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class (classification). This output can indicate, for example, the identity or classification of the content of the original image.

[0031] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0032] Figure 10 is a block diagram of a system that can be used for this purpose. The VMM system 32 includes nonvolatile memory cells and serves as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM system 32 includes a VMM array 33 with nonvolatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the nonvolatile memory cell array 33. Input to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0033] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, the VMM array 33 effectively multiplies the inputs by the weights stored in the VMM array 33 and adds them for each output line (source line or bit line) to produce an output, which becomes the input to the next layer or the input to the last layer. By performing the multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic and is also power efficient due to in-place memory computation.

[0034] The output of the VMM array 33 is fed to a differential summer (such as a summing operational amplifier or summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform summation of both positive and negative weight inputs to output a single value.

[0035] The summed output values ​​of the differential summer 38 are then provided to an activation function circuit 39, which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other nonlinear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in FIG. 8 ) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the VMM array 33 comprises multiple synapses (which receive input from a previous layer of neurons or from an input layer such as an image database), and the summers 38 and activation function circuit 39 comprise multiple neurons.

[0036] The inputs to the VMM system 32 of FIG. 10 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels), or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels (e.g., current, voltage, or charge), binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0037] FIG. 11 is a block diagram illustrating the use of multiple layers of VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 11, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to input VMM system 32a. The converted analog input can be a voltage or a current. The first layer of input D / A conversion can be performed by using a function or LUT (look-up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM system 32a. The input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to input VMM system 32a. The input conversion can also be performed by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse(s) to input VMM system 32a.

[0038] The output generated by input VMM system 32a is then provided as input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as input to the next input VMM system (hidden level 2) 32c, and so on. The various layers of VMM system 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each of VMM systems 32a, 32b, 32c, 32d, and 32e can be a standalone physical system with a corresponding non-volatile memory array, or multiple VMM systems can utilize different portions of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d, and 32e can also be time-multiplexed to various portions of its array or neurons. The example shown in Figure 11 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may alternatively include more than two hidden layers and more than two fully connected layers. <<VMMアレイ> >

[0039] 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1200 comprises a memory array 1201 of non-volatile memory cells and a reference array 1202 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0040] In VMM array 1200, control gate lines, such as control gate line 1203, run vertically (thus row-oriented reference array 1202 is orthogonal to control gate line 1203), and erase gate lines, such as erase gate line 1204, run horizontally. Here, inputs to VMM array 1200 are provided to control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 1200 appear on source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0, SL1, respectively) performs a summation function of all currents from memory cells connected to that particular source line.

[0041] As described herein for neural networks, the non-volatile memory cells of VMM array 1200 are preferably configured to operate in the sub-threshold region.

[0042] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in the sub-threshold region: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and

[0043] where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage = k * where T / q, k is Boltzmann's constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), where Cdep = capacitance of the depletion layer and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0044] When using an IV log converter that converts the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io]

[0045] where wp is the w of the reference or peripheral memory cell.

[0046] When using an IV log converter that converts the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io]

[0047] where wp is the w of the reference or peripheral memory cell.

[0048] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout=(wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt where wa=w for each memory cell in the memory array and wp is the w of the reference or peripheral memory cell.

[0049] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0050] Alternatively, the non-volatile memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=Beta * (Vgs-Vth) * Vds; beta=u * Cox * Wt / L W α (Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0051] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0052] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region, or resistors can be used to linearly convert input and output currents to input and output voltages.

[0053] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * beta * (Vgs-Vth) 2 ; beta=u * Cox * Wt / L W α (Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to

[0054] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0055] Alternatively, the memory cells of the VMM arrays described herein can be used in all regions or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0056] FIG. 13 shows a neuron VMM array 1300 particularly suited for the memory cells 210 shown in FIG. 2 and used as synapses between the input layer and the next layer. The VMM array 1300 comprises a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. The reference arrays 1301 and 1302, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1314 (only a portion of which is shown) with the current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level, which is provided by a reference mini-array matrix (not shown).

[0057] Memory array 1303 serves two purposes. First, it stores the weights used by VMM array 1300 in each memory cell. Second, memory array 1303 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1301 and 1302 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1303, then adds all the results (memory cell currents) to generate outputs on the respective bit lines (BL0-BLN), which serve as inputs to the next layer or the last layer. Having memory array 1303 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on the respective bit lines BL0-BLN during read (inference) operations. The current applied to each bit line BL0-BLN performs a summation function of the currents from all the non-volatile memory cells connected to that particular bit line.

[0058] Table 6 shows the operating voltages for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells, and FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations. Table 6: Operation of VMM Array 1300 in Figure 13 [Table 6]

[0059] FIG. 14 shows a neuron VMM array 1400 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1400 comprises a memory array 1403 of nonvolatile memory cells, a reference array 1401 of first nonvolatile reference memory cells, and a reference array 1402 of second nonvolatile reference memory cells. The reference arrays 1401 and 1402 extend in the row direction of the VMM array 1400. The VMM array is similar to the VMM 1300, except that the word lines extend vertically in the VMM array 1400. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during a read operation. The current applied to each source line performs a summation function of all the currents from the memory cells connected to that particular source line.

[0060] Table 7 shows the operating voltages for VMM array 1400. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 7: Operation of the VMM Array 1400 in Figure 14 [Table 7]

[0061] 15 shows a neuron VMM array 1500 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1500 comprises a memory array 1503 of nonvolatile memory cells, a reference array 1501 of first nonvolatile reference memory cells, and a reference array 1502 of second nonvolatile reference memory cells. The reference arrays 1501 and 1502 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1512 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Multiplexer 1512 each includes a respective multiplexer 1505 and cascoding transistor 1504 to ensure a constant voltage on each bit line (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation, where the reference cells are tuned to a target reference level.

[0062] Memory array 1503 serves two purposes. First, it stores the weights used by VMM array 1500. Second, memory array 1503 multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1501 and 1502 convert these current inputs to input voltages and provide them to control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory cell array, and then adds all the results (cell currents) to generate an output that appears on BL0 through BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic and is also power efficient. Here, inputs are provided to control gate lines (CG0, CG1, CG2, and CG3), and outputs appear on bit lines (BL0 through BLN) during read operations. The current applied to each bit line performs a summation function of all the currents from the memory cells connected to that particular bit line.

[0063] VMM array 1500 implements one-way tuning of the non-volatile memory cells in memory array 1503. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (in which case an incorrect value is stored in the cell), the cell is erased and the series of partial programming operations is restarted. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0064] Table 8 shows the operating voltages for VMM array 1500. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1500 in Figure 15 [Table 8]

[0065] 16 shows a neuron VMM array 1600 that is particularly suited for memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1600 includes a memory array 1603 of non-volatile memory cells; of the first non-volatile reference memory cell Reference Array 160 1 and, and a reference array 1602 of second non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1600 is similar to VMM array 1600 except that VMM array 1600 implements bidirectional tuning, whereby each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on its floating gate through the use of separate EG lines. As shown, reference arrays 1601 and 1602 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1614), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0066] Table 9 shows the operating voltages for VMM array 1600. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 9: Operation of the VMM Array 1600 in Figure 16 [Table 9]

[0067] The input to the VMM array can be analog levels, binary levels, timing pulses, or digital bits, and the output can be analog levels, binary levels, timing pulses, or digital bits (in this case, an output ADC is required to convert the output analog level current or voltage to digital bits).

[0068] For each memory cell in the VMM array, each weight W can be implemented by a single memory cell, by a differential cell, or by two blended memory cells (an average of two or more cells). In the case of differential cells, two memory cells are required to implement weight W as a differential weight (W=W+ - W-). In the case of two blended memory cells, two memory cells are required to implement weight W as an average of two cells.

[0069] One drawback of prior art arrays of non-volatile memory cells is that there is a large variation in the source impedance of the array and along the output lines (such as bit lines) of the array, with resulting variations in accuracy and power consumption depending on which cells and their states are selected for read, program, or erase operations. Another drawback is that they can be susceptible to noise.

[0070] What is needed is an improved VMM system that has low susceptibility to noise.

[0071] What is further needed is an improved VMM system that has a substantially constant source impedance of the array during operation (read, program, or erase) regardless of which cell or cells are selected.

[0072] What is further needed is an improved VMM system that has substantially constant power consumption during an operation (read, program, or erase) regardless of which cell or cells are selected. Summary of the Invention

[0073] Numerous embodiments of an analog neural memory array are disclosed. In particular embodiments, each memory cell in the array has a nearly constant source impedance when the cell is operating. In particular embodiments, power consumption is substantially constant from bit line to bit line within the array when the cell is read. In particular embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

[0074] In one embodiment, an analog neural memory system comprises an array of non-volatile memory cells, the cells arranged in rows and columns, the columns arranged in pairs of physically adjacent columns, and within each adjacent pair, one column of the adjacent pair comprises a cell that stores a W+ value, one column of the adjacent pair comprises a cell that stores a W− value, and adjacent cells of the adjacent pair store a differential weight W according to the formula W=(W+)−(W−).

[0075] In another embodiment, an analog neural memory system comprises a first array of non-volatile memory cells, the cells arranged in rows and columns, with the non-volatile memory cells in one or more of the columns storing a W+ value; and a second array of non-volatile memory cells, the cells arranged in rows and columns, with the non-volatile memory cells in one or more of the columns storing a W− value, wherein pairs of cells from the first and second arrays store differential weights W according to the formula W=(W+)−(W−).

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[0110] [Brief explanation of the drawings]

[0111] [Figure 1] 1 illustrates a prior art artificial neural network. [Figure 2] 1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] 1 illustrates another prior art split-gate flash memory cell. [Figure 7] 1 shows a prior art stacked gate flash memory cell. [Figure 8] 1 shows a twin split gate memory cell. [Figure 9] 1 illustrates different levels of an exemplary artificial neural network utilizing one or more VMM arrays. [Figure 10] 1 illustrates a VMM system comprising a VMM array and other circuits. [Figure 11] 1 illustrates an exemplary artificial neural network utilizing one or more VMM systems. [Figure 12] 1 illustrates an embodiment of a VMM array. [Figure 13] 1 illustrates another embodiment of a VMM array. [Figure 14] 1 illustrates another embodiment of a VMM array. [Figure 15] 1 illustrates another embodiment of a VMM array. [Figure 16] 1 illustrates another embodiment of a VMM array. [Figure 17] 1 shows a VMM system. [Figure 18A]1 shows a prior art VMM array. [Figure 18B] 1 shows a prior art VMM array. [Figure 18C] 1 shows a prior art VMM array. [Figure 19A] 1 illustrates an improved VMM array. [Figure 19B] 1 illustrates an improved VMM array. [Figure 19C] 1 illustrates an improved VMM array. [Figure 20] 1 illustrates another improved VMM array. [Figure 21A] 1 illustrates another improved VMM array. [Figure 21B] 1 illustrates another improved VMM array. [Figure 22] 1 illustrates another improved VMM array with redundant arrays. [Figure 23] 1 illustrates another improved VMM system with two VMM arrays and a shared dummy bit line switching circuit. [Figure 24] 1 illustrates another improved VMM system. [Figure 25] 1 illustrates an embodiment of a summer circuit. [Figure 26] 10 illustrates another embodiment of a summer circuit. [Figure 27A] 10 illustrates another embodiment of a summer circuit. [Figure 27B] 10 illustrates another embodiment of a summer circuit. [Figure 28A] 1 illustrates an embodiment of an output circuit. [Figure 28B] 10 illustrates another embodiment of an output circuit. [Figure 28C] 10 illustrates another embodiment of an output circuit. [Figure 29] The neuron output circuit is shown. [Figure 30] 1 illustrates an embodiment of an analog-to-digital converter. [Figure 31] 1 illustrates another embodiment of an analog-to-digital converter. [Figure 32] 1 illustrates another embodiment of an analog-to-digital converter. [Figure 33] 1 illustrates another embodiment of an analog-to-digital converter. DETAILED DESCRIPTION OF THE INVENTION

[0112] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. <<Embodiments of an Improved VMM System>>

[0113] 17 shows a block diagram of a VMM system 1700. The VMM system 1700 includes a VMM array 1701, a row decoder 1702, a high-voltage decoder 1703, a column decoder 1704, a bit line driver 1705, input circuits 1706, output circuits 1707, control logic 1708, and a bias generator 1709. The VMM system 1700 further includes a high-voltage generation block 1710 including a charge pump 1711, a charge pump regulator 1712, and a high-voltage level generator 1713. The VMM system 1700 further includes an algorithm controller 1714, analog circuits 1715, control logic 1716, and test control logic 1717. The systems and methods described below can be implemented in the VMM system 1700.

[0114] The input circuit 1706 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), a DTC (digital-to-time converter), an AAC (analog-to-analog converter such as a current-to-voltage converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 1706 may implement a normalization function, a scaling function, or an arithmetic function. The input circuit 1706 may implement a temperature compensation function on the input, such as modulating the output voltage / current / time / pulse as a function of temperature. The input circuit 1706 may implement an activation function such as a ReLU or a sigmoid.

[0115] The output circuit 1707 may include circuits such as an ADC (an analog-to-digital converter for converting neuron analog outputs to digital bits), an AAC (an analog-to-analog converter such as a current-to-voltage converter), an ATC (an analog-to-time converter), an APC (an analog-to-pulse converter), or any other type of converter. The output circuit 1707 may implement activation functions such as ReLU or sigmoid. The output circuit 1707 may implement statistical normalization, regularization, up / downscaling functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) on the neuron outputs that are the output of the VMM array 1701. The output circuit 1707 may implement temperature compensation functions on the neuron outputs (voltage / current / time / pulse, etc.) or array outputs (bit line outputs, etc.), such as to keep the power consumption of the VMM array 1701 approximately constant or to improve the accuracy of the VMM array 1701 (neuron) outputs, such as by keeping the IV slope approximately the same.

[0116] 18A illustrates a prior art VMM system 1800. The VMM system 1800 includes exemplary cells 1801 and 1802, exemplary bit line switches 1803a, 1803b, 1803c, and 1803d (which connect the bit lines to sensing circuits), exemplary dummy bit line switches 1804a, 1804b, 1804c, and 1804d (which couple to a low bias level, such as ground (or near ground) during read), and exemplary dummy cells 1805 and 1806 (source line pull-down cells). Bit line switch 1803a is coupled to a column of cells, including cells 1801 and 1802, which are used to store data in the VMM system 1800. Dummy bit line switches 1804a, 1804b, 1804c, and 1804d are each coupled to a column (bit line) of cells that are dummy cells and are not used to store data in the VMM system 1800. This dummy bit line, which may also be referred to as a source line pull-down bit line, is used as a source line pull-down during a read operation, meaning that it is used to pull the source line to a low bias level, such as ground (or near ground), through the dummy cells of the dummy bit line. Note that dummy bit line switches 1804a, 1804b, 1804c, 1804 and bit line switches 1803a, 1803b, 1803c, 1803d both appear at the same end of the array, i.e., they all appear at a common end of the columns of cells that they are coupled to, and thus are arranged in a single row.

[0117] One drawback of VMM system 1800 is that the input impedance of each cell varies significantly due to the length of the electrical path through the associated bit line switch, the cell itself, and the associated dummy bit line switch. For example, FIG. 18B shows an electrical path through bit line switch 1803, cell 1801, dummy cell 1805, and dummy bit line switch 1804. Similarly, FIG. 18C shows an electrical path through bit line switch 1803, vertical metal bit line 1807, cell 1802, dummy cell 1806, vertical metal bit line 1808, and dummy bit line switch 1804. As can be seen, the path through cell 1802 traverses a significantly greater length of bit line and dummy bit line, which is associated with higher capacitance and higher resistance. This results in cell 1802 having a larger parasitic impedance at the bit line or source line than cell 1801 of FIG. 18B. This variability is disadvantageous because it results in variations in the accuracy of the cell output applied to, for example, reading or verifying (for program / erase tuning cycles) the cell depending on the cell's location within the array.

[0118] 19A illustrates a VMM system 1900 that improves upon prior art VMM system 1800. VMM system 1900 includes exemplary cells 1901 and 1902, exemplary bit line switches 1903a, 1903b, 1903c, and 1903d that connect bit lines to sensing circuits, exemplary dummy cells 1905 and 1906 that can function as source line pull-down cells, and exemplary dummy bit line switches 1904a, 1904b, 1904c, and 1904d. By way of example, during a read operation, one end of dummy bit line switch 1904a connects to a low voltage level, such as ground, and the other end connects to dummy cells 1905 and 1906, which are used as source line pull-downs. As can be seen, exemplary dummy bit line switch 1904a and the other dummy bit line switches are located at the opposite end of the array from bit line switch 1903a and the other bit line switches.

[0119] The benefit of this design can be seen in Figures 19B and 19C, where cell 1901 is selected for reading and cell 1902 is selected for reading in Figure 19B.

[0120] 19B shows an electrical path through bit line switch 1903, cell 1901, dummy cell 1905 (a source line pull-down cell), vertical metal bit line 1908, and dummy bit line switch 1904 (which couples to a low level, such as ground, during a read operation). FIG. 19C shows an electrical path through bit line switch 1903, vertical metal line 1907, cell 1902, dummy cell 1906 (a source line pull-down cell), and dummy bit line switch 1904. The paths are substantially identical in terms of interconnect length, and this is true for all cells in VMM system 1900. As a result, the impedance of the bit line impedance plus the source line impedance for each cell is substantially the same, which means that the variation in the amount of parasitic voltage drop drawn during a read or verify operation for each cell in the array is substantially the same.

[0121] 20 shows a VMM system 2000 with global source line pull-down bit lines. VMM system 2000 is similar to VMM system 1900, except that dummy bit lines 2005a-2005n or 2007a-2007n are connected together (to act as global source line pull-down lines for pulling the memory cell source lines to ground during read or verify), dummy bit line switches such as dummy bit line switches 2001 and 2002 are connected or coupled to a common ground labeled ARYGND (array ground), and the source lines are coupled together to source line switch 2004, which selectively pulls the source lines to ground. These changes further reduce variations in parasitic impedance of each cell in the array during read or verify operations.

[0122] In an alternative embodiment, one or more dummy bit lines and one or more dummy bit line switches can be used in place of the source line switch 2004 to pull the source line to ground.

[0123] In another embodiment, to avoid FG-FG coupling (of two adjacent cells) between rows, a dummy row can be utilized between the rows as a physical barrier.

[0124] FIG. 21A illustrates a VMM system 2100. In some embodiments, the weights W stored in the VMM are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 2100, half of the bit lines are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines are designated as W− lines, i.e., bit lines connecting to memory cells that implement a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by summing circuits, such as summing circuits 2101 and 2102, that receive current from the W+ and W− lines. The outputs of the W+ and W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells on every pair of (W+, W−) lines. Optionally, dummy bit lines and source line pull-down bit lines such as those shown in Figures 19 and 20 can be used in VMM system 2100 to avoid FG-FG coupling (between two adjacent cells) and / or reduce IR voltage drop on the source line during read or verify operations.

[0125] 21B shows another embodiment, in which positive weights W+ are implemented in a first array 2111 and negative weights W− are implemented in a second array 2112 separate from the first array, with the resulting weights being appropriately combined together by summing circuit 2113. Optionally, dummy bit lines and source line pull-down bit lines, such as those shown in FIGS. 19 and 20, can be used in VMM system 2110 to avoid FG-FG coupling and / or reduce IR voltage drop on the source lines during read or verify operations.

[0126] The VMM system can be designed such that W+ and W− pairs are arranged within the array in a manner that reduces FG to FG coupling or spreads power consumption in a more uniform manner across the array and output circuitry. This is described below with reference to Tables 10 and 11. Additional details regarding the FG to FG coupling phenomenon can be found in U.S. Provisional Patent Application No. 62 / 981,757, filed February 26, 2020 by the same assignee, and entitled “Ultra-Precise Tuning of Analog Neural Memory Cells in a Deep Learning Artificial Neural Network,” which is incorporated herein by reference.

[0127] Table 10A shows an example physical layout of two pairs of (W+, W-) bit lines. One pair is BL0 and BL1, and the second pair is BL2 and BL3. In this example, four rows are coupled to a source line pull-down bit line BLPWDN. BLPWDN is placed between each pair of (W+, W-) bit lines to prevent coupling (e.g., FG to FG coupling) between one pair of (W+, W-) bit lines and another pair of (W+, W-) bit lines. Thus, BLPWDN acts as a physical barrier between pairs of (W+, W-) bit lines. Table 10A: Example layout of W, W-pairs [Table 10A]

[0128] Table 10B shows different example weight combinations, where "1" means the cell is used and has an actual output value, and "0" means the cell is not used and has no value or no significant output value. Table 10B: Exemplary weight combinations for W+, W- pairs [Table 10B]

[0129] Table 11A shows another array embodiment of the physical placement of (w+, w-) line pairs BL0 / 1 and BL2 / 3. The array includes redundant lines BL01 and BL23 and a source line pull-down bit line BLPWDN. Redundant bit line BL01 is used to remap values ​​from pair BL0 / 1, and redundant bit line BL23 is used to remap values ​​from pair BL2 / 3, as shown in the following table. Table 11A: Example layout of W+, W- pairs [Table 11A]

[0130] Table 11B shows an example where the distributed weight values ​​do not require remapping, essentially there are no adjacent "1's" between adjacent bit lines. Table 11B: Exemplary weight combinations for W+, W- pairs [Table 11B]

[0131] Table 11C shows an example where the distributed weights need to be remapped. Here, there are adjacent "1"s on BL1 and BL3, which cause adjacent bitline coupling. Therefore, the values ​​are remapped as shown in Table 11D, resulting in no adjacent "1" values ​​between adjacent bitlines. In addition, the remapping reduces the total current along the bitline, leading to more accurate values ​​on that bitline, which also leads to more distributed power consumption along the bitline. Optionally, additional bitlines (BL01, BL23) can be used to act as redundant columns. Table 11C: Exemplary weight combinations of w+, w- pairs [Table 11C] Table 11D: Remapped weight combinations of w+, w- pairs [Table 11D]

[0132] Tables 11E and 11F show another embodiment of remapping noisy cells (or defective cells) to redundant columns such as BL01, BL23 in Table 11E, or BL0B and BL1B in Table 11F. Table 11E: Remapped weight combinations of w+, w- pairs [Table 11E] Table 11F: Remapped weight combinations of w+, w- pairs [Table 11F]

[0133] Table 11G shows an embodiment of a physical layout for an array suitable for Figure 21B. Because each bit line has either a positive or negative weight, each bit line requires a dummy bit line to act as a source line pull-down, or an actual dummy bit line (unused, e.g., deeply or partially programmed, or partially erased), and a physical barrier to avoid FG-FG coupling. Table 11G: Example layout of w+, w- pairs [Table 11G] table In 10x-11x, the source line pull-down bit lines BLPWDN can be implemented as actual dummy bit lines BLDUM or as isolation bit lines BLISO, which means that these bit lines help isolate the data bit lines from each other, thereby avoiding FG-FG coupling of adjacent cells. These bit lines are unused, which leaves them susceptible to being tuned (programmed or erased) to a state that does not cause FG-FG coupling, or to being disturbed by other cells being tuned (programmed or erased) in the same row or sector, such as cells that are deeply or partially programmed or partially erased so that the FG voltage is in a low state.

[0134] In another embodiment, a tuning bitline coupled to a column of cells is adjacent to a target bitline coupled to the column of cells, and the tuning bitline cell is used to tune the target bitline cell to a desired target value during a programming operation using FG-FG coupling between adjacent cells. Optionally, a source line pull-down bitline may be used on the side of the target bitline opposite the side adjacent to the tuning bitline.

[0135] An alternative embodiment for mapping noisy or defective cells can be implemented where such cells are designated as unused cells, meaning they are (deeply) programmed not to contribute any value to the neuron output.

[0136] An alternative embodiment can be implemented to identify fast cells (which are cells that can be programmed to reach a particular value faster than typical cells), where the fast cells are identified and subjected to a more precise tuning algorithm to avoid overshooting the target during programming operations.

[0137] FIG. 22 illustrates a VMM system 2200. The VMM system 2200 includes a redundant array 2201, which may be included in any of the VMM arrays discussed above. The redundant array 2201 may be used as redundancy to replace defective columns if any of the columns attached to the bit line switches are deemed defective. The redundant array may have its own redundant array (neuron) outputs (e.g., bit lines), and / or redundant write and verify circuits, and / or ADC circuits for redundancy purposes. For example, when redundancy is required, the output of the redundant ADC replaces the output of the ADC of a bad bit line. The redundant array 2201 may also be used for weight mapping, such as that described in Tables 10A and 10B, to achieve relatively uniform power distribution among the bit lines.

[0138] 23 shows a VMM system 2300 including array 2301, array 2302, column multiplexer 2303, local bit lines LBL 2305a-2305d, global bit lines GBL 2308 and 2309, and dummy bit line switches 2305a-2305d. Column multiplexer 2303 is used to select a respective top local bit line 2305 of array 2301 or a bottom local bit line 2305 of array 2302 to global bit line 2308. In one embodiment, (metal) global bit lines 2308 have the same number of lines as the number of local bit lines, e.g., 8 or 16. In another embodiment, global bit lines 2308 have only one (metal) line per N local bit lines, e.g., one global bit line per 8 or 16 local bit lines. Column multiplexer 2303 can multiplex adjacent global bit lines (such as GBL2309) to a target global bit line (such as GBL2308), effectively increasing the width of the current global bit line, which reduces the voltage drop across the target global bit line (GBL2308).

[0139] We will now describe various output circuits that can be used with any of the VMM systems described herein.

[0140] 24 shows a VMM system 2400. The VMM system 2400 includes an array 2410, a shift register (SR) 2401, a digital-to-analog converter (DAC) 2402 that receives input from the SR 2401 and outputs an equivalent (analog or pseudo-analog) level or information (e.g., voltage / timing), a summer circuit 2403, an analog-to-digital converter (ADC) 2404, and a bit line switch (not shown). Dummy bit lines and dummy bit line switches are present but not shown. As shown, ADC circuits can be combined together to create a single ADC with higher precision (i.e., a greater number of bits).

[0141] The summer circuit 2403 may include the circuitry shown in Figures 25-27. It may include, without limitation, circuitry for normalization, scaling, arithmetic operations (e.g., addition, subtraction), activation, or statistical rounding.

[0142] 25 shows a variable resistor adjustable current-voltage summer circuit 2500, which includes current sources 2501-1, ..., 2501-n, which sink currents Ineu(1), ..., Ineu(n), respectively (which are the currents received from the bit lines of the VMM array), an operational amplifier 2502, a variable holding capacitor 2504, and a variable resistor 2503. The operational amplifier 2502 outputs a voltage Vneuout=R2503 * The output is (Ineu(1)+...+Ineu(n)), which is proportional to the sum of the currents Ineu(1),...,Ineu(n). A hold capacitor 2504 is used to hold the output voltage when switch 2506 is open. This held output voltage can be converted to digital bits, for example, by an ADC circuit.

[0143] 26 shows a current-voltage summer circuit 2600 adjustable by a variable capacitor (essentially an integrator) that includes current sources 2601-1, ..., 2601-n that sink currents Ineu(1), ..., Ineu(n), respectively (which are the currents received from the bit lines of the VMM array), an operational amplifier 2602, a variable capacitor 2603, and a switch 2604. The operational amplifier 2602 outputs a voltage Vneuout 2605=(Ineu(1)+, ..., +Ineu(n)). * It outputs the integration time / C2603, which is proportional to the sum of the currents Ineu(1), ..., Ineu(n).

[0144] 27A shows a voltage summer 2700 adjustable by a variable capacitor (i.e., a switch-cap SC circuit), which includes switches 2701 and 2702, variable capacitors 2703 and 2704, an operational amplifier 2705, a variable capacitor 2706, and a switch S1 2707. When switch 2701 is closed, an input Vin0 is provided to operational amplifier 2705. When switch 2702 is closed, an input Vin1 is provided to operational amplifier 2705. Optionally, switches 2701 and 2702 are not closed simultaneously. Operational amplifier 2705 generates an output Vout that is an amplified version of the input (either Vin0 and / or Vin1, depending on which of switches 2701 and 2702 is closed). That is, Vout=Cin / Cout * (Vin), Cin is C2703 or C2704, and Cout is C2706. For example, Vout = Cin / Cout * Σ(Vinx), Cin=C2703=C2704, where Vinx can be either Vin0 or Vin1. In one embodiment, Vin0 is the W+ voltage and Vin1 is the W- voltage, and voltage summer 2700 adds them together (W+ - W-, by enabling the appropriate polarity of the switches) to produce the output voltage Vout.

[0145] 27B shows voltage summer 2750, which includes switches 2751 (S1), 2752 (S3), 2753 (S2), and 2754 (S4), a variable input capacitor 2758, an operational amplifier 2755, a variable feedback capacitor 2756, and a switch 2757 (S5). In one embodiment, Vin0 is the W+ voltage, Vin1 is the W- voltage, and voltage summer 2750 adds them together to generate the output voltage Vout (W+ - W-, by enabling the appropriate polarities of the switches).

[0146] When input=Vin0: When switches 2754 and 2751 are closed and switches 2753, 2752, and 2757 are open, input Vin0 is provided to the top terminal of capacitor 2758, whose bottom terminal is connected to VREF. Switch 2751 is then opened and switch 2753 is closed, transferring charge from capacitor 2758 to feedback capacitor 2756. Essentially then, output VOUT=(C2758 / C2756) * Vin0 (for example, when VREF=0).

[0147] When input = Vin1: When switches 2753, 2754, and 2757 are closed and switches 2751, 2752, and 2757 are open, both terminals of capacitor 2758 are discharged to VREF. Then, switch 2754 is opened and switch 2752 is closed, charging the bottom terminal of capacitor 2758 to Vin1, and then connecting feedback capacitor 2756 to VOUT = -(C2758 / C2756). * Charge Vin1 (when VREF=0).

[0148] Therefore, if the above sequence is performed for Vin0 and then the above sequence is performed for Vin1 input, for example, when VREF=0, VOUT=(C2758 / C2756) * (Vin0-Vin1). This is used to realize, for example, W=W+-W-.

[0149] Each ADC shown in FIG. 27 can be configured to combine with the next ADC for higher bit implementations, with appropriate design of the ADC.

[0150] 17, the inputs to and outputs from the VMM array 1701 can be in digital or analog form. For example: Sequential input to DAC IN[0:q]: In one embodiment, input circuit 1706 receives digital inputs in the sequence IN0, then IN1, ..., then INq. All input bits have the same VCGin. The input bits are provided to a DAC, which then applies an analog signal as an input to VMM array 1701. All bit line (neuron) outputs are summed in a coordinated binary index multiplier, either before or after the ADC. In another embodiment, a tuning neuron (bit line) binary index multiplier method is used. As shown in FIG. 20, an exemplary summer has two bit lines BL0 and BLn. Weights are distributed across multiple bit lines BL0 to BLn. For example, there are four bit lines: BL0, BL1, BL2, and BL3. The output from bit line BL0 is multiplied by 2^0=1. The output from bit line BLn, representing the nth binary bit position, is multiplied by 2^n, e.g., 2^3=8 when n=3. The outputs from all bit lines, after being appropriately multiplied by the binary bit position 2^n, are then summed together. This is then digitized by an ADC. This method means that all cells have only a binary range; multilevel range (n bits) is achieved by peripheral circuitry (meaning "by the summer circuit"). Therefore, the voltage drop on all bit lines is approximately the same for the highest bias level of the memory cell. In another embodiment, the digital inputs IN0, IN1, ..., then INq are applied in a sequential manner. Each input bit has a corresponding analog value VCGin. All neuron outputs are summed for all input bit evaluations, either before the ADC or after the ADC. Parallel inputs to the DAC: In another embodiment, inputs IN0, ... INq are provided to the DAC in a parallel manner. Each input IN[0:q] has a corresponding analog value VCGin. All neuron outputs are summed in a coordinated binary index multiplier manner, either before or after the ADC.

[0151] In embodiments involving sequential operation of the array, power is distributed more evenly.

[0152] In embodiments utilizing neuron (bit line) binary indexing, power consumption is reduced within the array because each cell coupled to a bit line only contains a binary level, and the 2^n levels are achieved by a summer circuit.

[0153] 28A, 28B, and 28C show output circuits that can be used for summer circuit 2403 and analog-to-digital converter 2404 of FIG.

[0154] FIG. 28A shows an output circuit 2800 comprising an analog-to-digital converter 2802 that receives neuron outputs 2801 and outputs output digital bits 2803 .

[0155] FIG. 28B shows an output circuit 2810 comprising a neuron output circuit 2811 and an analog-to-digital converter 2812 that together receive the neuron output 2801 and produce an output 2813 .

[0156] FIG. 28C shows an output circuit 2820 comprising a neuron output circuit 2821 and a converter 2822 that together receive the neuron output 2801 and produce an output 2823 .

[0157] Neuron output circuit 2811 or 2821 may perform, for example, without limitation, summing, scaling, normalization, or arithmetic operations. Converter 2822 may perform, for example, without limitation, ADC, PDC, AAC, or APC operations.

[0158] FIG. 29 shows a neuron output, which includes an adjustable (scaling) current source 2901 and an adjustable (scaling) current source 2902, which together produce an output i OUT29 shows a neuron output circuit 2900 that generates a neuron current I. This circuit is capable of summing positive and negative weights W+ and W−, i.e., W=W+−W−, and simultaneously up- or down-scaling the output neuron current (through adjustment of adjustable current sources 2901 and 2902). W+ is a scaled version of W+, and I W- is a scaled version of W-.

[0159] Figure 30 shows a configurable serial analog-to-digital converter 3000. It includes an integrator 3070 that integrates the neuron output current onto an integrating capacitor 3002 (Cint).

[0160] In one embodiment, VRAMP 3050 is provided to the inverting input of comparator 3004. Digital output (count value) 3021 is generated by ramping VRAMP 3050 until comparator 3004 switches polarity, and counter 3020 counts clock pulses from the start of the ramp.

[0161] In another embodiment, VREF 3055 is provided to the inverting input of comparator 3004. VC 3010 is ramped down by ramp current 3051 (IREF) until VOUT 3003 reaches VREF 3055, at which point the EC 3005 signal disables counter 3020 from counting. The (n-bit) ADC 3000 is configurable to have lower precision (less than n bits) or higher precision (more than n bits) depending on the target application. Precision configurability is achieved by configuring, without limitation, the capacitance of capacitor 3002, current 3051 (IREF), the ramping rate of VRAMP 3050, or the clock frequency of clock 3041.

[0162] In another embodiment, the ADC circuitry of a VMM array is configured to have less than n-bit precision, and the ADC circuitry of another VMM array is configured to have more than n-bit precision.

[0163] In another embodiment, one instance of the serial ADC circuit 3000 of one neuron circuit is configured to generate an ADC circuit with an accuracy greater than n bits, such as by combining the integrating capacitors 3002 of the two instances of the serial ADC circuit 3000 with another instance of the serial ADC circuit 3000 of the next neuron circuit.

[0164] Figure 31 shows a configurable neuron SAR (successive approximation register) analog-to-digital converter 3100. This circuit is a successive approximation converter based on charge redistribution using binary capacitors. It includes a binary CDAC (capacitor-based DAC) 3101, an operational amplifier / comparator 3102, and a SAR logic and register 3103. As shown, GndV 3104 is a low voltage reference level, e.g., ground level. SAR logic and register 3103 provides a digital output 3106.

[0165] FIG. 32 shows a configurable neuron combo SAR analog-to-digital converter circuit 3200. This circuit combines two n-bit ADCs from two neuron circuits into one to achieve greater than n-bit accuracy. For example, in the case of a 4-bit ADC in one neuron circuit, this circuit can achieve greater than 4-bit accuracy, such as 8-bit ADC accuracy, by combining two 4-bit ADCs. The combo circuit topology is equivalent to a split-cap (bridge capacitor (cap) or attention cap) SAR ADC circuit. For example, an 8-bit 4C-4C SAR ADC is achieved by combining two adjacent 4-bit 4C SAR ADC circuits. To achieve this, a bridge circuit 3204 (C split) is used, where the capacitance of this circuit = (total number of CDAC cap units / total number of CDAC cap units - 1).

[0166] FIG. 33 shows a pipelined SAR ADC circuit 3300 that can be used in combination with a subsequent SAR ADC to increase the number of bits in a pipelined manner. The SAR ADC circuit 3300 includes a binary CDAC (capacitor-based DAC) 3301, an operational amplifier / comparator 3302, an operational amplifier / comparator 3303, and a SAR logic and register 3304. As shown, GndV 3104 is a low voltage reference level, e.g., ground. The SAR logic and register 3103 provides a digital output 3106. Vin is the input voltage, VREF is the reference voltage, and GndV is the ground voltage. Vresidual is generated by a capacitor 3305 and provided as an input to the next stage of the SAR ADC.

[0167] Additional implementation details regarding circuitry for configurable output neurons (such as configurable neuron ADCs) can be found in U.S. patent application Ser. No. 16 / 449,201, filed June 21, 2019 by the same assignee and entitled "Configurable Input Blocks and Output Blocks and Physical Layout for Analog Neural Memory in a Deep Learning Artificial Neural Network," which is incorporated herein by reference.

[0168] It should be noted that, as used herein, both the terms "over" and "on" inclusively include "directly on" (with no intermediate material, element, or gap disposed therebetween) and "indirectly on" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached to" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled to" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. An analog neural memory system, comprising: a first array of non-volatile memory cells, the cells arranged in rows and columns, the non-volatile memory cells in one or more of the columns storing a W+ value, the rows of non-volatile memory cells of the first array coupled to a first set of source lines, the first array including a first dummy column including dummy cells coupled to dummy bit lines and the first set of source lines; bit line switches on a first side of the first array coupled to columns of non-volatile memory cells of the first array for sensing circuitry; dummy bit line switches on a second side of the first array opposite the first side of the first array that couple the first dummy column and the first set of source lines to ground; a second array of non-volatile memory cells, the cells arranged in rows and columns, the non-volatile memory cells in one or more of the columns storing a W-value, the rows of non-volatile memory cells of the second array coupled to a second set of source lines, the second array including a second dummy column including dummy cells coupled to dummy bit lines and the second set of source lines; bit line switches on a first side of the second array coupled to columns of non-volatile memory cells of the second array for sensing circuitry; a dummy bit line switch on a second side of the second array opposite the first side of the second array coupling the second dummy column and the second set of source lines to ground; An analog neural memory system, wherein pairs of cells from the first array and the second array store differential weights W according to the formula W=(W+)-(W-).

2. The system of claim 1 further comprising a redundant column.

3. The system of claim 2 , wherein the redundant columns are used to remap weights from W+ or W− columns.

4. 4. The system of claim 3, wherein the redundant columns are used to remap weights to avoid floating gate to floating gate coupling.

5. The system of claim 3 , wherein the redundant columns are used to remap weights to distribute power more evenly among the columns.

6. The system of claim 3 , wherein the redundant columns are used to remap weights from noisy or defective cells.

7. 10. The system of claim 1, wherein the non-volatile memory cells in the first array and the second array are split-gate flash memory cells.

8. 10. The system of claim 1, wherein the non-volatile memory cells in the first array and the second array are stacked gate flash memory cells.

9. 10. The system of claim 1, further comprising a summer for summing outputs from one or more bit lines.

10. The system of claim 9 , wherein the summer is adjustable based on a variable resistor.

11. The system of claim 9 , wherein the summer is adjustable based on a variable capacitor.

12. The system of claim 9 , wherein the summer comprises a switched capacitor circuit and an operational amplifier.

13. 10. The system of claim 9, further comprising an analog-to-digital converter for converting the output of the summer to a digital signal.

14. 14. The system of claim 13, wherein the analog-to-digital converter comprises a successive approximation register.

15. The system of claim 13 , wherein the analog-to-digital converter is a pipelined analog-to-digital converter.

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