Closed-loop DAC glitch mitigation

Abstract

To provide an amplifier system that uses digital-analog converters to provide a regulated output over a large dynamic range.SOLUTION: A method of feedback control of an amplifier system includes: driving multiple amplifier circuits using at least one digital-analog converter (DAC) circuit to set a system output of the amplifier system; operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady state target output; detecting a high glitch transition of the first set of DAC codes that is greater than a specified threshold transition; and changing to operating the at least one DAC circuit using a second set of DAC codes to set the system output to substantially the same steady state target output. Operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the at least one DAC circuit.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] Priority Claim This application claims priority to U.S. Provisional Application No. 63 / 376,467, filed on 21 September 2022, which is incorporated herein by reference in its entirety.

[0002] The present invention relates, but is not limited to, to a circuit supply system that provides a controlled output, and more specifically to an amplifier system that uses a digital-to-analog converter to provide a controlled output over a large dynamic range. [Background technology]

[0003] Amplifier systems can be used as circuit supplies to provide a direct current (DC) output. These systems can be useful, for example, in automated test equipment (ATEs). In a test environment, a large dynamic range may be desirable for the circuit supply. One approach to increasing the dynamic range of an ATE is to use a digital-to-analog converter (DAC) to transition the ATE between multiple operating modes. However, using a DAC in a closed-loop controlled supply can introduce glitches, which is undesirable. [Overview of the project] [Means for solving the problem]

[0004] The present invention provides a method for feedback control of an amplifier system, the method comprising: driving a plurality of amplifier circuits using at least one digital-to-analog converter (DAC) circuit to set the system output of the amplifier system; operating the at least one DAC circuit using a first set of DAC codes to set the system output to a steady-state target output; detecting a high glitch condition at the output of the at least one DAC circuit when using the first set of DAC codes; and modifying to operate the at least one DAC circuit using a second set of DAC codes to set the system output to substantially the same steady-state target output, wherein operating the at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of the at least one DAC circuit.

[0005] While the drawings are not always drawn to scale, similar numbers may describe similar components in different drawings. Similar numbers with different subscripts may represent different examples of similar components. The drawings generally illustrate the various embodiments described in this document as examples, not as limitations. [Brief explanation of the drawing]

[0006] [Figure 1] This is a diagram of an example of an electronic circuit including an amplifier system. [Figure 2] This figure shows an example of a transfer function for the circuit in Figure 1. [Figure 3] This figure shows another example of the transfer function for the circuit in Figure 1. [Figure 4] This is a diagram of another example of an electronic circuit including an amplifier system. [Figure 5] This figure shows an example of a transfer function for the circuit shown in Figure 4. [Figure 6] This is a diagram illustrating an example of an electronic circuit including an amplifier system with multiple digital-to-analog converters (DACs). [Figure 7] This is a diagram of another example of an electronic circuit including an amplifier system with multiple DACs. [Figure 8] A graph showing an example of DAC code transitions is shown. [Figure 9] Figure 8 shows a graph of the output ripple that can arise from the DAC code transitions. [Figure 10] This is an example of a glitch waveform with a peak amplitude of 10 millivolts. [Figure 11] This is an example graph showing the output voltage glitch amplitude versus DAC code change for a segmented DAC. [Figure 12] This is an enlarged version of the closed-loop amplifier system in Figure 10, which has multiple DACs. [Figure 13] This is a switchless version of the multi-DAC system shown in Figure 12. [Figure 14] This is a closed-loop circuit in which one or more auxiliary DACs are used to generate the reference level for the main DAC. [Figure 15] This is a circuit diagram of another example of an amplifier system. [Figure 16] Figure 15 shows the amplifier system operating in high-voltage, low-resolution mode. [Figure 17] Figure 15 shows the amplifier system operating in low-voltage, high-resolution mode. [Figure 18] This is a circuit diagram of another example of an amplifier system. [Figure 19] Figure 18 shows the amplifier system operating in high-voltage, low-resolution mode. [Figure 20] Figure 18 shows the amplifier system operating in low-voltage, high-resolution mode. [Figure 21] These are graphs of the transfer curves for the amplifier systems shown in Figures 16 and 19, operating in high-voltage mode. [Figure 22] These graphs show the circuits in Figures 15 and 16 operating in the DAC code region, which has relatively low glitching. [Figure 23] These graphs show the circuits in Figures 15 and 16 operating in the DAC code region, which has relatively low glitching. [Figure 24] This is a plot of an example of a peak code transition in the steady state against the glitch magnitude of the transition. [Figure 25] This is a diagram of another example of an electronic circuit including an amplifier system with multiple DACs. [Figure 26] These figures show examples of transfer functions for the circuits in Figures 17, 20, and 25 operating in low-voltage mode. [Figure 27A] A flowchart illustrating an example of how to operate an amplifier system with one or more DACs is shown. [Figure 27B] A flowchart illustrating an example of how to operate an amplifier system with one or more DACs is shown. [Figure 28A] A flowchart illustrating an example of a foreground calibration method for an amplifier system with one or more DACs is shown. [Figure 28B] A flowchart illustrating an example of a foreground calibration method for an amplifier system with one or more DACs is shown. [Figure 29] This is a flowchart illustrating an example of a feedback control method for an amplifier system. [Modes for carrying out the invention]

[0007] Figure 1 shows the input signal (V) to provide lower resolution but high voltage (HV) range and higher resolution but low voltage (LV) range. IN This is a diagram of an example of an electronic circuit with an amplifier system having a switchable transfer function gain to provide a high signal gain (G) to the input signal. HV A circuit path that provides ) and a lower signal gain (G) due to the input signal LV The circuit includes a circuit path that provides ). The HV range circuit path or the LV range circuit path is selected using a switch mechanism (SW) that enables the desired circuit path.

[0008] Input (V IN ) to output (V OUT The signal gain up to ) is, respectively, for the low-resolution HV range circuit path and the high-resolution LV range circuit path, GHV and G LV is specified as, where G HV >G LV is. The input to the output transfer function depends on the state of the gain selection switch and, assuming that the forward gain G F is substantially single, is determined by one of the following equations.

[0009] V OUT(HV Range) =V IN G HV

[0010] V OUT(LV Range) =V IN G LV

[0011] The input V IN can be normalized as follows. 0V ≤ V IN ≤ 1V

[0012] Figure 2 is a diagram of the output voltage V IN as a function of V OUT for the HV range and the LV range. The HV range graph has a slope G HV and the LV range graph has a slope G LV . When operating with an output voltage common to the spans of both the HV and LV ranges, it may be desirable to switch between the two range settings without inducing voltage disturbances (e.g., signal glitches) or deviations at the output. This glitch mitigation is only possible within the range of the operating voltage V OUT common to both the HV and LV ranges.

[0013] However, even for those output voltages common to both the HV and LV ranges, when the switch is changed between circuit paths, there will be a deviation in the output for a given input voltage (V A ). This applies to all operating points except the point where the two graphs intersect (V IN = 0V in the example of Figure 2). This is because for all points that are not the intersection point, the output takes on different voltages for the corresponding input V A according to the different transfer functions defined above.

[0014] Figure 3 shows the V range relative to the HV range and LV range. IN V as a function of OUT The graph shows the operating point V where the two output graphs do not intersect. IN =V A Deviation (V A This indicates >0V). As shown in the graph in Figure 3, the deviation is the input V when the switch position in Figure 1 is changed between the HV range circuit path and the LV range circuit path. A Difference V A [G HV -G LV ]

[0015] Figure 4 is a schematic circuit diagram of an example of an amplifier system for switching between the HV range and the LV range. HV The amplifier was removed, and the switch SW was G LV and G X It is located on the input side of the amplifier.

[0016] The transfer function for the entire LV range is as follows:

[0017] V OUT =V IN G LV +V X G X

[0018] In the formula, gain G X This can be selected at will.

[0019] A feedback amplifier (FA) outputs (V OUT ) is the desired target signal V TARGET The input voltage V transitions toward IN Automatically adjusts to the appropriate voltage. Output (V OUT ) is the desired target signal V TARGET The amplifier system is in a steady state when it is maintained at or near that point (e.g., within the error margin). Switching the amplifier system G HV Gain G without using an amplifier HVThis makes it possible to achieve this. With the switch in the above setting (as shown in Figure 4), V IN From V OUT The gain to is G LV +G X =G HV Therefore, by changing the switch to the setting below, the total gain becomes G LV However, V X and G X It has a static offset determined by V. X By changing the LV range transfer function shown in the LV range graph, even when the LV range transfer function is slowly converted from one common mode span to another, the feedback mechanism acts to maintain the output at this target. The logic circuit 402 is used in processors, state machines, writable gate arrays (FPGAs), application-specific integrated circuits (ASICs), or V IN and V X It may include one or more other logic circuits that modify the value of .

[0020] Figure 5 is a graph of the HV and LV ranges illustrating the operation of the circuit in Figure 4, where the LV range transitions from the cross condition back to the preferred common-mode span. In the example shown in Figure 5, V X Voltage is V A It is reduced from to 0V. The feedback mechanism uses (for example, a digital-to-analog converter (DAC) or other logic circuit) V X Even while it is being adjusted, the output is V TARGET Maintain (V A From V B (to)V IN It automatically and dynamically adjusts the LV graph without interfering with the output. Before changing the switch setting, V X ga V IN By ensuring consistency, deviations in the output can be eliminated.

[0021] Figure 6 shows the input voltage V IN , V X Digital-to-analog converter (DAC) IN and DACX ) is a circuit schematic diagram of another example of an amplifier system created thereby. Further, a feedback amplifier (FA) is replaced with an analog-to-digital converter (ADC) 606 combined with a control circuit 602 that provides appropriate control of the DAC and ADC 606. The control circuit 602 may be implemented using a processor (e.g., a microprocessor), a state machine, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or other logic circuits. The amplifier system may be included in a system-on-chip (SoC) IC, a system-in-package (SiP), or may be made from a plurality of components.

[0022] G X and G LV The auxiliary signal gain G X and the LV signal gain G LV may be adjustable. When the switch SW is in the HV low resolution mode (as shown in FIG. 6), the gain from V IN to V OUT is G LV +G X =G HV and by changing the switch to the LV high resolution mode, the total gain is G LV but has a static offset determined by V X and G X as in the example of FIG. 4. The forward gain G F can be added to the reverse gain G R in the forward path to the output or in the feedback path. A second ADC 608 may optionally be used to monitor the output current using a sense impedance R S . The sense impedance R S can include impedance circuit elements such as a resistor or an active device impedance. The sense impedance can include unit resistors or unit impedances that can be configured in combinations of different types and sizes of impedances to achieve certain characteristics (e.g., a balanced temperature coefficient). Such an impedance may be calibrated, trimmed, or tuned. The gain G for monitoring the output currentM may also be adjustable.

[0023] FIG. 7 is a schematic circuit diagram of another example of an amplifier system in which the range control switch (SW) is removed. The operation of the switch SW is replaced by appropriate control of the DAC by the control circuit 702. For example, if operation in the HV low resolution mode is required, the control circuit 702 drives the DACs simultaneously so that they present a voltage equal to the input of the G IN amplifier and the G X amplifier. Thus, the composite gain is G LV +G X =G HV . If operation in the LV high resolution mode is required, the control circuit 702 freezes the DAC X path for the current operating condition of V X and proceeds to perform any subsequent control exclusively via the DAC IN path, thereby resulting in a gain of G LV . Since the inputs to the G LV and G X amplifiers are equal when exclusive control through the DAC IN path is initiated, any discontinuities or glitches are alleviated during the range switching operation. Reverse range switching (returning from the LV mode to the HV mode) is achieved by ramping the DAC TARGET towards the DAC IN while continuing digital feedback to the servo DAC X so that V IN is maintained at the output. When the contents of the DAC IN and the DAC X match again, any subsequent feedback control from that point on is achieved by driving the DACs simultaneously again so that the condition of V X =V IN is maintained. This effectively returns the system to the HV range while reducing output discontinuities, glitches, or deviations.

[0024] In the examples of FIGS. 6 and 7, in the feedback path (G RThe gain of ) can be set to scale the output voltage so that the voltage at the input of ADC1006 fluctuates within the limits of the full-scale range of a given ADC. Furthermore, the gain (or attenuation) G R The ADC input range may be switched between two or more levels, and the ADC input range may be optimized separately for each of the HV and LV modes. In practice, in LV mode, the DAC X The offset introduced by may be removed in the return path to further optimize the input range of the ADC1006. Also, the gain G R The input to the amplifier having gain G F It may be connected to the input of an amplifier having, or combined with, such an amplifier.

[0025] Using a DAC, input voltage (e.g., V IN , V X The closed-loop architectures in Figures 6 and 7, which generate (etc.), mitigate output glitches caused by changes in the voltage range between HV mode and LV mode. However, if the loop is V OUT =V TARGET While operating to maintain a steady state near V, output glitches can originate from the DAC during DAC code transitions. For example, control circuit 702 may change only one or two LSBs of the DAC input code to adjust the DAC's analog output to maintain a steady state. Changing the digital input can cause glitches in the analog output. If the amplitude of the glitch is sufficiently high, the control circuit loop compensation may become cyclic, and the compensation for the glitch will regenerate the glitch, returning the DAC code to a state where compensation is repeated. This results in V OUT Undesirable ripple may be introduced in this context. In power supply applications, output ripple or persistent oscillation in the steady state is of particular concern.

[0026] Figure 8 shows a graph of an example of a DAC code transition in a control loop that functions to maintain a steady state near the DAC code region, which has a relatively large transition (+ / -10LSB in this example). Figure 9 shows a graph of the ripple that may occur at the output. The control loop functions to settle around 20.15V, and the DAC code transition causes a glitch at the output, resulting in a 50mV ripple at the output.

[0027] The glitch energy of a glitch generated by a DAC can be defined as the net integral area over time of the worst-case glitch voltage waveform minus the endpoint-tuned step transition of the DAC. Figure 10 shows an example of a glitch waveform with a peak amplitude of 10 millivolts (10 mV). The glitch energy of a DAC depends on the circuit architecture, microarchitecture, design, and implementation layout. A category of DACs known as Nyquist DACs (including single-weighted, binary-weighted, thermometer-coded, and segmented DACs) requires synchronous switching of multiple elements and therefore tends to generate undesirable glitches in the analog output. For example, a binary-weighted DAC utilizes an array of capacitors or resistors that are switched between two reference levels. Clock skew between the respective logic circuits of different array elements results in imperfect switching and causes glitches during transitions. Care must be taken in the circuit and layout design to mitigate such shortcomings. Binary-weighted DACs may exhibit higher glitch energy than other DAC architectures (e.g., single-scaled architectures). Glitches are generally more severe in most effective bit (MSB) transitions where all bits are switched. Glitches generated during major carry transitions can result in amplitudes exceeding several least effective bits (LSBs), even though glitches generated during other DAC code transitions are benign.

[0028] Segmented DACs are implemented as a combination of multiple DAC architectures to achieve better linearity characteristics. Segmented DACs typically include both binary weighted (LSB) and single weighted (MSB) segments and require synchronous switching of multiple branches, and therefore tend to produce glitches, especially during MSB segment transitions. In segmented DACs, high-energy glitches typically repeat periodically across the DAC code range, depending on the number of MSB segments present.

[0029] Figure 11 is a plot of an example of output voltage glitch amplitude versus DAC code change in an 18-bit segmented DAC. The plot shows 64 high-energy glitch spikes present across the DAC code space corresponding to MSB segment code transitions. Additionally, higher glitch spikes may be present during midscale code transitions in the LSB sub-DAC of a segmented DAC, similar to those observed in other DAC code transitions in other parts of the DAC code range. This glitching depends on the DAC circuit architecture and microarchitecture details.

[0030] Figure 12 is an enlarged version of the closed-loop amplifier system of Figure 6, having multiple DACs or multiple DAC channels. The system in Figure 12 shows one ADC 606 which can be optionally used to monitor the output voltage and output current using any of circuit paths A-D, depending on the state of the multiplexer (MUX) 1210. In some examples, the system includes multiple ADCs, with the MUX 1210 located at the outputs of the ADCs. The MUX 1210 selects the ADC outputs for feedback to the control circuit 1202. In certain examples, both current and voltage information can be processed simultaneously, or current and voltage from all four circuit paths A-D can be processed simultaneously. Some circuit paths may be included in the control circuit loop, and some circuit paths may be monitored for other purposes, such as fault detection. The DACs can be combined with switches to form a multi-DAC system in which the DACs are connected in parallel, series, or a hybrid of parallel and series connections.

[0031] Figure 13 is a switchless version of the multi-DAC system in Figure 12. In these multi-DAC multi-amplifier systems, the voltage (or current) range of each DAC channel path is based on the range of the DAC within each channel and the gain of the subsequent amplification stage. In Figures 12 and 13, each DAC (V REFPi , V REFNi Upper and lower reference levels relative to the DAC determine the DAC range. These reference levels are voltages that may be fixed or programmable (e.g., using an additional DAC or DAC). The reference voltages may be provided using a gain or attenuation network.

[0032] Figure 14 shows the closed-loop circuit of Figure 12, in which one or more auxiliary DACs are used to generate the reference level of the main DAC. In the case of a current-mode DAC, the feedback ADC has a sense impedance R S It may be a differential ADC608 that measures current by monitoring its terminals.

[0033] In the multi-DAC systems shown in Figures 12-14, different gains (G i) or reference level (V REFPi Different DAC channels having ) can have completely or partially overlapping transcription curves. As a result, the mapping from DAC code to output voltage (or output current) can be intentionally many-to-one. In other words, there can be multiple different combinations of DAC code that produce exactly the same output voltage (or current) in a steady state. Thus, for each target output level (voltage or current), the control circuit can determine a combination of DAC code that is sufficiently far from high-glitch code transitions. DAC code can be determined iteratively or algorithmically based on closed-form solutions. Depending on range and resolution requirements, the control circuit 1402 may continuously update one or more of the DACs (e.g., the main DAC) while other DAC code (e.g., auxiliary DACs) are fixed.

[0034] If the glitch energy characteristics of a DAC (e.g., the main DAC) for all different code transitions are known from previous measurements, those glitch characteristics of the DAC code can be stored in memory. Since the control circuit knows the current steady state of the amplifier system, it can avoid loading DAC code with high glitch code transitions close to the steady state. Some examples of this glitch characteristic data include glitch magnitude (e.g., peak-to-peak magnitude), positive glitch magnitude, negative glitch magnitude, total or net glitch energy, positive glitch energy, and negative glitch energy. The system response may be optimized using combinations of these metrics. This glitch characteristic data may be transformed or compressed to reduce memory requirements and data processing time or power consumption when loading appropriate DAC code.

[0035] This many-to-one DAC code approach can also be used to avoid glitches in "black box" DACs where high glitch code transitions are unknown or characteristic glitch data is unavailable. For example, the magnitude and sign of the DAC code correction provided by the control circuit may be monitored while the control loop of the amplifier system is trying to settle the output to a steady state target or nearby. OUT ~V TARGET When a steady state is reached in the vicinity of the DAC, under normal conditions, the control circuit compensates for gradual changes due to noise, drift, etc., by small incrementing or decrementing units (e.g., one or two LSBs) of the DAC. IN The code may be updated. If loading a new set of DAC code does not result in a reduction of glitch energy in the DAC analog output, another set of DAC code can be loaded (e.g., from memory) and the glitch energy in the DAC analog output can be rechecked.

[0036] This monitoring may be performed in the digital domain (or software domain), using a control circuit as part of a code tuning algorithm, or the monitoring may be performed using a separate monitoring circuit included in an ASIC, FPGA, microcontroller, or processor (e.g., a microprocessor). In a steady state, a predetermined threshold (e.g., number of LSB thresholds N) is set. THRESHOLD When a code update exceeding 10LSB(N) is detected, the high glitch flag signal can be raised in the digital domain. For example, in Figure 8, 10LSB(N) THRESHOLD A high glitch flag signal for updating the DAC code (=10LSB).

[0037] Other methods may be used to detect high glitch transition conditions. In some examples, the analog output of the DAC or system output may be monitored to detect glitches. A high glitch condition may be detected by a glitch exceeding a specified glitch peak threshold (in either volts or amperes). In other examples, a high glitch condition can be detected by a glitch exceeding a specified glitch energy (e.g., in volt-seconds or ampere-seconds). When a control circuit detects a high glitch transition exceeding a specified threshold transition, a high glitch flag signal may be raised. The high glitch threshold transition may be specified as the number of LSBs, or in volts or amperes. In some examples, population-based analysis may be used. Combinations of DAC codes and target values ​​may be tracked. Worst-case combinations can be tracked (e.g., via machine learning) to identify which DAC code versions are most likely to result in a high glitch transition condition for a given target value. High glitch threshold transitions may be adaptable based on the system design or the system's machine learning algorithm.

[0038] The size of the set of DAC codes that can be mitigated (the subgroup of codes to be mitigated) is limited by the redundancy or contingencies built into the design to allow for code avoidance. Therefore, while analysis can typically identify codes to be mitigated against worst-case codes, DAC designs must ensure there are sufficient contingencies to address anticipated worst-case needs. In some applications, there may be specific codes or code regions of the transfer function that are more important in the final use case. Thus, glitch mitigation may be prioritized over such regions as part of this aforementioned analysis.

[0039] When the high glitch flag rises, the DAC code may be changed to a different code where the steady-state DAC code is sufficiently far from the high glitch transition so that high glitches do not occur in the steady state. This triggers a predetermined threshold N for the code update. THRESHOLDThis can be modified. In some examples, when the high glitch flag rises, an offset voltage is introduced into the loop so that the control circuit can settle the main DAC or DAC in the loop into one or more DAC codes far enough away from the high glitch transition. The offset may be introduced at any point in the loop using analog means (e.g., an op-amp based adder circuit) or it may be introduced directly into the DAC code in the digital domain. Furthermore, the reference level of one or more main DACs may be adjusted to create an offset effect or to change the gain.

[0040] Glitch characteristic data may be stored in memory and used to calculate the amount of offset required for a given high-glitch DAC code transition according to a predetermined function, optimization, approximation, or machine learning algorithm. Glitch characterization techniques may be implemented as foreground calibration when the system is idle or as background calibration when the system is operating. Foreground calibration may be performed during system manufacturing. Foreground calibration may be performed by the user (e.g., as part of a system reset or calibration procedure). The amplifier system may adaptively adjust the offset amount when encountering a new high-glitch code transition during operation. Glitch characteristic evaluation techniques may be used to respond to changes in the load of the amplifier system that bring a new steady state near a high-glitch transition.

[0041] Figure 15 is a circuit diagram of another example of an amplifier system. For the sake of simplicity, the example uses one ADC606 and one main DAC (DAC606). IN ) and one auxiliary DAC (DAC X ) and, as shown in the example in Figure 15, a voltage offset V in the control loop of two DAC architectures having a range control switch SW of the amplifier system in Figure 6. OFFSET The ADC606 may monitor either the output voltage or the output current, or two ADCs may be included to monitor both the output voltage and the output current. In the example in Figure 15, the voltage offset is G LV and G XThe amplifier output is added to the total node, but a voltage offset may be introduced to any other circuit node in the amplifier system's control loop. A switch SW changes the system's operation between HV mode and LV mode.

[0042] Figure 16 shows the amplifier system from Figure 15 operating in HV low-resolution mode. In HV mode, the DAC X The redundancy is achieved, and the amplifier system effectively becomes a single DAC system as shown in Figure 16. The voltage offset can be introduced at any point in the loop or by the DAC control circuit 1502. IN It can be digitally introduced into the code. Figure 17 shows the amplifier system of Figure 15 operating in LV high resolution mode. In LV mode, the DAC X to G X Because the switch SW is in the LV mode position to connect to the amplifier input, the DAC X This can be used to set the minimum and maximum range of the LV range.

[0043] Figure 18 is a schematic circuit diagram of another example of an amplifier system. In the example in Figure 18, another switch SW A DAC X It is added to the output, G LV and G X Voltage offset V at the summing node in the amplifier output OFFSET This will be introduced. Optionally, DAC X The gain G provided by the amplifier depends on the magnitude of the offset that needs to be applied over the full-scale range. Y A gain stage having a switch SW A It may be included after this.

[0044] Figure 19 shows the amplifier system in HV mode as shown in Figure 18. In HV mode, switch SW is G LV and G X V to the amplifier IN When the voltage is applied, the control circuit 1802 switches SW A Close V X Or G Y V XThe output is applied to the summing node. The control circuit 1802 processes the DAC code in HV mode. X The values ​​may be loaded to generate the offset values ​​provided to the summing node. Figure 20 shows the amplifier system of Figure 18 in LV mode. In LV mode, switch SW is G X V to the amplifier X Apply the switch SW A It is open, DAC X This is used to set the minimum and maximum ranges of the LV range.

[0045] Figure 21 shows the V ratio for the amplifier system of Figure 15 operating in high-voltage, low-resolution (HV) mode. OUT V IN This is a graph of the transfer curve. The transfer curve shows that when the switch SW is in HV mode, the added offset (±ΔV) is V OUT V IN This shows that it has the effect of shifting the transfer curve up or down. The vertical dashed line is an exemplary DAC that produces high glitch at the DAC output. IN This corresponds to a code transition boundary. In the example in Figure 21, the control loop of the amplifier system in Figure 15 corresponds to the input V IN ≒V A V brings about high glitch code transition boundaries OUT ≒V TARGET It is converging to V. To avoid this high-glitch DAC code boundary, the system is V OUT ≒V TARGET It also covers V near the DAC high glitch boundary. IN I want it to operate within an offset (high or low) HV range, not a value.

[0046] For example, V OFFSET When =+ΔV is applied, the transfer function is upper V OFFSET = Shifts to the +ΔV line. The control loop is V IN The value

[0047]

number

[0048] Reduce to V OUT ≒V TARGET Maintain the following. As shown in Figure 21, the offset causes the control loop to V IN The loop shifts to a glitch-free DAC code region corresponding to a lower value, and the loop moves away from the high-glitch transitions in the code space to the main DAC (DAC IN ) converges with the code. Figures 22 and 23 show the results of the shift to the new DAC code region. Figure 22 shows the DAC code transition as N in Figure 8. THRESHOLD Figure 23 shows that the output ripple is less than the value shown in Figure 9. The steady-state output voltage with offset exhibits significantly less glitch and ripple than the steady-state output voltage without offset.

[0049] Figure 24 is a plot of an example of a peak code transition (at the LSB) in a steady state against the glitch magnitude of the code transition. The plot shows that the relationship between the magnitude of the signed glitch and the code transition is substantially linear. The plot also shows that the required DAC code update is inversely proportional to the magnitude of the signed glitch. At the system level, when the high glitch flag rises, this glitch energy characteristic information regarding the glitch sign and magnitude can be recorded in memory (e.g., using a control circuit or a separate monitoring circuit) and used to determine an appropriate amount of offset to achieve a given code transition.

[0050] The peak amplitude of the glitch is determined according to the frequency response of the control loop of the amplifier system, resulting in a glitch waveform or output (V OUT This is relevant to closed-loop applications because it can directly manifest as ripple in the output. Furthermore, if the output glitch waveform is sampled by the ADC, the control loop may become unstable, potentially causing undesirable ringing or oscillating responses at the output.

[0051] As previously stated herein, glitch energy can be defined as the net integrated area of ​​the glitch waveform. In some applications, depending on the aperture window of the feedback ADC, glitch energy may be more important in terms of the control circuit response than glitch peak size. In other words, due to the averaging effect, the control circuit may not respond significantly to glitch waveforms of high magnitude (e.g., narrow glitches) even if the ADC has a sufficiently wide aperture window. Therefore, depending on the system, it may be preferable to reduce the glitch size, glitch energy, or both for a given application. The advantage of the glitch self-characterization and calibration techniques described herein is that updating the DAC code used for characterization depends on the response of the ADC (e.g., ADC606 in Figure 15) to DAC glitches in closed-loop control, and thus eliminates the dependence on the exact shape of the glitch waveform.

[0052] Figure 24 shows that when the magnitude of the DAC glitch is further reduced (for example, to a peak of less than ±1mV within the vertical dashed line), V OUT ≒V TARGET The amount of code update required to maintain the code is less than 1 LSB, indicating that the control circuit keeps the code constant. Therefore, if the glitch energy in the transition is less than the threshold, even though the loop is trying to settle near the code transition with a given glitch energy, V OUT In this case, there is virtually no ripple caused by DAC code updates. The magnitude or glitch energy of the threshold glitch may depend on the shape of the glitch waveform, system parameters, and control loop dynamics.

[0053] Figure 25 is a schematic circuit diagram of another example of an amplifier system. In the example of Figure 25, a voltage offset V is introduced into the control loop of the two DAC architectures without using the range control switch SW of the amplifier system in Figure 15. OFFSET This has been introduced. In HV mode, the effective total gain is G LV +G X =G HVThe control circuit 2502 is configured to act as a DAC. IN and DAC X Both are driven simultaneously. In an exemplary embodiment, given V TARGET Regarding DAC IN and DAC X The control loop may settle near a code transition known to generate high-energy glitches in one or both of the following: Alternatively, if the glitch profile of the code transition is unknown, the glitch event can be detected at the system level, as in the blockbox example described earlier herein. In either scenario, V TARGET If the value corresponds to a high glitch code boundary, the control circuit 2502 will V OUT ≒V TARGET While maintaining this, an arbitrary offset can be introduced into the DAC code.

[0054] For example, DAC X Increment the code, V X offset ΔV X It can only be increased by DAC IN Decrement the code, V IN ΔV X *G X / G LV It can be reduced by only this much, and this will result in V OUT =G X *V X +G LV *V IN This is maintained. The amount of offset is adjustable (V) using another DAC. OFFSET) may be controlled by adding to the summation node. The offset value may also be increased gradually, or using continuous approximation or other more complex search algorithms, until both DACs are comfortable in a glitch-free code space. After the offset in the code space is introduced between the two DACs, the control circuit 2502 may enable the control loop to control both DACs while maintaining a fixed offset. In this way, both DACs settle in a code region far from the high-glitch boundary to minimize ripple in the output. TARGET Upon receiving an update to the new target V, the control circuit 2502 will check the loop. OUT Before settling on a value, you can initially use only one DAC code.

[0055] Regarding the LV high-resolution mode operation of the amplifier system shown in Figure 17 and Figure 15, the range switch SW controls the auxiliary DAC. X The output is G X Connect to the amplifier input, and the main DAC IN The output is G LV Connect to the amplifier. As a result, the amplifier systems in Figures 15 and 25 can be substantially identical in LV high-resolution mode.

[0056] As mentioned above, regarding the amplifier system in Figure 15, DAC X The input is frozen, and the control circuit 1502 is V OUT ≒V TARGET While trying to maintain the DAC in a steady state, IN Update the DAC code. IN If the steady-state input is near a DAC code where a high glitch boundary exists, the control circuit may perform the ring compensation described earlier herein, potentially causing undesirable ripple at the output. The same applies to the amplifier system in Figure 25.

[0057] For the system architectures in Figures 15, 18, and 25, which have multiple DACs, steady state V OUT ≒V TARGETThe condition is the auxiliary DAC (DAC in the example). X Assuming that the DAC code space has sufficient resolution, it can be filled at multiple points within the DAC code space. If a high-glitch steady-state condition is detected, one or more DAC codes can be moved to other DAC code values ​​far enough away from the high-glitch DAC code boundary to minimize output ripple due to DAC code transitions.

[0058] Figure 26 shows different V in low voltage high resolution (LV) mode. IN and V X V of the amplifier system in Figures 15 and 25 relative to the value OUT V IN This is a graph of the transfer curve. The vertical dashed line represents a DAC with high glitch. IN This shows the code transition point. There are no glitches in the region between the vertical dashed lines. Point V is near the high-glitch boundary of the loop. IN =V A Assume that it is converging near V. The amplifier system can infer that the convergence point is close to the high-glitch code boundary by observing the DAC code. To avoid this high-glitch condition, the amplifier system V OUT =V TARGET It also covers V, but is not in the vicinity of the high-glitch code boundary. IN The value needs to operate within the LV range.

[0059] The multiple DAC architectures in the examples in Figures 15 and 25 are DAC X By incrementing the code vertically or by adding an offset (±ΔV), it is possible to shift the LV range transmission curve vertically. Figure 26 shows the constant V. X This shows the transfer lines for different values. DAC X The LV transfer line can be obtained by adjusting the code by ±ΔX or by adding an offset (±ΔV). For example, if the voltage output is +ΔV (curve V) X =V A The DAC increases by +ΔV) XIf the code is incremented, the loop is V IN Reduce the value of to the following:

[0060]

number

[0061] Go, V OUT =V TARGET This can be maintained. Therefore, the control loop is far from the high glitch code boundary of the DAC. IN The code will converge.

[0062] Figures 27A and 27B show a flowchart of an example of method 2700 for closed-loop glitch mitigation in an amplifier system. Method 2700 uses an offset to move the DAC code away from a high-glitch DAC code condition. The control circuit can determine what to offset based on the glitch condition of the system.

[0063] Figure 27A shows the initialization phase. In block 2710, it is determined whether the offset list is stored in memory or, if not, whether it is available. If the offset list is available, the offset list and glitch code list are loaded from memory into the control circuit or dedicated monitoring circuit. In block 2720, the target (V TARGET ) and glitch threshold (N THRESHOLD The system waits until the value is set.

[0064] In block 2730 of Figure 27B, if the offset list is unavailable, the control circuit will target (e.g., V OUT =V TARGET ) in order to satisfy the main DAC (DAC IN ) and auxiliary DAC (DAC X Set the DAC code for ). No offset is given. Determine the range of the main DAC and auxiliary DAC by setting a reference level (e.g., V). REFS ) may be set.

[0065] In block 2740, if an offset list is available, the control circuit provides an offset to the control loop. The offset can be provided in different ways. For example, the system may include analog adder or subtractor circuits to provide an offset (voltage offset or current offset) to the system's adder node, as in the example in Figure 15. In certain examples, the offset is provided using one or more auxiliary DACs, as in the example in Figure 18. In certain examples, the offset is included in the DAC code, and the control circuit loads the DAC code that incorporates the offset. In other examples, the reference to the DAC may be adjusted (e.g., by analog means or using an auxiliary DAC) to include the offset.

[0066] Once the DAC code is set, the system's control loop directs the system's output to a steady-state output target (e.g., V). OUT ≒V TARGET The control circuit guides the DAC to accept small changes below a threshold (e.g., one or two LSBs) in order to compensate for small changes in the condition. IN You may proceed to the code. Code updates are monitored, and in block 2750, changes exceed the threshold (N THRESHOLD If it is smaller than the LSB, the control circuit will continue to monitor system stability, and the glitch flag will not be raised or activated.

[0067] N THRESHOLD If a main DAC code change greater than the LSB is required, a high glitch flag signal is asserted or activated. In the 2760, when a high glitch code transition is encountered, the DAC code can be recorded in memory. The control circuit (or dedicated monitoring circuit) may record the magnitude of the sign of the glitch in a given transition based on the peak or average code update observed in the steady state. Subsequently, when a previously recorded high glitch transition condition is expected, a predetermined offset value may be given by the control circuit. The predetermined offset value may be used as part of a starting approximation to find a new steady state of the system.

[0068] In block 2770, the amount of offset given to a given transition may be fixed based on an optimization algorithm or a machine learning (ML) algorithm, or it may be continuously updated. For example, the amplifier system can observe the DAC code and, from the DAC code and the detected glitching, the system can determine where the glitch is located in the DAC code and how much energy the glitch has. The system can estimate that the current DAC code space is in a high-glitch condition and can settle the main DAC or DAC away from instability by providing one or both of the DAC code changes and / or offsets. Thus, the amplifier system can self-characterize the current system conditions.

[0069] In block 2780, the system may calculate the size of the glitch, the glitch sign, and the amount of offset required as a function of the DAC code, and update the offset list. The process returns to block 2740, giving the calculated offsets, and returns to monitoring system stability.

[0070] Up to this point, the glitch mitigation methods described herein can operate in the background without interrupting the normal operation of the system for extended periods. The glitch mitigation method can detect when the control loop settles near a highly glitchy DAC code transition and can acquire information about the sign and relative magnitude of the glitch based on DAC code updates performed by the control circuit in the steady state. The control circuit may then provide a fixed-amplitude or variable-amplitude offset calculated by the amplifier system as a function of the characterized glitch parameters.

[0071] If writable memory is available in the amplifier system, a control circuit or dedicated monitoring circuit may record high-energy glitch codes with relative magnitude along with code information. Other major artifacts may be recorded to enable efficient glitch mitigation. The amount of offset given to a given code transition can be proportional or inversely proportional to the relative magnitude and the code of the glitch, and the offset may be continuously updated as the system encounters new code transitions with high glitches.

[0072] Alternatively, a system-level foreground calibration can be devised. This calibration may be performed at power-on, when the system is idle and not operating, or periodically during system operation (e.g., when operating conditions such as temperature, power loss, or load change significantly). The calibration results are stored in memory as an offset list that can be read when configuring the amplifier system.

[0073] Figures 28A and 28B show a flowchart of an example of foreground calibration method 2800 for glitch characteristic evaluation and offset calculation in a closed-loop amplifier system. The target voltage is V. MIN From V MAX Assuming the range is up to V, during calibration of a given DAC in a single DAC system or a multi-DAC system, TARGET The value of the value is V MIN From V MAX Next, V MAX From V MIN It is swept in (or vice versa).

[0074] In 2810, the corresponding target measurement ADC code is V TARGET (Set for the value). In the 2820, based on the magnitude and direction of the DAC code update required in the steady state, the system records the magnitude and code information of the DAC glitch in memory for each code transition. To save memory space, a set threshold (N THRESHOLD Only glitches with a magnitude (or energy) exceeding the specified value can be recorded.

[0075] When a high-energy DAC code containing sign and magnitude information transitions, in block 2830, the system may calculate the amount of offset that should be given to each case during normal operation. The amount of offset may be calculated as a function of the glitch code, the glitch magnitude, and the glitch symbol. In this way, all relevant glitch characteristics can be determined for a system with multiple DACs without using previously available glitch characterization data. The system may utilize previous characterization data to complete system characterization during normal operation and / or at a faster rate.

[0076] In block 2840, the calculated offset is stored in memory. This offset list can then be loaded into the system's control circuit or a separate monitoring circuit to shift the DAC code away from high-glitch transitions. The advantage of system foreground calibration is that the system can systematically avoid high-glitch code transitions during normal operation by providing predetermined offsets based on glitch information (e.g., glitch characteristic data) stored in memory.

[0077] The glitch mitigation process can include machine learning as part of the process of identifying changes in the DAC code when a high-glitch transition condition is detected. Glitches from DAC code transitions are a negative attribute of the system and minimization is desirable. Glitch optimization can be a minimization exercise. In machine learning, minimizing glitches can be determined by optimizing a loss function or cost function. The loss function can be a combination of glitch attributes, and the goal of machine learning is to minimize the attributes.

[0078] Population-based analysis may be used to determine which DAC code sets are desired and which should be avoided in DAC code changes. The glitch performance of an amplifier system can have a multimodal distribution with low-glitch codes grouped separately from high-glitch codes. The distribution may be DAC architecture-dependent or system design-dependent. For example, a multi-stage DAC may tend to have a multimodal pattern, while a ladder DAC does not tend to have separate substages and therefore may have a different code distribution and may not exhibit a clear multimodal distribution. An optimization algorithm can analyze glitch performance to determine glitch transitions to be avoided. The energy or magnitude of DAC glitches may be characterized or quantified. Code contingency may be performed for the worst glitches characterized by the system in order to maintain a stable output. Characterized glitch data may be stored. Accidental DAC code sets may be selected according to previously recorded DAC glitch data. Code transitions may be limited to codes available to the system. Glitch data analysis can be used to determine the DAC code sets where glitches are mitigated, thus avoiding potential mitigation for code changes with minimal impact.

[0079] Figure 29 is a flowchart of an example of a feedback control method 2900 for an amplifier system. The amplifier system may be any of the DAC-controlled amplifier systems described herein. In block 2905, the amplifier circuit of the amplifier system is driven by one or more DAC circuits to set the output of the amplifier system. In block 2910, the DAC circuit operates using a first set of DAC codes to set the system output to a steady-state target output.

[0080] In block 2915, the control circuit of the amplifier system identifies that a first set of DAC codes includes DAC code transitions (or multiple DAC code transitions) associated with high glitch conditions, and that high glitch DAC code transitions are used, or will be used, to set the system output to a target output. In block 2920, the control circuit changes to operate the DAC circuit using a second set of DAC codes. The second set of DAC codes sets the output to the same, or substantially the same, target output as the first set of DAC codes. However, the second set of DAC codes does not include DAC code transitions associated with high glitch conditions. Therefore, the glitch energy at the output is reduced.

[0081] The final code set selection may be hardware-constrained. Optimization algorithms may use knowledge of the DAC architecture in the analysis (e.g., certain codes or bit transitions have repeatable patterns across the entire code set). Accidental DAC code sets may be determined based on knowledge of the system design. Contingent code sets may be included to address unknown artifacts that may occur within the system (e.g., parasitic).

[0082] The glitch mitigation technique described herein utilizes a closed-loop configuration, thereby allowing the DAC to settle into different DAC codes while maintaining a target output voltage or current. This technique provides glitch self-characterization for closed-loop DAC glitch mitigation, as well as background and foreground calibration. Additional explanations and examples

[0083] Embodiment 1 includes the subject (such as a method for feedback control of an amplifier system) and includes driving multiple amplifier circuits using at least one digital-to-analog converter (DAC) circuit to set the system output of the amplifier system; operating at least one DAC circuit using a first set of DAC codes to set the system output to a steady-state target output; detecting a high glitch condition at the output of at least one DAC circuit when using the first set of DAC codes; and modifying to operate at least one DAC circuit using a second set of DAC codes to set the system output to substantially the same steady-state target output, wherein operating at least one DAC circuit using the second set of DAC codes reduces glitch energy at the output of at least one DAC circuit.

[0084] In Example 2, the subject of Example 1 optionally includes detecting high-energy glitch transitions greater than threshold glitch transitions when operating at least one DAC circuit using a first set of DAC codes.

[0085] In Example 3, the subject matter of one or both of Examples 1 and 2 optionally includes identifying that a first set of DAC codes includes DAC code transitions associated with high glitch conditions when setting the system output to a steady-state target output.

[0086] In Example 4, the subject of one or any combination of Examples 1 to 3 optionally includes setting the system output to a steady-state target output using a control loop that includes a feedback circuit path, and adding an offset to the control loop to operate at least one DAC circuit using a second set of DAC codes.

[0087] In Example 5, the subject matter of Example 4 optionally includes adding a programmable offset to the control loop using a different DAC circuit.

[0088] In Example 6, the subject of one or any combination of Examples 1 to 5 optionally includes, when operating as an amplifier system in the first mode, providing the output of at least one DAC circuit to the input of the first amplifier circuit and the input of the second amplifier circuit of multiple amplifier circuits, and in the second mode, providing the output of at least one DAC circuit to the input of the first amplifier circuit and the output of another DAC circuit to the input of the second amplifier circuit, wherein the second mode has a lower voltage output than the first mode.

[0089] In Example 7, the subject of one or the opposite combination of Examples 1 to 6 optionally includes driving multiple DAC channels, each DAC channel comprising a main DAC and an amplifier circuit, the amplifier circuits of the DAC channels having different signal gains; operating the main DAC circuits of the DAC channels using a first set of DAC codes to set the system output by summing the outputs of the DAC channels; and modifying the control loop to set the system output to a steady-state target output and to operate the main DAC circuits using a second set of DAC codes to reduce the ripple in the system output caused by the multiple DAC channels.

[0090] In Example 8, the subject of Example 7 optionally includes detecting a high-energy glitch transition greater than a threshold glitch transition when operating at least one DAC circuit using a first set of DAC codes, determining an offset using the magnitude of the high-energy glitch transition and the current DAC code, and selecting one set of DAC codes as a second set of DAC codes using the determined offset.

[0091] In Example 9, the subject of one or any combination of Examples 1 to 8 optionally includes updating the DAC code of at least one DAC circuit using a DAC code value selected from a first set of DAC codes to set the system output to a steady-state target output; detecting when the DAC code of at least one DAC circuit settles near a high-glitch DAC code transition when setting the system output to a steady-state target output; and, in response to the detection, updating the DAC code of at least one DAC circuit using a DAC code value selected from a second set of DAC codes.

[0092] Example 10 includes a subject (such as an amplifier system), or is optionally combined with one or any combination of Examples 1 to 9, and includes a subject comprising: a DAC circuit, wherein setting DAC codes in the at least one DAC circuit sets the output of the at least one DAC circuit; a plurality of amplifier circuits, each having an input connected to the output of the at least one DAC circuit; a feedback circuit path connected to the system output of the amplifier system; and a control circuit connected to the at least one DAC circuit and the feedback circuit path. The control circuit is configured to operate the at least one DAC circuit using a first set of DAC codes to set the system output to a steady-state output target, and is configured to operate the at least one DAC circuit using a second set of DAC codes to maintain the same steady-state output target and reduce ripple at the system output caused by the at least one DAC circuit.

[0093] In Example 11, the subject of Example 10 optionally includes a control loop comprising a feedback circuit and a control circuit, and a control circuit configured to detect high glitch transitions of a first set of DAC codes greater than a threshold glitch transition, and to modify the control loop by adding an offset to select a DAC code from a second set of DAC codes.

[0094] In Example 12, the subject of Example 11 optionally includes another DAC circuit for adding an offset to the control loop, and a control circuit configured to set the offset according to the magnitude of the high glitch transition and one or more DAC code values ​​corresponding to the high glitch transition.

[0095] In Example 13, the subject matter of one or both of Examples 11 and 12 optionally includes an adder node connected to the outputs of multiple amplifier circuits and multiple DAC circuits, wherein the inputs of the multiple amplifier circuits are connected to the outputs of the multiple DAC circuits to form multiple DAC channels, and the outputs of the multiple amplifier circuits are connected to the adder node. The control circuit is optionally configured to update the DAC codes of the multiple DAC circuits to maintain a steady-state output target and to modify the adder node to select a DAC code from a second set of DAC codes by adding an offset.

[0096] In Example 14, the subject of one or any combination of Examples 11 to 13 optionally includes a first amplifier circuit and a second amplifier circuit, and at least one DAC circuit includes a first DAC circuit connected to the input of the first amplifier circuit and a second DAC circuit connected to the input of the second amplifier circuit. The control circuit is optionally configured to, in a first mode, update the DAC codes of both the first and second DAC circuits to provide equal DAC outputs to the first and second amplifier circuits, thereby setting the system output to a steady-state output target, and in a second mode, update only the DAC code of the first DAC circuit to set the system output to a steady-state output target, wherein the second mode has a lower output voltage range than the first mode.

[0097] In Example 15, the subject of one or any combination of Examples 10 to 14 optionally includes a switch circuit and a plurality of amplifier circuits, including a first amplifier circuit and a second amplifier circuit, and at least one DAC circuit includes a first DAC circuit and a second DAC circuit. The output of the first DAC circuit is connected to the input of the first amplifier circuit. The switch circuit is configured to connect the output of the first DAC circuit to the input of the second amplifier circuit in a first mode, and to connect the output of the second DAC circuit to the input of the second amplifier circuit in a second mode, the second mode having a lower voltage output range than the first mode.

[0098] In Example 16, the subject of one or any combination of Examples 10 to 15 optionally includes a system memory and a control circuit configured to sweep the DAC code of at least one DAC code over a specified range of DAC code values, store DAC glitch characteristic data for DAC code transitions in the system memory, and detect high glitch transitions using the stored DAC glitch magnitude for DAC code transitions.

[0099] In Example 17, the subject of one or any combination of Examples 10 to 16 optionally includes a feedback circuit path including an analog-to-digital converter (ADC) circuit operably coupled to the system output, and a control circuit configured to set the DAC code of at least one DAC circuit to set the system output current to a steady-state target output current.

[0100] In Example 18, the subject of one or any combination of Examples 10 to 17 optionally includes a sense impedance at the system output, a feedback circuit path including an analog-to-digital converter (ADC) circuit operably coupled to the sense impedance, and a control circuit configured to set the DAC code of at least one DAC circuit to set the system output current to a steady-state target output current.

[0101] Example 19 may include a subject (such as a power supply system with closed-loop control) or optionally be combined with one or any combination of Examples 1 to 18, and may include a subject comprising: a plurality of digital-to-analog converter (DAC) channels, each DAC channel including a DAC circuit connected to the input of an amplifier circuit; an adder node connected to the output of the amplifier circuit of the DAC channel to provide a system output; and a control circuit operably coupled to the DAC channel and the system output. The control circuit is configured to update the DAC circuits of the DAC channels with DAC codes to adjust the system output to a steady-state target output in a steady state, the DAC codes are selected from a first set of DAC codes, and are configured to detect when a DAC code selected from the first set of DAC codes results in a glitch condition at the output of a steady-state DAC circuit, and to change to select a DAC code from a second set of DAC codes that maintains the same steady-state target output and reduces glitches at the output of the DAC circuit.

[0102] Example 20 optionally includes a control circuit configured to modify the subject of Example 19 to determine a control loop offset according to the glitch magnitude of a high-glitch DAC code transition, and to add the control loop offset to an add node to select a DAC code from a second set of DAC codes.

[0103] These non-limiting examples may be combined in any substitution or combination. The above detailed description includes references to accompanying drawings which constitute part of the detailed description. The drawings illustrate specific embodiments in which the invention may be carried out. These embodiments are also referred to herein as “Examples.” All publications, patents, and patent documents referenced herein are incorporated herein by reference in whole, as if each individual were incorporated by reference. Where there is an inconsistent use between this document and those documents previously incorporated by reference, the use in the incorporated reference should be considered to complement the use in this document. Inconsistent contradictions are governed by the use in this document.

[0104] In this document, the terms “a” or “an” are used to mean one or more, as is common in patent documents, regardless of other examples or uses of “at least one” or “one or more.” In this document, the term “or” is used to mean non-exclusive “or,” such that “A or B” includes “A but not B,” “B but not A,” and “A and B.” In the attached claims, the terms “including” and “in which” are used as plain English equivalents of the terms “comprising” and “wherein.” Furthermore, in the following claims, the terms “including” and “in which” are unrestrictive; that is, any system, apparatus, article, or process containing elements in addition to those listed after such terms in the claims is still considered to be within the scope of those claims. Moreover, in the following claims, “first,” “second,” and “third,” etc., are used merely as symbols and are not intended to impose numerical requirements on their subjects. Embodiments of the methods described herein can be implemented at least partially by machine or computer. [Explanation of Symbols]

[0105] 402 Logic Circuits 602 Control Circuit 606 Analog-to-Digital Converter (ADC) 608 Second ADC 702 Control Circuit 1006 ADC 1202 Control Circuit 1210 Multiplexer (MUX) 1402 Control Circuit 1502 Control circuit 1802 Control Circuit 2502 Control Circuit 2700 method 2710 blocks 2720 ​​blocks 2730 blocks 2740 blocks 2750 blocks 2770 blocks 2780 blocks 2800 methods 2830 blocks 2840 blocks 2900 method 2905 Block 2910 blocks 2915 blocks 2920 blocks

Claims

1. A method for feedback control of an amplifier system, wherein the method is The system output of the amplifier system is set by driving multiple amplifier circuits using multiple digital-to-analog converter (DAC) circuits connected in parallel, Using the first set of DAC codes, the plurality of DAC circuits are operated to set the system output to the steady-state target output, When using the first set of DAC codes, a high glitch condition is detected at the output of the multiple DAC circuits, A method comprising: modifying the plurality of DAC circuits to operate using a second set of DAC codes to set the system output to substantially the same steady-state target output, wherein operating the plurality of DAC circuits using the second set of DAC codes reduces glitch energy in the output of the plurality of DAC circuits, the method further comprises When the amplifier system is operated in the first mode, the output of the first DAC circuit among the plurality of DAC circuits is supplied to the inputs of the first amplifier circuit and the second amplifier circuit among the plurality of amplifier circuits. A second mode of the method includes providing the output of the first DAC circuit to the input of the first amplifier circuit, and providing the output of a second DAC circuit among the plurality of DAC circuits to the input of the second amplifier circuit, wherein the output of the second DAC circuit has a lower voltage output than the output of the first DAC circuit.

2. The method according to claim 1, wherein detecting the high glitch condition includes detecting a high-energy glitch transition greater than a threshold glitch transition when operating the plurality of DAC circuits using the first set of DAC codes.

3. The method according to claim 1, wherein detecting the high glitch condition includes identifying that the first set of DAC codes includes a DAC code transition associated with the high glitch condition when setting the system output to the steady-state target output.

4. This includes setting the system output to the steady-state target output using a control loop that includes a feedback circuit path, The method according to claim 1, wherein the modification to operate the plurality of DAC circuits using a second set of DAC codes includes adding an offset to the control loop to operate the plurality of DAC circuits using the second set of DAC codes.

5. The method according to claim 4, wherein adding the offset to the control loop includes adding a programmable offset to the control loop using another DAC circuit.

6. Driving the aforementioned plurality of amplifier circuits is The method involves driving a plurality of amplifier circuits included in a plurality of DAC channels, wherein the inputs of the plurality of amplifier circuits are connected to the outputs of the plurality of DAC circuits to form the plurality of DAC channels, each DAC channel includes a main DAC and an amplifier circuit from the plurality of DAC circuits, and the amplifier circuits of the DAC channels have different signal gains. To drive, The first set of DAC codes is used to operate the main DAC of the DAC channel, and the outputs of the DAC channels are summed to set the system output, The method according to claim 1, further comprising using a control loop to set the system output to the steady-state target output and modifying the main DAC to operate using the second set of DAC codes to reduce the ripple in the system output caused by the plurality of DAC channels.

7. When operating the multiple DAC circuits using the first set of DAC codes, the detection of high-energy glitch transitions greater than threshold glitch transitions, The offset is determined using the magnitude of the high-energy glitch transition and the current DAC code. The method according to claim 6, comprising using the determined offset to select one set of DAC codes as the second set of DAC codes.

8. The DAC code of the plurality of DAC circuits is updated using the DAC code value selected from the first set of DAC codes, and the system output is set to the steady-state target output. When setting the system output to the steady-state target output, the system detects when the DAC code of the multiple DAC circuits settles near a high-glitch DAC code transition. The method according to claim 1, comprising updating the DAC codes of the plurality of DAC circuits using a DAC code value selected from the second set of DAC codes in response to the detection.

9. It is an amplifier system, A plurality of digital-to-analog converter (DAC) circuits connected in parallel, wherein setting the DAC code within the plurality of DAC circuits sets the output of the plurality of DAC circuits, A plurality of amplifier circuits, including inputs connected to the outputs of the plurality of DAC circuits, A feedback circuit path connected to the system output of the aforementioned amplifier system, The control circuit includes the plurality of DAC circuits and the feedback circuit path connected thereto, and the control circuit is The system is configured to operate the multiple DAC circuits using a first set of DAC codes to set the system output to a steady-state output target. An amplifier system configured to operate the plurality of DAC circuits using a second set of DAC codes in order to maintain the same steady-state output target and reduce the ripple in the system output caused by the plurality of DAC circuits, The amplifier system further includes a switch circuit, The plurality of amplifier circuits include a first amplifier circuit and a second amplifier circuit, the plurality of DAC circuits include a first DAC circuit and a second DAC circuit, and the output of the first DAC circuit is connected to the input of the first amplifier circuit. The aforementioned switch circuit In the first mode, the output of the first DAC circuit is connected to the input of the second amplifier circuit. In a second mode, the output of the second DAC circuit is connected to the input of the second amplifier circuit, and the amplifier system has a lower voltage output range in the second mode than in the first mode.

10. Includes a control loop comprising the feedback circuit path and the control circuit, The control circuit, It is configured to detect high glitch transitions in the first set of DAC codes that are greater than threshold glitch transitions, The amplifier system according to claim 9, configured to add an offset to the control loop to change it to select the DAC code from the second set of DAC codes.

11. The control loop includes another DAC circuit for adding the offset, The amplifier system according to claim 10, wherein the control circuit is configured to set the offset according to the magnitude of the high glitch transition and one or more DAC code values ​​corresponding to the high glitch transition.

12. Includes an adder node connected to the output of the plurality of amplifier circuits, The inputs of the plurality of amplifier circuits are connected to the outputs of the plurality of DAC circuits to form a plurality of DAC channels, and the outputs of the plurality of amplifier circuits are connected to the summing node. The control circuit, The system is configured to update the DAC codes of the multiple DAC circuits to maintain the steady-state output target. The amplifier system according to claim 10, wherein the offset is added to the summing node and configured to change the selection of the DAC code from the second set of DAC codes.

13. The plurality of amplifier circuits include a first amplifier circuit and a second amplifier circuit, and the plurality of DAC circuits include a first DAC circuit connected to the input of the first amplifier circuit and a second DAC circuit connected to the input of the second amplifier circuit. The control circuit, In the first mode, the DAC code of both the first DAC circuit and the second DAC circuit is updated to provide equal DAC outputs to the first amplifier circuit and the second amplifier circuit, thereby setting the system output to the steady-state output target. The amplifier system according to claim 10, wherein in the second mode, only the DAC code of the first DAC circuit is updated to set the system output to the steady-state output target, and the second mode has a lower output voltage range than the first mode.

14. Including system memory, The control circuit, It is configured to sweep the DAC codes of at least one DAC code across a specified range of DAC code values. The system is configured to store DAC glitch characteristic data for DAC code transitions in the system memory. The amplifier system according to claim 9, configured to detect high-glitch transitions using the magnitude of the stored DAC glitch with respect to the DAC code transition.

15. The feedback circuit path includes an analog-to-digital converter (ADC) circuit operably coupled to the system output. The amplifier system according to claim 9, wherein the control circuit is configured to set the DAC codes of the plurality of DAC circuits to set the system output voltage to a steady-state output target voltage.

16. The system output includes a detection impedance, The feedback circuit path includes an analog-to-digital converter (ADC) circuit operably coupled to the sensing impedance, The amplifier system according to claim 9, wherein the control circuit is configured to set the DAC codes of the plurality of DAC circuits to set the system output current to a steady-state target output current.

17. A power supply system having closed-loop control, wherein the power supply system is A plurality of digital-to-analog converter (DAC) channels connected in parallel, each DAC channel including a DAC circuit connected to the input of an amplifier circuit, and a plurality of DAC channels. An adder node connected to the output of the amplifier circuit of the DAC channel to provide a system output, The system comprises a control circuit operably coupled to the DAC channel and the system output, wherein the control circuit The DAC circuit of the DAC channel is configured to update with a DAC code to adjust the system output to a steady-state target output in a steady state, and the DAC code is selected from a first set of DAC codes. The system is configured to detect when a DAC code selected from the first set of DAC codes causes a glitch condition at the output of the DAC circuit in a steady state. A power supply system configured to change the selection of a DAC code from a second set of DAC codes that maintains the same steady-state target output and reduces glitches in the output of the DAC circuit, The aforementioned control circuit further, In the first mode, the output of the first DAC circuit of the DAC circuit is provided to the inputs of the first amplifier circuit and the second amplifier circuit of the amplifier circuit. In a second mode, the power supply system is configured such that the output of the first DAC circuit is supplied to the input of the first amplifier circuit, and the output of the second DAC circuit is supplied to the input of the second amplifier circuit, wherein the output of the second DAC circuit has a lower voltage output than the output of the first DAC circuit.

18. The control circuit, It is configured to determine the control loop offset according to the glitch magnitude of the high-glitch DAC code transition. The power supply system according to claim 17, wherein the control loop offset is configured to be added to the add node to change the selection of the DAC code from the second set of DAC codes.

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