Isolated gate drivers, traction inverters, electric vehicles

Abstract

An insulated gate driver 1 that has: a register 443 that stores adjustment data read from a non-volatile memory 445; a gate drive unit 441 that gate-drives a switch element using various characteristics set on the basis of stored values in the register 443; an abnormality detection unit 442 that detects abnormalities other than in the non-volatile memory 445; an error detection and correction circuit ECC that detects and corrects errors in adjustment data written to the non-volatile memory 445; a first external terminal FLT1 that externally outputs abnormality detection results; a second external terminal FLT2 that externally outputs error detection results; and a fault control unit 442 that, when a 1-bit error has been detected in the adjustment data, sets the second external terminal FLT2 to an output state at error detection and continues normal operation of the gate drive unit 441 and, when a 2-bit or longer error is detected in the adjustment data, force stops the gate drive unit 441.

Description

[Technical Field]

[0001] The invention disclosed in this specification relates to an insulated gate driver, and a traction inverter and an electric vehicle using the same. [Background technology]

[0002] Isolated gate drivers are used in a variety of applications, such as traction inverters in electric vehicles.

[0003] As an example of the related prior art, Patent Document 1 can be mentioned. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2011 / 055611 Summary of the Invention [Problem to be solved by the invention]

[0005] However, there is still room for further study on the miniaturization and cost reduction of the sets incorporating conventional insulated gate drivers.

[0006] In view of the above-mentioned problems discovered by the inventors of the present application, the invention disclosed in this specification aims to provide an insulated gate driver that can achieve a reduction in the size and cost of the set, and a traction inverter and an electric vehicle that use the same. [Means for solving the problem]

[0007] For example, an insulated gate driver disclosed in this specification includes a switch connection terminal configured to connect an external switch element, a non-volatile memory in which adjustment data is written, a register configured to store the adjustment data read from the non-volatile memory, a gate drive unit configured to drive the gate of the switch element with various characteristics set based on the stored value of the register, and a control logic unit that maintains the gate drive unit in an inactive state until the adjustment data has been read from the non-volatile memory and stored in the register.

[0008] Furthermore, for example, an insulated gate driver disclosed in this specification includes a switch connection terminal configured to connect an external switch element, a memory connection terminal configured to connect an external non-volatile memory in which adjustment data is written, a register configured to store the adjustment data read from the non-volatile memory, a gate drive unit configured to drive the gate of the switch element with various characteristics set based on the stored value of the register, and a control logic unit that maintains the gate drive unit in an inactive state until the adjustment data has been read from the non-volatile memory and stored in the register.

[0009] Furthermore, for example, an insulated gate driver disclosed in this specification includes a switch connection terminal configured to connect an external switch element, a non-volatile memory in which adjustment data is written, a register configured to store the adjustment data read from the non-volatile memory, a gate drive unit configured to drive the gate of the switch element with various characteristics set based on the stored value of the register, an abnormality detection unit configured to detect an abnormality other than in the non-volatile memory, an error detection and correction circuit configured to detect and correct an error in the adjustment data written to the non-volatile memory, a first external terminal configured to output a result of the abnormality detection to the outside, a second external terminal configured to output a result of the error detection to the outside, and a fault control unit configured to continue normal operation of the gate drive unit while setting the second external terminal to an output state at the time of error detection when a one-bit error is detected in the adjustment data, and to forcibly stop the gate drive unit when two or more errors are detected in the adjustment data.

[0010] Furthermore, for example, an insulated gate driver disclosed in this specification includes: a switch connection terminal configured to externally connect a switch element; a memory connection terminal configured to externally connect a non-volatile memory having adjustment data written thereto; a register configured to store the adjustment data read from the non-volatile memory; a gate drive unit configured to drive the gate of the switch element with various characteristics set based on the stored value of the register; an abnormality detection unit configured to detect an abnormality other than in the non-volatile memory; an error detection and correction circuit configured to detect and correct an error in the adjustment data written to the non-volatile memory; a first external terminal configured to externally output a result of the abnormality detection; a second external terminal configured to externally output the result of the error detection; and a fault control unit configured to, when a one-bit error is detected in the adjustment data, set the second external terminal to an output state at the time of error detection and continue normal operation of the gate drive unit, and to forcibly stop the gate drive unit when two or more errors are detected in the adjustment data.

[0011] Still other features, elements, steps, advantages, and characteristics will become more apparent from the detailed description that follows and the accompanying drawings related thereto. [Effects of the Invention]

[0012] According to the invention disclosed in this specification, it is possible to provide an insulated gate driver that can achieve a reduction in the size and cost of the set, and a traction inverter and an electric vehicle that use the same. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram showing the basic configuration of a signal transmission device. [Figure 2] FIG. 2 is a diagram showing the basic structure of a transformer chip. [Figure 3] FIG. 3 is a perspective view of a semiconductor device used as a two-channel transformer chip. [Figure 4] FIG. 4 is a plan view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. [Figure 8] FIG. 8 is an enlarged view (isolation structure) of region XIII shown in FIG. [Figure 9] FIG. 9 is a diagram schematically illustrating an example of the layout of a transformer chip. [Figure 10] FIG. 10 is a diagram showing the basic configuration of a traction inverter. [Figure 11] FIG. 11 shows a novel embodiment of an isolated gate driver. [Figure 12]FIG. 12 is a diagram showing the start-up sequence of the insulated gate driver. [Figure 13] FIG. 13 is a diagram showing a first implementation example of a nonvolatile memory. [Figure 14] FIG. 14 is a diagram showing a second implementation example of a nonvolatile memory. [Figure 15] FIG. 15 is a diagram showing a third implementation example of a nonvolatile memory. [Figure 16] FIG. 16 is a diagram illustrating a first operation example of the fault output. [Figure 17] FIG. 17 is a diagram illustrating a second operation example of the fault output. [Figure 18] FIG. 18 is a diagram illustrating a third operation example of the fault output. [Figure 19] FIG. 19 is a diagram illustrating a fourth operation example of the fault output. [Figure 20] FIG. 20 is a diagram showing a first example of sharing a fault signal output terminal. [Figure 21] FIG. 21 is a diagram showing a second example of sharing the fault signal output terminal. [Figure 22] FIG. 22 is a diagram showing a third example of sharing of the fault signal output terminal. [Figure 23] FIG. 23 is a diagram showing the appearance of an electric vehicle. DETAILED DESCRIPTION OF THE INVENTION

[0014] <Signal transmission device (basic configuration)> 1 is a diagram showing the basic configuration of a signal transmission device. The signal transmission device 200 of this configuration example is a semiconductor integrated circuit device (a so-called insulated gate driver IC) that transmits a pulse signal from the primary circuit system 200p to the secondary circuit system 200s while insulating the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system) and drives the gate of a switch element (not shown) provided in the secondary circuit system 200s. For example, the signal transmission device 200 is configured by sealing a controller chip 210, a driver chip 220, and a transformer chip 230 in a single package.

[0015] The controller chip 210 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC1 (for example, up to 7 V with respect to GND1). The controller chip 210 has integrated therein, for example, a pulse transmission circuit 211 and buffers 212 and 213.

[0016] The pulse transmitting circuit 211 is a pulse generator that generates transmission pulse signals S11 and S21 in response to the input pulse signal IN. More specifically, when the pulse transmitting circuit 211 notifies that the input pulse signal IN is at a high level, it pulse-drives the transmission pulse signal S11 (outputting a single or multiple transmission pulses), and when it notifies that the input pulse signal IN is at a low level, it pulse-drives the transmission pulse signal S21. That is, the pulse transmitting circuit 211 pulse-drives either the transmission pulse signals S11 or S21 in response to the logic level of the input pulse signal IN.

[0017] The buffer 212 receives the transmission pulse signal S11 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 231).

[0018] The buffer 213 receives the transmission pulse signal S21 from the pulse transmission circuit 211 and pulse-drives the transformer chip 230 (specifically, the transformer 232).

[0019] The driver chip 220 is a semiconductor chip that operates by receiving a supply of power supply voltage VCC2 (for example, up to 30 V with respect to GND2). The driver chip 220 has buffers 221 and 222, a pulse receiving circuit 223, and a driver 224 integrated therein.

[0020] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically, the transformer 231) and outputs the result to the pulse receiving circuit 223.

[0021] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically, the transformer 232) and outputs the result to the pulse receiving circuit 223.

[0022] The pulse receiving circuit 223 generates the output pulse signal OUT by driving the driver 224 in response to the received pulse signals S12 and S22 input via the buffers 221 and 222. More specifically, the pulse receiving circuit 223 drives the driver 224 so that the output pulse signal OUT rises to a high level in response to the pulse driving of the received pulse signal S12, and the output pulse signal OUT falls to a low level in response to the pulse driving of the received pulse signal S22. In other words, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT in response to the logic level of the input pulse signal IN. Note that an RS flip-flop, for example, can be suitably used as the pulse receiving circuit 223.

[0023] The driver 224 generates an output pulse signal OUT based on the drive control of the pulse receiving circuit 223 .

[0024] The transformer chip 230 provides DC insulation between the controller chip 210 and the driver chip 220 using transformers 231 and 232, and outputs transmission pulse signals S11 and S21 input from the pulse transmission circuit 211 as reception pulse signals S12 and S22, respectively, to the pulse reception circuit 223. In this specification, "DC-insulated" means that the objects to be insulated are not connected by a conductor.

[0025] More specifically, the transformer 231 outputs a reception pulse signal S12 from the secondary coil 231s in response to a transmission pulse signal S11 input to the primary coil 231p, while the transformer 232 outputs a reception pulse signal S22 from the secondary coil 232s in response to a transmission pulse signal S21 input to the primary coil 232p.

[0026] In this way, due to the characteristics of the spiral coil used for insulated communication, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (corresponding to the rise signal and fall signal), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0027] In addition, the signal transmission device 200 of this configuration example has an independent transformer chip 230 equipped with only transformers 231 and 232, in addition to the controller chip 210 and the driver chip 220, and these three chips are sealed in a single package.

[0028] With this configuration, the controller chip 210 and the driver chip 220 can both be formed using a general low to medium voltage withstand process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high voltage withstand process (withstand voltage of several kV), thereby enabling reduction in manufacturing costs.

[0029] The signal transmission device 200 can be suitably used, for example, in a power supply device or a motor drive device for on-board equipment mounted in a vehicle. The above-mentioned vehicles include not only engine vehicles but also electric vehicles (battery electric vehicles (BEVs), hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs) / plug-in hybrid vehicles (PHVs), or xEVs such as fuel cell electric vehicles (FCEVs) / FCVs (fuel cell electric vehicles)).

[0030] <Trans chip (basic structure)> Next, the basic structure of transformer chip 230 will be described. Fig. 2 is a diagram showing the basic structure of transformer chip 230. In transformer chip 230 shown in this figure, transformer 231 includes primary coil 231p and secondary coil 231s that face each other in the vertical direction. Transformer 232 includes primary coil 232p and secondary coil 232s that face each other in the vertical direction.

[0031] The primary coils 231p and 232p are both formed on a first wiring layer (lower layer) 230a of the transformer chip 230. The secondary coils 231s and 232s are both formed on a second wiring layer (upper layer in this figure) 230b of the transformer chip 230. The secondary coil 231s is disposed directly above the primary coil 231p and faces the primary coil 231p. The secondary coil 232s is disposed directly above the primary coil 232p and faces the primary coil 232p.

[0032] The primary coil 231p is laid spirally, starting from a first end connected to the internal terminal X21, so as to surround the periphery of the internal terminal X21 in a clockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. Meanwhile, the primary coil 232p is laid spirally, starting from a first end connected to the internal terminal X23, so as to surround the periphery of the internal terminal X23 in a counterclockwise direction, and its second end corresponding to its end point is connected to the internal terminal X22. The internal terminals X21, X22, and X23 are linearly arranged in the order shown in the figure.

[0033] The internal terminal X21 is connected to the external terminal T21 on the second layer 230b via a conductive wiring Y21 and a via Z21. The internal terminal X22 is connected to the external terminal T22 on the second layer 230b via a conductive wiring Y22 and a via Z22. The internal terminal X23 is connected to the external terminal T23 on the second layer 230b via a conductive wiring Y23 and a via Z23. The external terminals T21 to T23 are arranged linearly and are used for wire bonding with the controller chip 210.

[0034] The secondary coil 231s is laid in a spiral shape, starting from a first end connected to the external terminal T24 and surrounding the external terminal T24 in a counterclockwise direction, with a second end corresponding to the end point connected to the external terminal T25. Meanwhile, the secondary coil 232s is laid in a spiral shape, starting from a first end connected to the external terminal T26 and surrounding the external terminal T26 in a clockwise direction, with a second end corresponding to the end point connected to the external terminal T25. The external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure, and are used for wire bonding with the driver chip 220.

[0035] The secondary coils 231s and 232s are AC-connected to the primary coils 231p and 232p by magnetic coupling, and are DC-insulated from the primary coils 231p and 232p, respectively. That is, the driver chip 220 is AC-connected to the controller chip 210 via the transformer chip 230, and is DC-insulated from the controller chip 210 by the transformer chip 230.

[0036] <Transformer chip (2-channel type)> FIG. 3 is a perspective view showing a semiconductor device 5 used as a two-channel transformer chip. FIG. 4 is a plan view of the semiconductor device 5 shown in FIG. 3. FIG. 5 is a plan view showing a layer in which a low-potential coil 22 (corresponding to the primary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 6 is a plan view showing a layer in which a high-potential coil 23 (corresponding to the secondary coil of the transformer) is formed in the semiconductor device 5 shown in FIG. 3. FIG. 7 is a cross-sectional view taken along line VIII-VIII shown in FIG. 6. FIG. 8 is an enlarged view of region XIII shown in FIG. 7, showing an isolation structure 130.

[0037] 3 to 7, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. Semiconductor chip 41 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0038] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0039] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0040] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view seen from their normal direction Z (hereinafter simply referred to as "plan view").

[0041] The chip sidewalls 44A to 44D include a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long sides of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along the first direction X and face the second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short sides of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend in the second direction Y and face the first direction X. The chip sidewalls 44A to 44D are made of ground surfaces.

[0042] The semiconductor device 5 further includes an insulating layer 51 formed on the first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating side walls 53A to 53D. The insulating main surface 52 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 42 in a plan view. The insulating main surface 52 extends parallel to the first main surface 42.

[0043] The insulating side walls 53A to 53D include a first insulating side wall 53A, a second insulating side wall 53B, a third insulating side wall 53C, and a fourth insulating side wall 53D. The insulating side walls 53A to 53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are continuous with the chip side walls 44A to 44D. Specifically, the insulating side walls 53A to 53D are formed flush with the chip side walls 44A to 44D. The insulating side walls 53A to 53D form ground surfaces that are flush with the chip side walls 44A to 44D.

[0044] The insulating layer 51 has a multilayer insulating laminate structure including a bottom insulating layer 55, a top insulating layer 56, and a plurality of (11 in this embodiment) interlayer insulating layers 57. The bottom insulating layer 55 is an insulating layer that directly covers the first main surface 42. The top insulating layer 56 is an insulating layer that forms the insulating main surface 52. The plurality of interlayer insulating layers 57 are insulating layers interposed between the bottom insulating layer 55 and the top insulating layer 56. In this embodiment, the bottom insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 56 also has a single-layer structure containing silicon oxide. The thickness of the bottom insulating layer 55 and the top insulating layer 56 may each be 1 μm or more and 3 μm or less (for example, about 2 μm).

[0045] Each of the multiple interlayer insulating layers 57 has a stacked structure including a first insulating layer 58 on the side of the bottom insulating layer 55 and a second insulating layer 59 on the side of the top insulating layer 56. The first insulating layer 58 may contain silicon nitride. The first insulating layer 58 is formed as an etching stopper layer for the second insulating layer 59. The thickness of the first insulating layer 58 may be 0.1 μm or more and 1 μm or less (for example, approximately 0.3 μm).

[0046] The second insulating layer 59 is formed on the first insulating layer 58. It contains an insulating material different from that of the first insulating layer 58. The second insulating layer 59 may contain silicon oxide. The thickness of the second insulating layer 59 may be 1 μm or more and 3 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 59 is preferably greater than the thickness of the first insulating layer 58.

[0047] The total thickness DT of the insulating layers 51 may be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layers 51 and the number of stacked interlayer insulating layers 57 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 55, the top insulating layer 56, and the interlayer insulating layers 57 are arbitrary and are not limited to a specific insulating material.

[0048] The semiconductor device 5 includes a first functional device 45 formed on an insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (corresponding to the aforementioned transformers). In other words, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed inside the insulating layer 51 at intervals from the insulating side walls 53A to 53D. The multiple transformers 21 are formed at intervals in the first direction X.

[0049] Specifically, the multiple transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed in this order from the insulating side wall 53C side toward the insulating side wall 53D side in a plan view. The multiple transformers 21A to 21D each have a similar structure. The following description will be given using the structure of the first transformer 21A as an example. The description of the structure of the first transformer 21A applies mutatis mutandis to the structures of the second transformer 21B, third transformer 21C, and fourth transformer 21D, and will be omitted.

[0050] 5 to 7, the first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in an insulating layer 51. The high-potential coil 23 is formed in the insulating layer 51 so as to face the low-potential coil 22 in the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in a region sandwiched between a lowermost insulating layer 55 and an uppermost insulating layer 56 (i.e., a plurality of interlayer insulating layers 57).

[0051] The low-potential coil 22 is formed on the side of the lowest insulating layer 55 (semiconductor chip 41) within the insulating layer 51, and the high-potential coil 23 is formed on the side of the highest insulating layer 56 (insulating main surface 52) relative to the low-potential coil 22 within the insulating layer 51. In other words, the high-potential coil 23 faces the semiconductor chip 41 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed in any desired locations. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with one or more interlayer insulating layers 57 sandwiched between them.

[0052] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of the interlayer insulating layers 57) is adjusted appropriately depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the third interlayer insulating layer 57 counting from the bottom insulating layer 55 side. In this embodiment, the high-potential coil 23 is formed on the first interlayer insulating layer 57 counting from the top insulating layer 56 side.

[0053] The low-potential coil 22 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 that is wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in an elliptical shape (oval shape) in a plan view. The portion that forms the innermost periphery of the first spiral portion 26 defines a first inner region 66 that is elliptical in a plan view.

[0054] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0055] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and are not limited to the shapes shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The first inner region 66 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0056] The low-potential coil 22 may include at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may have a layered structure including a barrier layer and a body layer. The barrier layer defines a recess space in the interlayer insulating layer 57. The barrier layer may include at least one of titanium and titanium nitride. The body layer may include at least one of copper, aluminum, and tungsten.

[0057] The high-potential coil 23 is embedded in the interlayer insulating layer 57, penetrating the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in an elliptical (oval) shape in a planar view. In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 67 that is elliptical in a planar view. The second inner region 67 of the second spiral portion 29 faces the first inner region 66 of the first spiral portion 26 in the normal direction Z.

[0058] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0059] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0060] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0061] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 67 are arbitrary and are not limited to the form shown in Fig. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view. The second inner region 67 may be partitioned into a polygonal shape such as a triangular shape or a quadrangular shape, or a circular shape in a planar view, depending on the winding shape of the second spiral portion 29.

[0062] The high-potential coil 23 is preferably formed from the same conductive material as the low-potential coil 22. That is, like the low-potential coil 22, the high-potential coil 23 preferably includes a barrier layer and a main body layer.

[0063] 4, the semiconductor device 5 includes a plurality of (12 in this figure) low potential terminals 11 and a plurality of (12 in this figure) high potential terminals 12. The plurality of low potential terminals 11 are electrically connected to the low potential coils 22 of the corresponding transformers 21A to 21D, respectively. The plurality of high potential terminals 12 are electrically connected to the high potential coils 23 of the corresponding transformers 21A to 21D, respectively.

[0064] The plurality of low potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the plurality of low potential terminals 11 are formed in an area on the insulating sidewall 53B side at intervals in the second direction Y from the plurality of transformers 21A to 21D, and are arranged at intervals in the first direction X.

[0065] The plurality of low potential terminals 11 include a first low potential terminal 11A, a second low potential terminal 11B, a third low potential terminal 11C, a fourth low potential terminal 11D, a fifth low potential terminal 11E, and a sixth low potential terminal 11F. In this embodiment, two of each of the plurality of low potential terminals 11A to 11F are formed. The number of the plurality of low potential terminals 11A to 11F is arbitrary.

[0066] The first low potential terminal 11A faces the first transformer 21A in the second direction Y in plan view. The second low potential terminal 11B faces the second transformer 21B in the second direction Y in plan view. The third low potential terminal 11C faces the third transformer 21C in the second direction Y in plan view. The fourth low potential terminal 11D faces the fourth transformer 21D in the second direction Y in plan view. The fifth low potential terminal 11E is formed in a region between the first low potential terminal 11A and the second low potential terminal 11B in plan view. The sixth low potential terminal 11F is formed in a region between the third low potential terminal 11C and the fourth low potential terminal 11D in plan view.

[0067] The first low potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low potential coil 22). The second low potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low potential coil 22). The third low potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low potential coil 22). The fourth low potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low potential coil 22).

[0068] The fifth low potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low potential coil 22) and the first outer end 25 of the second transformer 21B (low potential coil 22). The sixth low potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low potential coil 22) and the first outer end 25 of the fourth transformer 21D (low potential coil 22).

[0069] The plurality of high potential terminals 12 are formed on the insulating main surface 52 of the insulating layer 51 at intervals from the plurality of low potential terminals 11. Specifically, the plurality of high potential terminals 12 are formed in an area on the insulating sidewall 53A side at intervals from the plurality of low potential terminals 11 in the second direction Y, and are arranged at intervals in the first direction X.

[0070] The multiple high potential terminals 12 are each formed in an area close to the corresponding transformer 21A to 21D in a plan view. The high potential terminals 12 being close to the transformers 21A to 21D means that the distance between the high potential terminal 12 and the transformer 21 in a plan view is less than the distance between the low potential terminal 11 and the high potential terminal 12.

[0071] Specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to face the multiple transformers 21A to 21D along the first direction X in a plan view. More specifically, the multiple high potential terminals 12 are formed at intervals along the first direction X so as to be located in the second inner region 67 of the high potential coil 23 and in a region between adjacent high potential coils 23 in a plan view. As a result, the multiple high potential terminals 12 are arranged in a line with the multiple transformers 21A to 21D in the first direction X in a plan view.

[0072] The plurality of high potential terminals 12 include a first high potential terminal 12A, a second high potential terminal 12B, a third high potential terminal 12C, a fourth high potential terminal 12D, a fifth high potential terminal 12E, and a sixth high potential terminal 12F. In this embodiment, two of each of the plurality of high potential terminals 12A to 12F are formed. The number of the plurality of high potential terminals 12A to 12F is arbitrary.

[0073] The first high potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high potential coil 23) in a plan view. The second high potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high potential coil 23) in a plan view. The third high potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high potential coil 23) in a plan view. The fourth high potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high potential coil 23) in a plan view. The fifth high potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in a plan view. The sixth high potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in a plan view.

[0074] The first high potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high potential coil 23). The second high potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high potential coil 23). The third high potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high potential coil 23). The fourth high potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high potential coil 23).

[0075] The fifth high potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high potential coil 23) and the second outer end 28 of the second transformer 21B (high potential coil 23). The sixth high potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high potential coil 23) and the second outer end 28 of the fourth transformer 21D (high potential coil 23).

[0076] 5 to 7, the semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34, each formed in an insulating layer 51. In this embodiment, a plurality of first low potential wirings 31, a plurality of second low potential wirings 32, a plurality of first high potential wirings 33, and a plurality of second high potential wirings 34 are formed.

[0077] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. The first low-potential wiring 31 and the second low-potential wiring 32 also fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all of the low-potential coils 22 of the transformers 21A to 21D to the same potential.

[0078] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. The first high-potential wiring 33 and the second high-potential wiring 34 also fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of the transformers 21A to 21D to the same potential.

[0079] The plurality of first low potential wirings 31 are electrically connected to the corresponding low potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low potential coils 22), respectively. The plurality of first low potential wirings 31 have the same structure. In the following, the structure of the first low potential wiring 31 connected to the first low potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the first low potential wiring 31 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first low potential wirings 31, and will not be repeated here.

[0080] The first low-potential wiring 31 includes a through wiring 71, a low-potential connection wiring 72, a lead-out wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (multiple in this embodiment) pad plug electrodes 76, and one or more (multiple in this embodiment) substrate plug electrodes 77.

[0081] The through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the through wiring 71, the low-potential connecting wiring 72, the drawing wiring 73, the first connecting plug electrode 74, the second connecting plug electrode 75, the pad plug electrode 76, and the substrate plug electrode 77 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0082] The through wiring 71 penetrates the multiple interlayer insulating layers 57 in the insulating layer 51 and extends in a columnar shape along the normal direction Z. In this embodiment, the through wiring 71 is formed in the region of the insulating layer 51 between the lowermost insulating layer 55 and the uppermost insulating layer 56. The through wiring 71 has an upper end on the uppermost insulating layer 56 side and a lower end on the lowermost insulating layer 55 side. The upper end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the high-potential coil 23 and is covered by the uppermost insulating layer 56. The lower end of the through wiring 71 is formed in the same interlayer insulating layer 57 as the low-potential coil 22.

[0083] In this embodiment, the through wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed from the same conductive material as the low-potential coil 22, etc. In other words, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 each include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0084] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and faces the low potential terminal 11 (first low potential terminal 11A) in the normal direction Z. The second electrode layer 79 is formed in an island shape and faces the first electrode layer 78 in the normal direction Z.

[0085] The plurality of wiring plug electrodes 80 are embedded in the plurality of interlayer insulating layers 57 located in the region between the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be electrically connected to one another, and electrically connect the first electrode layer 78 and the second electrode layer 79. The plurality of wiring plug electrodes 80 each have a planar area that is less than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0086] The number of stacked wiring plug electrodes 80 corresponds to the number of stacked interlayer insulating layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulating layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulating layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 may be formed penetrating the interlayer insulating layers 57.

[0087] The low-potential connecting wiring 72 is formed in the first inner region 66 of the first transformer 21A (low-potential coil 22) in the same interlayer insulating layer 57 as the low-potential coil 22. The low-potential connecting wiring 72 is formed in an island shape and faces the high-potential terminal 12 (first high-potential terminal 12A) in the normal direction Z. The low-potential connecting wiring 72 preferably has a planar area that exceeds the planar area of ​​the wiring plug electrode 80. The low-potential connecting wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0088] The lead-out wiring 73 is formed in the interlayer insulating layer 57 in a region between the semiconductor chip 41 and the through wiring 71. In this embodiment, the lead-out wiring 73 is formed in the first interlayer insulating layer 57 counting from the bottom insulating layer 55. The lead-out wiring 73 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the lower end of the through wiring 71. The second end of the lead-out wiring 73 is located in the region between the semiconductor chip 41 and the low-potential connecting wiring 72. The wiring portion extends along the first main surface 42 of the semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0089] The first connection plug electrode 74 is formed in the interlayer insulating layer 57 in a region between the through wiring 71 and the lead-out wiring 73, and is electrically connected to first ends of the through wiring 71 and the lead-out wiring 73. The second connection plug electrode 75 is formed in the interlayer insulating layer 57 in a region between the low potential connection wiring 72 and the lead-out wiring 73, and is electrically connected to second ends of the low potential connection wiring 72 and the lead-out wiring 73.

[0090] The plurality of pad plug electrodes 76 are formed in the uppermost insulating layer 56 in a region between the low potential terminal 11 (first low potential terminal 11A) and the through wiring 71, and are electrically connected to the upper ends of the low potential terminal 11 and the through wiring 71, respectively. The plurality of substrate plug electrodes 77 are formed in the lowermost insulating layer 55 in a region between the semiconductor chip 41 and the drawing wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in a region between the semiconductor chip 41 and the first ends of the drawing wiring 73, and are electrically connected to the semiconductor chip 41 and the first ends of the drawing wiring 73, respectively.

[0091] 6 and 7, the plurality of first high-potential wirings 33 are electrically connected to the corresponding high-potential terminals 12A-12D and the second inner ends 27 of the corresponding transformers 21A-21D (high-potential coils 23), respectively. The plurality of first high-potential wirings 33 each have a similar structure. In the following, the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A will be described as an example. The description of the structure of the first high-potential wiring 33 connected to the first transformer 21A applies mutatis mutandis to the structure of the other first high-potential wirings 33, and will not be repeated here.

[0092] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (multiple in this embodiment) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrode 82 are preferably formed from the same conductive material as the low-potential coil 22, etc. In other words, the high-potential connection wiring 81 and the pad plug electrode 82 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0093] The high-potential connection wiring 81 is formed in the second inner region 67 of the high-potential coil 23 within the same interlayer insulating layer 57 as the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and faces the high-potential terminal 12 (the first high-potential terminal 12A) in the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. The high-potential connection wiring 81 is formed at an interval from the low-potential connection wiring 72 in a plan view and does not face the low-potential connection wiring 72 in the normal direction Z. Thereby, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the breakdown voltage of the insulating layer 51 is enhanced.

[0094] The plurality of pad plug electrodes 82 are formed in the region between the high-potential terminal 12 (the first high-potential terminal 12A) and the high-potential connection wiring 81 within the uppermost insulating layer 56, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81, respectively. The plurality of pad plug electrodes 82 each have a planar area less than the planar area of the high-potential connection wiring 81 in a plan view.

[0095] Referring to FIG. 7, it is preferable that the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). It is preferable that the distance D1 exceeds the total thickness DT of the plurality of interlayer insulating layers 57 (DT < D1). The ratio D2 / D1 of the distance D2 to the distance D1 may be 0.01 or more and 0.1 or less. It is preferable that the distance D1 is 100 μm or more and 500 μm or less. The distance D2 may be 1 μm or more and 50 μm or less. It is preferable that the distance D2 is 5 μm or more and 25 μm or less. The values of the distance D1 and the distance D2 are arbitrary and are appropriately adjusted according to the breakdown voltage to be achieved.

[0096] Referring to FIGS. 6 and 7, the semiconductor device 5 includes dummy patterns 85 embedded in the insulating layer 51 so as to be located around the transformers 21A to 21D in a plan view.

[0097] The dummy pattern 85 is formed in a pattern (discontinuous pattern) different from the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A to 21D. In other words, the dummy pattern 85 does not function as a part of the transformers 21A to 21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A to 21D and suppresses electric field concentration on the high-potential coil 23. In this embodiment, the dummy pattern 85 is routed at a line density per unit area equal to that of the high-potential coil 23. The line density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the line density of the dummy pattern 85 falls within a range of ±20% of the line density of the high-potential coil 23.

[0098] The depth position of the dummy pattern 85 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The dummy pattern 85 is preferably formed in a region closer to the high-potential coil 23 than to the low-potential coil 22 in the normal direction Z. Note that the dummy pattern 85 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0099] In this case, electric field concentration on the high-potential coil 23 can be appropriately suppressed. The shorter the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the more electric field concentration on the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed in the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration on the high-potential coil 23 can be further appropriately suppressed. The dummy pattern 85 includes multiple dummy patterns with different electrical states. The dummy pattern 85 may include a high-potential dummy pattern.

[0100] The depth position of the high-potential dummy pattern 86 within the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed. The high-potential dummy pattern 86 is preferably formed in a region closer to the high-potential coil 23 than the low-potential coil 22 in the normal direction Z. The high-potential dummy pattern 86 being closer to the high-potential coil 23 in the normal direction Z means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0101] Dummy patterns 85 include floating dummy patterns formed in an electrically floating state within insulating layer 51 so as to be positioned around transformers 21A to 21D.

[0102] In this embodiment, the floating dummy pattern is routed in a dense line shape so as to partially cover and partially expose the area around the high-potential coil 23 in a plan view. The floating dummy pattern may be formed to have ends or to have no ends.

[0103] The depth position of the floating dummy pattern inside the insulating layer 51 is arbitrary and is adjusted according to the electric field intensity to be relaxed.

[0104] The number of floating lines is arbitrary and can be adjusted depending on the electric field to be relaxed. The floating dummy pattern may be made up of a plurality of floating lines.

[0105] 7, the semiconductor device 5 includes a second functional device 60 formed on the first main surface 42 of the semiconductor chip 41 in a device region 62. The second functional device 60 is formed using a surface layer portion of the first main surface 42 of the semiconductor chip 41 and / or a region above the first main surface 42 of the semiconductor chip 41, and is covered with an insulating layer 51 (lowermost insulating layer 55). In FIG. 7, the second functional device 60 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 42.

[0106] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring, and is electrically connected to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has a structure similar to that of the first low-potential wiring 31 (second low-potential wiring 32), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. The high-potential wiring has a structure similar to that of the first high-potential wiring 33 (second high-potential wiring 34), except that it is routed within the insulating layer 51 so as to be connected to the second functional device 60. A detailed description of the low-potential wiring and high-potential wiring related to the second functional device 60 will be omitted.

[0107] The second functional device 60 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The passive device may include a circuit network in which any two or more of the passive device, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuit network may form part or all of an integrated circuit.

[0108] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0109] 5 to 7, the semiconductor device 5 further includes a seal conductor 61 embedded in the insulating layer 51. The seal conductor 61 is embedded in the insulating layer 51 in a wall shape at a distance from the insulating side walls 53A to 53D in a plan view, and divides the insulating layer 51 into a device region 62 and an outer region 63. The seal conductor 61 prevents moisture and cracks from entering the device region 62 from the outer region 63.

[0110] The device region 62 is a region including the first functional device 45 (plurality of transformers 21), the second functional device 60, plural low potential terminals 11, plural high potential terminals 12, first low potential wiring 31, second low potential wiring 32, first high potential wiring 33, second high potential wiring 34, and dummy patterns 85. The outer region 63 is a region outside the device region 62.

[0111] The seal conductor 61 is electrically isolated from the device region 62. Specifically, the seal conductor 61 is electrically isolated from the first functional device 45 (plurality of transformers 21), the second functional device 60, the plurality of low potential terminals 11, the plurality of high potential terminals 12, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85. More specifically, the seal conductor 61 is fixed in an electrically floating state. The seal conductor 61 does not form a current path leading to the device region 62.

[0112] The seal conductor 61 is formed in a strip shape along the insulating side walls 53 to 53D in plan view. In this embodiment, the seal conductor 61 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. As a result, the seal conductor 61 defines a quadrangular (specifically, rectangular) device region 62 in plan view. The seal conductor 61 also defines a quadrangular (specifically, rectangular) outer region 63 surrounding the device region 62 in plan view.

[0113] Specifically, the seal conductor 61 has an upper end on the insulating principal surface 52 side, a lower end on the semiconductor chip 41 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 61 is formed at a distance from the insulating principal surface 52 toward the semiconductor chip 41 and is located within the insulating layer 51. In this embodiment, the upper end of the seal conductor 61 is covered by the uppermost insulating layer 56. The upper end of the seal conductor 61 may be covered by one or more interlayer insulating layers 57. The upper end of the seal conductor 61 may be exposed from the uppermost insulating layer 56. The lower end of the seal conductor 61 is formed at a distance from the semiconductor chip 41 toward the upper end.

[0114] Thus, in this embodiment, the seal conductor 61 is embedded in the insulating layer 51 so as to be located on the semiconductor chip 41 side with respect to the plurality of low potential terminals 11 and the plurality of high potential terminals 12. Furthermore, the seal conductor 61 faces the first functional device 45 (plurality of transformers 21), the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, the second high potential wiring 34, and the dummy pattern 85 in the insulating layer 51 in a direction parallel to the insulating principal surface 52. The seal conductor 61 may face a part of the second functional device 60 in the insulating layer 51 in a direction parallel to the insulating principal surface 52.

[0115] The seal conductor 61 includes a plurality of seal plug conductors 64 and one or more (in this embodiment, a plurality) seal via conductors 65. The number of seal via conductors 65 is arbitrary. The uppermost seal plug conductor 64 among the plurality of seal plug conductors 64 forms the upper end portion of the seal conductor 61. The plurality of seal via conductors 65 each form the lower end portion of the seal conductor 61. The seal plug conductor 64 and the seal via conductor 65 are preferably formed from the same conductive material as the low-potential coil 22. In other words, the seal plug conductor 64 and the seal via conductor 65 preferably include a barrier layer and a main body layer, similar to the low-potential coil 22, etc.

[0116] The multiple seal plug conductors 64 are embedded in the multiple interlayer insulating layers 57, respectively, and are each formed in a quadrangular ring shape (specifically, a rectangular ring shape) surrounding the device region 62 in plan view. The multiple seal plug conductors 64 are stacked from the lowermost insulating layer 55 to the uppermost insulating layer 56 so as to be connected to each other. The number of stacked multiple seal plug conductors 64 matches the number of stacked multiple interlayer insulating layers 57. Of course, one or more seal plug conductors 64 may be formed penetrating the multiple interlayer insulating layers 57.

[0117] As long as a single annular seal conductor 61 is formed by an assembly of a plurality of seal plug conductors 64, it is not necessary for all of the plurality of seal plug conductors 64 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 64 may be formed in an end shape. Also, at least one of the plurality of seal plug conductors 64 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture and cracks penetrating into the device region 62, it is preferable that the plurality of seal plug conductors 64 be formed in an endless (annular) shape.

[0118] The plurality of seal via conductors 65 are respectively formed in the region between the semiconductor chip 41 and the seal plug conductor 64 in the lowermost insulating layer 55. The plurality of seal via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the seal plug conductor 64. The plurality of seal via conductors 65 have a planar area smaller than the planar area of ​​the seal plug conductor 64. When a single seal via conductor 65 is formed, the single seal via conductor 65 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 64.

[0119] The width of the shield conductor 61 may be 0.1 μm or more and 10 μm or less. The width of the shield conductor 61 is preferably 1 μm or more and 5 μm or less. The width of the shield conductor 61 is defined as the width in a direction perpendicular to the direction in which the shield conductor 61 extends.

[0120] 7 and 8, the semiconductor device 5 further includes an isolation structure 130 that is interposed between the semiconductor chip 41 and the seal conductor 61 and electrically isolates the seal conductor 61 from the semiconductor chip 41. The isolation structure 130 preferably includes an insulator. In this embodiment, the isolation structure 130 is made of a field insulating film 131 formed on the first main surface 42 of the semiconductor chip 41.

[0121] The field insulating film 131 includes at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). The field insulating film 131 is preferably made of a LOCOS (local oxidation of silicon) film, which is an example of an oxide film formed by oxidizing the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary as long as it can insulate the semiconductor chip 41 and the seal conductor 61. The thickness of the field insulating film 131 may be 0.1 μm or more and 5 μm or less.

[0122] The isolation structure 130 is formed on the first main surface 42 of the semiconductor chip 41, and extends in a strip shape along the seal conductor 61 in plan view. In this embodiment, the isolation structure 130 is formed in a quadrangular ring shape (specifically, a rectangular ring shape) in plan view. The isolation structure 130 has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 may form an anchor portion where the lower end portion (seal via conductor 65) of the seal conductor 61 bites in toward the semiconductor chip 41. Of course, the connection portion 132 may be formed flush with the main surface of the isolation structure 130.

[0123] The isolation structure 130 includes an inner end 130A on the device region 62 side, an outer end 130B on the outer region 63 side, and a main body 130C between the inner end 130A and the outer end 130B. The inner end 130A defines the region in which the second functional device 60 is formed (i.e., the device region 62) in plan view. The inner end 130A may be formed integrally with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0124] The outer end 130B is exposed from the chip sidewalls 44A to 44D of the semiconductor chip 41 and is continuous with the chip sidewalls 44A to 44D of the semiconductor chip 41. More specifically, the outer end 130B is formed flush with the chip sidewalls 44A to 44D of the semiconductor chip 41. The outer end 130B forms a flush ground surface between the chip sidewalls 44A to 44D of the semiconductor chip 41 and the insulating sidewalls 53A to 53D of the insulating layer 51. Of course, in other embodiments, the outer end 130B may be formed in the first main surface 42 at a distance from the chip sidewalls 44A to 44D.

[0125] The main body 130C has a flat surface extending substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connection portion 132 to which the lower end portion (seal via conductor 65) of the seal conductor 61 is connected. The connection portion 132 is formed in a portion of the main body 130C spaced apart from the inner end portion 130A and the outer end portion 130B. The isolation structure 130 can take various forms in addition to the field insulating film 131.

[0126] 7, the semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating principal surface 52 of the insulating layer 51 so as to cover the seal conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from above the insulating principal surface 52.

[0127] In this embodiment, the inorganic insulating layer 140 has a laminated structure including a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may contain silicon oxide. The first inorganic insulating layer 141 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may contain silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the dielectric strength voltage on the high-potential coil 23 can be increased.

[0128] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the inorganic insulating layer 140 is thickened, it is preferable to form the first inorganic insulating layer 141 thicker than the second inorganic insulating layer 142.

[0129] The first inorganic insulating layer 141 may contain at least one of BPSG (boron-doped phosphor silicate glass) and PSG (phosphorus silicate glass), which are examples of silicon oxide. In this case, however, since impurities (boron or phosphorus) are contained in the silicon oxide, it is particularly preferable to form the first inorganic insulating layer 141 made of USG in order to increase the dielectric strength voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may have a single-layer structure made of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0130] The inorganic insulating layer 140 covers the entire area of ​​the seal conductor 61, and has a plurality of low potential pad openings 143 and a plurality of high potential pad openings 144 formed in an area outside the seal conductor 61. The plurality of low potential pad openings 143 expose the plurality of low potential terminals 11, respectively. The plurality of high potential pad openings 144 expose the plurality of high potential terminals 12, respectively. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the low potential terminals 11. The inorganic insulating layer 140 may have overlapping portions that rise up onto the peripheral edges of the high potential terminals 12.

[0131] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may include a photosensitive resin. The organic insulating layer 145 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 includes polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0132] The thickness of the organic insulating layer 145 preferably exceeds the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably equal to or greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably equal to or greater than 2 μm and equal to or less than 10 μm. Furthermore, the thickness of the organic insulating layer 145 is preferably equal to or greater than 5 μm and equal to or less than 50 μm. These structures can prevent the inorganic insulating layer 140 and the organic insulating layer 145 from becoming thicker, and at the same time, the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145 can appropriately increase the dielectric strength voltage on the high-potential coil 23.

[0133] The organic insulating layer 145 includes a first portion 146 covering the region on the low potential side and a second portion 147 covering the region on the high potential side. The first portion 146 covers the seal conductor 61 with the inorganic insulating layer 140 sandwiched therebetween. The first portion 146 has a plurality of low potential terminal openings 148 that expose a plurality of low potential terminals 11 (low potential pad openings 143) in the region outside the seal conductor 61. The first portion 146 may have an overlap portion that rises onto the periphery (overlap portion) of the low potential pad opening 143.

[0134] The second portion 147 is formed at a distance from the first portion 146, and exposes the inorganic insulating layer 140 between the second portion 147 and the first portion 146. The second portion 147 has a plurality of high-potential terminal openings 149 that expose the plurality of high-potential terminals 12 (high-potential pad openings 144), respectively. The second portion 147 may have an overlapping portion that rises onto the periphery (overlapping portion) of the high-potential pad opening 144.

[0135] The second portion 147 collectively covers the transformers 21A to 21D and the dummy pattern 85. Specifically, the second portion 147 collectively covers the plurality of high-potential coils 23, the plurality of high-potential terminals 12, the first high-potential dummy pattern 87, the second high-potential dummy pattern 88, and the floating dummy pattern 121.

[0136] The embodiments of the present invention can be implemented in other forms. In the above-described embodiment, an example in which the first functional device 45 and the second functional device 60 are formed has been described. However, a form in which only the second functional device 60 is provided without the first functional device 45 may be adopted. In this case, the dummy pattern 85 may be removed. According to this structure, the second functional device 60 can achieve the same effects as those described in the first embodiment (excluding the effects related to the dummy pattern 85).

[0137] That is, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the high potential terminal 12 and the seal conductor 61. Furthermore, when a voltage is applied to the second functional device 60 via the low potential terminal 11 and the high potential terminal 12, it is possible to suppress undesired conduction between the low potential terminal 11 and the seal conductor 61.

[0138] In the above embodiment, an example was described in which the second functional device 60 was formed. However, the second functional device 60 is not necessarily required, and may be removed.

[0139] In the above embodiment, an example was described in which the dummy pattern 85 was formed. However, the dummy pattern 85 is not necessarily required and may be removed.

[0140] In the above embodiment, an example has been described in which the first functional device 45 is a multi-channel type that includes multiple transformers 21. However, a first functional device 45 that is a single-channel type that includes a single transformer 21 may also be employed.

[0141] <Transformer arrangement> 9 is a plan view (top view) schematically showing an example of a transformer arrangement in a two-channel transformer chip 300 (corresponding to the aforementioned semiconductor device 5). The transformer chip 300 in this figure has a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1 to a8, pads b1 to b8, pads c1 to c4, and pads d1 to d4.

[0142] In the transformer chip 300, pads a1 and b1 are connected to one end of a secondary coil L1s that forms a first transformer 301, and pads c1 and d1 are connected to the other end of the secondary coil L1s. Pads a2 and b2 are connected to one end of a secondary coil L2s that forms a second transformer 302, and pads c1 and d1 are connected to the other end of the secondary coil L2s.

[0143] Furthermore, pads a3 and b3 are connected to one end of a secondary coil L3s that forms the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of a secondary coil L4s that forms the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0144] Note that the primary coils forming the first transformer 301, the primary coils forming the second transformer 302, the primary coils forming the third transformer 303, and the primary coils forming the fourth transformer 304 are not shown in this figure. However, the primary coils basically have the same configuration as the secondary coils L1s to L4s, and are arranged directly below the secondary coils L1s to L4s, respectively, so as to face the secondary coils L1s to L4s.

[0145] That is, pads a5 and b5 are connected to one end of the primary coil forming first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. Also, pads a6 and b6 are connected to one end of the primary coil forming second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0146] Pads a7 and b7 are connected to one end of the primary coil forming third transformer 303, and pads c4 and d4 are connected to the other end of the primary coil. Pads a8 and b8 are connected to one end of the primary coil forming fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary coil.

[0147] However, the pads a5 to a8, pads b5 to b8, pads c3 and c4, and pads d3 and d4 are led out from the inside of the transformer chip 300 to the surface through vias (not shown).

[0148] Of the multiple pads, pads a1 to a8 correspond to first current supply pads, pads b1 to b8 correspond to first voltage measurement pads, pads c1 to c4 correspond to second current supply pads, and pads d1 to d4 correspond to second voltage measurement pads.

[0149] Therefore, with the transformer chip 300 of this configuration example, the series resistance component of each coil can be accurately measured during the defective product inspection. Therefore, it is possible to not only reject defective products in which a break occurs in each coil, but also to appropriately reject defective products in which an abnormal resistance value occurs in each coil (for example, a short circuit between coils), thereby making it possible to prevent defective products from being released onto the market.

[0150] For the transformer chip 300 that has passed the above-mentioned defective product inspection, the above-mentioned plurality of pads may be used as a means for connecting the primary chip and the secondary chip (for example, the above-mentioned controller chip 210 and driver chip 220).

[0151] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 may be connected to the signal input or output terminals of the secondary chip, respectively, and pads c1 and d1, and pads c2 and d2 may be connected to the common voltage application terminal (GND2) of the secondary chip, respectively.

[0152] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 may be connected to the signal input or output terminal of the primary chip, respectively, and pads c3 and d3, and pads c4 and d4 may be connected to the common voltage application terminal (GND1) of the primary chip, respectively.

[0153] Here, the first transformer 301 to the fourth transformer 304 are arranged in a manner that couples them in the respective signal transmission directions, as shown in Fig. 9. Referring to this figure, for example, the first transformer 301 and the second transformer 302 that transmit signals from the primary-side chip to the secondary-side chip are connected as a first pair by a first guard ring 305. Also, for example, the third transformer 303 and the fourth transformer 304 that transmit signals from the secondary-side chip to the primary-side chip are connected as a second pair by a second guard ring 306.

[0154] The reason for such coupling is to ensure a withstand voltage between the primary coil and the secondary coil when the primary coil and the secondary coil that respectively form the first transformer 301 to the fourth transformer 304 are stacked in the vertical direction of the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0155] The first guard ring 305 and the second guard ring 306 may be connected to low impedance wiring such as a ground terminal via pads e1 and e2, respectively.

[0156] In the transformer chip 300, pads c1 and d1 are shared between the secondary coil L1s and the secondary coil L2s. Pads c2 and d2 are shared between the secondary coil L3s and the secondary coil L4s. Pads c3 and d3 are shared between the primary coil L1p and the primary coil L2p. Pads c4 and d4 are shared between the corresponding primary coils. This configuration reduces the number of pads, making it possible to miniaturize the transformer chip 300.

[0157] 9, the primary coil and secondary coil forming each of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track shape with rounded corners) in a plan view of the transformer chip 300. This configuration increases the area where the primary coil and secondary coil overlap, thereby improving the transmission efficiency of the transformer.

[0158] Of course, the transformer arrangement in this figure is merely an example, and the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices in which coils are integrated on a semiconductor chip.

[0159] <Traction inverter> 10 is a diagram showing the basic configuration of a traction inverter mounted on an electric vehicle. The traction inverter 400 of this configuration example is a type of motor drive device that converts DC power supplied from an on-board battery (not shown) into AC power to drive a motor M, and includes an insulated gate driver 1, an ECU (electronic control unit) 2, and various discrete components (a high-side switch SWH, a low-side switch SWL, an npn-type bipolar transistor Q1, a pnp-type bipolar transistor Q2, resistors R1 to R3, and capacitors C1 and C2).

[0160] Examples of electric vehicles (so-called xEVs) equipped with the traction inverter 400 include BEVs (battery electric vehicles), HEVs (hybrid electric vehicles), PHEVs (plug-in hybrid electric vehicles) / PHVs (plug-in hybrid vehicles), and FCEVs (fuel cell electric vehicles) / FCVs (fuel cell vehicles).

[0161] The isolated gate driver 1 is a semiconductor integrated circuit device (e.g., equivalent to the signal transmission device 200 in FIG. 1) that transmits a gate drive signal from a primary circuit system (VCC1-GND1) that receives power from a DC voltage source E1 to a secondary circuit system (VCC2-GND2) that receives power from a DC voltage source E2, while isolating the two circuits.

[0162] The isolated gate driver 1 has a plurality of external terminals (in this figure, a VCC1 terminal, an IN terminal, an FLT1 terminal, an FLT2 terminal, a GND1 terminal, a VCC2 terminal, an OUT terminal, a CLAMP terminal, a PROOUT terminal, and a GND2 terminal) as means for establishing electrical connection with the outside of the device.

[0163] The VCC1 terminal is the power supply terminal for the primary circuit system. The IN terminal is the control input terminal. The FLT1 terminal and FLT2 terminal are fault signal output terminals. The GND1 terminal is the ground terminal for the primary circuit system. The VCC2 terminal is the power supply terminal for the secondary circuit system. The OUT terminal is the output terminal. The CLAMP terminal is a Miller clamp terminal. The PROOUT terminal is a soft turn-off terminal. The GND2 terminal is the ground terminal for the secondary circuit system.

[0164] The internal configuration and operation of the insulated gate driver 1 will be described in detail later.

[0165] The ECU 2 is a means for performing overall electrical control of the electric vehicle, and exchanges various signals (input signal IN, external fault signals FLT1 and FLT2, etc.) with the isolated gate driver 1.

[0166] The connections of the discrete components are as follows: Resistor R1 is connected between the VCC1 terminal and the FLT1 terminal. Resistor R2 is connected between the VCC1 terminal and the FLT2 terminal. Resistor R3 is connected between the CLAMP terminal and the PROOUT terminal. Capacitor C1 is connected between the VCC1 terminal and the GND1 terminal. Capacitor C2 is connected between the VCC2 terminal and the GND2 terminal.

[0167] The collector of transistor Q1 is connected to the VCC2 terminal. The emitters of transistors Q1 and Q2 and the control terminal (e.g., gate) of high-side switch SWH are all connected to the CLAMP terminal. The collector of transistor Q2 is connected to the GND2 terminal. The bases of transistors Q1 and Q2 are all connected to the OUT terminal.

[0168] The high-side switch SWH and the low-side switch SWL are respectively connected between the application terminal of the first motor drive voltage VD1 and each phase input terminal of the motor M (specifically, one end of each phase motor coil), and between each phase input terminal of the motor M and the application terminal of the second motor drive voltage VD2 (<VD1), and form a half-bridge output stage that controls the supply of the motor drive current according to the on / off control of each.

[0169] In addition, in the traction inverter 400 of this configuration example, insulated gate bipolar transistors (IGBTs [insulated gate bipolar transistors]) are used as the high-side switch SWH and the low-side switch SWL respectively, but the configuration of the half-bridge output stage is not limited to this, and MOS [metal oxide semiconductor] field effect transistors using SiC [silicon carbide] semiconductors or MOS field effect transistors using Si semiconductors may be adopted. In particular, MOS field effect transistors using SiC semiconductors have lower power consumption and higher heat resistance temperatures than MOS field effect transistors using Si semiconductors, so they are suitable for installation in electric vehicles.

[0170] Also, in this figure, for the convenience of explanation, only the half-bridge output stage for one phase is depicted, and only the insulated gate driver 1 connected to the high-side switch SWH is shown. Actually, the insulated gate driver 1 is connected to each of the high-side switch SWH and the low-side switch SWL that form the half-bridge output stage for each phase. Therefore, for example, when the motor M is a three-phase AC motor, a half-bridge output stage for three phases is prepared, so a total of six insulated gate drivers 1 are required.

[0171] <Insulated Gate Driver (Basic Configuration)> Next, the insulated gate driver 1 will be described in detail while referring to FIG. 10. The insulated gate driver 1 is formed by encapsulating the first semiconductor chip 410, the second semiconductor chip 420, and the third semiconductor chip 430 in one package.

[0172] The first semiconductor chip 410 is a controller chip that is driven by a power supply voltage VCC1 (e.g., 5 V or 3.3 V based on GND1) supplied from a DC voltage source E1 and integrates a controller that generates switch control signals S1 and S2 based on an input signal IN. The main functions of the first semiconductor chip 410 include generating the switch control signals S1 and S2, generating external fault signals FLT1 and FLT2, and providing a UVLO (under voltage lock out) function. The withstand voltage of the first semiconductor chip 410 may be designed to an appropriate withstand voltage (e.g., 7 V) taking into account the power supply voltage VCC1 (based on GND1).

[0173] The second semiconductor chip 420 is a driver chip that integrates a driver that is driven by a power supply voltage VCC2 (10 to 30 V based on GND2) supplied from a DC voltage source E2 and controls the drive of a high-side switch SWH, one end of which is applied with a high voltage of several hundred volts, based on switch control signals S1 and S2 input from the first semiconductor chip 410 via the third semiconductor chip 430. The main functions of the second semiconductor chip 420 include generating an output signal OUT, generating internal fault signals S3 and S4, and a UVLO function. The withstand voltage of the second semiconductor chip 420 may be designed to an appropriate withstand voltage (e.g., 40 V) taking into account the power supply voltage VCC2 (based on GND2).

[0174] The third semiconductor chip 430 is a transformer chip that integrates transformers that transmit and receive switch control signals S1 and S2 and internal fault signals S3 and S4 while providing DC isolation between the first semiconductor chip 410 and the second semiconductor chip 420.

[0175] As described above, the insulated gate driver 1 of this configuration example is configured to include an independent third semiconductor chip 430 that mounts only a transformer, in addition to the first semiconductor chip 410 that integrates a controller and the second semiconductor chip 420 that integrates a driver, and these are sealed in a single package.

[0176] With this configuration, the first semiconductor chip 410 and the second semiconductor chip 420 can both be fabricated using a general low-voltage process (withstand voltage of several volts to several tens of volts), eliminating the need to use a dedicated high-voltage process (withstand voltage of several kV), thereby reducing manufacturing costs.

[0177] Furthermore, both the first semiconductor chip 410 and the second semiconductor chip 420 can be manufactured using existing processes with a proven track record, and there is no need to conduct new reliability tests, which can contribute to shortening development time and reducing development costs.

[0178] Next, the internal configurations of the first semiconductor chip 410, the second semiconductor chip 420, and the third semiconductor chip 430 built into the insulated gate driver 1 will be individually described in detail.

[0179] The first semiconductor chip 410 has a first transmitting unit 411, a second transmitting unit 412, a first receiving unit 413, a second receiving unit 414, a logic unit 415, a first UVLO unit 416, and N-channel MOS field effect transistors Na and Nb.

[0180] The second semiconductor chip 420 has a third receiving unit 421, a fourth receiving unit 422, a third transmitting unit 423, a fourth transmitting unit 424, a logic unit 425, a driver unit 426, a second UVLO unit 427, a P-channel MOS field effect transistor P1, N-channel MOS field effect transistors N1 to N3, and an SR flip-flop FF.

[0181] The third semiconductor chip 430 includes a first transformer 431, a second transformer 432, a third transformer 433, and a fourth transformer 434.

[0182] The first transmitting unit 411 transmits the switch control signal S 1 input from the logic unit 415 to the third receiving unit 421 via the first transformer 431 .

[0183] The second transmitting unit 412 transmits the switch control signal S2 input from the logic unit 415 to the fourth receiving unit 422 via the second transformer 432.

[0184] The first receiver 413 receives the internal fault signal S3 input from the third transmitter 423 via the third transformer 433 and transmits it to the logic unit 415.

[0185] The second receiving unit 414 receives the internal fault signal S4 input from the fourth transmitting unit 424 via the fourth transformer 434 and transmits it to the logic unit 415.

[0186] The logic unit 415 exchanges various signals (input signal IN and external fault signals FLT1 and FLT2) with the ECU2, and also exchanges various signals (S1 to S4) with the second semiconductor chip 420 using the first transmitting unit 411, the second transmitting unit 412, the first receiving unit 413, and the second receiving unit 414.

[0187] When the input signal IN is at a high level, the logic unit 415 generates a pulse in the switch control signal S1 so as to set the output signal OUT to a high level, and conversely, when the input signal IN is at a low level, the logic unit 415 generates a pulse in the switch control signal S2 so as to set the output signal OUT to a low level. For example, the logic unit 415 detects a positive edge (a rising edge from a low level to a high level) of the input signal IN to generate a pulse in the switch control signal S1, and detects a negative edge (a falling edge from a high level to a low level) of the input signal IN to generate a pulse in the switch control signal S2.

[0188] Furthermore, the logic unit 415 switches the logic levels of the external fault signals FLT1 and FLT2 by turning on / off the transistors Na and Nb according to the state of the isolated gate driver 1.

[0189] The drains of the transistors Na and Nb are connected to the FLT1 terminal and the FLT2 terminal, respectively. The sources of the transistors Na and Nb are both connected to the ground terminal (GND1 terminal) of the primary circuit system. The gates of the transistors Na and Nb are both connected to the logic unit 415.

[0190] For example, when no abnormality occurs in the isolated gate driver 1, both transistors Na and Nb are turned off, and both terminals FLT1 and FLT2 are in a high-impedance state (= pulled-up state by resistor R1). At this time, both external fault signals FLT1 and FLT2 are at a high level (= VCC1). On the other hand, when some abnormality occurs in the isolated gate driver 1, at least one of transistors Na and Nb is turned on, and at least one of terminals FLT1 and FLT2 is shorted to GND. At this time, at least one of external fault signals FLT1 and FLT2 is at a low level (= GND1). With this configuration, the ECU 2 can grasp the state of the isolated gate driver 1 by monitoring the external fault signals FLT1 and FLT2. This fault output function will be described in detail later.

[0191] The first UVLO unit 416 monitors whether the power supply voltage VCC1 is in a low voltage state, and transmits the monitoring result to the logic unit 415.

[0192] The third receiver 421 receives the switch control signal S1 input from the first transmitter 411 via the first transformer 431 and transfers it to the set input terminal (S) of the SR flip-flop FF.

[0193] The fourth receiver 422 receives the switch control signal S2 input from the second transmitter 412 via the second transformer 432 and transmits it to the reset input terminal (R) of the SR flip-flop FF.

[0194] The third transmitting unit 423 transmits the internal fault signal S3 input from the logic unit 425 to the first receiving unit 413 via the third transformer 433.

[0195] The fourth transmitting unit 424 transmits the internal fault signal S4 input from the logic unit 425 to the second receiving unit 414 via the fourth transformer 434.

[0196] The SR flip-flop FF sets the logic level of the output terminal (Q) to a high level when triggered by a pulse edge of the switch control signal S1 input to its set input terminal (S). The SR flip-flop FF also resets the logic level of the output terminal (Q) to a low level when triggered by a pulse edge of the switch control signal S2 input to its reset input terminal (R). In other words, the output signal sent from the SR flip-flop FF to the logic unit 425 is a pulse signal having the same logic level as the input signal IN input from the ECU 2 to the logic unit 415.

[0197] The logic unit 425 generates a drive signal for the driver unit 426 based on the output signal of the SR flip-flop FF. Furthermore, when the second UVLO unit 427 detects a low voltage abnormality, the logic unit 425 notifies the driver unit 426 directly and also notifies the logic unit 415 by using an internal fault signal S3. With this configuration, even if a low voltage abnormality occurs in the second semiconductor chip 420, the driver unit 426 can quickly perform a protective operation, and the logic unit 415 can output a fault to the ECU 2.

[0198] Although not explicitly shown in the figure, the second semiconductor chip 420 may be provided with an abnormality detection unit (such as an overvoltage detection unit OVP [over voltage protection], a short circuit detection unit SCP [short circuit protection], or an overheat detection unit OTP [over temperature protection]) other than the second UVLO unit 427. In this case, when an abnormality is detected in the second semiconductor chip 420, a protective operation for the driver unit 426 may be performed, as described above, and a fault may be output to the logic unit 415 (and ultimately the ECU 2) using the internal fault signal S3.

[0199] Furthermore, as will be described in detail later, a non-volatile memory for register settings can also be built into the second semiconductor chip 420. In this case, when an error is detected in the data stored in the non-volatile memory, a fault may be output to the logic unit 415 (and therefore the ECU 2) using, for example, an internal fault signal S4 provided separately from the above-mentioned internal fault signal S3.

[0200] The source of the transistor P1 is connected to the VCC2 terminal. The drains of the transistors P1 and N1 are both connected to the OUT terminal. The drain of the transistor N2 is connected to the CLAMP terminal. The drain of the transistor N3 is connected to the PROOUT terminal. The sources of the transistors N1 to N3 are all connected to the GND2 terminal. The gates of the transistors P1 and N1 to N3 are all connected to the driver unit 426.

[0201] The driver unit 426 controls the on / off of the transistors P1 and N1 based on a drive signal input from the logic unit 425, and outputs an output signal OUT from the connection node between the transistors P1 and N1. The output signal OUT is input to the high-side switch SWH via a drive circuit consisting of transistors Q1 and Q2. In the drive circuit, the rise / fall time (slew rate) of the output signal OUT is set so that the output signal OUT has the driving capability of the high-side switch SWH. When the output signal OUT is at a high level, the high-side switch SWH is turned on, and conversely, when the output signal OUT is at a low level, the high-side switch SWH is turned off.

[0202] The driver unit 426 has a function (active mirror clamp function) of turning on the transistor N2 so as to absorb charge (mirror current) from the gate of the high-side switch SWH via the CLAMP terminal when the voltage level (GND2 reference) of the output signal OUT becomes low. With this configuration, when turning off the high-side switch SWH, it is possible to quickly drop the gate potential of the high-side switch SWH to low via the transistor N2, regardless of the slew rate set by the above-mentioned drive circuit.

[0203] Furthermore, when the driver unit 426 determines that a protective operation is necessary based on the abnormality detection signal input from the logic unit 425, it turns off transistors P1, N1, and N2, while turning on transistor N3 (a soft turn-off function). This type of switch control allows charge to be drawn from the gate of the high-side switch SWH via resistor R3 more slowly than during normal operation during protective operation. This configuration prevents momentary interruptions in the motor current during protective operation, thereby suppressing surges caused by the back electromotive force of the motor coil. The fall time during protective operation can be adjusted arbitrarily by appropriately selecting the resistance value of resistor R3.

[0204] The second UVLO unit 427 monitors whether the power supply voltage VCC2 is in a low voltage state, and transmits the monitoring result to the logic unit 425.

[0205] The first transformer 431 is a DC insulating element for transmitting the switch control signal S1 from the first semiconductor chip 410 to the second semiconductor chip 420.

[0206] The second transformer 432 is a DC insulating element for transmitting the switch control signal S2 from the first semiconductor chip 410 to the second semiconductor chip 420.

[0207] The third transformer 433 is a DC insulating element for transmitting the internal fault signal S3 from the second semiconductor chip 420 to the first semiconductor chip 410.

[0208] The fourth transformer 434 is a DC insulating element for transmitting the internal fault signal S4 from the second semiconductor chip 420 to the first semiconductor chip 410.

[0209] In this way, if the first semiconductor chip 410 and the second semiconductor chip 420 are configured to exchange not only the switch control signals S1 and S2 but also the internal fault signals S3 and S4, it becomes possible to appropriately realize not only the on / off control of the high-side switch SWH but also various abnormality detection functions.

[0210] The functions of the insulated gate driver 1 of this configuration example will be explained again.

[0211] [UVLO1 (controller-side low voltage malfunction prevention function)] The isolated gate driver 1 is configured such that the power supply voltage VCC1 is equal to or lower than a predetermined lower threshold voltage V UVLO1L When the power supply voltage VCC1 is equal to or lower than a predetermined upper threshold voltage V, the high-side switch SWH is turned off and the FLT1 terminal is set to low level. UVLO1H When this occurs, normal operation begins and the FLT1 terminal is put into a high impedance state (high level).

[0212] [UVLO2 (Driver side undervoltage malfunction prevention function)] The isolated gate driver 1 is configured to operate when the power supply voltage VCC2 is lower than the predetermined lower threshold voltage V UVLO2L When the power supply voltage VCC2 is equal to or lower than a predetermined upper threshold voltage V, the high-side switch SWH is turned off and the FLT1 terminal is set to low level. UVLO2H When this occurs, normal operation begins and the FLT1 terminal is put into a high impedance state (high level).

[0213] [Soft turn-off during protection operation] When the isolated gate driver 1 forcibly turns off the high-side switch SWH, it sets the PROOUT terminal to low level and the OUT terminal to a high-impedance state. This control makes it possible to turn off the high-side switch SWH slowly. The slew rate when turning off can be adjusted as desired by appropriately selecting the resistance value of the external resistor R3.

[0214] [Active Miller Clamp] The isolated gate driver 1 is configured to drive the high-side switch SWH so that its gate potential is equal to or higher than a predetermined threshold voltage V AMC When the voltage drops below this level, the CLAMP terminal is set to low level. This type of control makes it possible to reliably turn off the high-side switch SWH.

[0215] <Considerations on miniaturization and cost reduction of sets> In the traction inverter 400, if the switching characteristics of a switch element (e.g., a high-side switch SWH) using an IGBT or the like and the operating threshold of an abnormality detection unit (e.g., an overvoltage detection unit OVP, a short-circuit detection unit SCP, or an overheat detection unit OTP) can be optimized, the safety margin against heat generation and destruction of the switch element can be reduced, thereby reducing the chip size of the switch element and realizing a smaller set and lower costs.

[0216] Specifically, it is only necessary to make it possible to arbitrarily adjust the characteristics of the isolated gate driver 1, such as the drive speed (slew rate) of the gate drive unit or the detection threshold or release threshold of the abnormality detection unit, according to the individual differences (manufacturing variations) of the switch elements. Below, we propose a new embodiment to achieve this.

[0217] <Insulated gate driver (embodiment)> 11 is a diagram showing a new embodiment of the isolated gate driver 1. The isolated gate driver 1 of this embodiment has a gate drive unit 441, an abnormality detection / fault control unit 442, a register 443, a control logic unit 444, a non-volatile memory 445, a memory control unit 446, and an interface unit 447. In the following, the description will be given assuming that the above components are basically integrated into a second semiconductor chip 420 (driver chip) of the isolated gate driver 1.

[0218] The gate driver 441 is a circuit corresponding to the driver 426 in FIG. 10, and drives the gate of the high-side switch SWH by generating an output signal OUT based on a drive signal input from a logic unit 425 (not shown in this figure). The gate driver 441 switches between operating and not operating based on an abnormality detection signal input from an abnormality detection / fault control unit 442. The characteristics of the gate driver 441 can be adjusted as desired based on the value stored in a register 443 (adjustment data D1 in this figure). The drive speed of the gate driver 441, i.e., the rise / fall time (slew rate) of the output signal OUT, can be cited as an example of the above characteristics.

[0219] The anomaly detection / fault control unit 442 functions as both an anomaly detection unit (such as an overvoltage detection unit OVP, short circuit detection unit SCP, or overheat detection unit OTP) that detects anomalies other than those in the nonvolatile memory 445 and a fault control unit that sends external fault signals FLT1 and FLT2 to the ECU 2 using the FLT1 and FLT2 terminals. For example, the FLT1 terminal corresponds to a first external terminal for externally outputting the result of an anomaly detection other than that in the nonvolatile memory 445, and the FLT2 terminal corresponds to a second external terminal for externally outputting the result of an error detection in the nonvolatile memory 445. The various characteristics of the anomaly detection / fault control unit 442 can be arbitrarily adjusted based on the value stored in the register 443 (adjustment data D2 in this figure). Examples of the aforementioned various characteristics include a detection threshold or a release threshold for determining whether an abnormal state exists.

[0220] The abnormality detection / fault control unit 442 includes, as its components, a fault signal transmission mechanism (e.g., the first receiving unit 413, the second receiving unit 414, the third transmitting unit 423, the fourth transmitting unit 424, the third transformer 433, and the fourth transformer 434 in FIG. 10) that transmits the abnormality detection result from the second semiconductor chip 420 to the first semiconductor chip 410, and a fault terminal control mechanism (e.g., the logic unit 415, the transistors Na and Nb in FIG. 10) that controls the FLT1 terminal and the FLT2 terminal. Therefore, it can be understood that not all of the components of the fault control unit 442 are integrated into the second semiconductor chip 420, but the components are distributed and integrated into the first semiconductor chip 410, the second semiconductor chip 420, and the third semiconductor chip 430.

[0221] The register 443 volatilely stores the adjustment data (in this figure, adjustment data D1 for the gate drive unit 441 and adjustment data D2 for the abnormality detection / fault control unit 442) read from the nonvolatile memory 445 by the control logic unit 444.

[0222] The control logic unit 444 reads the adjustment data D1 and D2 from the nonvolatile memory 445 and stores them in the register 443 every time the traction inverter 400 is started (=every time the isolated gate driver 1 is powered on). The control logic unit 444 has a function of controlling the abnormality detection / fault control unit 442 so as to maintain the gate drive unit 441 in an inactive state until the adjustment data D1 and D2 read from the nonvolatile memory 445 have been stored in the register 443 (details will be described later). The control logic unit 444 also incorporates an error check and correct (ECC) circuit that detects and corrects errors in the adjustment data D1 and D2 written to the nonvolatile memory 445 (details will be described later).

[0223] The nonvolatile memory 445 stores in a nonvolatile manner adjustment data for the isolated gate driver 1 (in the figure, adjustment data D1 for the gate drive unit 441 and adjustment data D2 for the abnormality detection / fault control unit 442). Note that, although the nonvolatile memory 445 is built into the isolated gate driver 1 in this embodiment, the nonvolatile memory 445 may be attached externally to the isolated gate driver 1 (a specific example will be described later).

[0224] The memory control unit 446 performs address control of the nonvolatile memory 445 when the nonvolatile memory 445 is accessed from outside the insulated gate driver 1 via the interface unit 447 (for example, when reading or writing the adjustment data D1 and D2).

[0225] The interface unit 447 is a front end for accessing the non-volatile memory 445 from outside the insulated gate driver 1. Note that the interface unit 447 may be, for example, a two-wire serial interface conforming to the I2C (inter-integrated circuit) standard that performs bidirectional serial communication using a data signal SDA and a clock signal SCL.

[0226] In the insulated gate driver 1 of this embodiment, by reading out the adjustment data D1 and D2 written in advance in the nonvolatile memory 445 and storing them in the register 443, it is possible to optimize the characteristics of the gate drive unit 441 and the abnormality detection / fault control unit 442 based on the values ​​stored in the register 443. This makes it possible to reduce the margin for heat generation and breakdown of the switch element (for example, the high-side switch SWH), thereby reducing the chip size of the switch element and realizing miniaturization and cost reduction of the set.

[0227] However, if the gate driver 441 operates before the characteristics of the gate driver 441 and the abnormality detection / fault controller 442 have been set, in other words, before the adjustment data D1 and D2 have been stored in the register 443, the switch element will be driven with inappropriate characteristics that do not take into account the individual differences (variations) of the switch element. In such a situation, the reduction in the safety margin may backfire and cause a malfunction in the switch element.

[0228] In particular, since the register 443 is a type of volatile memory, the above series of operations of reading the adjustment data D1 and D2 from the nonvolatile memory 445 and storing them in the register 443 is performed every time the power supply to the traction inverter 400 is turned on. Therefore, the start-up sequence from power-on to the start of gate drive needs to be carefully considered.

[0229] <Startup sequence> 12 is a flowchart showing the start-up sequence of the isolated gate driver 1. When this flow starts, in step #1, the power supply of the set (=traction inverter 400) is started and power supply voltages VCC1 and VCC2 are applied to the isolated gate driver 1.

[0230] In step #2, in response to the rise in the power supply voltages VCC1 and VCC2, the UVLO of the isolated gate driver 1 is released. However, at this point, reading of the adjustment data D1 and D2 from the non-volatile memory 445 has not yet started, and naturally, data storage in the register 443, and hence characteristic adjustment of the gate driver 441 and the abnormality detection / fault control unit 442, have not yet been completed. Therefore, the gate driver 441 is maintained in an inactive state. Note that the gate driver 441 can be set in an inactive state, for example, by maintaining the abnormality detection signal input from the abnormality detection / fault control unit 442 to the gate driver 441 at the logic level at which an abnormality was detected.

[0231] In step # 3 , the control logic unit 444 reads the adjustment data D 1 and D 2 from the nonvolatile memory 445 and stores them in the register 443 .

[0232] In step #4, it is determined whether data storage in register 443 and, consequently, characteristic adjustment of each of gate drive unit 441 and abnormality detection / fault control unit 442 have been completed. If the determination here is YES, the flow proceeds to step #5. On the other hand, if the determination is NO, the flow returns to step #3, and data storage in register 443 continues while gate drive unit 441 is maintained in a non-operating state.

[0233] In step #3, when data storage in the register 443 is completed, the characteristics of the gate driver 441 and the abnormality detection / fault controller 442 are optimized, and the switch element (for example, the high-side switch SWH) can be driven. When the flow proceeds to step #5 after a YES determination in step #4, the insulated gate driver 1 enters a fault release state, and the abnormality detection signal input to the gate driver 441 is switched from the logic level when an abnormality is detected to the logic level when no abnormality is detected.

[0234] As a result, in the following step #6, the non-operating state of the gate driving section 441 is released, and driving control (normal operation) of the switch element according to the input signal IN is started.

[0235] As shown in the above series of flows, the insulated gate driver 1 employs a startup sequence that keeps the gate driver 441 in an inactive state until the various characteristics of the gate driver 441 and the abnormality detection / fault controller 442 have been set, in other words, until the adjustment data D1 and D2 have been stored in the register 443.

[0236] With this configuration, even if the input signal IN is input from the ECU 2 before the characteristics of the gate drive unit 441 and the abnormality detection / fault control unit 442 are set, there is no risk of driving the switch elements with inappropriate characteristics that do not take into account the individual differences (variations) of the switch elements. Therefore, even if the safety margin of the switch elements is reduced, malfunctions in the switch elements are less likely to occur.

[0237] <Example of non-volatile memory implementation> 13 is a diagram showing a first implementation example of the non-volatile memory 445. As described above, the traction inverter 400 of the first implementation example is a type of motor drive device that controls the drive of the motor M, and has three insulated gate drivers 1H(u / v / w), three insulated gate drivers 1L(u / v / w), three high-side switches SWH(u / v / w), three low-side switches SWL(u / v / w), and an ECU 2.

[0238] The motor M is a three-phase motor that is rotationally driven in response to three-phase drive voltages U / V / W input from three-phase (U-phase / V-phase / W-phase) half-bridge output stages.

[0239] The insulated gate drivers 1H(u / v / w) drive the high-side switches SWH(u / v / w) by generating an upper gate drive signal (corresponding to the aforementioned output signal OUT) in response to an upper gate control signal (corresponding to the aforementioned input signal IN) input from the ECU 2 while insulating the ECU 2 from the high-side switches SWH(u / v / w).

[0240] The insulated gate drivers 1L(u / v / w) drive the low-side switches SWL(u / v / w) by generating a low-side gate drive signal in response to a low-side gate control signal input from the ECU2 while insulating the ECU2 from the low-side switches SWL(u / v / w).

[0241] The high-side switches SWH(u / v / w) are upper power transistors that form three-phase (U phase / V phase / W phase) half-bridge output stages, and are externally attached to the switch connection terminals T1 (OUT terminal, CLAMP terminal, PROOUT terminal, GND2 terminal, etc. provided on the second semiconductor chip 420 side in FIG. 10) of the insulated gate driver 1H(u / v / w), and are gate-driven by the insulated gate driver 1H(u / v / w). The high-side switches SWH(u / v / w) are connected between the power system power supply terminal (=application terminal of the first motor drive voltage VD1) and each phase input terminal of the motor M.

[0242] The low-side switches SWL(u / v / w) are lower-side power transistors that form three-phase (U phase / V phase / W phase) half-bridge output stages, and are externally attached to the switch connection terminals T1 (such as the OUT terminal, CLAMP terminal, PROOUT terminal, and GND2 terminal provided on the second semiconductor chip 420 side in FIG. 10) of the insulated gate driver 1L(u / v / w), and are gate-driven by the insulated gate driver 1L(u / v / w). The low-side switches SWL(u / v / w) are connected between the input terminal of each phase of the motor M and the power system ground terminal (= the terminal to which the second motor drive voltage VD2 is applied).

[0243] In this diagram, IGBTs are used as the high-side switches SWH (u / v / w) and low-side switches SWL (u / v / w), but as mentioned above, SiC-MOSFETs or Si-MOSFETs can also be used instead of IGBTs.

[0244] The ECU2 controls the rotational drive of the motor M by driving the high-side switch SWH(u / v / w) and the low-side switch SWL(u / v / w) via the isolated gate drivers 1H(u / v / w) and 1L(u / v / w). The ECU2 also has a function to monitor the FLT1 terminal and the FLT2 terminal of each of the isolated gate drivers 1H(u / v / w) and 1L(u / v / w) and perform various safety controls.

[0245] Here, the aforementioned insulated gate driver 1 can be suitably used as each of the insulated gate drivers 1H(u / v / w) and 1L(u / v / w).

[0246] In the traction inverter 400 of the first implementation example, the insulated gate drivers 1H (u / v / w) and 1L (u / v / w) each have a built-in nonvolatile memory 445 that stores the respective adjustment data D1 and D2. With this configuration, the number of parts required to configure the traction inverter 400 can be reduced.

[0247] 14 is a diagram showing a second implementation example of the non-volatile memory 445. The traction inverter 400 of the second implementation example is based on the first implementation example (FIG. 13), but the non-volatile memory 445 is changed to be external.

[0248] More specifically, in the traction inverter 400 of the second implementation example, a nonvolatile memory 445, into which adjustment data D1 and D2 for the isolated gate drivers 1H(u / v / w) and 1L(u / v / w) are written, is externally attached to the memory connection terminal T2 provided on the secondary side (i.e., the second semiconductor chip 420 side in FIG. 10 ) of each of the isolated gate drivers 1H(u / v / w) and 1L(u / v / w). This configuration allows the adjustment data D1 and D2 written in the secondary-side nonvolatile memory 445 to be used to adjust the characteristics of the gate driver 441 and the abnormality detection / fault controller 442 on the secondary side. This eliminates the need for signal transmission from the primary side to the secondary side, i.e., from the first semiconductor chip 410 to the second semiconductor chip 420 via the third semiconductor chip 430. This simplifies the circuit configuration of the isolated gate driver 1.

[0249] 15 is a diagram showing a third implementation example of the non-volatile memory 445. The traction inverter 400 of the third implementation example is based on the first implementation example (FIG. 13), but the non-volatile memory 445 is changed to be external.

[0250] More specifically, in the traction inverter 400 of the third implementation example, a single nonvolatile memory 445, into which adjustment data D1 and D2 for the isolated gate drivers 1H(u / v / w) and 1L(u / v / w) are written, is externally connected to the memory connection terminal T2 provided on the primary side (i.e., the first semiconductor chip 410 side in FIG. 10 ) of each of the isolated gate drivers 1H(u / v / w). This configuration makes it possible to reduce the number of external nonvolatile memories 445. However, it should be noted that the isolated gate driver 1 requires signal transmission from the primary side to the secondary side, i.e., signal transmission from the first semiconductor chip 410 to the second semiconductor chip 420 via the third semiconductor chip 430.

[0251] <Considerations on Degradation of Non-Volatile Memory> Incidentally, there is a concern that the adjustment data D1 and D2 written to the nonvolatile memory 445 may be lost due to aging or the like. In this case, multiple bits are not suddenly lost at once, but rather one bit at a time. To prepare for this, it is desirable to introduce an error detection and correction circuit ECC into the control logic unit 444 (or the nonvolatile memory 445) to detect and correct errors in the adjustment data D1 and D2 written to the nonvolatile memory 445.

[0252] When the error detection and correction circuit ECC is installed, even if a single-bit error occurs in the adjustment data D1 and D2 written to the non-volatile memory 445, it can be detected and corrected. Therefore, it is possible to correctly adjust the characteristics of the isolated gate driver 1 and continue running the electric vehicle without any problems. On the other hand, if an error of two or more bits occurs in the adjustment data D1 and D2 written to the non-volatile memory 445, it cannot be corrected even with the error detection and correction circuit ECC. As a result, it becomes impossible to correctly adjust the characteristics of the isolated gate driver 1, and the electric vehicle cannot be run safely.

[0253] In view of the above considerations, it is desirable to switch the fault output of the isolated gate driver 1 depending on whether the adjustment data D1 and D2 contain an error of only one bit or two or more bits. Below, we propose an example of the operation of an appropriate fault output.

[0254] <Fault output> FIG. 16 is a table showing a first operation example of the fault output, which shows the error detection result of the nonvolatile memory 445, the operation status of the gate driver 441, and the output status of each of the FLT1 terminal and the FLT2 terminal.

[0255] The error detection and correction circuit ECC mainly detects errors in the nonvolatile memory 445. On the other hand, the operation enable / disable switching of the gate driver 441 and the fault output using the FLT1 terminal and the FLT2 terminal are mainly performed by the abnormality detection / fault controller 442.

[0256] As shown in the first line, when the adjustment data D1 and D2 written to the nonvolatile memory 445 are normal, normal operation is performed by the gate driver 441. At this time, the FLT1 terminal and the FLT2 terminal are both set to a high impedance state, and therefore the external fault signals FLT1 and FLT2 transmitted to the ECU 2 are set to a high level (=normal logic level) by being pulled up by the resistors R1 and R2.

[0257] As shown in the second line, when a one-bit error is detected in the adjustment data D1 and D2 written to the non-volatile memory 445, the FLT2 terminal is set to low level (= the logic level at the time of error detection), and normal operation of the gate driver 441 continues. Note that the FLT1 terminal remains in a high impedance state. In this way, if it is a one-bit error, it can be detected and corrected by the error detection and correction circuit ECC, so that normal operation of the gate driver 441, and ultimately, the running of the electric vehicle, can continue without hindrance.

[0258] Even if a single-bit error is detected in the adjustment data D1 and D2, the characteristics of the isolated gate driver 1 can be adjusted correctly, so it is not necessarily necessary to output a fault to the ECU 2 (i.e., outputting the external fault signal FLT2 at a low level). However, if the above fault output is issued as a sign that an error will soon occur in another bit, it becomes possible to notify the driver of the electric vehicle of the possibility of a malfunction in advance. This makes it possible to avoid a situation in which the electric vehicle suddenly stops moving without warning when a double-bit error occurs.

[0259] As shown in the third line, when an error of two or more bits is detected in the adjustment data D1 and D2 written to the non-volatile memory 445, both the FLT1 terminal and the FLT2 terminal are set to low level and the gate driver 441 is forcibly stopped. In this way, when an error of two or more bits occurs, the adjustment data D1 and D2 cannot be corrected, and it becomes impossible to correctly adjust the characteristics of the isolated gate driver 1. For this reason, it is most important to ensure the safety of the electric vehicle by forcibly stopping the gate driver 441.

[0260] Furthermore, by lowering the external fault signal FLT1 to a low level, it is possible to quickly notify the ECU 2 that some serious abnormality has occurred in the isolated gate driver 1 or the high-side switch SWH (in this case, a forced stop of the gate driver 441 due to an error of two or more bits occurring in the non-volatile memory 445).

[0261] FIG. 17 is a table showing a second example of the operation of the fault output, and like FIG. 16 above, it shows the error detection results of the non-volatile memory 445, the operation status of the gate driving unit 441, and the output status of the FLT1 terminal and the FLT2 terminal.

[0262] The second operation example in this figure is basically the same as the first operation example (FIG. 16) described above, and differs only in that the FLT2 terminal is set to a high impedance state when an error of two or more bits is detected in the adjustment data D1 and D2 written to the non-volatile memory 445. In this way, when an error of two or more bits is detected, a fault signal is output to the ECU 2 using the FLT1 terminal, and the output state of the FLT2 terminal does not matter.

[0263] FIG. 18 is a table showing a third example of the operation of the fault output, which shows the error detection results of the non-volatile memory 445, the abnormality detection results (UVLO, OVP, SCP, OTP, etc.) other than the non-volatile memory 445, the operation status of the gate driving unit 441, and the output status of the FLT1 terminal and the FLT2 terminal.

[0264] The error detection and correction circuit ECC is mainly used to detect errors in the nonvolatile memory 445. On the other hand, the abnormality detection / fault control unit 442 is mainly used to detect abnormalities other than those in the nonvolatile memory 445 (UVLO, OVP, SCP, OTP, etc.), switch the operation of the gate drive unit 441, and output a fault using the FLT1 terminal and the FLT2 terminal.

[0265] As shown in the first line, when the adjustment data D1 and D2 written in the nonvolatile memory 445 are normal and no abnormality other than that of the nonvolatile memory 445 has been detected, the gate drive unit 441 performs normal operation. At this time, the FLT1 terminal and the FLT2 terminal are both set to a high impedance state, and therefore the external fault signals FLT1 and FLT2 transmitted to the ECU 2 are set to a high level (=normal logical level) by being pulled up by the resistors R1 and R2.

[0266] As shown in the second line, if the adjustment data D1 and D2 written to the non-volatile memory 445 are normal, but an abnormality other than that of the non-volatile memory 445 is detected, the FLT1 terminal is set to low level (= the output state when an abnormality is detected) regardless of the error detection result, and the gate driver 441 is forcibly stopped. This ensures the safety of the electric vehicle while quickly notifying the ECU 2 that some serious abnormality (UVLO, OVP, SCP, OTP, etc.) has occurred in the isolated gate driver 1 or the high-side switch SWH. Note that since no error has occurred in the adjustment data D1 and D2, the FLT2 terminal remains in a high impedance state.

[0267] As shown in the third line, when a one-bit error is detected in the adjustment data D1 and D2 written to the non-volatile memory 445 and no abnormality other than that of the non-volatile memory 445 is detected, the FLT2 terminal is set to low level (= the logic level when an error is detected) and the gate driver 441 continues normal operation. The FLT1 terminal remains in a high impedance state. As such, if it is a one-bit error, it can be detected and corrected by the error detection and correction circuit ECC, so that the gate driver 441 can continue normal operation, and ultimately the electric vehicle can continue running without any problems. In addition, because the FLT2 terminal is set to low level, it is also possible to notify the driver of the electric vehicle of a possible malfunction.

[0268] As shown in the fourth line, when a one-bit error is detected in the adjustment data D1 and D2 written to the non-volatile memory 445 and an abnormality is also detected other than in the non-volatile memory 445, both the FLT1 terminal and the FLT2 terminal are set to low level and the gate driver 441 is forcibly stopped. In this way, when an abnormality other than in the non-volatile memory 445 is detected, as in the first line above, the FLT1 terminal is set to low level (= the output state when an abnormality is detected) and the gate driver 441 is forcibly stopped regardless of the result of the error detection. Therefore, it is possible to ensure the safety of the electric vehicle and quickly notify the ECU 2 that some serious abnormality (UVLO, OVP, SCP, OTP, etc.) has occurred in the isolated gate driver 1 or the high-side switch SWH.

[0269] As shown in the fifth line, when an error of two or more bits is detected in the adjustment data D1 and D2 written to the non-volatile memory 445, both the FLT1 terminal and the FLT2 terminal are set to low level and the gate driver 441 is forcibly stopped, regardless of the abnormality detection result other than that of the non-volatile memory 445. In this way, when an error of two or more bits occurs, the adjustment data D1 and D2 cannot be corrected, and therefore it becomes impossible to correctly adjust the characteristics of the isolated gate driver 1. For this reason, it is most important to ensure the safety of the electric vehicle by forcibly stopping the gate driver 441.

[0270] Furthermore, by causing the external fault signal FLT1 to fall to low level, it is possible to quickly notify the ECU 2 that some serious abnormality (here, forced stop of the gate driver 441 due to an error of two or more bits occurring in the non-volatile memory 445) has occurred in the isolated gate driver 1 or the high-side switch SWH. In these respects, this is no different from the first operation example (FIG. 16) and the second operation example (FIG. 17) described above.

[0271] FIG. 19 is a table showing a fourth example of the operation of the fault output, and like FIG. 18 above, it shows the error detection results of the non-volatile memory 445, the abnormality detection results (UVLO, OVP, SCP, OTP, etc.) other than the non-volatile memory 445, the operation status of the gate drive unit 441, and the output status of the FLT1 terminal and the FLT2 terminal.

[0272] The fourth operation example in this figure is basically the same as the third operation example (FIG. 18) described above, and differs only in that the FLT2 terminal is set to a high impedance state when an error of two or more bits is detected in the adjustment data D1 and D2 written to the non-volatile memory 445. In this way, when an error of two or more bits is detected, a fault signal is output to the ECU 2 using the FLT1 terminal, so the output state of the FLT2 terminal does not matter.

[0273] <Sharing of fault signal output terminals> In the first to fourth operation examples of the fault output explained above (FIGS. 16 to 19), when a one-bit error is detected in the adjustment data D1 and D2 written to the nonvolatile memory 445, a fault output (=failure sign notification) is performed using the FLT2 terminal, and when an error of two or more bits is detected, a fault output (=failure notification) is performed using the FLT1 terminal, but it is also possible to perform both of the above fault outputs using only the FLT2 terminal without using the FLT1 terminal. Below, an example of sharing the FLT2 terminal will be proposed with reference to the drawings.

[0274] 20 is a diagram showing a first example of sharing of the fault signal output terminal (here, the FLT2 terminal). As shown in this diagram, the fault control unit 442 may set the FLT2 terminal to a high level (e.g., VCC1) when the adjustment data D1 and D2 are normal, set the FLT2 terminal to a middle level (e.g., VCC1 / 2) when a one-bit error is detected in the adjustment data D1 and D2, and set the FLT2 terminal to a low level (e.g., GND1) when an error of two or more bits is detected in the adjustment data D1 and D2. With this configuration, the result of error detection can be determined from the voltage level of the FLT2 terminal.

[0275] 21 is a diagram showing a second example of sharing the fault signal output terminal (here, the FLT2 terminal). As shown in this diagram, the fault control unit 442 may fix the FLT2 terminal to a high level when the adjustment data D1 and D2 are normal, pulse-drive the FLT2 terminal between a high level and a low level when a one-bit error is detected in the adjustment data D1 and D2, and fix the FLT2 terminal to a low level when an error of two or more bits is detected in the adjustment data D1 and D2. With this configuration, the result of error detection can be determined from the logic level of the FLT2 terminal and whether or not it is pulse-driven.

[0276] 22 is a diagram showing a third example of sharing of the fault signal output terminal (here, the FLT2 terminal). As shown in this diagram, the fault control unit 442 may fix the FLT2 terminal to a high level when the adjustment data D1 and D2 are normal, pulse-drive the FLT2 terminal at a pulse frequency f1 when a one-bit error is detected in the adjustment data D1 and D2, and pulse-drive the FLT2 terminal at a pulse frequency f2 (e.g., f2>f1) when an error of two or more bits is detected in the adjustment data D1 and D2. With this configuration, the result of error detection can be determined from the logic level and pulse frequency of the FLT2 terminal.

[0277] Although not shown further, the method of sharing the fault signal output terminal is not limited to the above, and the output state of the FLT2 terminal may be arbitrarily switched depending on the error detection result of the adjustment data D1 and D2. For example, various parameters (pulse width, duty, modulation method, etc.) during pulse driving of the FLT2 terminal may be switched.

[0278] <Application to electric vehicles> 23 is a diagram showing the external appearance of an electric vehicle. As explained above, the above-mentioned isolated gate driver 1 and the traction inverter 400 using the same can be suitably used as a motor drive means for the electric vehicle X10.

[0279] <Summary> The various embodiments described above will be generally described below.

[0280] For example, the isolated gate driver disclosed in this specification may have a configuration (first configuration) including a switch connection terminal configured to connect an external switch element, a non-volatile memory in which adjustment data is written, a register configured to store the adjustment data read from the non-volatile memory, a gate drive unit configured to drive the gate of the switch element with various characteristics set based on the stored value of the register, and a control logic unit that maintains the gate drive unit in an inactive state until the adjustment data has been read from the non-volatile memory and stored in the register.

[0281] Furthermore, for example, the isolated gate driver disclosed in this specification may have a configuration (second configuration) including a switch connection terminal configured to connect an external switch element, a memory connection terminal configured to connect an external non-volatile memory in which adjustment data is written, a register configured to store the adjustment data read from the non-volatile memory, a gate drive unit configured to drive the gate of the switch element with various characteristics set based on the stored value of the register, and a control logic unit that maintains the gate drive unit in an inactive state until the adjustment data has been read from the non-volatile memory and stored in the register.

[0282] The insulated gate driver according to the first or second configuration may be configured (third configuration) to further include an abnormality detection unit configured to perform abnormality detection using various characteristics set based on the stored values ​​of the registers.

[0283] Furthermore, in the isolated gate driver having any of the first to third configurations, the control logic unit may be configured (fourth configuration) to start reading the adjustment data from the non-volatile memory after UVLO is released as the power supply voltage applied to the isolated gate driver increases, continue storing data in the register while maintaining the gate drive unit in the non-operating state until data storage in the register is completed, and release the non-operating state of the gate drive unit when data storage in the register is completed.

[0284] Furthermore, the isolated gate driver according to any one of the first, third and fourth configurations may have a configuration (fifth configuration) in which a first semiconductor chip on which circuit elements of a primary circuit system are integrated, a second semiconductor chip on which circuit elements of a secondary circuit system are integrated, and a third semiconductor chip on which insulating elements for transmitting signals while insulating the first semiconductor chip from the second semiconductor chip are integrated are sealed in a single package.

[0285] Furthermore, the isolated gate driver according to the second configuration may have a configuration (sixth configuration) in which a first semiconductor chip on which circuit elements of a primary circuit system are integrated, a second semiconductor chip on which circuit elements of a secondary circuit system are integrated, and a third semiconductor chip on which insulating elements for transmitting signals while insulating the first semiconductor chip from the second semiconductor chip are integrated are sealed in a single package.

[0286] In the isolated gate driver according to the fifth or sixth configuration, the register and the gate drive unit may both be integrated into the second semiconductor chip (seventh configuration).

[0287] Furthermore, for example, the traction inverter disclosed in this specification may have a configuration (eighth configuration) including an insulated gate driver according to the first configuration described above, and a switch element that is externally attached to the switch connection terminal of the insulated gate driver and configured to be gate-driven by the insulated gate driver.

[0288] Furthermore, for example, the traction inverter disclosed in this specification may have a configuration (ninth configuration) including an insulated gate driver according to the second configuration described above, the switch element configured to be externally attached to the switch connection terminal of the insulated gate driver and to be gate-driven by the insulated gate driver, and the non-volatile memory configured to be externally attached to the memory connection terminal of the insulated gate driver and to store the adjustment data for the insulated gate driver.

[0289] Furthermore, for example, the traction inverter disclosed in this specification may have a configuration (tenth configuration) including a plurality of insulated gate drivers according to the sixth configuration described above, a plurality of the switch elements configured to be externally attached to a plurality of the switch connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers and to be gate-driven by the plurality of insulated gate drivers, respectively, and a plurality of the non-volatile memories connected to a plurality of the memory connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers and configured to store the adjustment data for each of the plurality of insulated gate drivers.

[0290] Furthermore, for example, the traction inverter disclosed in this specification may have a configuration (eleventh configuration) including a plurality of insulated gate drivers according to the sixth configuration described above, a plurality of the switch elements configured to be externally attached to a plurality of the switch connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers and to be gate-driven by the plurality of insulated gate drivers, respectively, and the single non-volatile memory commonly connected to a plurality of the memory connection terminals provided on the first semiconductor chip side of each of the plurality of insulated gate drivers and configured to store the adjustment data for each of the plurality of insulated gate drivers.

[0291] Furthermore, for example, the electric vehicle disclosed in this specification may be configured to have a traction inverter according to any one of the eighth to eleventh configurations (twelfth configuration).

[0292] Furthermore, for example, the insulated gate driver disclosed in this specification may have a configuration (a thirteenth configuration) including: a switch connection terminal configured to connect an external switch element; a non-volatile memory in which adjustment data is written; a register configured to store the adjustment data read from the non-volatile memory; a gate drive unit configured to drive the gate of the switch element with various characteristics set based on the stored value of the register; an abnormality detection unit configured to detect an abnormality other than that in the non-volatile memory; an error detection and correction circuit configured to detect and correct an error in the adjustment data written to the non-volatile memory; a first external terminal configured to output a result of the abnormality detection to the outside; a second external terminal configured to output a result of the error detection to the outside; and a fault control unit configured to, when a one-bit error is detected in the adjustment data, set the second external terminal to an output state at the time of error detection and continue normal operation of the gate drive unit, and, when two or more bits of error are detected in the adjustment data, to forcibly stop the gate drive unit (a thirteenth configuration).

[0293] Furthermore, for example, the isolated gate driver disclosed in this specification may have a configuration (fourteenth configuration) including: a switch connection terminal configured to externally connect a switch element; a memory connection terminal configured to externally connect a non-volatile memory to which adjustment data is written; a register configured to store the adjustment data read from the non-volatile memory; a gate drive unit configured to drive the gate of the switch element with various characteristics set based on the stored value of the register; an abnormality detection unit configured to detect an abnormality other than in the non-volatile memory; an error detection and correction circuit configured to detect and correct an error in the adjustment data written to the non-volatile memory; a first external terminal configured to externally output a result of the abnormality detection; a second external terminal configured to externally output the result of the error detection; and a fault control unit configured to, when a one-bit error is detected in the adjustment data, set the second external terminal to an output state at the time of error detection and continue normal operation of the gate drive unit, and to forcibly stop the gate drive unit when two or more errors are detected in the adjustment data.

[0294] In the insulated gate driver having the thirteenth or fourteenth configuration, the fault control unit may be configured (fifteenth configuration) to set the first external terminal to the output state at the time of abnormality detection when an error of two or more bits is detected in the adjustment data, regardless of the result of the abnormality detection.

[0295] Furthermore, in the insulated gate driver according to any one of the thirteenth to fifteenth configurations, the fault control unit may be configured (a sixteenth configuration) to forcibly stop the gate drive unit when an abnormality other than that of the non-volatile memory is detected, after setting the first external terminal to the output state at the time of abnormality detection, regardless of the result of the error detection.

[0296] Alternatively, in the insulated gate driver according to the thirteenth or fourteenth configuration, the fault control unit may be configured to set the second external terminal to a first output state when a one-bit error is detected in the adjustment data, and to set the second external terminal to a second output state different from the first output state when two or more bits of error are detected in the adjustment data (seventeenth configuration).

[0297] Furthermore, the insulated gate driver according to any one of the 13th and 15th to 17th configurations may have a configuration (18th configuration) in which a first semiconductor chip on which circuit elements of a primary circuit system are integrated, a second semiconductor chip on which circuit elements of a secondary circuit system are integrated, and a third semiconductor chip on which insulating elements for transmitting signals while insulating the first semiconductor chip from the second semiconductor chip are integrated are sealed in a single package.

[0298] Furthermore, the isolated gate driver according to the fourteenth configuration may have a configuration (a nineteenth configuration) in which a first semiconductor chip on which circuit elements of a primary circuit system are integrated, a second semiconductor chip on which circuit elements of a secondary circuit system are integrated, and a third semiconductor chip on which insulating elements for transmitting signals while insulating the first semiconductor chip from the second semiconductor chip are integrated are sealed in a single package.

[0299] In the isolated gate driver according to the eighteenth or nineteenth configuration, the register and the gate drive unit may both be integrated into the second semiconductor chip (twentieth configuration).

[0300] Furthermore, for example, the traction inverter disclosed in this specification may have a configuration (21st configuration) including an insulated gate driver according to the 13th configuration and the switch element configured to be externally attached to the switch connection terminal of the insulated gate driver and to be gate-driven by the insulated gate driver.

[0301] Furthermore, for example, the traction inverter disclosed in this specification may have a configuration (22nd configuration) including an insulated gate driver according to the above-mentioned 14th configuration, the switch element configured to be externally attached to the switch connection terminal of the insulated gate driver and to be gate-driven by the insulated gate driver, and the non-volatile memory configured to be externally attached to the memory connection terminal of the insulated gate driver and to store the adjustment data for the insulated gate driver.

[0302] Furthermore, for example, the traction inverter disclosed in this specification may have a configuration (23rd configuration) including a plurality of insulated gate drivers according to the 19th configuration, a plurality of the switch elements configured to be externally attached to a plurality of the switch connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers and to be gate-driven by the plurality of insulated gate drivers, respectively, and a plurality of the non-volatile memories configured to be externally attached to a plurality of the memory connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers and to store the adjustment data for each of the plurality of insulated gate drivers.

[0303] Furthermore, for example, the traction inverter disclosed in this specification may have a configuration (24th configuration) including a plurality of insulated gate drivers according to the 19th configuration, a plurality of the switch elements configured to be externally attached to a plurality of the switch connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers and to be gate-driven by the plurality of insulated gate drivers, respectively, and the single non-volatile memory commonly connected to a plurality of the memory connection terminals provided on the first semiconductor chip side of each of the plurality of insulated gate drivers and configured to store the adjustment data for each of the plurality of insulated gate drivers.

[0304] Furthermore, for example, the electric vehicle disclosed in this specification may be configured to have a traction inverter according to any one of the twenty-first to twenty-fourth configurations (twenty-fifth configuration).

[0305] <Other variations> In the above embodiment, the traction inverter mounted on an electric vehicle is given as an example of an application of the isolated gate driver, but the application of the isolated gate driver is not limited to this, and it can be widely applied to industrial equipment, medical equipment, etc.

[0306] Furthermore, the implementation of non-volatile memory and the related novel startup sequence and fault output are not limited to isolated gate drivers, but can be widely applied to signal transmission devices in general, regardless of whether they are isolated or non-isolated.

[0307] As described above, in addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0308] 1, 1H(u / v / w), 1L(u / v / w) isolated gate driver 2 ECU 5. Semiconductor Devices 11, 11A~11F Low potential terminal 12, 12A~12F high potential terminal 21, 21A~21D Transformer 22 Low potential coil (primary coil) 23 High potential coil (secondary coil) 24 1st medial end 25 First outer end 26 1st spiral part 27 Second medial end 28 Second outer end 29 Second spiral part 31 1st low potential wiring 32 2nd low potential wiring 33 1st high potential wiring 34 2nd high potential wiring 41 Semiconductor chips 42 First main surface 43 Second main surface 44A~44D Chip sidewall 45 First Functional Device 51 Insulating layer 52 Main insulating surface 53A~53D Insulated sidewall 55 Bottom insulating layer 56 Top insulating layer 57 Interlayer insulation layer 58 First insulating layer 59 Second insulating layer 60 Second Function Device 61 Sealed conductor 62 Device Area 63 Outer area 64 Seal plug conductor 65 Seal via conductor 66 1st medial area 67 Second medial area 71 Through-wiring 72 Low-potential connection wiring 73 Lead Wiring 74 First connecting plug electrode 75 Second connecting plug electrode 76 Pad plug electrode 77 PCB plug electrode 78 1st electrode layer 79 Second electrode layer 80 Wiring plug electrode 81 High-potential connection wiring 82 Pad plug electrode 85 Dummy Pattern 86 High-potential dummy pattern 87 First high potential dummy pattern 88 Second high potential dummy pattern 89 First area 90 Second area 91 Third area 92 First connection part 93 First Pattern 94 Second Pattern 95 Third Pattern 96 First Outer Line 97 Second Outer Line 98 First Intermediate Line 99 First connecting line 100 slits 130 Separation structure 140 Inorganic insulating layer 141 First inorganic insulating layer 142 Second inorganic insulating layer 143 Low potential pad opening 144 High potential pad opening 145 Organic insulating layer 146 Part 1 147 Part 2 148 Low potential terminal opening 149 High potential terminal opening 200 Signal Transmission Device 200p primary circuit system 200s secondary circuit system 210 Controller Chip (1st Chip) 211 Pulse transmitting circuit (pulse generator) 212, 213 buffer 220 Driver Chip (Second Chip) 221, 222 buffer 223 Pulse receiving circuit (RS flip-flop) 224 Driver 230 Transformer Chip (3rd Chip) 230a 1st wiring layer (lower layer) 230b 2nd wiring layer (upper layer) 231, 232 transformer 231p, 232p Primary coil 231s, 232s Secondary coil 300 Trans Chip 301 1st transformer 302 2nd transformer 303 Third Transformer 304 4th Transformer 305 1st Guard Ring 306 Second Guard Ring 400 Traction Inverter 410 First semiconductor chip (controller chip) 411 First Transmission Unit 412 Second Transmission Unit 413 First Receiving Unit 414 Second Receiving Unit 415 Logic Section 416 1st UVLO Department 420 Second semiconductor chip (driver chip) 421 Third Receiving Unit 422 4th Receiving Unit 423 Third Transmission Unit 424 4th Transmission Unit 425 Logic Section 426 Driver section 427 2nd UVLO Department 430 Third Semiconductor Chip (Transchip) 431 1st Trans 432 2nd Transformer 433 3rd Trans 434 4th Trans 441 Gate driver 442 Abnormality detection / fault control section 443 Register 444 Control Logic Section 445 Non-volatile memory 446 Memory Control Unit 447 Interface Section a1 to a8 pads (corresponding to the first current supply pads) b1~b8 pads (corresponding to the first voltage measurement pads) c1 to c4 pads (corresponding to the second current supply pads) d1~d4 pads (corresponding to the second voltage measurement pads) e1, e2 pads C1, C2 capacitors E1, E2 DC voltage source ECC Error Detection and Correction Circuit FF SR flip-flop L1p, L2p Primary coil L1s, L2s, L3s, L4s Secondary coil Medium motor Na, Nb, N1 to N3 N-channel MOS field effect transistors P1 P-channel MOS field effect transistor Q1 npn bipolar transistor Q2 pnp bipolar transistor R1~R3 ​​resistance SWH, SWH(u / v / w) High-side switch SWL, SWL(u / v / w) Low-side switch T1 switch connection terminal T2 memory connection terminal T21, T22, T23, T24, T25, T26 external terminals X 1st direction X10 electric car X21, X22, X23 Internal terminals Y Second direction Y21, Y22, Y23 wiring Z normal direction Z21, Z22, Z23 vias

Claims

1. a switch connection terminal configured to externally connect a switch element; a non-volatile memory in which adjustment data is written; a register configured to store the adjustment data read from the non-volatile memory; a gate driver configured to drive the gate of the switch element with various characteristics set based on the stored value of the register; an abnormality detection unit configured to detect an abnormality other than that of the nonvolatile memory; an error detection and correction circuit configured to perform error detection and error correction on the adjustment data written to the nonvolatile memory; a first external terminal configured to output a result of the abnormality detection to an external device; a second external terminal configured to output the result of the error detection to an external device; a fault control unit configured to, when a one-bit error is detected in the adjustment data, set the second external terminal to an output state at the time of error detection and continue normal operation of the gate driving unit, and, when two or more bits of error are detected in the adjustment data, forcibly stop the gate driving unit; 1. An isolated gate driver having:

2. a switch connection terminal configured to externally connect a switch element; a memory connection terminal configured to externally connect a nonvolatile memory in which adjustment data is written; a register configured to store the adjustment data read from the non-volatile memory; a gate driver configured to drive the gate of the switch element with various characteristics set based on the stored value of the register; an abnormality detection unit configured to detect an abnormality other than that of the nonvolatile memory; an error detection and correction circuit configured to perform error detection and error correction on the adjustment data written to the nonvolatile memory; a first external terminal configured to output a result of the abnormality detection to an external device; a second external terminal configured to output the result of the error detection to an external device; a fault control unit configured to, when a one-bit error is detected in the adjustment data, set the second external terminal to an output state at the time of error detection and continue normal operation of the gate driving unit, and, when two or more bits of error are detected in the adjustment data, forcibly stop the gate driving unit; 1. An isolated gate driver having:

3. 3. The insulated gate driver according to claim 1, wherein the fault control unit sets the first external terminal to an output state at the time of abnormality detection when an error of two or more bits is detected in the adjustment data, regardless of a result of the abnormality detection.

4. 4. The insulated gate driver according to claim 1, wherein when an abnormality other than that in the non-volatile memory is detected, the fault control unit forcibly stops the gate drive unit after setting the first external terminal to an output state at the time of abnormality detection, regardless of the result of the error detection.

5. 3. The insulated gate driver according to claim 1, wherein the fault control unit sets the second external terminal to a first output state when a one-bit error is detected in the adjustment data, and sets the second external terminal to a second output state different from the first output state when two or more bits of error are detected in the adjustment data.

6. a first semiconductor chip on which circuit elements of a primary circuit system are integrated; a second semiconductor chip on which circuit elements of a secondary circuit system are integrated; a third semiconductor chip on which an insulating element for transmitting signals while insulating the first semiconductor chip from the second semiconductor chip is integrated; are sealed in a single package, the non-volatile memory, the register, the gate driver, and the error detection and correction circuit are integrated on the second semiconductor chip; the abnormality detection unit and the fault control unit are distributed and integrated in the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip; the first external terminal and the second external terminal are provided on the first semiconductor chip side; The insulated gate driver according to claim 1 , wherein the switch connection terminal is provided on the second semiconductor chip side.

7. a first semiconductor chip on which circuit elements of a primary circuit system are integrated; a second semiconductor chip on which circuit elements of a secondary circuit system are integrated; a third semiconductor chip on which an insulating element for transmitting signals while insulating the first semiconductor chip from the second semiconductor chip is integrated; are sealed in a single package, the register, the gate driver, and the error detection and correction circuit are integrated on the second semiconductor chip; the abnormality detection unit and the fault control unit are distributed and integrated in the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip; the first external terminal and the second external terminal are provided on the first semiconductor chip side; The insulated gate driver according to claim 2 , wherein the switch connection terminals and the memory connection terminals are provided on the second semiconductor chip side.

8. an insulated gate driver according to claim 1; the switch element configured to be externally connected to the switch connection terminal of the insulated gate driver and gate-driven by the insulated gate driver; A traction inverter having:

9. an insulated gate driver according to claim 2; the switch element configured to be externally connected to the switch connection terminal of the insulated gate driver and gate-driven by the insulated gate driver; the nonvolatile memory configured to be externally attached to the memory connection terminal of the insulated gate driver and to store the adjustment data of the insulated gate driver; A traction inverter having:

10. a plurality of insulated gate drivers according to claim 7; a plurality of switch elements that are externally connected to a plurality of switch connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers and are gate-driven by the plurality of insulated gate drivers, respectively; a plurality of nonvolatile memories externally attached to a plurality of memory connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers, respectively, and configured to store the adjustment data for each of the plurality of insulated gate drivers; A traction inverter having

11. a plurality of insulated gate drivers according to claim 7; a plurality of switch elements that are externally connected to a plurality of switch connection terminals provided on the second semiconductor chip side of each of the plurality of insulated gate drivers and are gate-driven by the plurality of insulated gate drivers, respectively; a single nonvolatile memory commonly connected to a plurality of memory connection terminals provided on the first semiconductor chip side of each of the plurality of insulated gate drivers, the single nonvolatile memory being configured to store the adjustment data for each of the plurality of insulated gate drivers; A traction inverter having:

12. An electric vehicle comprising the traction inverter according to any one of claims 8 to 11.

Images