Photoelectric conversion device and camera

Abstract

To improve performance of a photoelectric conversion device.SOLUTION: A photoelectric conversion device has a pixel region including a plurality of photoelectric conversion elements. The photoelectric conversion device includes a first surface and a second surface opposite to the first surface, and comprises a semiconductor layer in which the plurality of photoelectric conversion elements is arranged between the first surface and the second surface. A virtual flat surface along the second surface between the first surface and the second surface is set to a third surface. The pixel region includes: an element isolation part constructed by an insulator arranged on the side closer to the first surface than the third surface; and first and second separation parts constructed by a groove provided to the semiconductor layer so as to pass the third surface. The first separation part is overlapped to the element isolation part in a normal direction to the third surface. An end of the first surface of the second separation part is positioned closer to the side of the second surface than an end of the first surface of the first separation part.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] The creation of grooves in the semiconductor layer of photoelectric conversion devices such as CMOS image sensors used in cameras is being considered. The grooves form isolation barriers that act as barriers against light and electric charges, improving sensitivity and suppressing color mixing, thereby improving the performance of the photoelectric conversion device.

[0003] Patent document 1 describes the provision of a trench (105) extending from the back surface (101b) of a substrate (101) on which a photoelectric conversion element (102) is provided to an STI (111) on the front surface (101a) of the substrate (101). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent Application Publication No. 2013 / 0069190 Summary of the Invention [Problem to be solved by the invention]

[0005] Although Patent Document 1 does not describe the planar layout of the trenches, depending on the layout of the trenches, the improvement in performance of the photoelectric conversion device may not be sufficient, or the performance of the photoelectric conversion device may actually be reduced. This can be attributed to, for example, limitations on sensitivity improvement or increased noise depending on the location of the trenches.

[0006] SUMMARY OF THE INVENTION It is therefore an object of the present invention to improve the performance of a photoelectric conversion device. [Means for solving the problem]

[0007] An aspect of the present invention is a photoelectric conversion device having a pixel region including a plurality of photoelectric conversion elements, the photoelectric conversion device having a first surface and a second surface opposite to the first surface, the plurality of photoelectric conversion elements being arranged between the first surface and the second surface. a MOS transistor having a gate electrode disposed on the first surface side; a first semiconductor region of a first conductivity type which is a source region or a drain region of the MOS transistor; a well region of the pixel region; and a well contact disposed on the first surface for controlling the potential of the well region. Semiconductor layer and , a lattice-shaped groove that is arranged in the pixel region of the semiconductor layer, extends from the second surface toward the first surface, and is arranged along a first direction and a second direction intersecting the first direction in a plan view with respect to the first surface; in a cross-sectional view with respect to a cross section along the first direction, the lattice-shaped groove has a first region and a second region, the semiconductor layer extends between the first region and the first surface, the second region has a length from the second surface longer than that of the first region, a part of the first region overlaps with the well contact in a plan view with respect to the first surface, the well region is located between an end of the first region on the first surface side and the well contact in the cross-sectional view, and a plurality of the gate electrodes are arranged between two of the plurality of second regions that are closest to each other in a plan view with respect to the first surface. It is characterized by: [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a photoelectric conversion device with improved performance. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a schematic diagram illustrating a photoelectric conversion device. [Figure 2] FIG. 1 is a schematic diagram illustrating a photoelectric conversion device. [Figure 3] FIG. 1 is a schematic diagram illustrating a photoelectric conversion device. [Figure 4] FIG. 1 is a schematic diagram illustrating a photoelectric conversion device. [Figure 5] 5A to 5C are schematic diagrams illustrating a method for manufacturing a photoelectric conversion device. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description and drawings, common reference numerals are used to designate common components across multiple drawings. Therefore, common configurations will be described by mutually referring to multiple drawings, and descriptions of configurations with common reference numerals will be omitted as appropriate.

[0011] Fig. 1(a) is a cross-sectional view showing an embodiment of a back-illuminated imaging device as an example of a photoelectric conversion device, and Fig. 1(b) is an enlarged view of a semiconductor layer of the photoelectric conversion device and its surrounding structure.

[0012] The photoelectric conversion device 1000 has a pixel region PX including a plurality of photoelectric conversion elements PD. As will be described later, the pixel region PX further includes an isolation section that electrically or optically isolates various elements. The pixel region PX may also include a color filter array or a microlens array. In addition to the pixel region, the photoelectric conversion device 1000 also includes a peripheral region (not shown). The peripheral region is provided with a drive circuit for driving the circuit (pixel circuit) of the pixel region PX and a signal processing circuit for processing signals from the pixel circuit. The configuration of the pixel region PX of the photoelectric conversion device 1000 will be described in detail below.

[0013] The photoelectric conversion device 1000 includes a semiconductor layer 100 having a front surface 1 and a back surface 2 opposite to the front surface 1. The photoelectric conversion elements PD in the pixel regions PX are arranged in the semiconductor layer 100. The photoelectric conversion elements PD are arranged between the front surface 1 and the back surface 2. The semiconductor layer 100 is, for example, a single-crystal silicon layer, but is not limited to a single-crystal silicon layer as long as it is a semiconductor layer capable of photoelectric conversion. The semiconductor layer 100 has a thickness T of approximately 1 to 10 μm (see FIG. 1(b)). The thickness T of the semiconductor layer 100 corresponds to the distance between the front surface 1 and the back surface 2.

[0014] The photovoltaic conversion device 1000 is arranged on the side of the surface 1 and includes an element isolation region 10 configured by a groove 11 in the semiconductor layer 100 and an insulator 12 in the groove 11. The element isolation region 10 may have an STI structure or a LOCOS structure. The groove 11 of the element isolation region 10 has a depth D1 of about 100 to 1000 nm from the surface 1 (see FIG. 1(b)). The insulator 12 configuring the element isolation region 10 is made of, for example, silicon oxide.

[0015] The photoelectric conversion device 1000 also includes a pixel separator 20 configured by a trench 21 provided in the semiconductor layer 100. The pixel separator 20 is arranged across the plane 3. The plane 3 is located between the front surface 1 and the back surface 2, closer to the back surface 2 than the element separator 10, and is an imaginary plane that extends along the front surface 1 and / or the back surface 2. The plane 3 can be set between the back surface 2 and an intermediate plane, which is an imaginary plane equidistant from the front surface 1 and the back surface 2, for example, at a position T / 4 from the back surface 2. The plane 3 can be parallel to the back surface 2. A direction perpendicular to the plane 3 is referred to as the normal direction N, and a direction parallel to the plane 3 is referred to as the in-plane direction P. In the normal direction N, the pixel separator 20 extends to both the front surface 1 side and the back surface 2 side with respect to the plane 3. In this example, the trench 21 is provided in the semiconductor layer 100 from the back surface 2 toward the front surface 1. Therefore, the trench 21 has a side surface that is continuous with the back surface 2. However, the grooves 21 may be provided in the semiconductor layer 100 from the front surface 1 side toward the back surface 2, and the grooves 21 do not have to reach the back surface 2. The grooves 21 in the pixel separating section 20 have a depth D2 of about 1 to 10 μm from the front surface 1 (see FIG. 1(b)). Within the plane 3, the semiconductor layer 100 is discontinuous on both sides of the pixel separating section 20. The grooves 21 of the pixel separator 20 may contain a solid 22, a vacuum space, a gas, or both a gas and a solid 22. The solid 22 present in the grooves 21 may be an insulator, a conductor, or a semiconductor. Silicon oxide is typically used as an insulator for the solid 22 present in the grooves 21, but silicon nitride, silicon oxynitride, tantalum oxide, hafnium oxide, titanium oxide, and the like can also be used. Metal or polysilicon is typically used as a conductor for the solid 22 present in the grooves 21, but aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, metal silicide, and the like can also be used. Single-crystal silicon is typically used as a semiconductor for the solid 22 present in the grooves 21, but amorphous silicon may also be used. The conductivity type of the semiconductor for the solid 22 present in the grooves 21 is preferably the opposite conductivity type to the signal charge stored in the photoelectric conversion element described below.

[0016] The photoelectric conversion device 1000 further includes a pixel separating section 30 configured by a groove 31 provided in the semiconductor layer 100. The pixel separating section 30 is also arranged across the plane 3. The groove 31 is provided in the semiconductor layer 100 from the back surface 2 toward the front surface 1. Therefore, the groove 31 has a side surface that is continuous with the back surface 2. The groove 31 in the pixel separating section 30 has a depth D3 of approximately 1 to 10 μm from the front surface 1 (see FIG. 1(b)). Within the plane 3, the semiconductor layer 100 is discontinuous with the pixel separating section 30 sandwiched between them. A solid 32 may exist within the groove 31 in the pixel separating section 30, or a vacuum space or gas may exist, or both a gas and a solid 32 may be disposed. The solid 32 existing within the groove 31 is similar to the solid 32 existing within the groove 31 in the pixel separating section 20, and therefore a description thereof will be omitted.

[0017] The pixel isolation section 20 and the pixel isolation section 30 are located at different positions in the in-plane direction P. The pixel isolation section 20 overlaps with the element isolation section 10 in the normal direction N. That is, as shown in FIG. 1( a), the pixel isolation section 20 is disposed below the element isolation section 10. The pixel isolation section 30 is disposed at a different position from the pixel isolation section 20 on the plane 3. The positions of the pixel isolation section 20 and the pixel isolation section 30 in the in-plane direction P will be described in detail later.

[0018] The pixel separation part 20 and the pixel separation part 30 have different depths in the normal direction N. The pixel separation part 30 is arranged shallower with respect to the back surface 2 than the pixel separation part 20. The pixel separation part 20 and the pixel separation part 30 will be described using FIG. 1(b). The depth D2 from the back surface 2 of the pixel separation part 20 is larger than the depth D3 from the back surface 2 of the pixel separation part 30 (D2 > D3). In other words, the end 39 on the side of the surface 1 of the pixel separation part 30 is located on the side of the back surface 2 rather than the end 29 on the side of the surface 1 of the pixel separation part 20. FIG. 1(a) depicts the plane 4. The plane 一4 is a virtual plane along the surface 1 and / or the back surface 2, which is located on the side of the back surface 2 rather than the element separation part 10 and on the side of the surface 1 rather than the plane 3 between the surface 1 and the back surface 2. The plane 一4 can be set at a position, for example, T / 4 from the surface 1 between the intermediate plane, which is a virtual plane equidistant from the surface 1 and the back surface 2, and the surface 1. The pixel separation part 20 is arranged through the plane 4, while the pixel separation part 30 does not pass through the plane 4. The end 29 on the side of the surface 1 of the pixel separation part 20 is located between the element separation part 10 and the plane 4, while the end 39 on the side of the surface 1 of the pixel separation part 30 is located between the plane 3 and the plane 4.

[0019] In this example, the pixel separation part 20 is connected to the element separation part 10. Therefore, the sum of the depth D1 of the element separation part 10 with respect to the surface 1 and the depth D2 of the pixel separation part 20 with respect to the back surface 2 is equal to or larger than the thickness T of the semiconductor layer 一100 (D1 + D2 ≧ T). The depth D3 of the pixel separation part 30 with respect to the back surface 2 is smaller than the thickness T of the semiconductor layer 一100 (D3 < T). The depth of the pixel separation part 30 is preferably about half of the thickness T of the semiconductor layer 一100, for example, 1 / 4 to 3 / 4 (T×1 / 4 ≦ D3 ≦ T×3 / 4).

[0020] A photoelectric conversion element PD is provided between the front surface 1 and the back surface 2 of the semiconductor layer 100. In this example, the photoelectric conversion element PD is a photodiode, but it may also be a photogate or the like. The photoelectric conversion element PD as a photodiode includes an n-type impurity region 40 that functions as an accumulation region for accumulating signal charge (electrons) and a p-type impurity region 50 that forms a pn junction with the impurity region 40. Electrons generated by photoelectric conversion in the p-type impurity region 50 are accumulated in the impurity region 40. The impurity region 40 is preferably located within the plane 3. The impurity region 50 is located between the plane 3 and the back surface 2. While an electron accumulation type photodiode is exemplified here, a hole accumulation type photodiode can also be used. In that case, the conductivity type of the impurity region is simply reversed from that of the electron accumulation type. A conductivity type in which the signal charge is the majority carrier is referred to as the first conductivity type, and a conductivity type in which the signal charge is the minority carrier is referred to as the second conductivity type. If the signal charge is electrons, the n-type in which electrons are the majority carriers is the first conductivity type. The portion of the semiconductor layer 100 regarded as the photoelectric conversion element PD is the portion that generates charges read out as signal charges through photoelectric conversion. Strictly speaking, the portion regarded as the photoelectric conversion element PD is determined by the impurity concentration distribution in the semiconductor layer 100 and a potential profile based on the applied voltage.

[0021] A pixel transistor 90 is provided on the surface 1 side of the semiconductor layer 100. FIG. 1 shows the channel region 70 and gate electrode 80 of the pixel transistor 90. The pixel transistor 90 includes a transfer transistor, an amplification transistor, a reset transistor, and a selection transistor. The transfer transistor transfers the signal charge of the photoelectric conversion element PD to the charge detection region. The charge detection region is composed of a floating diffusion region. The amplification transistor generates a signal based on the charge using a source follower circuit, and has a gate connected to the charge detection region. The reset transistor has a drain connected to the charge detection region, and resets the charge of the photoelectric conversion element PD. The selection transistor selects whether to connect or disconnect the amplification transistor to an output line.

[0022] The semiconductor layer 100 includes a p-type impurity region 60 outside the photoelectric conversion element PD. This p-type impurity region 60 has a higher impurity concentration than the p-type impurity region 50. A portion of the impurity region 60 can function as a potential barrier that suppresses the mixing of charges between pixels. Furthermore, a portion of the impurity region 60 can also function as a potential barrier that suppresses the capture of noise charges generated at the interface between the semiconductor layer 100 and an insulator into the photoelectric conversion element PD. The impurity region 60 also includes a concentrated p-type well contact connected to a conductive member that supplies a fixed potential such as a ground potential. A potential is supplied from the well contact to the impurity region 50 of the photoelectric conversion element PD via the impurity region 60.

[0023] The pixel separating sections 20 and 30 are arranged around the photoelectric conversion element PD. The pixel separating sections 20 and 30 have a configuration that can suppress color mixing between adjacent pixels.

[0024] An insulating film 300 made up of a plurality of wiring layers 310, 320, and 330 and a plurality of interlayer insulating layers surrounding them is provided on the side of the surface 1. The output line made up of the wiring layers is provided so as to output the signal charge generated by the photoelectric conversion element PD as an electric signal via the pixel transistor 90 to the subsequent stage.

[0025] In the back-illuminated imaging device shown in FIG. 1(a), a dielectric film 410, a light-shielding member 420, a color filter array 430, and a microlens array 440 are provided on the back surface 2 side. The dielectric film 410 functions as a protective film (passivation film), a planarizing film, and / or an anti-reflection film. A support substrate 400 is provided on the insulating film 300 on the surface 1 side. An integrated circuit such as a signal processing circuit can also be provided on the support substrate 400. The thickness of the semiconductor layer 100 is about 1 to 10 μm. The thickness of the support substrate is about 50 to 800 μm.

[0026] The color filter array 430 is configured to selectively transmit only light of a specific wavelength. For example, color filters that transmit red, green, and blue wavelengths may be arranged. Pixels that transmit white light may also be mixed in. Each microlens of the microlens array 440, which is arranged corresponding to each pixel, is configured to focus incident light onto the photoelectric conversion element PD.

[0027] As shown in FIG. 1(b), the semiconductor layer 100 has an element region defined by an element isolation portion 10. The element region is divided by its position relative to the element isolation portion 10. The bottom end of the element region in the depth direction coincides with the bottom surface of the element isolation portion 10 at a depth D1. FIG. 2 shows element regions 111, 112, 113, and 114 as element regions included in the semiconductor layer 100. The element region 111 is provided with an n-type impurity region 41 as an accumulation region for a photoelectric conversion element PD1, and the element region 112 is provided with an n-type impurity region 42 as an accumulation region for a photoelectric conversion element PD2. The element region 113 is disposed between the element regions 111 and 112, and is provided with semiconductor elements such as transistors, capacitance elements, and resistance elements. The shape of the element region 113 is different from the shapes of the element regions 111 and 112. This is because the element region 113 is provided with semiconductor elements such as transistors other than the photoelectric conversion element PD. Typically, the area of ​​the element region 113 is smaller than the areas of the element regions 111 and 112 .

[0028] In this example, a pixel transistor is provided as the semiconductor element of the element region 113 described above. A typical pixel transistor can be a MOS transistor. FIG. 2 shows a channel region 70 as an impurity region of the pixel transistor, which is a MOS transistor, but the element region 113 also has a source region and a drain region (not shown). A gate electrode 80 of the pixel transistor is provided on the channel region 70. An n-type impurity region 43 is provided in the element region 114 as an accumulation region of the photoelectric conversion element PD3. Note that the ranges shown as photoelectric conversion elements PD1, PD2, and PD3 in FIG. 1(b) correspond to the n-type impurity region 40, which is the accumulation region of the photoelectric conversion element PD in FIG. 1. Outside the ranges shown as impurity regions 41, 42, and 43 in FIG. 2, there is an impurity region corresponding to the p-type impurity region 50 that constitutes the photoelectric conversion element.

[0029] The element isolation portion 10 includes isolation regions 101, 102, and 103. The isolation region 101 is located between the element region 111 and the element region 113. The isolation region 102 is located between the element region 112 and the element region 113. The isolation region 103 is located between the element region 111 and the element region 114.

[0030] The semiconductor layer 100 has semiconductor regions on the back surface 2 side of the device isolation section 10 that correspond to the distribution of element regions and isolation regions on the front surface 1 side. The semiconductor regions on the back surface 2 side are divided by their positions relative to the isolation regions or element regions of the device isolation section 10. Each semiconductor region is located between the back surface 2 and any isolation region in the device isolation section 10 or any element region in the semiconductor layer 100 in the normal direction N. The semiconductor layer 100 includes semiconductor regions 121, 122, 123, 124, 125, 126, and 127 as such semiconductor regions. The semiconductor region 121 is located between the element region 111 and the back surface 2, the semiconductor region 122 is located between the element region 112 and the back surface 2, and the semiconductor region 123 is located between the element region 113 and the back surface 2. The semiconductor region 127 is located between the element region 114 and the back surface 2. The semiconductor region 124 is located between the isolation region 101 and the back surface 2, the semiconductor region 125 is located between the isolation region 102 and the back surface 2, and the semiconductor region 126 is located between the isolation region 103 and the back surface 2. In the following description, the term "semiconductor region" refers to a position associated with the isolation region and the element region, as described above. Meanwhile, a region in the semiconductor layer 100 that is divided by a predetermined conductivity type, impurity type, and impurity concentration for the operation of a semiconductor element will be described as an "impurity region."

[0031] The pixel separating section 20 overlaps the isolation region 103 in the normal direction N. The pixel separating section 20 is constituted by a groove 21. In the in-plane direction P, the pixel separating section 20 is located between the semiconductor region 121 and the semiconductor region 127. The pixel separating section 20 divides the semiconductor region 126 into multiple parts. As a result, the semiconductor region 126 includes a part 1261 located between the pixel separating section 20 and the semiconductor region 121 and a part 1262 located between the pixel separating section 20 and the semiconductor region 127. In this example, the pixel separating section 20 is connected to the isolation region 103. Also, in this example, the pixel separating section 20 reaches the rear surface 2. In other words, the groove 21 constituting the pixel separating section 20 is continuous with the rear surface 2. When the pixel separating section 20 and the isolation region 103 are spaced apart, part of the semiconductor region 126 is located between the pixel separating section 20 and the isolation region 103. When the pixel isolation section 20 and the rear surface 2 are spaced apart, a part of the semiconductor region 126 is located between the pixel isolation section 20 and the rear surface 2. It is sufficient that at least a part of the pixel isolation section 20 in the in-plane direction P has a portion that overlaps with the element isolation section 10 in the normal direction N. The pixel isolation section 20 may have a portion in the in-plane direction P that does not overlap with the element isolation section 10 in the normal direction N.

[0032] The pixel isolation section 30 overlaps the intermediate region 110 between the element region 111 and the element region 112 in the normal direction N. The intermediate region 110 between the element region 111 and the element region 112 includes the isolation region 101, the isolation region 102, and the element region 113, and in this example, the pixel isolation section 30 overlaps the element region 113. The pixel isolation section 30 may overlap the isolation region 101 and / or the isolation region 102 in the normal direction N. The pixel isolation section 30 does not have to overlap the element region 113 in the normal direction N. In this way, the pixel isolation section 30 may have a portion that does not overlap with the element isolation section 10 in the normal direction N.

[0033] The pixel separating section 30 is formed by a groove 31. In the in-plane direction P, the pixel separating section 30 is located between the semiconductor region 121 and the semiconductor region 122. The pixel separating section 30 overlapping the element region 113 is located between the semiconductor region 124 and the semiconductor region 125 in the in-plane direction P. The pixel separating section 30 divides the semiconductor region 123 into a plurality of parts. As a result, the semiconductor region 123 includes a portion 1231 located between the pixel separating section 30 and the semiconductor region 121, and a portion 1232 located between the pixel separating section 30 and the semiconductor region 122.

[0034] In this way, within plane 3, semiconductor region 121 and semiconductor region 127 are discontinuous due to pixel separation section 20. Also, semiconductor region 121 and semiconductor region 122 are discontinuous due to pixel separation section 30. This reduces light mixing between pixels, improving the optical characteristics of the photoelectric conversion device. Also, this reduces charge mixing between pixels, improving the electrical characteristics of the photoelectric conversion device.

[0035] The pixel isolation section 30 is spaced apart from the region between the element region 111 and the element region 112, i.e., the isolation region 101, the isolation region 102, and the element region 113. This makes it possible to reduce noise generated in the pixel transistor 90 due to the pixel isolation section 30. It is also possible to reduce the influence on the operation of the pixel transistor 90 of stress concentration generated in the vicinity of the isolation region 101, the isolation region 102, and the element region 113. It is also possible to prevent defects (such as dislocation defects) from occurring in the semiconductor layer 100 due to stress concentration, thereby reducing the dark current taken in the photoelectric conversion element PD.

[0036] In particular, the channel region 70 is located in the gate electrode 80 of the pixel transistor 90. The channel region 70 is more sensitive to noise than the source / drain regions of the transistor. Therefore, it is preferable to arrange the pixel separation portion 30 shallower than the pixel separation portion 20 so as to overlap the channel region 70 and the gate electrode 80. In particular, it is effective that the pixel separation portion 30 does not contact at least the gate insulating film of the pixel transistor 90. Furthermore, the pixel separation portion 30 may be provided with a first portion shallower than the pixel separation portion 20 and a second portion shallower than the first portion. In other words, the end of the second portion on the front surface 1 side is located closer to the back surface 2 than the end of the second portion on the front surface 1 side. The second portion may overlap the channel region 70 or the gate electrode 80, and the first portion may overlap another region, for example, the source / drain region.

[0037] It is desirable to provide a concentrated p-type impurity region to separate the pixel separating section 30 from the photoelectric conversion element PD. If the pixel separating section 30 is disposed below the isolation region 101 or isolation region 102, the size of the photoelectric conversion element PD will be limited by the amount of this concentrated p-type impurity region. Therefore, by disposing the pixel separating section 30 below the element region 113, the photoelectric conversion element PD can also be made larger.

[0038] Furthermore, it is possible to use the semiconductor regions 124 and 125 adjacent to the semiconductor region 123 as the photoelectric conversion element PD. If the pixel separation section 20 were arranged in the semiconductor region 124, the pixel separation section 20 would hinder the movement of charges between the semiconductor region 123 and the semiconductor region 121. This would make it difficult to effectively use the semiconductor region 123 as the photoelectric conversion element PD. By arranging the pixel separation section 30 below the element region 113 in this way, the photoelectric conversion element PD1 can be extended from the semiconductor region 121 to the semiconductor region 124. Furthermore, the photoelectric conversion element PD2 can be extended from the semiconductor region 122 to the semiconductor region 125. This can improve sensitivity.

[0039] No pixel separating section 20 is provided between the isolation region 101 and the back surface 2. Therefore, the semiconductor region 121 and the semiconductor region 123 are continuous within the plane 3 via the semiconductor region 124. That is, within the plane 3, the semiconductor layer 100 is continuous between the element region 111, the element region 113, and the isolation region 101. Because the semiconductor layer 100 is continuous without the pixel separating section 20 below the isolation region 101, scattering of light by the grooves 21 in the pixel separating section 20 is suppressed. This increases the amount of light incident on the photoelectric conversion element PD, improving sensitivity. Furthermore, by separating the pixel separating section 20, which is a noise source, from the impurity region 40, which serves as an accumulation region for the photoelectric conversion element PD, noise generated near the pixel separating section 20 can be prevented from being absorbed by the photoelectric conversion element PD. Furthermore, it is possible to use not only the element region 111 and the semiconductor region 121 but also the semiconductor region 124 as the photoelectric conversion element PD. If the pixel separating section 20 were arranged in the semiconductor region 124, the volume of the photoelectric conversion element PD would be reduced by the amount of the pixel separating section 20, resulting in a decrease in sensitivity.

[0040] In the example shown in FIG. 1, the photoelectric conversion element PD is arranged up to the region corresponding to the semiconductor regions 123 and 124 in FIG. 2. This makes it easy to align or bring the center of the photoelectric conversion element PD and the light-focusing position of the microlens (typically the optical axis of the microlens) close to each other. To bring the light-focusing position of the microlens and the center of the photodiode close to each other, the distance between the optical axis of the microlens and the isolation region 101 should be smaller than the distance between the optical axis of the microlens and the isolation region 103. This allows the microlens to focus light at positions that are approximately the same distance from the pixel isolation units 20 and 30.

[0041] 2(a) to 2(d) show modified examples of the pixel isolation section 20 connected to the element isolation section 10. As shown in FIG. 2(a), a concentrated p-type impurity region 61 for a p-type channel stop can be provided around the element isolation section 10. It is desirable to provide the bottom of the pixel isolation section 20 so that it contacts the impurity region 61. This makes it possible to suppress problems such as dark current even when there is a defect near the bottom of the pixel isolation section 20, just like the element isolation section 10.

[0042] 2(b), the pixel isolation section 20 may be arranged so that the bottom of the pixel isolation section 20 bites into the bottom of the element isolation section 10. In this way, the interface between the element isolation section 10 and the pixel isolation section 20 can be kept away from the semiconductor layer 100, thereby reducing defects that may occur around the bottom of the pixel isolation section 20.

[0043] 2(a) and 2(b), the width W1 of the isolation region of the element isolation section 10 to which the pixel isolation section 20 is connected is preferably made larger than the width W2 of the pixel isolation section 20 (W1>W2). This makes it easy to connect the bottom of the pixel isolation section 20 to the bottom of the element isolation section 10 even if misalignment occurs.

[0044] 2(c) and 2(d), a portion of the pixel isolation section 20 may face the element region. Furthermore, as shown in FIGS. 2(c) and 2(d), the pixel isolation section 20 may be connected to both of a plurality of isolation regions that face each other across the element region. FIGS. 2(c) and 2(d) show a case where the portion of the pixel isolation section 20 that faces the element region is located closer to the front surface 1 than the bottom surface of the element isolation section 10. FIG. 2(c) shows a case where the portion of the pixel isolation section 20 that faces the isolation region is located closer to the back surface 2 than the portion that faces the element region. FIG. 2(d) shows a case where the portion of the element isolation section 10 that does not face the pixel isolation section 20 is located closer to the back surface 2 than the portion that faces the pixel isolation section 20.

[0045] As shown in FIGS. 2( e) and 2(f), a concentrated p-type impurity region 62 can be provided around the pixel isolation section 20 to suppress the intrusion of noise-causing charges from the pixel isolation section 20 into the semiconductor element. Similarly, a concentrated p-type impurity region 62 can be provided around the pixel isolation section 20 to suppress the intrusion of noise-causing charges from the pixel isolation section 20 into the semiconductor element. Similarly, a concentrated p-type impurity region 63 can be provided around the pixel isolation section 30 to suppress the intrusion of noise-causing charges from the pixel isolation section 30 into the semiconductor element. As shown in FIG. 2( e), the positions at which the impurity region 62 and the impurity region 63 are provided may be the same regardless of the depth of the pixel isolation sections 20 and 30. In FIG. 2( e), the impurity region 62 and the impurity region 63 are provided to approximately the same depth as the element isolation section 10. Furthermore, as shown in FIG. 2( e), the positions at which the impurity region 62 and the impurity region 63 are provided may differ depending on the depth of the pixel isolation sections 20 and 30. 2(e), an impurity region 62 around the pixel separating section 20, which is deeper than the pixel separating section 30 with respect to the back surface 2, is provided to a position deeper than an impurity region 63 around the pixel separating section 30, which is shallower than the pixel separating section 20 with respect to the back surface 2. The concentrated p-type impurity regions 62, 63 may be continuous with the concentrated p-type impurity region 61 shown in FIG. 2(a), or may be formed integrally with it.

[0046] 2(e) shows a case where pixel isolation section 20 is not connected to element isolation section 10. FIG. 2(f) shows a case where pixel isolation section 20 does not reach rear surface 2. Even in the cases of FIGS. 2(e) and 2(f), pixel isolation section 20 and pixel isolation section 30 pass through plane 3, pixel isolation section 20 passes through plane 4, and pixel isolation section 30 does not pass through plane 4.

[0047] As shown in FIG. 2(g), the pixel separating section 20 and pixel separating section 30, which have different depths, may have different inclination angles of the side surfaces of the grooves 21 and 31. For example, the inclination angle θ1 of the side surfaces of the grooves 21 in the deep pixel separating section 20 is set smaller than the inclination angle θ2 of the side surfaces of the grooves 31 in the shallow pixel separating section 30 (θ1<θ2). In addition, the widths of the grooves 21 and 31 are narrowed toward the front surface 1. In this way, in areas around the pixel separating section 30 where there is concern that defects or stress concentrations may affect the operation of the transistor, the effect on the operation of the transistor can be suppressed by reducing the volume of the pixel separating section 30.

[0048] Alternatively, as shown in Figure 2(h), the pixel isolation section 20 and the pixel isolation section 30, which have different depths, may have different curvatures of their bottoms. For example, the curvature of the bottom surface of the groove 21 in the deep pixel isolation section 20 may be made larger than the curvature of the bottom surface of the groove 31 in the shallow pixel isolation section 30. By reducing the curvature of the bottom surface of the groove 31 in the pixel isolation section 30, it becomes possible to alleviate local stress. When the curvature of the bottom surface of the groove 21 in the pixel isolation section 20 is large, the tip of the pixel isolation section 20 may be made to bite into the element isolation section 10, as shown in Figure 2(h).

[0049] The shape of the pixel separator 20 is not limited to that of this embodiment, and any known trench shape can be used as appropriate. For example, the pixel separator 20 may be tapered forward or backward from the rear surface 2 side to the front surface 1 side of the semiconductor layer 100. Alternatively, the pixel separator 20 may have a structure with multiple inclination angles. By adjusting the shape of the pixel separators 20 and 30 in this manner, it is possible to suppress color mixing in each pixel, improve sensitivity, and reduce noise.

[0050] An example of the layout of the pixel region PX will be shown below with reference to Figures 3 and 4. In the following examples, the above-mentioned in-plane direction P will be described as being divided into the X direction and the Y direction, which intersect (are perpendicular to) each other. The normal direction P will be described as the Z direction, which intersects (is perpendicular to) the X direction and the Y direction. The layout of the XY plane in Figures 3 and 4 is described as if the semiconductor layer 100, the element isolation portion 10, and the pixel isolation portions 20 and 30 are seen through from the rear surface 2 side.

[0051] Therefore, in the portion where the element isolation section 10 and the pixel isolation sections 20 and 30 overlap, the hatching of the element isolation section 10 and the hatching of the pixel isolation sections 20 and 30 are shown overlapping each other.

[0052] A first example of a pixel layout is shown in Figure 3. The pixel isolation sections are arranged in a grid pattern and are formed so that their depths differ in the X and Y directions. That is, deep pixel isolation sections 20 extend in the X direction, and shallow pixel isolation sections 30 extend in the Y direction.

[0053] Figure 3 shows four types of element regions. The first type of element region contains a photodiode PDm, a transfer gate TXm, and a floating diffusion FDm. The second type of element region contains a reset transistor RSn. The third type of element region contains an amplifier transistor SFn and a select transistor SLn. Well contacts WCn are arranged in the fourth-type element region. Here, m is a number determined for each of m pixels, and in FIG. 4, n = 1 to 4, and are indicated by affixing numbers such as PD1, PD3, FD2, and FD4. n is a number determined for each pixel, and in FIG. 4, m = 1 or 2, and are indicated by affixing numbers such as RS1, RS2, SD1, and SF2. If m is an odd number, n = (m + 1) / 2, and if m is an even number, n = m / 2.

[0054] After the potential of the floating diffusion FDm is reset by the reset transistor RSn, the charge from the photodiode PDm is transferred to the floating diffusion FDm via the transfer gate TXm. The potential change at the floating diffusion FDm is transmitted to the gate of the amplification transistor SFn through a wiring (not shown). The signal amplified by the amplifier transistor SFn that constitutes the source follower circuit is sequentially read out to the output signal line (not shown) via the select transistor SLn. In other words, the operations of photoelectric conversion, accumulation, charge detection, amplification, and pixel selection are performed within one pixel. The well contact WCn controls the potential of the pixel's well region. Multiple photodiodes PDm share the reset transistor RSn, amplifier transistor SFn, and select transistor SLn. In this case, the sharing relationship satisfies n = (m + 1) / 2 if m is odd, and n = m / 2 if m is even.

[0055] It is also possible to arrange a pixel transistor for each pixel instead of sharing it among multiple photodiodes. Alternatively, signals may be read out separately from multiple photodiodes PD in one pixel and then combined. In this way, light rays split into pupils are separately detected by multiple photodiodes PD in one pixel, enabling distance measurement or focus detection using a phase difference detection method. Furthermore, the dynamic range can be expanded by varying the sensitivity of multiple photodiodes PDp in one pixel and combining the signals.

[0056] Photodiodes PD1 and PD2 are aligned in the X direction. Photodiodes PD1 and PD3 are aligned in the Y direction. The element region in which photodiode PD3 is arranged is adjacent to the element region in which photodiode PD1 is arranged. Here, two element regions adjacent to each other means that no element region exists between the two element regions. The element region in which photodiode PD1 is arranged corresponds to element region 111 described in FIG. 1(a), and the element region in which photodiode PD2 is arranged corresponds to element region 112 described in FIG. 2. The element region in which amplifier transistor SFn and select transistor SLn are arranged corresponds to element region 113 described in FIG. 2. The element region in which photodiode PD3 is arranged corresponds to element region 114 described in FIG. 2.

[0057] The element isolation section 10 has an isolation region 103 between an element region in which the photodiode PD1 is arranged and an element region in which the photodiode PD3 is arranged. The pixel isolation section 20 overlaps the isolation region 103 in the Z direction.

[0058] Furthermore, the pixel separating section 30 is provided with a first section 36 that is shallower than the pixel separating section 20, and a second section 37 that is even shallower than the first section 36. In other words, the end of the second section 27 on the front surface 1 side is located closer to the back surface 2 than the end of the second section 36 on the front surface 1 side. The second section 37 may overlap the channel region 70 or the gate electrode 80, and the first section 36 may overlap another region, for example, a source / drain region.

[0059] A second portion 37 of the pixel separation portion 30 is provided shallower below the channel region where there is concern that the operation of the pixel transistor may be affected. A first portion 36 of the pixel separation portion 30 is provided deeper below the source / drain region than below the channel region, but the pixel separation portion 30 (first portion 36) can also be provided shallower below the source / drain region than the other pixel separation portions 30. Depending on the structure of the front surface 1 side of the semiconductor layer 100, the depth may be varied continuously along the longitudinal direction of the pixel separation portions 20, 30. In this case, the width of the pixel separation portions 20, 30 may be varied continuously along the longitudinal direction of the pixel separation portions 20, 30. It is also desirable to provide a gradual change in the line width or depth of the pixel separation portions 20, 30 where the line width or depth changes.

[0060] A second example of a pixel layout is shown in Fig. 4. As shown in Fig. 4, an element isolation portion 10 made of silicon oxide is provided between an element region in which a plurality of photodiodes PDn (n = 1 to 4) are arranged and an element region in which pixel transistors are provided around the element region. No element isolation portion 10 is provided between adjacent photodiodes PDn. Although not shown, adjacent photodiodes PDn are isolated by p-type high density impurity regions 63 formed by ion implantation.

[0061] 4, the width of the pixel isolation portion is locally wide at a position facing the element isolation portion 10, and the width is relatively narrow in other regions. The pixel isolation portion with a relatively wide width can be formed deeper.

[0062] The width W2 of the deep pixel isolation portion 20 that contacts the element isolation portion 10 on the surface 1 side of the semiconductor layer 100 is wider than the width W3 of the shallow pixel isolation portion 30 that has a depth D3 that extends partway through the semiconductor layer 100 (W2>W3). Furthermore, even in pixel isolation portions 30 that extend partway through the semiconductor layer 100, the widths vary depending on the depth. That is, the width W3 of the first portion 36 of the pixel isolation portion 30 that has a depth D3 is wider than the width W4 of the second portion 37 of the pixel isolation portion 30 that has a depth D4 that is smaller than the depth D3 (W3>W4). Thus, the smaller the depth of the pixel isolation portion, the smaller the width of the pixel isolation portion can be. Note that when the widths of the pixel isolation portions 20 and 30 vary in the Z direction (thickness direction of the semiconductor layer 100), the widths of the pixel isolation portions 20 and 30 on the third surface 3 can be used as representative widths. Because both the pixel isolation portion 20 and the pixel isolation portion 30 are located on the third surface 3, comparison of the widths is easy.

[0063] According to the present embodiment described above, even when the pixel isolation portions 20, 30 surround an area including two adjacent photodiodes, the depths of the pixel isolation portions 20, 30 are made to differ depending on the structure on the front surface 1 side of the semiconductor layer 100. This makes it possible to suppress effects on the photoelectric conversion characteristics or transistor characteristics, and to effectively suppress color mixing between adjacent pixels.

[0064] Next, a method for manufacturing the solid-state imaging device according to this embodiment will be described with reference to FIG.

[0065] 5(a), a trench 11 for an isolation portion 10 is formed on the front surface F side of the semiconductor substrate SUB. A channel stop layer (not shown) is formed around the trench 11 by ion implantation.

[0066] Next, in step b shown in FIG. 5(b), the trench 11 is filled with an insulator 12 for the element isolation portion 10. Silicon oxide is suitable for the insulator 12. Excess insulator outside the trench 11 is removed by a CMP method or the like. This forms the element isolation portion 10 having an STI (Shallow Trench Isolation) structure.

[0067] 5(c), a gate insulating film (not shown) and a gate electrode 80 are laminated on the surface F of the semiconductor substrate SUB to form pixel transistors (not shown). Furthermore, ion implantation performed from the surface F side of the semiconductor substrate SUB forms the photoelectric conversion element PD and source / drain regions of the pixel transistors. Furthermore, impurity regions 62 and 63 can be formed in the semiconductor regions where the pixel isolation portions 20 and 30 are to be formed in this process.

[0068] Next, in step d shown in FIG. 5(d), an insulating layer is laminated to cover the gate electrode 80, and then a contact hole is formed in the insulating layer. A wiring layer and an interlayer insulating layer are further laminated on the insulating layer with the contact hole formed therein, thereby forming a multilayer wiring structure. In this example, three wiring layers 310, 320, and 330 are formed. For example, copper wiring or aluminum wiring can be used for the wiring structure.

[0069] 5(e), a support substrate 400 is bonded from above the insulating film 300. The bonding may be performed by adhesive bonding, or other known methods may be used as appropriate. However, it is preferable to perform the process at 400°C or less so as not to affect the wiring structure, etc.

[0070] Next, in step f shown in FIG. 5(f), the semiconductor substrate SUB is thinned from the back surface B1 side until the semiconductor substrate SUB reaches a desired thickness. This thinning of the semiconductor substrate SUB exposes a new back surface B2 in place of the back surface B1. The thinning may be performed so that the photoelectric conversion element PD is exposed on the back surface B2. For example, chemical mechanical polishing (CMP), dry etching, wet etching, etc. can be used. These methods can also be combined. For example, the film thickness of the thinned semiconductor substrate SUB is set to a range of 1 to 10 μm, and preferably to a range of 2 to 5 μm from the viewpoint of improving the light sensitivity of the photodiode and the mechanical strength of the semiconductor substrate.

[0071] Next, in step g shown in FIG. 5(g), grooves 21 of the pixel isolation section 20 are formed from the back surface B2 side of the semiconductor substrate SUB at positions facing the element isolation section 10 formed on the front surface F side of the semiconductor substrate SUB. At this time, the depth of the grooves 21 of the pixel isolation section 20 from the back surface B2 is preferably set to a depth such that the bottom of the pixel isolation section 20 reaches the element isolation section 10. For example, if the thickness of the thinned semiconductor substrate SUB is approximately 2 μm and the depth of the element isolation section 10 is approximately 0.3 μm, the opposing grooves 21 are formed to a depth of approximately 1.7 μm. Such pixel isolation section 20 is formed by the following procedure. Note that the width of the bottom of the pixel isolation section 20 is preferably narrower than the width of the bottom of the element isolation section 10. This makes it easier for the bottom of the pixel isolation section 20 to contact the bottom of the element isolation section 10 even if misalignment occurs.

[0072] The grooves 21 of the pixel isolation section 20 are not provided under the isolation region 101 of the element isolation section 10 adjacent to the photoelectric conversion element PD, which makes it possible to improve the photoelectric conversion performance described above.

[0073] The method for forming the pixel isolation portion 20 will now be described in more detail. First, to form the grooves 21 of the pixel isolation portion 20 and the grooves 31 of the pixel isolation portion 30 in the semiconductor substrate SUB, the grooves 21, 31 having the desired widths are formed using, for example, an anisotropic dry etching method. For etching silicon, the Bosch process, in which a protective film formation step and an etching step are repeated every few seconds, can also be used. Note that when processing the grooves 21 of the pixel isolation portion 20 by dry etching, the element isolation portion 10 may be used to detect the end of etching of the semiconductor substrate SUB. Alternatively, the etching time may be specified according to the film thickness of the semiconductor substrate SUB. Also, a portion of the bottom of the element isolation portion 10 may be etched.

[0074] The trenches 21 and 31 of different depths can be simultaneously formed using the same etching mask (not shown). By etching the semiconductor substrate SUB under etching conditions utilizing the microloading effect, a deep trench 21 is formed under the wide opening of the mask pattern of the etching mask, and a shallow trench 31 is formed under the narrow opening. The microloading effect is a phenomenon in which the etching rate decreases as the opening width decreases. By setting the mask pattern of the etching mask, trenches of different depths can be formed in a simple process. It is also possible to etch the semiconductor substrate SUB under etching conditions utilizing the inverse microloading effect. In this case, the deep trench 21 can be formed under the narrow opening of the mask pattern of the etching mask, and the shallow trench 31 can be formed under the wide opening. Of course, it is also possible to form the deep trench 21 and the shallow trench 31 in separate processes, but this has many disadvantages, such as an increased number of lithography processes and problems with mask residue getting into the deep trench 21.

[0075] 5(g), solids 22, 32 are formed in the grooves 21, 31. First, a fixed charge film (not shown) is formed to suppress dark current generated on the rear surface 2 of the semiconductor layer 100. For this purpose, a fixed charge film (not shown) is formed along the shape of the rear surface B2 of the semiconductor substrate SUB. This fixed charge film is formed on at least the rear surface B2 of the semiconductor substrate SUB, and may also be formed so as to cover the side walls and bottom surfaces of the grooves 21 in the pixel separation section 20. By covering the sidewalls and bottom surface of the pixel separating portion 20 with a fixed charge film in this manner, it is possible to suppress dark current that may occur, for example, on the surface of the groove 21. As the fixed charge film, for example, a hafnium oxide film formed by atomic layer deposition (ALD) can be used.

[0076] Next, a solid 22 made of a dielectric, metal material, other light-shielding material, or a combination of these materials is formed inside the pixel separation portion 20 of the semiconductor substrate SUB. For example, a material with a lower refractive index than the silicon that forms the semiconductor substrate SUB, such as a silicon oxide film or titanium oxide film, is formed on the fixed charge film. Subsequently, a conductive material can be embedded using chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form the pixel separation portion 20. Alternatively, a silicon oxide film may be formed on the fixed charge film using atomic layer deposition (ALD), and then a silicon oxide film may be deposited using HDP (High Density Plasma) CVD. The pixel separation section 20 may be formed by burying the fixed charge film with a two-layer insulating film in this manner. Materials that can be formed at low temperatures of 400°C or less are particularly preferred, and it is desirable to form amorphous silicon, copper, or tungsten doped with P-type impurities using chemical vapor deposition (CVD) or atomic layer deposition (ALD), for example. The fixed charge film described above may also be used as the solid 22.

[0077] Although the above describes an example in which the solid 22 is embedded inside the pixel separating section 20, the configuration inside the groove 21 is not limited to this, and any structure that can suppress color mixing can be used, and known configurations and manufacturing methods can be applied. Also, for example, the pixel separating section 20 may have the groove 21 partially or entirely hollow.

[0078] In this example, the pixel separating section 20 is formed from the rear surface B2 side of the semiconductor substrate, but the method for forming the pixel separating section 20 is not limited to the method described here. For example, before forming the element isolation portion 10 described in steps a and b, the trench 21 may be formed from the front surface F side of the semiconductor substrate SUB.

[0079] 1A is then formed. A dielectric film 410 is formed on the rear surface B2 side of the semiconductor substrate SUB, and a light blocking member 420 is patterned between pixels on the dielectric film 410. The light-shielding member 420 is formed by forming a film by sputtering or chemical vapor deposition (CVD), and then processing it to remove all areas other than those requiring a light-shielding structure, including between pixels. The material of the light-shielding member 420 may be, for example, a laminated film of titanium and tungsten, or a laminated film of titanium nitride and tungsten.

[0080] Next, a planarization film (not shown) is formed, and a color filter array 430, for example, red, green, and blue, is formed on the planarization film corresponding to each pixel, and a microlens array 440 is formed on top of that. Each color filter and microlens is formed corresponding to each unit pixel of the pixel array. This completes the photoelectric conversion device. The semiconductor substrate SUB is used as the semiconductor layer 100 described above.

[0081] According to the above-described embodiment, a deep pixel isolation portion 20 and a shallow pixel isolation portion 30 are used together in the pixel region PX. By extending the deep pixel isolation portion 20 in the depth direction toward the element isolation portion 10, it is possible to effectively suppress color mixing between adjacent pixels. Furthermore, even if the shallow pixel isolation portion 30 is disposed below an element region where transistors and the like are provided or an isolation region where defects are likely to occur, the effects of noise and the like can be reduced. This allows the pixel isolation portions 20, 30 to be arranged in a layout suitable for photoelectric conversion. This makes it possible to improve the performance of the photoelectric conversion device.

[0082] The photoelectric conversion device described above can be applied to imaging devices (image sensors) used in cameras and the like. It can also be applied to sensors for focus detection (AF: autofocus) and photometry (AE: autoexposure). In addition to the photoelectric conversion device as an imaging device, a camera can include at least one of a signal processing device, a storage device, a display device, and an optical device. The signal processing device is, for example, a CPU or DSP, and processes signals obtained from the imaging device. The storage device is, for example, a DRAM or flash memory, and stores information based on signals obtained from the imaging device. The display device is, for example, a liquid crystal display or an organic EL display, and displays information based on signals obtained by the imaging device. The optical device is, for example, a lens, mirror, shutter, or filter, and guides light to the imaging device. The term "camera" as used herein includes not only dedicated camera devices such as still cameras, video cameras, and surveillance cameras, but also information terminals with imaging functions and mobile objects (vehicles and aircraft) with imaging functions.

[0083] Furthermore, even if not explicitly described in this specification, matters that can be understood from the accompanying drawings or common general technical knowledge also constitute part of this disclosure. The present invention can be appropriately modified without departing from the scope of the technical idea of ​​this disclosure. [Explanation of symbols]

[0084] 100 Semiconductor layer 1 surface 2 Back side 3 planes 10 Element isolation section 20 Pixel separation section 30 Pixel separation section

Claims

1. A photoelectric conversion device having a pixel region including a plurality of photoelectric conversion elements, a semiconductor layer having a first surface and a second surface opposite to the first surface, the plurality of photoelectric conversion elements being arranged between the first surface and the second surface, a MOS transistor having a gate electrode arranged on the first surface side, a first semiconductor region of a first conductivity type which is a source region or a drain region of the MOS transistor, a well region of the pixel region, and a well contact arranged on the first surface for controlling the potential of the well region; a lattice-shaped groove that is arranged in the pixel region of the semiconductor layer, extends from the second surface toward the first surface, and is arranged along a first direction and a second direction intersecting the first direction in a plan view of the first surface; In a cross-sectional view along the first direction, the lattice-shaped groove has a first region and a second region, the semiconductor layer extends between the first region and the first surface, and the second region has a longer length from the second surface than the first region, a portion of the first region overlaps with the well contact in a plan view of the first surface; In the cross-sectional view, the well region is located between an end of the first region on the first surface side and the well contact, a plurality of the gate electrodes being arranged between two of the second regions that are closest to each other in a plan view relative to the first surface;

2. In the pixel region, an element isolation portion is arranged on the side of the first surface of the semiconductor layer and includes an insulator, a portion of the insulator is located between the semiconductor layer and the gate electrode of the MOS transistor; The photoelectric conversion device according to claim 1 , wherein the second region overlaps with the element isolation portion in a plan view relative to the first surface.

3. A photoelectric conversion device as described in Claim 2, characterized in that, in a planar view of the first surface, another portion of the first region overlaps with the element isolation portion.

4. A photoelectric conversion device as described in Claim 3, characterized in that, when viewed in a plane relative to the first surface, a portion of the first region does not overlap with the element isolation portion.

5. A photoelectric conversion device described in any one of claims 2 to 4, characterized in that the element isolation portion is shallow trench isolation.

6. A photoelectric conversion device described in any one of claims 2 to 5, characterized in that a portion of the semiconductor layer is arranged between at least a portion of the insulator and at least a portion of the second region.

7. A photoelectric conversion device described in any one of claims 2 to 5, characterized in that a portion of the second region is connected to the insulator.

8. The plurality of photoelectric conversion elements include a first photoelectric conversion element, a second photoelectric conversion element, and a third photoelectric conversion element; the first photoelectric conversion element and the second photoelectric conversion element are arranged along the second direction, the second photoelectric conversion element and the third photoelectric conversion element are arranged along the first direction, the first region is disposed between the first photoelectric conversion element and the second photoelectric conversion element; 8. The photoelectric conversion device according to claim 1, wherein the second region is disposed between the second photoelectric conversion element and the third photoelectric conversion element.

9. A photoelectric conversion device described in any one of claims 1 to 8, characterized in that, in a planar view of the first surface, the first region overlaps the MOS transistor.

10. A photoelectric conversion device described in any one of claims 1 to 9, characterized in that an insulator is arranged in the groove.

11. A photoelectric conversion device described in any one of claims 1 to 10, characterized in that when the length of the first region from the second surface is D1 and the distance between the first surface and the second surface is T, T x 1 / 4 ≦ D1 ≦ T x 3 / 4 is satisfied.

12. A photoelectric conversion device described in any one of claims 1 to 11, characterized in that the second region is located at least at a corner of the lattice shape when viewed in a plane relative to the first surface.

13. The photoelectric conversion device according to any one of claims 1 to 12, At least one of a signal processing device that processes a signal output from the photoelectric conversion device, a storage device that stores information based on the signal output from the photoelectric conversion device, a display device that displays information based on the signal output from the photoelectric conversion device, and an optical device that guides light to the photoelectric conversion device; A camera comprising:

Images