Solid-state imaging device and electronic device

Abstract

To suppress registration applied to a wiring while an optimizing a layout area by increasing a degree-of-freedom of the wiring.SOLUTION: In a solid state image sensor (1), a timing generating circuit (14) includes a first terminal (6) a second terminal (7) as a same node, respectively. Each node of the first terminal (6) and the second terminal (7) is a node used for a circuit operation only in logic board (3), and a bonding part (5) contains: a first wiring (11) that contacts the first terminal (6) to a pixel substrate (2); and a second wiring (12) that connects the second terminal (7) to the pixel substrate (2). The pixel substrate (2) contains a first connection wiring (13) that connects the first wiring (11) and the second wiring (12).SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a solid-state imaging element in which unit pixels, each including an active element that converts a signal charge photoelectrically converted by a photoelectric conversion element into an electrical signal and outputs the electrical signal, are arranged in a matrix, and to an electronic device equipped with this solid-state imaging element, and in particular to a solid-state imaging element configured by stacking a plurality of substrates, and to an electronic device equipped with this solid-state imaging element. [Background technology]

[0002] Well-known solid-state imaging devices include charge-transfer type solid-state imaging devices, such as CCD (Charge Coupled Device) image sensors, and XY-address type solid-state imaging devices, such as CMOS (Complementary Metal Oxide Semiconductor) image sensors. These solid-state imaging devices are widely used in digital still cameras and digital video cameras. In recent years, CMOS image sensors have become increasingly popular in mobile devices such as camera-equipped mobile phones, in-vehicle cameras, surveillance cameras, and factory automation (FA) equipment.

[0003] An XY-address type solid-state imaging device, such as a CMOS image sensor, consists of a pixel area that receives light, photoelectrically converts the signal charge, and extracts it as an electrical signal, and a peripheral circuit area that drives and reads the pixels, processes the signal, and outputs it.

[0004] In the pixel region, photodiodes, which function as photoelectric conversion elements, and multiple pixel transistors are arranged in a two-dimensional matrix as unit pixels. Incident light is photoelectrically converted by the photodiodes formed on a substrate (e.g., a silicon substrate) and stored as signal charge. The multiple pixel transistors consist of three transistors that transfer, reset, and amplify the signal charge, or four transistors, including a selection transistor that selects the pixel address to be read.

[0005] The substrate has at least one metal wiring layer on top. In addition to a front-illuminated pixel structure in which the wiring layer side is the surface and incident light is received from the wiring layer side, a back-illuminated pixel structure in which incident light is received from the substrate surface opposite the wiring layer is also known (see, for example, Patent Document 1). Some devices have microlenses to increase light sensitivity and color filters to obtain color information on the upper layer on the light-receiving surface side of the substrate.

[0006] The peripheral circuit region includes various logic circuits, such as pixel drive circuits and signal processing circuits including AD conversion circuits. In recent years, there has been a trend toward using high-speed clock signals in these logic circuits to speed up data transfer.

[0007] Conventionally, a known configuration of a solid-state imaging device is one in which a pixel substrate on which a pixel region is formed and a logic substrate on which a peripheral circuit region is formed are stacked (see, for example, Patent Document 2). The stacked pixel substrate and logic substrate are electrically connected by junctions of conductive material connecting the top metal layers of both substrates and by through-holes that penetrate both substrates, and electrical signals are exchanged between both substrates via these junctions and through-holes (see, for example, Patent Document 3). Copper, for example, is used as the conductive material at the junctions and the material filling the through-holes.

[0008] As shown in Patent Documents 2 and 3, in a CMOS image sensor having a structure in which a pixel substrate and a logic substrate are stacked, the pixel substrate and the logic substrate are interconnected in the area excluding the electrode pads only by output signal wiring from the pixel substrate, pixel drive wiring, power supply wiring necessary for circuit operation on each substrate, and ground wiring. In the area other than the above-mentioned wiring that is essential for connection between the two substrates, the wiring for all circuits is completed within each substrate. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent No. 3759435 specification [Patent Document 2] Patent No. 5773379 specification [Patent Document 2] Japanese Patent Application Publication No. 2017-117828 Summary of the Invention [Problem to be solved by the invention]

[0010] As seen in the above-mentioned prior art, solid-state imaging devices with a structure in which a pixel substrate and a logic substrate are stacked and electrically connected to each other are widely known. However, the wiring connecting the two substrates in this case was limited to the bare minimum, such as wiring for output signals from the pixels, except for the electrode pad area, and each circuit block was completed within each substrate.

[0011] Furthermore, because the pixel substrate and logic substrate that are stacked are each produced using different manufacturing processes, the layout rules for things like the spacing between wiring may differ. At the beginning of the design process, after determining the minimum types of wiring that must be connected between the pixel substrate and logic substrate and the locations of the junctions where they connect, the circuit layout is often carried out independently for each substrate. This makes it difficult to create an optimized layout that avoids wasted space across the entire stacked chip.

[0012] For semiconductor elements, including solid-state imaging devices, the chip size directly affects mass productivity and cost. This demands smaller chips, but the circuit layout becomes more difficult with limited metal wiring layers and narrow wiring space. Furthermore, in stacked chips, both substrates must be the same size, so the size must match the larger of the pixel substrate and logic substrate. In this case, empty space will be created on one of the substrates where wiring and elements are not placed, resulting in waste in the layout.

[0013] If the wiring resistance of the power supply wiring and ground wiring of a circuit with high power consumption is too high, the voltage may drop momentarily, preventing the circuit from operating as expected. Therefore, these wirings must be made sufficiently wide. However, the smaller the chip is made in the trade-off with chip size mentioned above, the more difficult it becomes to secure wiring space, making it difficult to lay out wide power supply wiring and ground wiring.

[0014] To achieve high-frame-rate imaging, solid-state imaging devices require circuit operation using a faster clock. The waveform of the clock signal wiring through which the high-speed clock signal passes is particularly susceptible to distortion due to the influence of wiring resistance, and high wiring resistance can prevent the circuit from operating as expected. Therefore, it is desirable to minimize wiring resistance as much as possible, even for high-speed clock signal wiring, by using a layout that ensures a sufficiently wide line width. However, as chips become smaller in tradeoff with chip size, it becomes more difficult to secure wiring space, making it difficult to lay out clock signal wiring with a wide line width.

[0015] The present invention has been made to solve the above-mentioned problems, and its object is to provide a solid-state imaging element and electronic device that have a structure in which a pixel substrate and a logic substrate are stacked, and that can increase the degree of freedom in wiring, optimize the layout area, and suppress the resistance on the wiring. [Means for solving the problem]

[0016] In order to solve the above problem, a solid-state imaging element according to one embodiment of the present invention comprises a pixel substrate having a pixel array in which unit pixels each including a photoelectric conversion element are arranged in a matrix, a logic substrate having a logic circuit associated with the pixel array and stacked on the pixel substrate, and a junction portion electrically connecting the pixel substrate and the logic substrate by bonding the topmost wiring of the pixel substrate and the logic substrate so that they face each other, wherein the logic circuit has a first terminal and a second terminal which are the same node, and the node of the first terminal and the second terminal is a node used for circuit operation only on the logic substrate, the junction portion includes a first wiring connecting the first terminal to the pixel substrate and a second wiring connecting the second terminal to the pixel substrate, and the pixel substrate includes a first connection wiring connecting the first wiring and the second wiring.

[0017] In order to solve the above problem, a solid-state imaging element according to another aspect of the present invention comprises a pixel substrate having a pixel array in which unit pixels each including a photoelectric conversion element are arranged in a matrix and a pixel circuit associated with the pixel array; a logic substrate having a logic circuit associated with the pixel array and stacked on the pixel substrate; and a junction portion electrically connecting the pixel substrate and the logic substrate by joining the respective top layer wirings of the pixel substrate and the logic substrate so that they face each other, wherein the pixel circuits have a first terminal and a second terminal which are the same node, and the nodes of the first terminal and the second terminal are nodes used for circuit operation only on the pixel substrate, the junction portion includes a first wiring connecting the first terminal to the logic substrate and a second wiring connecting the second terminal to the logic substrate, and the logic substrate includes a first connection wiring connecting the first wiring and the second wiring.

[0018] In order to solve the above-described problems, an electronic device according to an aspect of the present invention includes the solid-state imaging device according to an aspect of the present invention. [Effects of the Invention]

[0019] According to one aspect of the present invention, it is possible to provide a solid-state imaging element and an electronic device that can increase the degree of freedom of wiring to optimize the layout area while suppressing the resistance applied to the wiring. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a cross-sectional view of a solid-state imaging device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of a pixel substrate provided in the solid-state imaging device. [Figure 3] FIG. 2 is a plan view of a logic board provided in the solid-state imaging device. [Figure 4] FIG. 2 is a circuit diagram of a unit pixel disposed on the pixel substrate. [Figure 5] FIG. 2 is a detailed cross-sectional view of the solid-state imaging device. [Figure 6] FIG. 2 is a schematic diagram for explaining the relationship between the logic substrate and the pixel substrate. [Figure 7] FIG. 10 is a detailed cross-sectional view of a modified example of the solid-state imaging device. [Figure 8] FIG. 10 is a detailed cross-sectional view of another modified example of the solid-state imaging device. [Figure 9] FIG. 10 is a detailed cross-sectional view of a solid-state imaging device according to a second embodiment. [Figure 10] FIG. 10 is a plan view of a main part of a pixel substrate provided in a solid-state imaging device according to a third embodiment. [Figure 11] FIG. 10 is a detailed cross-sectional view of a solid-state imaging device according to a fourth embodiment. [Figure 12] FIG. 10 is a detailed cross-sectional view of a modified example of the solid-state imaging device according to the fourth embodiment. [Figure 13] FIG. 10 is a detailed cross-sectional view of another modified example of the solid-state imaging device according to the fourth embodiment. [Figure 14] FIG. 10 is a detailed cross-sectional view of another modified example of the solid-state imaging device according to the fourth embodiment. [Figure 15] FIG. 10 is a schematic diagram of a camera according to a fifth embodiment. [Figure 16] FIG. 10 is a block diagram of a camera according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] [Embodiment 1] An embodiment of the present invention will be described in detail below. Fig. 1 is a cross-sectional view of a solid-state imaging element 1 according to embodiment 1. Fig. 2 is a plan view of a pixel substrate 2 provided in the solid-state imaging element 1. Fig. 3 is a plan view of a logic substrate 3 provided in the solid-state imaging element 1. Fig. 4 is a circuit diagram of a unit pixel 17 arranged in a pixel array 4 on the pixel substrate 2. Fig. 5 is a detailed cross-sectional view of the solid-state imaging element 1.

[0022] The solid-state imaging device 1 comprises a pixel substrate 2 having a pixel array 4 in which unit pixels 17, each including a photodiode 18 (photoelectric conversion element), are arranged in a matrix, a logic substrate 3 having a logic circuit 8 associated with the pixel array 4 and stacked on the pixel substrate 2, and a junction 5 in which the top layer wiring of the pixel substrate 2 and the logic substrate 3 are joined together so that they face each other, electrically connecting the pixel substrate 2 and the logic substrate 3.

[0023] The logic circuit 8 includes a pixel driving circuit 9 for driving the unit pixels 17 of the pixel array 4, a signal processing circuit 10 for processing signals output from the pixel array 4, a voltage generation circuit 29 for generating a voltage level different from a voltage input from the outside through the electrode pads of the chip to be used as a power supply voltage, etc., a timing generation circuit 14 for generating a clock signal that serves as a reference for the operation of each circuit, an AD conversion circuit 15 for AD converting the signals output from the pixel array 4, and an amplifier circuit 16 for amplifying image data output outside the chip by applying an analog gain or a digital gain.

[0024] The timing generation circuit 14 has a first terminal 6 and a second terminal 7, which are the same node. The nodes of the first terminal 6 and the second terminal 7 are nodes that are used only on the logic board 3 for circuit operation.

[0025] Although an example will be described in which the first terminal 6 and the second terminal 7 are provided in the timing generation circuit 14, the present invention is not limited to this. The first terminal 6 and the second terminal 7 may be provided in the logic circuit 8. For example, the first terminal 6 and the second terminal 7 may be provided in at least one of the pixel drive circuit 9, the signal processing circuit 10, the voltage generation circuit 29, the AD conversion circuit 15, and the amplifier circuit 16.

[0026] The junction 5 includes a first wiring 11 that connects the first terminal 6 to the pixel substrate 2, and a second wiring 12 that connects the second terminal 7 to the pixel substrate 2. The pixel substrate 2 includes a first connection wiring 13 that connects the first wiring 11 and the second wiring 12.

[0027] The pixel substrate 2 includes a first wiring layer 27. The logic substrate 3 includes a second wiring layer 28. The first connection wiring 13 is formed in the first wiring layer 27. The first terminal 6 and the second terminal 7 are not electrically connected by the second wiring layer 28. The first terminal 6 and the second terminal 7 are electrically connected only by the first wiring layer 27.

[0028] The first terminal 6 is preferably one of a power terminal and a ground terminal, and the second terminal 7 is preferably the other of a power terminal and a ground terminal.

[0029] The first wiring layer 27 is preferably a multi-layer wiring layer, and the first connection wiring 13 is preferably formed in at least one layer of the multi-layer wiring layer.

[0030] The pixel substrate 2 and the logic substrate 3 have the same shape and area, and the solid-state imaging device 1 is formed in a chip shape.

[0031] The pixel substrate 2 has a pixel array 4 in which unit pixels 17 shown in Fig. 4 are arranged in a two-dimensional matrix. Pixel output signals read out from the pixel array 4 are supplied to the logic board 3, where they are subjected to various signal processing before being output outside the chip.

[0032] 4, light incident on a unit pixel 17 is photoelectrically converted by a photodiode 18 formed on a pixel substrate 2 (e.g., a silicon substrate) and stored as a signal charge. The pixel transistor is composed of four transistors: a transfer transistor 19, a reset transistor 22, an amplification transistor 20, and a selection transistor 21.

[0033] Then, by turning on the transfer transistor 19, the signal charge accumulated in the photodiode 18 is transferred to the floating diffusion FD. Next, by turning on the amplification transistor 20, the signal charge transferred to the floating diffusion FD is amplified. After that, by turning on the selection transistor 21 corresponding to the pixel address to be read out, the amplified signal charge is read out of the pixel array 4 through the vertical signal line 23. Then, by turning on the reset transistor 22, the signal charge transferred to the floating diffusion FD is discarded and the potential of the floating diffusion FD is initialized.

[0034] The logic circuit 8 includes various logic circuits, such as a voltage generation circuit 29, a pixel drive circuit 9, an AD conversion circuit 15, a signal processing circuit 10, a timing generation circuit 14, and an amplifier circuit 16. The pixel drive circuit 9 provides pixel drive signals to the pixel transistors in the pixel array 4, and drives the pixels by storing, transferring, amplifying, and reading out the signal charge. The AD conversion circuit 15 receives the pixel output signal read from the pixel array 4 and performs analog-to-digital conversion. The AD-converted pixel output signal is then processed by the signal processing circuit 10, which subtracts a zero level from the signal level to remove fixed pattern variations from each pixel, before outputting it as image data off-chip. The voltage generation circuit 29 generates a voltage level different from the voltage input from the outside through the chip's electrode pads. This voltage is used as a power supply voltage, etc. The timing generation circuit 14 generates a clock signal that serves as the basis for the operation of each circuit. The faster the clock signal, i.e., the higher the frequency of the clock signal, the faster the circuit can operate. The amplifier circuit 16 amplifies the image data output off-chip by applying analog or digital gain.

[0035] The joints 5 electrically connect the pixel substrate 2 and the logic substrate 3 when they are stacked together, and are a set of junctions made of a conductive material that connects the top metal layers of the two substrates. The conductive material at the junctions is, for example, copper.

[0036] As is clear from FIG. 5 , in the solid-state imaging device 1 of the first embodiment, the uppermost metal layers of the wiring layers of the pixel substrate 2 having the pixel array 4 and the logic substrate 3 having the signal processing circuit 10 are electrically connected by a joint 5, and electrical signals, including pixel output signals, are exchanged between the two substrates. Wiring 31 is a power supply wiring that supplies pixel power generated by the voltage generation circuit 29 of the logic substrate 3 to the pixel substrate 2. Wiring 32 is a ground wiring that, like the power supply wiring, supplies ground potential from the ground circuit 30 of the logic substrate 3 to the pixel substrate 2. Wiring 33 is a pixel drive signal wiring that connects the pixel drive circuit 9 of the logic substrate 3 to the gates of pixel transistors included in the pixel array 4 of the pixel substrate 2, and drives the pixels by storing, transferring, amplifying, and reading out signal charges. Wiring 34 is a pixel output signal wiring that connects pixel signals output from the pixel array 4 of the pixel substrate 2 to the AD conversion circuit 15 of the logic substrate 3. The pixel signals are sent to the signal processing circuit 10 via the AD conversion circuit 15, where they are subjected to various signal processing operations and then output as image data outside the chip.

[0037] In the laminated substrate of a conventional solid-state imaging device, only the power supply wiring, ground wiring, pixel drive signal wiring, and pixel output signal wiring described above are connected between the pixel substrate 2 and the logic substrate 3 via the joint 5. In this way, only the same nodes present in the circuits of both the pixel substrate 2 and the logic substrate 3 are wired between the two substrates via the joint 5.

[0038] In contrast, the structure of a specific portion of the solid-state imaging device 1 according to embodiment 1 shown in FIG. 5 will be described. The first terminal 6 and the second terminal 7 of the same node in the timing generation circuit 14 included in the logic substrate 3 are not directly connected using the second wiring layer 28 of the logic substrate 3, but are connected by the first connection wiring 13 using the free space in the first wiring layer 27 of the pixel substrate 2, which are connected via the first wiring 11 and the second wiring 12. The nodes of the first terminal 6 and the second terminal 7 are used only in the timing generation circuit 14 of the logic substrate 3, and are not used in the pixel substrate 2, so that the wiring can be completed within the logic substrate 3. However, the solid-state imaging device 1 according to embodiment 1 has a wiring structure in which the node between the first terminal 6 and the second terminal 7 passes through the unused first wiring layer 27 of the pixel substrate 2, in order to smoothly connect the first terminal 6 and the second terminal 7.

[0039] FIG. 6 is a schematic diagram for explaining the relationship between the logic substrate 3 and the pixel substrate 2. As shown in FIG.

[0040] When considering connecting the first terminal 6 and the second terminal 7 by wiring, there are cases where the connection on the logic board 3 is difficult in terms of layout. For example, as shown in FIG. 6, there is a case where a signal processing circuit 10 is arranged between the first terminal 6 provided on the electrode pad 26 of the drive power supply for the logic circuit 8 and the second terminal 7 provided on the logic circuit 8. In this case, in order to connect the first terminal 6 and the second terminal 7 on the logic board 3, it becomes necessary to divide the signal processing circuit 10 into two blocks and run wiring connecting the first terminal 6 and the second terminal 7 between the two blocks. This not only increases the layout area, but also disrupts the periodicity of the arrangement of the signal processing circuits 10, resulting in problems of a large layout impact.

[0041] In this case, rather than forcibly connecting the first terminal 6 and the second terminal 7 using the second wiring layer 28 of the logic substrate 3, it is possible to minimize the layout area by connecting the first terminal 6 and the second terminal 7 in the free space using only the first wiring layer 27 of the pixel substrate 2.

[0042] In the first embodiment, at the beginning of the design stage, the types of wiring that must be connected between the pixel substrate 2 and the logic substrate 3 and the locations of the junctions where those wirings will be connected are determined. In conventional solid-state imaging devices, it is decided that only wiring that is essential to the structure of the stacked chip, such as pixel output signal wiring, will be connected between the substrates, and basically, the types of wiring to be connected are not increased in the subsequent design stages. On the other hand, in the solid-state imaging device 1 according to the first embodiment, junctions and wiring that connect the two substrates may be added depending on the circuit layout situation in the subsequent design stages.

[0043] Next, the arrangement of circuit blocks is determined for each of the pixel substrate 2 and logic substrate 3, and the layout of each circuit block is advanced. At this time, the chip size is adjusted to the size of the larger of the two stacked substrates. Because the stacked pixel substrate 2 and logic substrate 3 are produced using different manufacturing processes, the layout rules for things like the spacing between wires may differ.

[0044] In conventional solid-state imaging devices, circuit layouts for the pixel substrate 2 and the logic substrate 3 are often developed independently. In contrast, in the solid-state imaging device 1 according to the first embodiment, the layouts are developed in parallel to effectively utilize the space on both substrates, while taking into consideration the different layout rules for the two substrates. To match the chip size to the larger substrate, free space is left on at least one of the substrates. As shown in FIG. 5 , when connecting the first terminal 6 and the second terminal 7 provided on the timing generation circuit 14 included in the logic substrate 3, if there is insufficient layout space on the second wiring layer 28 of the logic substrate 3 but free space is available on the first wiring layer 27 of the pixel substrate 2, a wiring structure can be created in which the first wiring 11 and the second wiring 12 are routed through the first wiring layer 27 of the pixel substrate 2.

[0045] The solid-state imaging device 1 according to the first embodiment allows for a flexible layout, such that even if it is difficult to connect the first terminal 6 and the second terminal 7 within the second wiring layer 28 of the logic substrate 3 due to space limitations, the connection can be made by effectively utilizing the available space within the first wiring layer 27 of the pixel substrate 2. In this way, optimizing the layout area of ​​each circuit block for each of multiple stacked substrates makes it possible to reduce the total number of wiring layers and the overall chip size. Reducing the number of wiring layers also reduces the number of fabrication masks, resulting in cost savings. Reducing the chip size also allows for an increase in the number of chips that can be mounted on a semiconductor wafer, leading to cost savings during mass production.

[0046] As described above, in a solid-state imaging element 1 having a structure in which a pixel substrate 2 and a logic substrate 3 are stacked, by connecting wiring that is used for circuit operation only on one of the substrates to the other substrate that is not used for circuit operation, and then passing the wiring through a wiring layer that the other substrate has and connecting it again to the one of the substrates, it is possible to provide a solid-state imaging element that increases the degree of freedom in wiring, optimizes the layout area, and suppresses the resistance on the wiring.

[0047] 7 is a detailed cross-sectional view of a solid-state imaging device 1A according to a modification. Components similar to those described above are given the same reference numerals, and detailed description thereof will not be repeated.

[0048] The first terminal 6 and the second terminal 7 may be connected to the pixel substrate 2 via multiple junctions. For example, as shown in FIG. 7 , the junction 5 includes, in addition to the first wiring 11 and the second wiring 12, a third wiring 41 connecting the first terminal 6 to the pixel substrate 2 and a fourth wiring 42 connecting the second terminal 7 to the pixel substrate 2. The third wiring 41 is electrically connected in parallel with the first wiring 11. The fourth wiring 42 is electrically connected in parallel with the second wiring 12. Note that the first wiring 11 and the third wiring 41 only need to be electrically connected in parallel; they do not need to be physically arranged side by side and may be arranged at physically separated positions. Similarly, the second wiring 12 and the fourth wiring 42 do not need to be physically arranged side by side and may be arranged at physically separated positions.

[0049] 8 is a detailed cross-sectional view of a solid-state imaging device 1B according to another modification. Components similar to those described above are given the same reference numerals, and detailed description thereof will not be repeated.

[0050] Two or more pairs of terminals may be provided, each having a different node. For example, as shown in FIG. 8, the solid-state imaging device 1B further includes a timing generation circuit 14B. The timing generation circuit 14B further includes a third terminal 6B and a fourth terminal 7B, which are at the same node. Thus, two pairs are provided: a pair of the first terminal 6 and the second terminal 7, and a pair of the third terminal 6B and the fourth terminal 7B. The joint 5 further includes a fifth wiring 11B connecting the third terminal 6B to the pixel substrate 2 and a sixth wiring 12B connecting the fourth terminal 7B to the pixel substrate 2. The pixel substrate 2 further includes a third connection wiring 13B connecting the fifth wiring 11B and the sixth wiring 12B.

[0051] In a semiconductor device such as that according to this embodiment, multiple types of power supplies with different voltages may be used within the chip. For example, these may be power supplies for driving pixels, power supplies for driving logic circuits, etc. In addition to power supply and ground terminals, there are also nodes such as high-speed clock signal lines where the effects of wiring resistance can be a major problem. By applying the structure proposed in this embodiment (a wiring structure via the other substrate) to each of these nodes, rather than just one of them, it is possible to address the wiring resistance between terminals with multiple different nodes.

[0052] [Embodiment 2] Other embodiments of the present invention will be described below. For ease of explanation, the same reference numerals will be used to designate components having the same functions as those described in the above embodiment, and the description thereof will not be repeated.

[0053] FIG. 9 is a detailed cross-sectional view of a solid-state imaging device 1C according to the second embodiment.

[0054] 9, in the second embodiment, similarly to the first embodiment, the solid-state imaging device 1C has a pixel substrate 2 having a pixel array 4 and a logic substrate 3 having a signal processing circuit 10, and the uppermost metal layers of the respective wiring layers are electrically connected by a joint 5. The wiring connecting the two substrates includes a power supply wiring, a ground wiring, a pixel drive signal wiring, a pixel output signal wiring, and the like.

[0055] The structure unique to the solid-state imaging device 1C according to the second embodiment, shown in FIG. 9, will now be described. The first terminal 6 and the second terminal 7 of the same node in the timing generation circuit 14 included in the logic substrate 3 are directly connected using the second connection wiring 24 of the second wiring layer 28 of the logic substrate 3, and are then further connected by the first connection wiring 13 using the free space in the first wiring layer 27 of the pixel substrate 2, which is connected via the first wiring 11 and the second wiring 12. The nodes of the first terminal 6 and the second terminal 7 are used only in the timing generation circuit 14 of the logic substrate 3 and are not used in the pixel substrate 2, so that the wiring can be completed within the logic substrate 3. However, the solid-state imaging device 1C according to the second embodiment is characterized by a wiring structure in which the node between the first terminal 6 and the second terminal 7 is backed by the first connection wiring 13 of the first wiring layer 27 of the pixel substrate 2, which is not used, in order to reduce the resistance in the wiring between the first terminal 6 and the second terminal 7.

[0056] The design procedure for the wiring structure in the second embodiment is similar to the design procedure for the wiring structure in the first embodiment described above, and therefore the description thereof will not be repeated.

[0057] According to the solid-state imaging device 1C of embodiment 2, even if two or more terminals cannot be connected with wiring of a sufficiently wide line width on the second wiring layer 28 of the logic substrate 3, the above-described wiring structure enables a layout in which wide wiring can be easily connected on the first wiring layer 27 of the pixel substrate 2. This allows the wiring to be backed by the first wiring layer 27 of the stacked pixel substrate 2, thereby reducing the resistance of the wiring between the first terminal 6 and the second terminal 7 on the logic substrate 3, thereby suppressing voltage drop. Creating this backing wiring structure for power supply wiring and ground wiring strengthens the power supply and ground of the circuit. Furthermore, since wide wiring is required for signal lines such as high-speed clocks, adopting this structure can suppress clock waveform distortion. Implementation of a faster clock signal in the solid-state imaging device 1A enables faster readout of image data, thereby realizing a solid-state imaging device 1C with a high frame rate.

[0058] [Embodiment 3] 10 is a plan view of a main part of a pixel substrate 2D provided in a solid-state imaging device 1D according to embodiment 3. Components similar to those described above are given the same reference numerals, and detailed description of these components will not be repeated.

[0059] In the third embodiment, a grid wiring structure in which wires intersect vertically and horizontally in a grid pattern as shown in Fig. 10 is provided as wiring that connects via empty spaces in the first wiring layer 27 of the pixel substrate 2 in the first and second embodiments. The first wiring 11 and the second wiring 12 are connected by first connection wiring 13D formed in a grid pattern. Generally, layout rules prohibit the use of thick wiring having a line width greater than a certain level, but by laying individual thin wires in a grid pattern like the first connection wiring 13D, it is possible to achieve a layout that minimizes wiring resistance while adhering to the layout rules.

[0060] This makes it possible to further reduce the resistance of the first connection wiring 13D connected by the first wiring layer 27 of the pixel substrate 2D, and to further suppress voltage drop and distortion of the clock signal waveform.

[0061] [Embodiment 4] In the fourth embodiment, a wiring structure is provided in which a first terminal 6 and a second terminal 7 of the same node present in a circuit of the pixel substrate 2 are connected via an empty space in the second wiring layer 28 of the logic substrate 3. The positions of the pixel substrate 2 and the logic substrate 3 are reversed in the solid-state imaging devices 1, 1A, 1B, and 1C according to the first to third embodiments described above. The fabrication procedure and effects of the structure according to the fourth embodiment are also the same as those of the first to third embodiments.

[0062] 11 is a detailed cross-sectional view of a solid-state imaging device 1E according to embodiment 4. Components similar to those described above are denoted by the same reference numerals, and detailed description thereof will not be repeated.

[0063] The solid-state imaging element 1E includes a pixel substrate 2 having a pixel array 4 and a pixel readout circuit 45 (pixel circuit) associated with the pixel array 4, a logic substrate 3 having a logic circuit 8 associated with the pixel array 4 and stacked on the pixel substrate 2, and a junction 5 that electrically connects the pixel substrate 2 and the logic substrate 3 by joining the top layer wiring of the pixel substrate 2 and the logic substrate 3 so that they face each other.

[0064] The pixel readout circuit 45 has a first terminal 46 and a second terminal 47, which are the same node. The node of the first terminal 46 and the second terminal 47 is a node that is used only on the pixel substrate 2 for circuit operation.

[0065] The joint 5 includes a first wiring 48 that connects the first terminal 46 to the logic board 3, and a second wiring 49 that connects the second terminal 47 to the logic board 3. The logic board 3 includes a first connection wiring 50 that connects the first wiring 48 and the second wiring 49.

[0066] 12 is a detailed cross-sectional view of a solid-state imaging device 1F according to embodiment 4. Components similar to those described above are denoted by the same reference numerals, and detailed description thereof will not be repeated.

[0067] The pixel substrate 2 includes a first wiring layer 27. The logic substrate 3 includes a second wiring layer 28. The first terminal 46 and the second terminal 47 are not electrically connected by the first wiring layer 27. The first terminal 46 and the second terminal 47 are electrically connected only by the second wiring layer 28.

[0068] 13 is a detailed cross-sectional view of a solid-state imaging device 1G according to embodiment 4. Components similar to those described above are given the same reference numerals, and detailed description thereof will not be repeated.

[0069] The joint 5 further includes a third wire 52 that connects the first terminal 46 to the logic board 3 and a fourth wire 53 that connects the second terminal 47 to the logic board 3 .

[0070] 14 is a detailed cross-sectional view of a solid-state imaging device 1H according to embodiment 4. Components similar to those described above are denoted by the same reference numerals, and detailed description thereof will not be repeated.

[0071] The solid-state imaging device 1H includes a pixel readout circuit 45H. The pixel readout circuit 45H has a third terminal 46H and a fourth terminal 47H which are the same node as the other terminals.

[0072] The joint 5 includes a fifth wiring 48H that connects the third terminal 46H to the logic board 3, and a sixth wiring 49H that connects the fourth terminal 47H to the logic board 3. The logic board 3 includes a third connection wiring 50H that connects the fifth wiring 48H and the sixth wiring 49H.

[0073] (Variation) The solid-state imaging devices according to the above-described first to fourth embodiments can be combined in any desired manner.

[0074] [Embodiment 5] 15 is a schematic diagram of a camera 54 (electronic device) according to embodiment 5. Components similar to those described above are given the same reference numerals, and detailed description thereof will not be repeated.

[0075] The camera 54 includes a solid-state imaging device 1 and a lens 55 that collects light 56 ​​from a subject onto a pixel array 4 provided on a pixel substrate 2 of the solid-state imaging device 1 as incident light.

[0076] 16 is a block diagram of the camera 54. Components similar to those previously described are given the same reference numerals, and detailed descriptions thereof will not be repeated.

[0077] A camera 54 according to a fifth embodiment includes a lens 55, a solid-state imaging device 1, a data processing unit 57 including a DSP (Digital Signal Processor) that performs various processes (e.g., demosaicing) on ​​data generated by the solid-state imaging device 1 to generate image data, a frame memory 58 that stores data when the data processing unit 57 processes it, a display unit 59 that displays image data and images for operation generated by the data processing unit 57, a recording unit 60 that records the image data generated by the data processing unit 57 as needed, an operation unit 61 including buttons, a touch panel, and the like for accepting user operations, a power supply unit 62 that supplies power for operating the camera 54, a control unit 63 that controls the operation of the camera 54, and a bus 64 that connects the above-mentioned units. The camera 54 may be configured such that part of the data processing unit 57 is provided on the logic board 3 of the solid-state imaging device 1.

[0078] First, light incident from the direction of the subject is collected by the lens 55 and forms an image on the solid-state imaging device 1. Then, a signal photoelectrically converted by the solid-state imaging device 1 is output to a display or the like via a signal processing circuit including a data processing unit 57.

[0079] 〔summary〕 Solid-state imaging devices 1, 1A to 1D according to a first aspect of the present invention comprise a pixel substrate 2 having a pixel array 4 in which unit pixels 17, each including a photoelectric conversion element (photodiode 18), are arranged in a matrix; a logic substrate 3 having a logic circuit 8 associated with the pixel array 4 and stacked on the pixel substrate 2; and a junction 5 in which the pixel substrate 2 and the logic substrate 3 are joined together so that their respective top-layer wiring faces each other, electrically connecting the pixel substrate 2 and the logic substrate 3; the logic circuit 8 (timing generation circuit 14) has a first terminal 6 and a second terminal 7, which are the same node, respectively, and the node of the first terminal 6 and the second terminal 7 is a node used for circuit operation only on the logic substrate 3; the junction 5 includes a first wiring 11 connecting the first terminal 6 to the pixel substrate 2 and a second wiring 12 connecting the second terminal 7 to the pixel substrate 2; and the pixel substrate 2 includes first connection wiring 13 and 13B connecting the first wiring 11 and the second wiring 12.

[0080] According to the above configuration, the first terminal and the second terminal, which are the same node of the logic circuit provided on the logic substrate, are connected via the first connection wiring provided on the pixel substrate. Therefore, when free space is generated in the pixel circuit stacked on the logic circuit, the free space can be effectively used for connecting the first terminal and the second terminal of the logic circuit. As a result, it is possible to increase the degree of freedom of wiring, optimize the layout area, and suppress the resistance on the wiring.

[0081] In the solid-state imaging elements 1, 1A, and 1B of aspect 2 of the present invention, in the above-mentioned aspect 1, it is preferable that the pixel substrate 2 includes a first wiring layer 27, the logic substrate 3 includes a second wiring layer 28, the first terminal 6 and the second terminal 7 are not electrically connected by the second wiring layer 28, and the first terminal 6 and the second terminal 7 are electrically connected only by the first wiring layer 27.

[0082] According to the above configuration, when it is difficult in terms of layout to secure space on the logic substrate for wiring connecting the first and second terminals of the logic circuit, the layout area can be minimized by using only the first wiring layer of the pixel substrate to make the connection in the available space.

[0083] In the solid-state imaging element 1A of aspect 3 of the present invention, in aspect 1 or 2 above, it is preferable that the logic circuit 8 includes a pixel driving circuit 9 for driving the unit pixel 17 and a signal processing circuit 10 for processing signals output from the pixel array 4, and the junction 5 further includes a third wiring 41 connecting the first terminal 6 to the pixel substrate 2 and a fourth wiring 42 connecting the second terminal 7 to the pixel substrate 2.

[0084] According to the above configuration, the first terminal of the logic circuit can be connected to the pixel substrate via a plurality of junctions, and the second terminal can be connected to the pixel substrate via a plurality of junctions.

[0085] In the solid-state imaging devices 1, 1A to 1D according to aspect 4 of the present invention, in any one of aspects 1 to 3 above, it is preferable that the first terminal 6 is one of a power supply terminal and a ground terminal, and the second terminal 7 is the other of the power supply terminal and the ground terminal.

[0086] According to the above configuration, the line width of the power supply wiring and ground wiring of a circuit that consumes high power can be made sufficiently wide.

[0087] A solid-state imaging element 1B according to aspect 5 of the present invention is preferably any one of aspects 1 to 4 above, wherein the logic circuit 8 further has a third terminal 6B and a fourth terminal 7B which are the same node, the junction 5 further includes a fifth wiring 11B connecting the third terminal 6B to the pixel substrate 2 and a sixth wiring 12B connecting the fourth terminal 7B to the pixel substrate 2, and the pixel substrate 2 further includes a third connection wiring 13B connecting the fifth wiring 11B and the sixth wiring 12B.

[0088] According to the above configuration, it is possible to increase the degree of freedom in wiring of two or more pairs of first terminals and second terminals, each having a different node from each other, thereby optimizing the layout area and suppressing the resistance on the wiring.

[0089] A solid-state imaging element 1D according to aspect 6 of the present invention is preferably such that, in aspect 2 above, the first wiring layer 27 is a multi-layer wiring layer, the first connection wiring 13D is formed in at least one layer of the multi-layer wiring layer, and the first connection wiring 13D has a structure in which it is connected in a grid-like pattern, crossing vertically and horizontally.

[0090] According to the above configuration, by laying out wires each having a narrow line width in a grid pattern, it is possible to realize a layout that minimizes wiring resistance while adhering to layout rules.

[0091] Solid-state imaging devices 1E to 1H according to a seventh aspect of the present invention each include a pixel substrate 2 having a pixel array 4 in which unit pixels 17, each including a photoelectric conversion element (photodiode 18), are arranged in a matrix, a pixel circuit (pixel readout circuit 45) associated with the pixel array 4, and a logic circuit 8 associated with the pixel array 4, and a logic substrate 3 laminated on the pixel substrate 2, and a bonding layer for electrically connecting the pixel substrate 2 and the logic substrate 3 by bonding the uppermost wirings of the pixel substrate 2 and the logic substrate 3 so that they face each other. the pixel circuit (pixel readout circuit 45) has a first terminal 46 and a second terminal 47 which are the same node, the node of the first terminal 46 and the second terminal 47 is a node used for circuit operation only on the pixel substrate 2, the junction 5 includes a first wiring 48 which connects the first terminal 46 to the logic substrate 3 and a second wiring 49 which connects the second terminal 47 to the logic substrate 3, and the logic substrate 3 includes a first connection wiring 50 which connects the first wiring 48 and the second wiring 49.

[0092] According to the above configuration, the first terminal and the second terminal, which are the same node of the pixel circuit provided on the pixel substrate, are connected via the first connection wiring provided on the logic substrate. Therefore, when free space is generated in the logic circuit stacked on the pixel circuit, the free space can be effectively used for connecting the first terminal and the second terminal of the pixel circuit. As a result, it is possible to increase the degree of freedom of wiring, optimize the layout area, and suppress the resistance on the wiring.

[0093] A solid-state imaging element 1F relating to aspect 8 of the present invention is preferably such that, in aspect 7 above, the pixel substrate 2 includes a first wiring layer 27, the logic substrate 3 includes a second wiring layer 28, and the first terminal 46 and the second terminal 47 are not electrically connected by the first wiring layer 27, and the first terminal 46 and the second terminal 47 are electrically connected only by the second wiring layer 28.

[0094] A solid-state imaging element 1G according to aspect 9 of the present invention is preferably such that, in aspect 7 or 8 above, the logic circuit 8 includes a pixel driving circuit 9 for driving the unit pixel 17 and a signal processing circuit 10 for processing signals output from the pixel array 4, and the junction 5 further includes a third wiring 52 connecting the first terminal 46 to the logic board 3 and a fourth wiring 53 connecting the second terminal 47 to the logic board 3.

[0095] In the solid-state imaging elements 1E to 1H according to aspect 10 of the present invention, in any one of aspects 7 to 9 above, it is preferable that the first terminal 46 is one of a power supply terminal and a ground terminal, and the second terminal 47 is the other of the power supply terminal and the ground terminal.

[0096] A solid-state imaging element 1H according to aspect 11 of the present invention is preferably any one of aspects 7 to 10 above, wherein the pixel circuit (pixel readout circuit 45) has a third terminal 46H and a fourth terminal 47H which are the same node, the junction 5 includes a fifth wiring 48H connecting the third terminal 46H to the logic board 3 and a sixth wiring 49H connecting the fourth terminal 47H to the logic board 3, and the logic board 3 includes a third connection wiring 50H connecting the fifth wiring 48H and the sixth wiring 49H.

[0097] In a solid-state imaging element 1D according to aspect 12 of the present invention, in the above aspect 8, it is preferable that the second wiring layer 28 is a multi-layer wiring layer, the first connection wiring 50 is formed in at least one layer of the multi-layer wiring layer, and the first connection wiring 50 has a structure in which it is connected in a grid-like, crossing pattern.

[0098] An electronic device (camera 54) according to a thirteenth aspect of the present invention includes the solid-state imaging devices 1·1A to 1H according to any one of the first to twelfth aspects of the present invention.

[0099] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment. [Explanation of symbols]

[0100] 1. Solid-state imaging element 2 Pixel substrate 3 Logic Board 4 pixel array 5 Joint 6 1st terminal 6B 3rd terminal 7 2nd terminal 7B 4th terminal 8 Logic Circuits 9 Pixel driving circuit 10 Signal processing circuit 11 1st wiring 11B 5th wiring 12 2nd wiring 12B 6th wiring 13 First connection wiring 13B Third connection wiring 17 unit pixels 18 Photodiode (photoelectric conversion element) 24 Second connection wiring 27 1st wiring layer 28 2nd wiring layer 41 3rd wiring 42 4th wiring 45 Pixel readout circuit (pixel circuit) 46 1st terminal 47 2nd terminal 48 1st wiring 49 2nd wiring 50 First connection wiring 52 3rd wiring 53 4th wiring 54 Camera (electronic device)

Claims

1. a pixel substrate having a pixel array in which unit pixels each including a photoelectric conversion element are arranged in a matrix; a logic substrate having logic circuits associated with the pixel array and stacked on the pixel substrate; a joint portion that electrically connects the pixel substrate and the logic substrate by joining the uppermost wirings of the pixel substrate and the logic substrate so that the uppermost wirings of the pixel substrate and the logic substrate face each other, the logic circuit has a first terminal and a second terminal, each of which is the same node; a node of the first terminal and the second terminal is a node used for circuit operation only on the logic board, a first wiring, the junction connecting the first terminal to the pixel substrate; a second wiring connecting the second terminal to the pixel substrate; The pixel substrate includes a first connection wiring that connects the first wiring and the second wiring.

2. the pixel substrate includes a first wiring layer; the logic board includes a second wiring layer; the first terminal and the second terminal are not electrically connected in the second wiring layer; 2. The solid-state imaging device according to claim 1, wherein the first terminal and the second terminal are electrically connected only through the first wiring layer.

3. the logic circuit includes a pixel driving circuit for driving the unit pixel; a signal processing circuit for processing a signal output from the pixel array; a third wiring, the junction connecting the first terminal to the pixel substrate; 3. The solid-state imaging device according to claim 1, further comprising a fourth wiring that connects the second terminal to the pixel substrate.

4. the first terminal is one of a power terminal and a ground terminal, 4. The solid-state imaging device according to claim 1, wherein the second terminal is the other of the power supply terminal and the ground terminal.

5. the logic circuit further has a third terminal and a fourth terminal, each of which is the same node; a fifth wiring, the junction connecting the third terminal to the pixel substrate; a sixth wiring connecting the fourth terminal to the pixel substrate; The solid-state imaging device according to claim 1 , wherein the pixel substrate further includes a third connection wiring that connects the fifth wiring and the sixth wiring.

6. the first wiring layer is a multi-layer wiring layer, the first connection wiring is formed in at least one layer of the multilayer wiring layer, 3. The solid-state imaging device according to claim 2, wherein the first connection wirings are connected in a grid-like intersecting pattern.

7. a pixel substrate having a pixel array in which unit pixels each including a photoelectric conversion element are arranged in a matrix, and a pixel circuit associated with the pixel array; a logic substrate having logic circuits associated with the pixel array and stacked on the pixel substrate; a joint portion that electrically connects the pixel substrate and the logic substrate by joining the uppermost wirings of the pixel substrate and the logic substrate so that the uppermost wirings of the pixel substrate and the logic substrate face each other, the pixel circuit has a first terminal and a second terminal that are the same node, a node of the first terminal and the second terminal is a node used for circuit operation only on the pixel substrate, the junction portion is a first wiring that connects the first terminal to the logic board; a second wiring connecting the second terminal to the logic board; The solid-state imaging device, wherein the logic board includes a first connection wiring that connects the first wiring and the second wiring.

8. the pixel substrate includes a first wiring layer; the logic board includes a second wiring layer; the first terminal and the second terminal are not electrically connected in the first wiring layer; 8. The solid-state imaging device according to claim 7, wherein the first terminal and the second terminal are electrically connected only through the second wiring layer.

9. the logic circuit includes a pixel driving circuit for driving the unit pixel; a signal processing circuit for processing a signal output from the pixel array; a third wiring, the junction connecting the first terminal to the logic board; 9. The solid-state imaging device according to claim 7, further comprising a fourth wiring that connects the second terminal to the logic board.

10. the first terminal is one of a power terminal and a ground terminal, 10. The solid-state imaging device according to claim 7, wherein the second terminal is the other of the power supply terminal and the ground terminal.

11. the pixel circuit has a third terminal and a fourth terminal which are the same node; a fifth wiring, the junction connecting the third terminal to the logic board; a sixth wiring connecting the fourth terminal to the logic board; 11. The solid-state imaging device according to claim 7, wherein the logic board includes a third connection wiring that connects the fifth wiring and the sixth wiring.

12. the second wiring layer is a multi-layer wiring layer, the first connection wiring is formed in at least one layer of the multilayer wiring layer, 9. The solid-state imaging device according to claim 8, wherein the first connection wirings are connected in a crossing manner in a lattice pattern.

13. An electronic device comprising the solid-state imaging device according to claim 1 .

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