Image sensor device

Abstract

To provide an image sensor device with reduced cost, improved reliability, improved performance, and the like.SOLUTION: The image sensor device includes: a first digital pixel including a first optical detector and a first memory cell configured to store a first digital signal corresponding to a first output from the first optical detector; and a second digital pixel including a second optical detector and a second memory cell configured to store a second digital signal corresponding to a second output from the second optical detector, and disposed adjacent to the first digital pixel on a first direction side. The first and second memory cells are connected to a plurality of bit lines. The first memory cell is connected to first and third word lines. The second memory cell is connected to second and fourth word lines. The second word line is positioned between the first and the third word lines. The third word line is positioned between the second and the fourth word lines.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to semiconductor devices, and more particularly to image sensor devices. [Background technology]

[0002] Image sensors can convert optical signals into electrical signals. With the recent development of the computer and communications industries, there is an increasing demand for image sensors with improved performance in a variety of fields, including digital cameras, video cameras, smartphones, tablet PCs, laptops, game consoles, security cameras, and medical micro cameras.

[0003] Conventional image sensors operate based on analog pixels. Each analog pixel outputs an analog signal corresponding to an optical signal, which is then converted into a digital signal. However, analog signals are more susceptible to noise and coupling than digital signals, making them difficult to process high-resolution image signals. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 9,986,181 [Patent Document 2] U.S. Patent No. 8,729,448 [Patent Document 3] U.S. Patent No. 10,021,331 [Patent Document 4] U.S. Patent No. 7,244,918 [Patent Document 5] U.S. Patent No. 8,773,562 [Patent Document 6] U.S. Patent No. 10,182,198 [Patent Document 7] U.S. Patent No. 9,911,781 [Patent Document 8] U.S. Patent No. 9,654,713 [Patent Document 9] U.S. Patent No. 7,924,333 [Patent Document 10] U.S. Patent No. 9,972,652 Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention has been made in consideration of the above-mentioned conventional techniques, and an object of the present invention is to provide an image sensor device having reduced costs, improved reliability, improved performance, etc. [Means for solving the problem]

[0006] An image sensor device according to an embodiment of the present invention includes: a first digital pixel including a first photodetector and a first memory cell configured to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel located adjacent to the first digital pixel in a first direction, the second digital pixel including a second photodetector and a second memory cell configured to store a second digital signal corresponding to a second output from the second photodetector. The first memory cell and the second memory cell are connected to a plurality of bit lines, the first memory cell is connected to first and third word lines, respectively, and the second memory cell is connected to second and fourth word lines, respectively, the second word line is located between the first word line and the third word line, and the third word line is located between the second word line and the fourth word line.

[0007] An image sensor device according to an embodiment of the present invention includes: a first digital pixel including a first photodetector and a first memory cell configured to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and a second memory cell configured to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel being adjacent to the first digital pixel in a first direction. The first memory cell and the second memory cell are formed on a first semiconductor wafer. The first semiconductor wafer includes: a first region including the first memory cell; a second region including the second memory cell and located in the first direction from the first region; a first shared dummy pattern region located between the first region and the second region; a first dummy pattern region located adjacent to the first region in the opposite direction to the first direction; and a second dummy pattern region located adjacent to the second region in the first direction. The first width of the first shared dummy pattern region along the first direction is smaller than twice the second width of the first dummy pattern region along the first direction or twice the third width of the second dummy pattern region along the second direction.

[0008] An image sensor device according to an embodiment of the present invention includes: a first digital pixel including a first photodetector and a first memory cell configured to store a first digital signal corresponding to a first detection signal from the first photodetector; and a second digital pixel including a second photodetector and a second memory cell configured to store a second digital signal corresponding to a second detection signal from the second photodetector, the second digital pixel being located adjacent to the first digital pixel along a first direction, the first memory cell and the second memory cell being included in a single memory cell array.

[0009] An image sensor device according to an embodiment of the present invention includes a first digital pixel including a first photodetector and a first memory cell configured to store a first digital signal corresponding to a first detection signal from the first photodetector, and a second digital pixel including a second photodetector and a second memory cell configured to store a second digital signal corresponding to a second detection signal from the second photodetector, wherein the second digital pixel is adjacent to the first digital pixel along a first direction, a dummy memory cell is located between the first memory cell and the second memory cell, and the dummy memory cell, the first memory cell, and the second memory cell are included in a single memory cell array. [Effects of the Invention]

[0010] According to an embodiment of the present invention, digital pixels included in an image sensor device share one memory cell region or one memory cell array. This reduces the area of ​​the dummy cell or dummy pattern region required to maintain the reliability of the memory cells, and the reduced area can be used for the peripheral region to form other components. As the area of ​​the peripheral region increases, the reliability of components formed in the peripheral region can be improved, or other components can be added to perform additional functions of the digital pixel. Therefore, an image sensor device with reduced cost, improved reliability, improved performance, etc. is provided. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating an image sensor device according to an embodiment of the present invention. [Figure 2A] 2 is an exemplary block diagram of the pixel driver of FIG. 1; FIG. [Figure 2B] FIG. 2 is a block diagram illustrating the digital logic circuit of FIG. 1 as an example. [Figure 3A] 2 is a diagram for explaining the digital pixel of FIG. 1 in more detail; [Figure 3B]2 is a diagram for explaining the digital pixel of FIG. 1 in more detail; [Figure 3C] 2 is a diagram for explaining the digital pixel of FIG. 1 in more detail; [Figure 3D] 2 is a diagram for explaining the digital pixel of FIG. 1 in more detail; [Figure 4A] 2 is a diagram illustrating an example of the configuration of a pixel array 110 of FIG. 1; [Figure 4B] 2 is a diagram illustrating an example of the configuration of a pixel array 110 of FIG. 1; [Figure 5A] 4B is a plan view showing a schematic layout of the upper and lower wafers included in the pixel array of FIG. 4A. FIG. [Figure 5B] FIG. 4B is a plan view showing a schematic layout of the lower wafer included in the pixel array of FIG. 4A. [Figure 5C] FIG. 4B is a plan view showing a schematic layout of the lower wafer included in the pixel array of FIG. 4A. [Figure 6] 4B is a plan view showing an example layout of the upper and lower wafers of the pixel array of FIG. 4A. FIG. [Figure 7A] FIG. 7 is a plan view showing in more detail the layout of the memory cell region shown in FIG. 6. [Figure 7B] 7B is a plan view of an exemplary bottom wafer reflecting the memory cell region of FIG. 7A. FIG. [Figure 8] FIG. 7 is a plan view showing an example of the layout of the memory cell region of FIG. 6. [Figure 9] 2 is a diagram illustrating an example of a structure in which digital pixels included in the pixel array of FIG. 1 share a comparator; [Figure 10A] 4B is a plan view showing an example layout of the lower wafer and memory cell region of FIG. 4A. FIG. [Figure 10B] 4B is a plan view showing an example layout of the lower wafer and memory cell region of FIG. 4A. FIG. [Figure 11A] 4B is a plan view showing an example layout of the lower wafer and memory cell region of FIG. 4A. FIG. [Figure 11B] 4B is a plan view showing an example layout of the lower wafer and memory cell region of FIG. 4A. FIG. [Figure 12] 1 is a plan view illustrating an example of a memory cell region according to an embodiment of the present invention. [Figure 13] 1 is a plan view illustrating an example of a memory cell region according to an embodiment of the present invention. [Figure 14A] 1 is a plan view illustrating an example layout of a lower wafer and a memory cell region according to an embodiment of the present invention; [Figure 14B] 1 is a plan view illustrating an example layout of a lower wafer and a memory cell region according to an embodiment of the present invention; [Figure 15A] 2 is a plan view illustrating an example of a layout of an upper wafer and a lower wafer of an image sensor device according to an embodiment of the present invention; [Figure 15B] 2 is a plan view illustrating an example of a layout of an upper wafer and a lower wafer of an image sensor device according to an embodiment of the present invention; [Figure 16A] FIG. 2 is a perspective view showing the image sensor device of FIG. 1 as an example. [Figure 16B] FIG. 2 is a plan view showing the image sensor device of FIG. 1 as an example. [Figure 17] 1 is a block diagram illustrating an example of an electronic device to which an image sensor device according to an embodiment of the present invention is applied; DETAILED DESCRIPTION OF THE INVENTION

[0012] In the following, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

[0013] 1 is a block diagram illustrating an image sensor device according to an embodiment of the present invention. Referring to FIG. 1, the image sensor device 100 may include a pixel array 110, a pixel driver 120, and a digital logic circuit 130. In an example embodiment, the image sensor device 100 may be a camera module included in various electronic devices, such as a CCTV, a black box, a digital camera, a smartphone, a tablet PC, a laptop, etc.

[0014] The pixels of a conventional CIS (CMOS Image Sensor)-based image sensor output an analog signal based on the optical signal. The analog signal from the pixels of the CIS-based image sensor is converted into a digital signal by a separate analog-to-digital converter arranged in columns. In this case, noise and coupling may occur during the transfer of the analog signal from the pixels of the CIS-based image sensor to the analog-to-digital conversion circuit, which may result in a decrease in the quality of the final image.

[0015] The pixel array 110 according to the embodiment of the present invention may include a plurality of digital pixels (DPs), each of which may be configured to detect an external optical signal and output a digital signal (DOUT) corresponding to the detected optical signal.

[0016] For example, a digital pixel (DP) may include a photodetector (PDT), an analog-to-digital converter (ADC), and a memory circuit (MCT). The photodetector (PDT) may be configured to convert an externally detected optical signal into an electrical signal, i.e., an analog signal. The analog-to-digital converter (ADC) is configured to convert the analog signal output from the photodetector (PDT) into a digital signal. The memory circuit (MCT) is configured to store the digital signal (DOUT) converted by the analog-to-digital converter (ADC) and output the stored digital signal (DOUT). As described above, the digital pixel (DP) according to an embodiment of the present invention can output a digital signal (DOUT) at the pixel level, unlike pixels in conventional CIS images.

[0017] The pixel driver 120 can output various control signals (CTRL) (e.g., photodetector control signals, memory control signals, ramp signals, count information, etc.) to control the plurality of digital pixels (DP) included in the pixel array 110. Based on the control signals (CTRL) generated by the pixel driver 120, each of the plurality of digital pixels (DP) can perform a series of pixel operations or image detection operations, such as detecting a light signal to generate an analog signal, converting the analog signal to a digital signal, storing the digital signal, and outputting the stored digital signal.

[0018] The digital logic circuit 130 may perform digital signal processing on the digital signal (DOUT) received from the pixel array 130 and provide a final image to an external device (e.g., an image signal processor (ISP), an application processor (AP), etc.). In an example embodiment, the digital logic circuit 130 may provide drive signals to the pixel driver 120 under the control of the external device. The pixel driver 120 may operate in response to the drive signals.

[0019] As described above, unlike conventional CIS devices, each of the digital pixels (DP) according to an embodiment of the present invention can generate and output a digital signal (DOUT) at the pixel level. Therefore, distortion of the digital signal (DOUT) output from the digital pixels 110 is reduced, and image signals can be processed at high speed. In other words, the digital signal (DOUT) output from the digital pixels (DP) may be less sensitive (unaffected) by noise and coupling.

[0020] Figure 2A is an example block diagram of the pixel driver of Figure 1. Referring to Figures 1 and 2A, the pixel driver 120 may include a counter 121, a row driver 122, a ramp generator 123, and a voltage generator 124.

[0021] The counter 121 can sequentially increase or decrease the value of the code (CODE) in response to a predetermined clock (e.g., an operation clock or a system clock) for a predetermined time, i.e., the value of the code (CODE) can change sequentially over time.

[0022] The row driver 122 can generate control signals for controlling each of the digital pixels (DP). For example, the row driver 122 can generate photodetector control signals (CS-PD) for controlling the photodetectors (PDT) of each of the digital pixels (DP). The row driver 122 can generate memory control signals (CD-MC) for controlling the memory circuits (MCT) of each of the digital pixels (DP).

[0023] The ramp generator 123 can generate a ramp signal (VRAMP), which is used as a reference signal to which the analog signal is compared in the digital pixel (DP). In an example embodiment, the ramp signal (VRAMP) can be a steadily decreasing or increasing signal (i.e., an increasing / decreasing signal with a single slope).

[0024] The voltage generator 124 may be configured to generate various voltages (eg, a power supply voltage (VDDA), a bias voltage (VB), etc.) required for the image sensor device 100 to operate.

[0025] The photodetector control signal (CS-PD), memory circuit (CS-MC), code (CODE), ramp signal (VRAMP), etc. may be included in the control signal (CTRL) described with reference to Figure 1. In an example embodiment, each of the multiple digital pixels (DP) included in the pixel array 110 may operate based on various signals (CODE, CS-PD, CS-MC, VRAMP, VDDA, VB, etc.) generated from the pixel driver 120 described with reference to Figure 2A.

[0026] Fig. 2B is a block diagram illustrating an example of the digital logic circuit of Fig. 1. Referring to Fig. 1 and Fig. 2B, the digital logic circuit 130 may include a sensor controller 131, a digital signal processing unit 132, and an input / output interface 133.

[0027] The sensor controller 131 is configured to control various operations of the image sensor device 100. For example, the sensor controller 131 can control various operations of the image sensor device 100 based on control information (CI) provided from an external device (e.g., an ISP, an AP, etc.) via the input / output interface 133. The sensor controller 131 can be a timing controller for controlling the operation timing of the pixel driver 120. In an example embodiment, the pixel driver 120 can generate the various signals described above based on the timing signal from the sensor controller 131.

[0028] The digital signal processor 132 may receive a digital signal (DOUT) from the pixel array 110 and perform digital signal processing on the received digital signal (DOUT).

[0029] In an exemplary embodiment, the digital signal (DOUT) output from one digital pixel 110 may include a reset sampling value and a signal sampling value. The digital signal processor 132 can perform arithmetic processing on the reset sampling value and the signal sampling value to determine a final digital value corresponding to the optical signal detected by one digital pixel (DP).

[0030] The final digital values ​​determined for each of the plurality of digital pixels are combined to generate final image data (IMG). That is, a correlated double sampling (CDS) operation can be performed through a digital signal (DOUT) generated by the operation of an analog-to-digital converter (ADC) or a comparator included in the digital pixel (DP) and a digital signal processing operation of a digital signal processing unit 132 included in the digital logic circuit 130.

[0031] The input / output interface 133 may be configured to receive control information (CI) from an external device (e.g., an ISP, AP, etc.) or to output final image data (IMG). In an example embodiment, the input / output interface 330 may exchange the above-described information with an external device based on a predetermined protocol. In an example embodiment, the input / output interface 330 may include a physical layer for supporting the above-described predetermined protocol.

[0032] 3A to 3D are diagrams for explaining the digital pixel of FIG. 1 in more detail. For the sake of simplicity of the drawings and ease of explanation, one digital pixel (DP) is described, but the scope of the present invention is not limited thereto. Furthermore, to easily explain the technical concept of the present invention, the structure or operation of the digital pixel (DP) is described based on an example circuit diagram or block diagram, but the scope of the present invention is not limited thereto, and the digital pixel (DP) may be modified into various forms.

[0033] Referring to FIGS. 1, 2, and 3A to 3D, the digital pixel (DP) may include a photodetector (PDT), a comparator (COMP), and a memory circuit (MCT).

[0034] The photodetector (PDT) is configured to output a detection signal (DET) in response to a pixel control signal (CS-PD) from the pixel driver 120. For example, as shown in FIG. 3B , the photodetector (PDT) may include a photodiode (PD), a transfer transistor (TX), and a reset transistor (RX). The photodiode (PD) is connected between a ground node and the transfer transistor (TX) and configured to accumulate photocharges in response to the intensity of externally incident light. The transfer transistor (TX) is connected between the floating diffusion node (FD) and the photodiode (PD) and may operate in response to a transfer signal (TG). For example, the transfer transistor (TX) may be configured to transfer the charge accumulated in the photodiode (PD) to the floating diffusion node (FD) in response to the transfer signal (TG). The reset transistor (RX) is connected between a power supply voltage (VDDA) and the floating diffusion node (FD) and may operate in response to a reset signal (RG). For example, the reset transistor (RX) resets the voltage level of the floating diffusion node (FD) in response to the reset signal (RG). In an example embodiment, the pixel control signal (CS-PD) may include the transfer signal (TG) and reset signal (RG) described above. In an example embodiment, the voltage of the floating diffusion node (FD) (i.e., VFD) may change depending on the operation of the photodetector (PDT), which may be output as the detection signal (DET).

[0035] The comparator (COMP) compares the detection signal (DET) from the photodetector (PDT) (or the voltage (VFD) of the floating diffusion node (FD)) with the ramp signal (VRAMP) and outputs a comparison signal (COMP-OUT) based on the comparison result.

[0036] In an exemplary embodiment, the comparator (COMP) may be implemented as a low-power comparator. For example, as shown in FIG. 3B, the comparator 112 may include first to third PMOS transistors (MP1 to MP3) and first to fourth NMOS transistors (MN1 to MN4). The first PMOS transistor (MP1), the first NMOS transistor (MN1), and the third NMOS transistor (MN3) are serially coupled between a power supply voltage (VDDA) and a ground voltage (GND). The gate of the first PMOS transistor (MP1) is coupled between the first PMOS transistor (MP1) and the first NMOS transistor (MN1). The gate (MN1) of the first NMOS transistor (MN1) is coupled to the floating diffusion node (FD) and configured to receive the detection signal (DET). The gate of the third NMOS transistor (NM3) may be configured to receive a bias voltage (VB). The second PMOS transistor (MP2) and the second NMOS transistor (MN2) are connected in series between the power supply voltage (VDDA) and the ground voltage. The gate of the second PMOS transistor (MP2) is connected to the gate of the first PMOS transistor (MP1). The gate of the second NMOS transistor (MN2) is configured to receive a ramp signal (VRAMP). The third PMOS transistor (MP3) and the fourth NMOS transistor (MN4) are connected in series between the power supply voltage and the ground voltage. The gate of the third PMOS transistor (MP3) is connected between the second PMOS transistor (MP2) and the second NMOS transistor (MN2). The gate of the fourth NMOS transistor (MN4) may be configured to receive a bias voltage (VB).

[0037] In the comparator (COMP) as shown in FIG. 3B, when the detection signal (DET) is lower than the ramp signal (VRAMP), the comparison signal (COMP-OUT) can have a high level logic, and when the detection signal (DET) is higher than the ramp signal (VRAMP), the comparison signal (COMP-OUT) can have a low level logic.

[0038] 3B is for illustrative purposes only and is not intended to limit the scope of the present invention. The comparator 112 may have various types of comparator or differential amplifier structures configured to compare the detection signal (DET) with the ramp signal (VRAMP) and output a comparison signal (COMP-OUT) based on the comparison result.

[0039] The memory circuit (MCT) is configured to store a code (CODE) or output the stored code as a digital signal (DOUT) in response to a comparison signal (COMP-OUT) and a memory control signal (CS-MC). For example, as shown in FIG. 3B, the memory circuit (MCT) may include first and second selection circuits (SEL1, SEL2) and a plurality of memory cells (MC1, MC2).

[0040] Each of the plurality of memory cells (MC1, MC2) may be a DRAM, an SRAM, a latch, or various other forms of data storage components (DSC) configured to store a code (CODE) at a specific timing. Each of the plurality of memory cells (MC1, MC2) may be connected to first and second word lines (WL1, WL2) and a bit line (BL). Each of the plurality of memory cells (MC1, MC2) may store the code (CODE) provided via the bit line (BL) according to the levels of the first and second word lines (WL1, WL2), or may output the stored code (CODE) as a digital signal (DOUT) via the bit line (BL).

[0041] In an example embodiment, the number of first memory cells (MC1) among the plurality of memory cells (MC1, MC2) is N (where N is a natural number greater than 2), and the number of second memory cells (MC2) among the plurality of memory cells (MC1, MC2) is M (where M is a natural number). In an example embodiment, the number (N) of first memory cells (MC1) and the number (M) of second memory cells (MC2) can be the same or different.

[0042] In an example embodiment, a first memory cell (MC1) is configured to store a reset sampling value (R), and a second memory cell (MC2) is configured to store a signal sampling value (S). The first memory cell (MC1) is coupled to a first word line (WL1) and a bit line (BL), and the second memory cell (MC2) is coupled to a second word line (WL2) and a bit line (BL).

[0043] The first selection circuit (SEL1) is configured to control the first and second word lines (WL1, WL2) in response to the comparison signal (COMP-OUT) and the memory control signal (CS-MC). For example, as shown in FIG. 3C, the first selection circuit (SEL1) may include first switches (SW1). Each of the first switches (SW1) is configured to provide a first voltage (V1) to either the first word line (WL1) or the second word line (WL2) in response to the comparison signal (COMP-OUT) and the memory control signal (CS-MC). In an example embodiment, the first voltage (V1) may be a high voltage that activates each of the plurality of memory cells (MC1, MC2) (e.g., a high voltage that activates a select transistor if the memory cells are DRAM).

[0044] For example, the memory control signal (CS-MC) may include first and second sampling signals (SMP1, SMP2) and first and second read signals (RD1, RD2). The first sampling signal (SMP1) is a signal for storing a reset sampling value (R) in the first memory cell (MC1), and the second sampling signal (SMP2) is a signal for storing a sampled value (S) of the signal in the second memory cell (MC2). The first read signal (RD1) is a signal for outputting the reset sampling signal (R) stored in the first memory cell (MC1) as a digital signal (DOUT), and the second read signal (RD2) is a signal for outputting the sampled signal of the signal stored in the second memory cell (MC2) as a digital signal (DOUT). However, the scope of the present invention is not limited thereto, and the memory control signal (CS-MC) for controlling the memory circuit 113 may be variously modified.

[0045] When the first sampling signal (SMP1) or the first read signal (RD1) is activated, the first switch (SW1) may provide the first voltage (V1) to the first word line (WL1) in response to the falling edge (or rising edge) of the comparison signal (COMP-OUT), thereby activating the first memory cell (MC1) connected to the first word line (WL1), and the value of the code (CODE) may be stored in the activated first memory cell (MC1), or the value stored in the activated first memory cell (MC1) (e.g., the reset sampling value (R)) may be output.

[0046] When the second sampling signal (SMP2) or the first read signal (RD2) is activated, the first switch (SW1) may provide the second voltage (V2) to the second word line (WL2) in response to the falling edge (or rising edge) of the comparison signal (COMP-OUT), thereby activating the first memory cell (MC2) connected to the second word line (WL2), and the value of the code (CODE) may be stored in the activated second memory cell (MC2), or the value stored in the activated second memory cell (MC2) (e.g., the sampled value (S) of the signal) may be output.

[0047] As described above, the first selection circuit (SEL1) can select at least one group of the first memory cells (MC1) and the second memory cells (MC2) based on the comparison signal (COMP-OUT) and the memory control signal (CS-MC).

[0048] The second selection circuit (SEL2) is configured to provide a code (CODE) to the bit line (BL) or output a digital signal (DOUT) from the bit line (BL) in response to a memory control signal (CS-MC). For example, as shown in FIG. 3C, the second selection circuit (SEL2) may include a second switch (SW2). The second switch (SW2) is configured to connect the bit line (BL) to any group of lines that receive the code (CODE) and lines that output the digital signal (DOUT) in response to the memory control signal (CS-MC).

[0049] For example, when the first sampling signal (SMP1) or the second sampling signal (SMP2) is activated, the second switch (SW2) can connect the bit line (BL) to a line that receives a code (CODE). In this case, the code (CODE) provided from the counter 121 can be provided to the first memory cell (MC1) or the second memory cell (MC2) via the bit line (BL). When the first read signal (RD1) or the second read signal (RD2) is activated, the second switch (SW2) can connect the bit line (BL) to a line that outputs a digital signal (DOUT). In this case, the value stored in the first memory cell (MC1) or the second memory cell (MC2) (e.g., the reset sampled value (R) or the signal sampled value (S)) is output as the digital signal (DOUT).

[0050] In the example embodiment, the first selection circuit (SEL1) and the second selection circuit (SEL2) shown in FIG. 3C are merely examples, and the scope of the present invention is not limited thereto. For example, each of the first and second selection circuits (SEL1, SEL2) may be modified in various ways to store or read information (e.g., a reset sampling value (R) or a signal sampling value (S)) corresponding to a memory cell associated with a digital pixel (DP). In the example embodiment, each of the first and second selection circuits (SEL1, SEL2) may be modified in various ways depending on the number of word lines, the number of bit lines, the word line routing scheme, and the bit line routing scheme. In the example embodiment, the first and second selection circuits (SEL1, SEL2) are illustrated as being included in one pixel (DP), but the scope of the present invention is not limited thereto. For example, the first and second selection circuits (SEL1, SEL2) may be configured to be arranged in pixel group units including a plurality of digital pixels.

[0051] As described above, a digital pixel (DP) according to an embodiment of the present invention may be configured to generate an analog signal corresponding to the amount of light received from an external source, convert the generated analog signal into a digital signal, and output the digital signal. Below, a schematic operation of the digital pixel (DP) will be described with reference to FIG. 3D.

[0052] 3D, the first sampling signal (SMP1) may be activated from the first time point (T1) to the third time point (T3), i.e., a sampling operation for the reset level of the photodetector (PDT) may be performed from the first time point (T1) to the third time point (T3).

[0053] For example, during activation of the first sampling signal (SMP1), the ramp signal generator 123 may output a ramp signal (VRAMP) that decreases steadily (i.e., decreases with a single slope), and the counter 121 may sequentially output codes (CODE) that increase or decrease at predetermined intervals. At this time, at a second time point (T2), the level of the ramp signal (VRAMP) may become smaller than the level (i.e., VFD) of the floating diffusion node (FD) of the photodetector (PDT). In this case, the output signal (COMP-OUT) transitions from a high level to a low level due to the comparison operation of the comparator (COMP). In other words, when the ramp signal (VRAMP) crosses a predetermined threshold, the output signal (COMP-OUT) transitions.

[0054] At the falling edge of the output signal (COMP-OUT) of the comparator (COMP) (i.e., at the second time point (T2)), the first sampling signal (SMP1) is in an activated state, so that the second selection circuit (SEL2) provides the code (CODE) to the bit line (BL), and the first selection circuit (SEL1) can activate the first memory cell (MC1). That is, at the second time point (T2), the value of the code (CODE) is stored in the first memory cell (MC1) as the reset sampling value (R).

[0055] Then, in response to the activated transfer signal (TG) at a fourth time point (T4), the transfer transistor (TX) of the photodetector (PDT) is turned on, and the charge accumulated by the photodiode (PD) can be transferred to the floating diffusion node (FD), thereby causing the level of the floating diffusion node (FD) (i.e., VFD) (or the detection signal (DET)) to decrease by a level corresponding to the transferred charge at the fourth time point (T4).

[0056] Thereafter, the second sampling signal (SMP2) is activated from the fifth time point (T5) to the seventh time point (T7), i.e., a signal sampling operation is performed on the detection signal (DET) from the photodetector (PDT) during the time period from the fifth time point (T5) to the seventh time point (T7).

[0057] For example, as described above, during the activation of the second sampling signal (SMP2), the ramp signal generator 123 may output the ramp signal (VRAMP) and the counter 121 may output the code (CODE). At this time, at the fifth time point (T5), the detection signal (DET) may become lower than the ramp signal (VRAMP). In this case, the output signal (COMP-OUT) of the comparator 112 may transition from a high level to a low level. In other words, the output signal (COMP-OUT) transitions when the ramp signal (VRAMP) previously crosses another predetermined threshold.

[0058] At the falling edge of the output signal (COMP-OUT) of the comparator (COMP) (i.e., the sixth time point (T6)), the second sampling signal (SMP2) is in an active state, so that the second selection circuit (SEL2) provides the code (CODE) to the bit line (BL), and the second selection circuit (SEL2) activates the second memory cell (MC2). That is, at the sixth time point (T6), the value (S) of the code (CODE) can be stored in the second memory cell (MC2).

[0059] Thereafter, during the activation period of the first read signal (RD1), the first selection circuit (SEL1) activates the first memory cell (MC1), and the second selection circuit (SEL2) connects the bit line (BL) to the output signal line (i.e., the line that outputs the digital signal (DOUT)). In this case, the value stored in the first memory cell (MC1) (i.e., the reset sampling value (R)) is output as the digital signal (DOUT). For example, the reset sampling value "R" stored in the first memory cell (MC1) is output as the digital signal (DOUT) between the seventh time point (T7) and the eighth time point (T8).

[0060] Thereafter, during the activation period of the second read signal (RD2), the second selection circuit (SEL2) activates the second memory cell (MC2), and the second selection circuit (SEL2) connects the bit line (BL) to the output signal line. In this case, the value stored in the second memory cell (MC2) (i.e., the sampled value (S) of the signal) is output as a digital signal (DOUT). For example, the sampled value "S" of the signal stored in the second memory cell (MC2) is output as a digital signal (DOUT) between the seventh time point (T7) and the eighth time point (T8).

[0061] Thereafter, at an eighth time point (T8), the reset transistor (TX) is turned on in response to activation of the reset signal (RG), thereby resetting the level (VFD) of the floating diffusion node (FD).

[0062] In an example embodiment, the digital signal (DOUT) output from the memory circuit (MCT) (or the reset sampling value (R) and the signal sampling value (S)) is provided to the digital logic circuit 130 via a sense amplifier (SA). In an example embodiment, the sense amplifiers (SA) are arranged for each column of pixels included in the pixel array 110.

[0063] The structure or operation of the digital pixel (DP) described with reference to Figures 3A to 3D is merely an example, and the scope of the present invention is not limited thereto. The structure or operation of the digital pixel (DP) may be modified in various ways depending on the implementation method of the digital pixel (DP).

[0064] 4A and 4B are diagrams illustrating an example of the configuration of the pixel array 110 of FIG. 1. Referring to FIGS. 1, 4A, and 4B, the pixel array 110 may include an upper wafer (WF-u) and a lower wafer (WF-d). The upper wafer (WF-d) may be stacked on top of the lower wafer (WF-d) (i.e., on the third direction (DR3) side).

[0065] The upper wafer (WF-u) and the lower wafer (WF-d) may each include a semiconductor pattern formed on a semiconductor substrate, where the upper wafer (WF-u) includes a plurality of first pixel circuits (PXC1) and the lower wafer (WF-d) includes a plurality of second pixel circuits (PXC2).

[0066] In an example embodiment, each of the plurality of first pixel circuits (PXC1) is formed in a corresponding first pixel circuit region of the upper wafer (WF-u), and each of the plurality of second pixel circuits (PXC2) is formed in a corresponding second pixel circuit region of the lower wafer (WF-d). Hereinafter, for convenience of explanation, the term "pixel circuit" will be used simply, but the term "pixel circuit" may refer to a corresponding component or a region in which a corresponding component is formed depending on the embodiment or described context.

[0067] Any one of the plurality of first pixel circuits (PXC1) and any one of the plurality of second pixel circuits (PXC2) can constitute one digital pixel (DP). For example, one first pixel circuit (PXC1) included in the upper wafer (WF-u) includes some of the components of one digital pixel (DP) described with reference to FIGS. 3A to 3D, and one second pixel circuit (PXC2) included in the lower wafer (WF-d) includes some of the remaining components of that digital pixel (DP). In an example embodiment, one digital pixel (DP) can be implemented by electrically connecting the first pixel circuit (PXC1) of the upper wafer (WF-u) and the second pixel circuit (PXC2) of the lower wafer (WF-d) to each other. In an example embodiment, the first pixel circuit (PXC1) and the second pixel circuit (PXC2) may be electrically connected to each other via a connection structure (e.g., TVS (through silicon via), Cu-to-Cu bonding, etc.) between the upper wafer (WF-u) and the lower wafer (WF-d).

[0068] In an example embodiment, the first pixel circuit (PXC1) and the second pixel circuit (PXC2) constituting one digital pixel (DP) are arranged to overlap or be aligned with each other on a plane defined by the first and second directions (DR1, DR2). For example, as shown in FIG. 4B, the first pixel circuit (PXC1) of the upper wafer (WF-u) may include part of the photodetector (PDT) and comparator (COMP) of FIG. 3B. In this case, as shown in FIG. 4B, a photodiode (PD) may be formed on the first substrate (SUB1), and a color filter (CF) and a lens (LS) may be formed on top of the photodiode (PD).

[0069] A first pixel circuit layer (PCX-LAY1) may be formed on a lower portion of the first substrate (SUB1). The transfer transistor (TX) and reset transistor (RX) of the photodetector (PDT), as well as a portion of the comparator (COMP), may be formed in the first pixel circuit layer (PCX-LAY1). In an example embodiment, the portion of the comparator (COMP) may include at least one of various transistors included in the comparator (COMP).

[0070] A first metal layer (ML-LAY1) may be formed below the first pixel circuit layer (PCX-LAY1). Metal wiring for connecting various components included in the upper wafer (WF-u) may be formed in the first metal layer (ML-LAY1).

[0071] The lower wafer (WF-d) may be formed on a second substrate (SUB2). For example, the second pixel circuit (PXC2) included in the lower wafer (WF-d) may include a remaining portion of the comparator (COMP) and a memory circuit (MCT). The remaining portion of the comparator (COMP) and the memory circuit (MCT) may be formed in a second pixel circuit layer (PCX-LAY2) on the second substrate (SUB2).

[0072] A second metal layer (ML-LAY2) may be formed on top of the second pixel circuit layer (PCX-LAY2). The second metal layer (ML-LAY2) may include metal wiring for connecting each of the components.

[0073] In an example embodiment, the memory circuit (MCT) of the digital pixel (DP) is included in the second pixel circuit (PXC2) of the bottom wafer (WF-d). In this case, the memory cells (MC) included in the memory circuit (MCT) may be formed in a memory cell area (MCA) located in the second pixel circuit layer (PXC-LAY2), and the remaining components of the second pixel circuit (PCX2) may be formed in the peripheral area (PRA).

[0074] As described above, the pixel array 110 or a plurality of digital pixels of the image sensor device 100 according to the present invention can be implemented by stacking and electrically interconnecting the upper wafer (WF-u) and the lower wafer (WF-d).

[0075] 5A to 5C are plan views showing the schematic layout of an upper wafer and a lower wafer included in a pixel array. For the sake of simplicity and ease of explanation, the layout for four digital pixels is shown in the following drawings, but the scope of the present invention is not limited thereto, and other digital pixels may also be similarly extended.

[0076] Referring to FIG. 5A, the upper wafer (WF-u) includes four first pixel circuits (PXC11, PXC21, PXC31, PXC41), which may be arranged in a 2×2 configuration. The lower wafer (WF-d) includes four second pixel circuits (PXC12, PXC22, PXC32, PXC42), which may be arranged in a 2×2 configuration. Four digital pixels are formed by electrically connecting each of the four first pixel circuits (PXC11-PXC41) to each of the four second pixel circuits (PXC12-PXC42). For example, one digital pixel (DP) may be formed by electrically connecting a first pixel circuit (PXC11) and a second pixel circuit (PXC12).

[0077] In this case, the size, length, or pitch of one first pixel circuit (e.g., PXC11) on the upper wafer (WF-u) may be the same as the size, length, or pitch of one second pixel circuit (e.g., PXC12) on the lower wafer (WF-d). That is, the first pixel circuits (PXC11 to PXC41) may be formed to overlap the second pixel circuits (PXC12 to PXC42) on the plane formed by the first and second directions (DR1, DR2).

[0078] As described above, each of the four first pixel circuits (PXC11 to PXC41) may include a photodetector (PDT) and a portion of the comparator (COMP), and each of the four second pixel circuits (PXC12 to PXC42) may include the remaining portion of the comparator (COMP) and a memory circuit (MCT). Each of the four second pixel circuits (PXC12 to PXC42) may be formed in the peripheral regions (PRA1 to PRA4) and memory cell regions (mca1 to mca4) of the lower wafer (WF-d).

[0079] As a more detailed example, the pixel circuit of PXC12 corresponding to the pixel circuit of PXC11 is formed in a first peripheral area (PRA1) and a first memory cell area (mca1), the pixel circuit of PXC22 corresponding to the pixel circuit of PXC21 is formed in a second peripheral area (PRA2) and a second memory cell area (mca2), the pixel circuit of PXC32 corresponding to the pixel circuit of PXC31 is formed in a third peripheral area (PRA3) and a third memory cell area (mca3), and the pixel circuit of PXC42 corresponding to the pixel circuit of PXC41 is formed in a fourth peripheral area (PRA4) and a fourth memory cell area (mca4).

[0080] The memory cells of the memory circuit (MCT) included in the second pixel circuit (e.g., PXC12) are formed in the first memory cell area (mca1), and the remaining components of the second pixel circuit (e.g., PXC12) are formed in the first peripheral area (PRA1). At this time, the memory cells of the memory circuit (MCT) may be provided in the form of an array in the first memory cell area (mca1).

[0081] For example, as shown in FIG. 5B, a plurality of memory cells may be formed in a first memory cell region (mca1). Some of the plurality of memory cells may be real memory cells (RMC) used to store actual data (e.g., a reset sampling value (R) or a signal sampling value (S)), and the remaining memory cells may be dummy cells (DC) for ensuring the reliability of the data stored in the real memory cells (RMC). The dummy cells (DC) may be formed on a dummy pattern area (DPA) of the first memory cell region (mca1).

[0082] For example, real memory cells (RMC) may be connected to first and second word lines (WL1, WL2) and bit lines (BL). As described with reference to FIGS. 3A to 3D, the real memory cells (RMC) connected to the first word line (WL1) are used to store a reset sampling value (R), and the real memory cells (RMC) connected to the second word line (WL2) are used to store a signal sampling value (S). As shown in FIG. 5B, dummy cells (DC) may be formed in a first direction (DR1), a direction opposite to the first direction (DR1), a second direction (DR2), and a direction opposite to the second direction (DR2) from the region of the first memory cell region (mca1) where the real memory cells (RMC) are formed. In other words, cells located in edge regions of the first memory cell region (mca1) may be used as dummy cells (DC).

[0083] For simplicity of illustration, the real memory cells (RMC) and dummy cells (DC) are shown connected to bit lines (BL) or word lines (WL), but the scope of the present invention is not limited thereto. The real memory cells (RMC) may be configured to store a digital signal (DOUT) by being electrically connected to first and second word lines (WL1, WL2) and the bit lines (BL). Meanwhile, the dummy cells (DC) may have a structure similar to the real memory cells (RMC), but may not be electrically connected to external wiring (e.g., metal lines).

[0084] 5B is merely an example, and the scope of the present invention is not limited thereto. For example, the total number of memory cells formed in the first memory cell region (mca1), the number of real memory cells, the number of dummy cells, the number of word lines, or the number of bit lines may be variously modified.

[0085] In an example embodiment, the other memory cell regions (e.g., mca2, mca3, mca4) may have a similar configuration to the first memory cell region (mca1). In this case, the pattern of the memory cell regions in the four second pixel circuits (PXC12-PXC42) may be the same as that shown in FIG. 5C.

[0086] In this case, the area of ​​one second pixel circuit (e.g., PXC12) is "L1 × L2," and the area of ​​one memory area (e.g., mca1) is "L3 × L4." In this case, the area of ​​the peripheral area (e.g., pra1) in one second pixel circuit (e.g., PXC12) is "(L1 × L2) - (L3 × L4)."

[0087] In an example embodiment, the first memory cell region (mca1) shown in FIG. 5B may have a third length (L3) in the first direction (DR1) and a fourth length (L4) in the second direction (DR2). In the first memory cell region (mca1), a region where the real memory cells (RMC) are located may have a sixth length (L6) in the first direction (DR1) and an eighth length (L8) in the second direction (DR2). From the region where the real memory cells (RMC) are located, only a fifth length (L5) along each of the first direction (DR1) and the direction opposite to the first direction (DR1), and only a seventh length (L7) along each of the second direction (DR2) and the direction opposite to the second direction (DR2), may be dummy pattern regions (DPA).

[0088] That is, the total area of ​​the first memory cell area (mca1) is "L3 x L4", of which the area where the real memory cells (RMC) are located is "L6 x L8", and the area of ​​the dummy pattern area (DPA) is "(L3 x L4) - (L6 x L8)".

[0089] As described above, the area of ​​the entire peripheral region (pra1, pra2, pra3, pra4) may be limited due to the area occupied by the dummy pattern area (DPA) of the memory cell region formed for each unit pixel. In this case, the limited area of ​​the peripheral region (pra1, pra2, pra3, pra4) may reduce the reliability of components formed in the peripheral region. Therefore, in the present invention, the dummy region may be reduced by sharing the dummy region with adjacent peripheral memory cell regions in the memory cell region formed for each digital pixel unit. Memory layouts according to embodiments of the present invention will be described in more detail with reference to the following drawings.

[0090] 6 is a plan view showing an example of the layout of the upper and lower wafers of the pixel array of FIG. 4A. Referring to FIG. 4A and FIG. 6, the upper wafer (WF-u) includes four first pixel circuits (PXC11, PXC21, PXC31, PXC41), which may be arranged in a 2x2 configuration. The four first pixel circuits (PXC11 to PXC41) are the same as those described above, so a detailed description thereof will be omitted.

[0091] The lower wafer (WF-d) includes four second pixel circuits (PXC12, PXC22, PXC32, PXC42), which may be arranged in a 2x2 configuration. As described above, each of the four first pixel circuits (PXC11-PXC41) and the four second pixel circuits (PXC12-PXC42) has an area of ​​L1 x L2. The four first pixel circuits (PXC11-PXC41) and the four second pixel circuits (PXC12-PXC42) may be electrically connected to each other to form four digital pixels (DP). For example, the first pixel circuit (PXC11) may be electrically connected to the second pixel circuit (PXC12) to form one digital pixel (DP).

[0092] Unlike the second pixel circuits (PXC12 to PXC42) of the lower wafer (WF-d) of FIG. 5A, the four second pixel circuits (PXC12 to PXC42) of the lower wafer (WF-d) of FIG. 6 can share one memory cell area (MCA). For example, each of the second pixel circuits (PXC12 to PXC42) of FIG. 5A includes a different memory cell area (mca1 to mca4). On the other hand, in the lower wafer (WF-d) of FIG. 6, memory cells are formed in one memory cell area (MCA), and the four second pixel circuits (PXC12 to PXC42) can share one memory cell area (MCA).

[0093] As a more detailed example, one memory cell area (MCA) may be divided into first to fourth sub-memory cell areas (sMCA1 to sMCA4) (hereinafter, for convenience of explanation, referred to as "sub-areas"). In an example embodiment, the first sub-memory cell area (sMCA1) may be located in a first peripheral area (PRA1), the second sub-memory cell area (sMCA2) may be located in a second peripheral area (PRA2), the third sub-memory cell area (sMCA3) may be located in a third peripheral area (PRA3), and the fourth sub-memory cell area (sMCA4) may be located in a fourth peripheral area (PRA4). Each of the first to fourth sub-areas (sMCA1 to sMCA4) may include a real memory cell (RMC). The real memory cells (RMC) included in the first sub-memory area (sMCA1) can be used to store digital signals of digital pixels (DP) formed by "PXC11" and "PXC12". The real memory cells (RMC) included in the second sub-memory area (sMCA2) can be used to store digital signals of digital pixels (DP) formed by "PXC21" and "PXC22". The real memory cells (RMC) included in the third sub-memory area (sMCA3) can be used to store digital signals of digital pixels (DP) formed by "PXC31" and "PXC32". The real memory cells (RMC) included in the first sub-memory area (sMCA4) can be used to store digital signals of digital pixels (DP) formed by "PXC41" and "PXC42".

[0094] In an example embodiment, a shared dummy pattern area (sPDA) may exist between each of the first to fourth sub-areas (sMCA1 to sMCA4). The shared dummy pattern area (sPDA) may refer to a dummy pattern area shared by each of the first to fourth sub-areas (sMCA1 to sMCA4). For example, to ensure the reliability of the real memory cells (RMC) in the first memory cell area (mca1) of FIG. 5B, a dummy pattern area (DPA) exists in an edge area of ​​the first memory cell area (mca1). In other words, the dummy pattern area (DPA) may surround the real memory cells (RMC). Meanwhile, the memory cell area (MCA) of FIG. 6 may include shared dummy pattern areas (sPDA) located between the real memory cells (RMC) of the first to fourth sub-areas (sMCA1 to sMCA4) to ensure the reliability of the real memory cells (RMC) of each of the first to fourth sub-areas (sMCA1 to sMCA4). In other words, the first to fourth sub-areas (sMCA1 to sMCA4) may share a dummy pattern area (i.e., a shared dummy pattern area (sPDA)) located in a specific area with each other. In this case, compared to the embodiment of FIGS. 5A to 5C, the dummy pattern area (DPA) required to form four digital pixels (more specifically, the dummy pattern area for the real memory cells (RMC)) is reduced, and the area of ​​the peripheral areas (PRA1 to PRA4) may be relatively larger. As the area of ​​the peripheral regions (PRA1 to PRA4) increases, the reliability of components formed in the peripheral regions (PRA1 to PRA4) can be improved, or components for other functions can be additionally mounted.

[0095] 7A is a plan view showing in more detail the layout of the memory cell area shown in FIG. 6. FIG. 7B is a plan view showing an example of a lower wafer reflecting the memory cell area of ​​FIG. 7A. For example, the layout of the memory cell area (MCA) shown in FIGS. 7A and 7B is for illustrative purposes only, and the scope of the present invention is not limited thereto. For example, the total number of memory cells included in the memory cell area (MCA), the number of real memory cells (RMC), the number of dummy cells (DC), or the number of shared dummy cells (sDC) may be variously modified.

[0096] 6 and 7A, a memory cell area (MCA) may include a plurality of memory cells. The plurality of memory cells are arranged in a row direction (i.e., a first direction (DR1)) and a column direction (i.e., a second direction (DR2)) on the memory cell area (MCA). Each of the plurality of memory cells may be connected to a bit line or a word line. Hereinafter, for convenience of explanation, description of word lines or bit lines for remaining cells (e.g., dummy cells (DC), shared dummy cells (sDC), etc.) other than real memory cells (RMC) will be omitted. However, the scope of the present invention is not limited thereto. For example, word lines or bit lines corresponding to remaining cells (e.g., dummy cells (DC), shared dummy cells (sDC), etc.) may be generated on the memory cell area (MCA), but the word lines or bit lines corresponding to the remaining cells (e.g., dummy cells (DC), shared dummy cells (sDC), etc.) may not be electrically connected to other circuits (e.g., components in a peripheral area).

[0097] The plurality of memory cells may include real memory cells (RMC), dummy cells (DC), and shared dummy cells (sDC). The real memory cells (RMC) may be used to store corresponding digital signals (e.g., reset sampling values ​​(R) or signal sampling values ​​(S)). The dummy cells (DC) and shared dummy cells (sDC) may be cells or patterns for ensuring the reliability of the real memory cells (RMC).

[0098] In an example embodiment, one memory cell area (MCA) may constitute one memory cell array or a single memory cell array. A memory cell array may refer to adjacent memory cells or a structure in which a pattern for memory cells is repeatedly formed within a particular area. As a more detailed example, the embodiment of FIG. 5C may be an embodiment in which a memory cell array is implemented in units of one digital pixel, and the embodiment of FIG. 6 may be an embodiment in which a memory cell array is implemented in units of multiple adjacent digital pixels. In an example embodiment, a single memory cell array may refer to a set or structure of memory cells surrounded by a dummy pattern area. In an example embodiment, a single memory cell array may include only repeated patterns such as memory cells or dummy cells, and other additional components may be formed in a peripheral area outside the single memory cell.

[0099] The memory cell area (MCA) can be divided into first to fourth sub-memory areas (sMCA1 to sMCA4). Each of the first to fourth sub-memory areas (sMCA1 to sMCA4) can include real memory cells (RMC), dummy cells (DC), and shared dummy cells (sDC).

[0100] For example, the first sub-memory area (sMCA1) may include real memory cells (RMC) located in the first area (RA1), a first portion of dummy cells (DC) located in the dummy pattern area (DPA), and a first portion of shared dummy cells (sDC) located in the shared dummy pattern area (sPDA). The real memory cells (RMC) located in the first area (RA1) may be respectively coupled to word lines (WL11, WL12) and bit lines (BL11, BL12) and configured to store corresponding digital signals (DOUT) as described above. The first portion of dummy cells (DC) located in the dummy pattern area (DPA) of the first sub-memory area (sMCA1) may include dummy cells located on the opposite side of the word line (WL11) in the second direction (DR2) and on the opposite side of the bit line (BL12) in the first direction (DR1) of the plurality of dummy cells (DC). A first portion of the shared dummy cells (sDC) located in the shared dummy pattern area (sPDA) of the first sub-memory area (sMCA1) may include shared dummy cells (sDC) located on the opposite side of the word line (WL31) in the second direction (DR2) and on the opposite side of the bit line (BL21) in the first direction (DR1).

[0101] The second sub-memory area (sMCA2) may include real memory cells (RMC) located in the second area (RA2), a second portion of the dummy cells (DC) located in the dummy pattern area (DPA), and a second portion of the shared dummy cells (sDC) located in the shared dummy pattern area (sPDA). The real memory cells (RMC) located in the second area (RA2) may be respectively coupled to word lines (WL21, WL22) and bit lines (BL21, BL22) and configured to store corresponding digital signals (DOUT) as described above. The second portion of the dummy cells (DC) located in the dummy pattern area (DPA) of the second sub-memory area (sMCA2) may include dummy cells located on the opposite side of the word line (WL22) in the second direction (DR2) and on the opposite side of the bit line (BL12) in the first direction (DR1) among the plurality of dummy cells (DC). A second portion of the shared dummy cells (sDC) located in the shared dummy pattern area (sPDA) of the second sub-memory area (sMCA2) may include shared dummy cells (sDC) located on the opposite side of the word line (WL41) in the second direction (DR2) and on the first direction (DR1) side of the bit line (BL12).

[0102] The third sub-memory area (sMCA3) may include real memory cells (RMC) located in the third area (RA3), a third portion of the dummy cells (DC) located in the dummy pattern area (DPA), and a third portion of the shared dummy cells (sDC) located in the shared dummy pattern area (sPDA). The real memory cells (RMC) located in the third area (RA3) may be respectively coupled to word lines (WL32, WL32) and bit lines (BL11, BL12) and configured to store corresponding digital signals (DOUT) as described above. The third portion of the dummy cells (DC) located in the dummy pattern area (DPA) of the third sub-memory area (sMCA3) may include dummy cells located on the second direction (DR2) side from the word line (WL32) and on the opposite side of the first direction (DR1) from the bit line (BL11) among the plurality of dummy cells (DC). A third portion of the shared dummy cells (sDC) located in the shared dummy pattern area (sPDA) of the third sub-memory area (sMCA3) may include shared dummy cells (sDC) located on the second direction (DR2) side from the word line (WL12) and on the opposite side in the first direction (DR1) from the bit line (BL21).

[0103] The fourth sub-memory area (sMCA4) may include real memory cells (RMC) located in the fourth area (RA4), a fourth portion of the dummy cells (DC) located in the dummy pattern area (DPA), and a fourth portion of the shared dummy cells (sDC) located in the shared dummy pattern area (sPDA). The real memory cells (RMC) located in the fourth area (RA4) are respectively connected to word lines (WL41, WL42) and bit lines (BL21, BL22) and configured to store corresponding digital signals (DOUT) as described above. The fourth portion of the dummy cells (DC) located in the dummy pattern area (DPA) of the fourth sub-memory area (sMCA4) may include dummy cells located on the second direction (DR2) side from the word line (WL41) and on the first direction (DR1) side from the bit line (BL21) among the plurality of dummy cells (DC). A fourth portion of the shared dummy cells (sDC) located in the shared dummy pattern area (sPDA) of the fourth sub-memory area (sMCA4) may include shared dummy cells (sDC) located on the second direction (DR2) side from the word line (WL22) and on the first direction (DR1) side from the bit line (BL12).

[0104] As described above, each of the first to fourth sub-regions (sMCA1 to sMCA4) can share the shared dummy cells (sDC) located in the shared dummy pattern region (sPDA). For example, in the embodiment of FIGS. 5B and 5C, two dummy pattern regions (DPAs) should exist between the real memory cells of each of the first and second memory cell regions (mca1, mca2). In other words, when the length (length in the first direction (DR1)) of one dummy pattern region (DPA) is "L5," the real memory cells of each of the first and second memory cell regions (mca1, mca2) should be spaced apart by at least twice "L5," and a dummy pattern region (DPA) with a length of about "2×L5" should exist between the real memory cells of each of the first and second memory cell regions (mca1, mca2).

[0105] Meanwhile, in the memory cell area (MCA) of FIG. 7A, only shared dummy pattern areas (sPDA) exist between the first to fourth areas (RA1 to RA4) where real memory cells (RMC) are located. For example, the first area (RA1) and the second area (RA2) should be spaced apart from each other by the shared dummy pattern areas (sPDA). In this case, the shared dummy pattern areas (sPDA) may have a length of "L9" in the first direction (DR1). In an exemplary embodiment, the length of "L9" may be the same as "L5," the length of one dummy pattern area (DPA) in the first direction (DR1), or may be less than twice "L5." That is, compared to the embodiments of FIGS. 5B and 5C, the dummy pattern areas between adjacent real memory cells (RMC) may be reduced in the embodiment of FIG. 7A.

[0106] In an example embodiment, the reduced area of ​​the dummy pattern area can be used as a peripheral area. For example, referring to FIG. 7B , the lower wafer (WF-d) can include four second pixel circuits (PXC12-PXC42). As described above, the four second pixel circuits (PXC12-PXC42) share one memory cell area (MCA), thereby reducing the size of the dummy pattern area (DPA) used in the memory cell area (MCA). For a more detailed example, assume that the area of ​​the area for the real memory cells (RMC) required for each of the four second pixel circuits (PXC12-PXC42) is “L6×L6” (see FIG. 5B ), and the length of the dummy pattern area (DPA) from the area for the real memory cells (RMC) is “L5” in each of the first and second directions (DR1, DR2).

[0107] 5B and 5C, based on four digital pixels, the total area for the real memory cells (RMC) is 4×L6×L6, and the total area for the dummy pattern region is 4×{(L5+L6+L5)×(L5+L6+L5)-(L6×L6)}. That is, based on four digital pixels, the total area for the memory cell region is 4×L6×L6+4×{(L5+L6+L5)×(L5+L6+L5)-(L6×L6)}=4×L3×L3.

[0108] Meanwhile, according to the embodiment of FIGS. 7A and 7B, based on four digital pixels, the total area of ​​the area for the real memory cells (RMC) is "4×L6×L6", and the total area of ​​the dummy pattern area is "4×{(L5+L6+L9+L6+L5) 2 -4×L6×L6)}. In other words, based on four digital pixels, the total area for the memory cell area is "4×L6×L6+4×{(L5+L6+L9+L6+L5) 2 -4×L6×L6)=L10×L10. In this case, "L10" may be smaller than twice "L3".

[0109] As a result, as in the embodiment of the present invention, the total area of ​​the memory cell area can be reduced by having multiple digital pixels share one memory cell area or by having the memory cell areas of each of multiple digital pixels share a dummy pattern area with each other. The reduced area of ​​the memory cell area can be utilized as a peripheral area, thereby increasing the reliability of components formed in the peripheral area or adding other components for additional functions.

[0110] In an example embodiment, as shown in FIGS. 7A and 7B, word lines coupled to real memory cells (RMCs) can be coupled to metal lines (see FIG. 4B) through word line contacts in corresponding peripheral regions.

[0111] For example, word lines (WL11, WL12) connected to real memory cells (RMC) in the first region (RA1) may be connected to metal lines through word line contacts formed in the first peripheral region (PRA1). Word lines (WL21, WL22) connected to real memory cells (RMC) in the second region (RA2) may be connected to metal lines through word line contacts formed in the second peripheral region (PRA2). Word lines (WL31, WL32) connected to real memory cells (RMC) in the third region (RA3) may be connected to metal lines through word line contacts formed in the third peripheral region (PRA3). Word lines (WL41, WL42) connected to real memory cells (RMC) in the fourth region (RA4) may be connected to metal lines through word line contacts formed in the fourth peripheral region (PRA4). In an example embodiment, metal lines connected to a plurality of word lines (WL11 to WL42) may be connected to other components (e.g., a comparator (COMP) or a first selection circuit (SEL1)) formed in the corresponding peripheral regions (PRA1 to PRA4) and may operate according to the operation methods described above.

[0112] In an example embodiment, the bit lines (BL11, BL12, BL21, BL22) are coupled to metal lines through contacts formed in at least one of the peripheral regions (PRA1-PRA4). The metal lines coupled to the bit lines (BL11, BL12, BL21, BL22) are coupled to other components (e.g., counters, sense amplifiers, second selection circuits, etc.) formed in at least one of the peripheral regions (PRA1-PRA4).

[0113] As described above, according to embodiments of the present invention, adjacent digital pixels may share one memory cell region (or memory cell array) or one dummy pattern region. This reduces the area of ​​the dummy pattern region, which is used to ensure the reliability of the real memory cells used in each of the digital pixels. The reduced area of ​​the dummy pattern region may be used as a peripheral region for forming other components, thereby improving the reliability of components formed in the peripheral region or allowing additional components to be formed for adding other functions to the digital pixel. This provides an image sensor device including digital pixels with reduced cost, improved reliability, and improved performance.

[0114] 8 is a plan view showing an example of the layout of the memory cell region of FIG. 6. For convenience of explanation, detailed descriptions of previously described components will be omitted. Also, for simplicity of the drawing, some previously described components will be omitted, or some reference numerals describing previously described components will be omitted. However, the scope of the present invention is not limited thereto, and the technical concept of the present invention will be understood by considering not only the embodiment of FIG. 8 but also all of the above-described embodiments.

[0115] 6 and 8, as described above, the memory cell array (MCA-a) is divided into first to fourth sub-regions (sMCA1 to sMCA4). The real memory cells (RMC) included in the first sub-region (sMCA1) may be connected to word lines (WL11, WL12) and bit lines (BL11, BL12). The real memory cells (RMC) included in the second sub-region (sMCA2) may be connected to word lines (WL21, WL22) and bit lines (BL21, BL22). The real memory cells (RMC) included in the third sub-region (sMCA3) may be connected to word lines (WL31, WL32) and bit lines (BL11, BL12). The real memory cells (RMC) included in the fourth sub-region (sMCA4) may be connected to word lines (WL41, WL42) and bit lines (BL21, BL22).

[0116] The memory cell area (MCA-a) may include a plurality of memory cells. The plurality of memory cells may include real memory cells (RMC), dummy cells (DC), and shared dummy cells (sDC). The memory cell area (MCA-a) of FIG. 8 may further include a shared dummy cell (sDC-iso) for isolation (hereinafter, for convenience of explanation, referred to as an "isolated cell").

[0117] The shared dummy cells for isolation (sDC-iso) may be dummy cells for separating word lines of real memory cells (RMC) located in the same row. For example, first and second digital pixels located in the same row and adjacent to each other may operate independently. That is, the first and second digital pixels may store data at different timings depending on the light incident thereon. For this reason, the memory cells corresponding to the first and second digital pixels may be controlled via separate signal lines (e.g., word lines).

[0118] 8, it is assumed that the real memory cells (RMC) included in the first sub-region (sMCA1) correspond to a first digital pixel, and the real memory cells (RMC) included in the second sub-region (sMCA2) correspond to a second digital pixel adjacent to the first digital pixel in the same row. In this case, to realize independent operations of the first and second digital pixels, the real memory cells (RMC) included in the first sub-region (sMCA1) are connected to word lines (WL11, WL12), and the memory cells included in the second sub-region (sMCA2) are connected to other word lines (WL21, WL22).

[0119] In this case, the real memory cells (RMC) included in the first sub-region (sMCA1) and the real memory cells (RMC) included in the second sub-region (sMCA2) may be located in the same row at the memory cell array level, and the memory cells may be formed in a repeated pattern. Therefore, the real memory cells (RMC) included in the first sub-region (sMCA1) and the real memory cells (RMC) included in the second sub-region (sMCA2) may be connected to the same word line. To prevent the real memory cells (RMC) of other sub-regions (sMCA) from being connected to the same word line, an isolation cell (sDC-iso) may be added between the real memory cells (RMC) included in the first sub-region (sMCA1) and the real memory cells (RMC) included in the second sub-region (sMCA2). The isolation cell (sDC-iso) may be part of a shared dummy cell (sDC) located between the real memory cells (RMC) included in the first sub-region (sMCA1) and the second sub-region (sMCA2). The isolation cell (sDC-iso) may not be electrically connected to other cells (e.g., shared dummy cells (sDC)) in the same row. For example, a word line pattern may not be formed for the isolation cell (sDC-iso). In other words, the isolation cell (sDC-iso) may not be connected to a word line. In this case, the isolation cell (sDC-iso) connects the real memory cells (RMC) included in the first sub-area (sMCA1) and the real memory cells (RMC) included in the second sub-area (sMCA2) to different word lines, thereby ensuring independent operation of the first and second digital pixels.

[0120] Although not shown in the drawings, the memory cell area (MCA-a) may further include additional isolation cells located between the real memory cells (RMC) of the first sub-area (sMCA1) and the real memory cells (RMC) of the third sub-area (sMCA3), or between the real memory cells (RMC) of the second sub-area (sMCA2) and the real memory cells (RMC) of the fourth sub-area (sMCA4), thereby separating the bit lines for each area.

[0121] 9 is a diagram illustrating an example of a structure in which digital pixels included in the pixel array of FIG. 1 share a comparator. Referring to FIG. 1 and FIG. 9, four digital pixels (DP1 to DP4) can share one comparator (sCOMP) (hereinafter referred to as a "shared comparator").

[0122] For example, the first to fourth digital pixels (DP1 to DP4) may include first to fourth photodetectors (PDT1 to PDT4), one shared comparator (sCOMP), and a memory circuit (MCT). Each of the first to fourth photodetectors (PDT1 to PDT4) is similar to the photodetector (PDT) described with reference to FIGS. 3A to 3D, and therefore a detailed description thereof will be omitted. The output (i.e., detection signal (DET)) of each of the first to fourth photodetectors (PDT1 to PDT4) is provided to the shared comparator (sCOMP).

[0123] The shared comparator (sCOMP) can compare the outputs of each of the first to fourth photodetectors (PDT1 to PDT4) with the ramp signal (VRAMP) and output a comparison signal. In an exemplary embodiment, the outputs of each of the first to fourth photodetectors (PDT1 to PDT4) are output at different timings, thereby allowing the shared comparator (sCOMP) to output comparison signals corresponding to each of the first to fourth photodetectors (PDT1 to PDT4) at different timings.

[0124] The memory circuit (MCT) can store codes (CODE) corresponding to the first to fourth photodetectors (PDT1 to PDT4) based on the comparison signal from the shared comparator (sCOMP). For example, the memory circuit (MCT) can include a first selection circuit (SEL1), a second selection circuit (SEL2), a first memory cell (MC1), a second memory cell (MC2), a third memory cell (MC3), and a fourth memory cell (MC4).

[0125] When the shared comparator (sCOMP) outputs a comparison signal corresponding to the first photodetector (PDT1), the first selection circuit (SEL1) of the memory circuit (MCT) can select the word line corresponding to the first memory cell (MC1). When the shared comparator (sCOMP) outputs a comparison signal corresponding to the second photodetector (PDT2), the first selection circuit (SEL1) of the memory circuit (MCT) can select the word line corresponding to the second memory cell (MC2). When the shared comparator (sCOMP) outputs a comparison signal corresponding to the third photodetector (PDT2), the first selection circuit (SEL1) of the memory circuit (MCT) can select the word line corresponding to the third memory cell (MC3). When the shared comparator (sCOMP) outputs a comparison signal corresponding to the fourth photodetector (PDT4), the first selection circuit (SEL1) of the memory circuit (MCT) can select the word line corresponding to the fourth memory cell (MC4).

[0126] That is, the first memory cell (MC1) may be configured to store a digital signal corresponding to the optical signal detected by the first photodetector (PDT1), the second memory cell (MC2) may be configured to store a digital signal corresponding to the optical signal detected by the second photodetector (PDT2), the third memory cell (MC3) may be configured to store a digital signal corresponding to the optical signal detected by the third photodetector (PDT3), and the fourth memory cell (MC4) may be configured to store a digital signal corresponding to the optical signal detected by the fourth photodetector (PDT4). As a result, the first photodetector (PDT1), the shared comparator (sCOMP), and the first memory cell (MC1) can operate as a first digital pixel (DP1), the second photodetector (PDT2), the shared comparator (sCOMP), and the second memory cell (MC2) can operate as a second digital pixel (DP2), the third photodetector (PDT3), the shared comparator (sCOMP), and the third memory cell (MC3) can operate as a third digital pixel (DP3), and the fourth photodetector (PDT4), the shared comparator (sCOMP), and the fourth memory cell (MC4) can operate as a fourth digital pixel (DP4). Except for the fact that the comparators are shared, each digital pixel is similar to that described with reference to FIGS. 3A to 3D, and therefore further description thereof will be omitted.

[0127] In the example embodiment, the operation timing of the first to fourth photodetectors (PDT1 to PDT4) and the memory circuit (MCT) may be controlled by a control signal (CTRL) (e.g., CS-PD, CS-MC, etc.) from the pixel driver 120.

[0128] In an example embodiment, the first to fourth photodetectors (PDT1 to PDT4) may be respectively included in the four first pixel circuits (PXC11 to PXC41) of the upper wafer (WF-u) described with reference to FIG. 6. The first to fourth memory cells (MC1 to MC4) may be respectively formed in the first to fourth sub-regions (sMCA1 to sMCA4) of the memory cell region (MCA or MCA-a) of the lower wafer (WF-d) described with reference to FIGS. 6 to 8.

[0129] In an example embodiment, the shared comparator (sCOMP), first selection circuit (SEL1), and second selection circuit (SEL2) may be included in the first pixel circuits (PXC11-PXC41) of the upper wafer (WF-u) or the peripheral regions (PRA1-PRA4) of the lower wafer (WF-d) described with reference to Figures 6-8. That is, one comparator per unit of four digital pixels may be formed on the upper wafer (WF-u) or the lower wafer (WF-d).

[0130] In an example embodiment, one memory cell area (MCA) (or memory cell array) according to an embodiment of the present invention may be arranged in units of pixel groups including multiple digital pixels, or in units of a single comparator.

[0131] 10A and 10B are plan views illustrating, by way of example, the layout of the lower wafer and memory cell region of FIG. 4A. For clarity and convenience of illustration, descriptions or reference numerals for previously described components may be omitted. However, the scope of the present invention is not limited in this respect, and the embodiments of FIGS. 10A and 10B should be understood in light of the above-described or following embodiments as a whole.

[0132] 10A and 10B, the lower wafer (WF-db) may include a plurality of second pixel circuits (PXC12 to PXCn2). The plurality of second pixel circuits (PXC12 to PXCn2) may be arranged in pairs along the second direction (DR2). For example, PXC12 / PXC22, PXC31 / PXC42, PXC51 / PXC62, PXC71 / PXC82, ..., PXC(n-1)2 / PXCn2 may be located in the same row as each other, PXC12 / PXC32 / PXC52 / PXC72, ..., PXC(n-1)2 may be located in the same column, and PXC22 / PXC42 / PXC62 / PXC82 ... PXCn2 may be located in the same column.

[0133] The second pixel circuits (PXC12 / PXC32 / PXC52 / PXC72, ..., PXC(n-1)2) located in the same column and the second pixel circuits (PXC22 / PXC42 / PXC62 / PXC82, ..., PXCn2) located in other adjacent columns can share one memory cell area (MCA-b).

[0134] For example, as shown in FIG. 10B, the memory cell area (MCA-b) includes a plurality of memory cells, and the plurality of memory cells include real memory cells (RMC), dummy cells (DC), and shared dummy cells (sDC).

[0135] In this case, real memory cells (RMCs) corresponding to second pixel circuits (PXC12 / PXC32 / PXC52 / PXC72...PXC(n-1)2) located in the same column may be connected to corresponding word lines (WL11 / WL12, WL31 / WL32, WL51 / WL52, WL71 / WL72, ...WL(n-1)1 / WL(n-1)2). The corresponding word lines are connected to metal lines via corresponding word line contacts. Real memory cells (RMCs) corresponding to second pixel circuits (PXC22 / PXC42 / PXC62 / PXC82...PXCn2) located in another adjacent column may be connected to corresponding word lines (WL21 / WL22, WL41 / WL42, WL61 / WL62, WL81 / WL82, ...WLn1 / WLn2). The corresponding word lines are connected to metal lines via corresponding word line contacts.

[0136] A shared dummy memory cell (sDC) may be arranged between the real memory cells (RMC) corresponding to the second pixel circuits (PXC12 / PXC32 / PXC52 / PXC72...PXC(n-1)2) located in the same column and the real memory cells (RMC) corresponding to the second pixel circuits (PXC22 / PXC42 / PXC62 / PXC82...PXCn2) located in the other same column. This is similar to the configuration of the shared dummy cell (sDC) described above, so a detailed description thereof will be omitted.

[0137] Unlike those described with reference to FIGS. 6A to 8, in the memory cell area (MCA-b) of FIG. 10B, dummy cells (DC) or dummy pattern areas (DPA) between adjacent real memory cells (RMC) along the second direction (DR2) may be omitted. As an example, the dummy cells (DC), dummy pattern areas (DPA), shared dummy cells (sDC), and shared dummy pattern areas (sPDA) may be omitted between the real memory cells (RMC) corresponding to PXC32 (i.e., the real memory cells connected to word lines (WL31 / WL32)) and the real memory cells (RMC) corresponding to PXC52 (i.e., the real memory cells connected to word lines (WL51 / WL52)). In this case, the two groups of real memory cells described above may be formed physically adjacent to each other. That is, by removing the dummy pattern areas (DPA) between adjacent real memory cells (RMC) along the second direction (DR2), the total area of ​​the dummy pattern areas is reduced, thereby increasing the area of ​​the peripheral area.

[0138] In an example embodiment, a dummy cell (DC) or a dummy pattern area (DPA) may be present along the second direction (DR2) for a real memory cell (RMC) corresponding to a second pixel circuit (e.g., PXC12, PXC22, PXC(n-1)2, PXCn2, etc.) located in an edge region of the pixel array 110. For example, a dummy cell (DC) may be formed on the opposite side of the second direction (DR2) from the real memory cell (RMC) corresponding to PXC12 (i.e., the real memory cell associated with word lines (WL11, WL12)). For example, in FIG. 10B, the dummy cell (DC) of the second pixel circuit (PXC12) is located to the left of the real memory cell (RMC) of the second pixel circuit (PXC12). The configuration for forming dummy cells in the remaining edge regions is similar, and therefore, a detailed description thereof will be omitted. For example, in FIG. 10B, the dummy cell (DC) of the second pixel circuit (PXC12) is located above the real memory cell (RMC) of the second pixel circuit (PXC12) (for example, in the direction facing the second direction (DR2)).

[0139] 11A and 11B are plan views showing, by way of example, the layout of the lower wafer and memory cell region of FIG. 4A. For the sake of clarity and convenience of illustration, descriptions or reference numerals of previously described components may be omitted. However, the scope of the present invention is not limited thereto.

[0140] 11A and 11B, the lower wafer (WF-dc) may include four second pixel circuits (PXC12 to PXC42). The four second pixel circuits (PXC12 to PXC42) may share a memory cell area (MCA-c).

[0141] The memory cell area (MCA-c) may include a plurality of memory cells. The plurality of memory cells may include real memory cells (RMC) and dummy cells (DC). The memory cell area (MCA-c) may be divided into first to fourth sub-areas (sMCA1 to sMCA4).

[0142] In the previously described embodiment, the real memory cells (RMC) included in each of the first to fourth sub-regions (sMCA1 to sMCA4) are configured to store the digital signals of the corresponding digital pixels. Meanwhile, the first to fourth sub-regions (sMCA1 to sMCA4) of the memory cell array (MCA) in Fig. 11B refer to regions separated by digital pixel units, and the real memory cells (RMC) included in each of the first to fourth sub-regions (sMCA1 to sMCA4) may be configured to store the digital signals of the corresponding digital pixels or the digital signals of adjacent digital pixels.

[0143] For example, the real memory cells (RMC) included in the first sub-region (sMCA1) may be connected to the first to fourth word lines (WL1 to WL4) and connected to the first and second bit lines (BL1, BL2). The real memory cells (RMC) included in the second sub-region (sMCA2) may be connected to the first to fourth word lines (WL1 to WL4) and connected to the third and fourth bit lines (BL3, BL4). The real memory cells (RMC) included in the third sub-region (sMCA3) may be connected to the fifth to eighth word lines (WL5 to WL8) and connected to the first and second bit lines (BL1, BL2). The real memory cells included in the fourth sub-region (sMCA4) may be connected to the fifth to eighth word lines (WL5 to WL8) and connected to the third and fourth bit lines (BL3, BL4).

[0144] In this case, the real memory cells (RMC) connected to the first and third word lines (WL1, WL3) are configured to store a digital signal corresponding to a first digital pixel. The real memory cells (RMC) connected to the second and fourth word lines (WL2, WL4) are configured to store a digital signal corresponding to a second digital pixel. In this case, the first digital pixel may be a digital pixel including a second pixel circuit in which the first sub-region (sMCA1) is located, and the second digital pixel may be a digital pixel including a second pixel circuit in which the second sub-region (sMCA2) is located. That is, memory cells included in adjacent digital pixels may be configured to share the same bit line. That is, the real memory cells of the digital pixels according to the embodiments of FIGS. 11A and 11B may have a bit line sharing structure.

[0145] According to the above-described embodiment, memory cells corresponding to a first digital pixel are connected to the first and third word lines (WL1, WL3), and memory cells corresponding to a second digital pixel are connected to the second and fourth word lines (WL2, WL4). That is, real memory cells storing digital signals corresponding to digital pixels located on the opposite side of the first direction (DR1) are connected to odd-numbered word lines, and real memory cells storing digital signals corresponding to digital pixels located on the first direction (DR1) side are connected to even-numbered word lines.

[0146] The first and third word lines (WL1, WL3) are connected to metal lines through word line contacts located in the first peripheral region (PRA1), and the second and fourth word lines (WL2, WL4) are connected to metal lines through word line contacts located in the second peripheral region (PRA2). In this case, the distance between word line contacts formed in the same peripheral region (i.e., word line pitch (WLpt)) can be increased compared to the previous embodiments. For example, in the embodiments described with reference to FIGS. 5A to 10B, word line contacts connected to adjacent word lines are formed consecutively in the same peripheral region. On the other hand, in the embodiment of FIG. 11A, word line contacts connected to word lines (e.g., WL1, WL3) that are not physically adjacent to each other are formed in the same peripheral region (e.g., PRA1).

[0147] In other words, since the distance (i.e., word line pitch) between word line contacts formed along the second direction, i.e., in one peripheral region, increases, the process complexity or wiring complexity for forming the word line contacts can be reduced.

[0148] According to the above-described embodiment, the memory cell area (MCA-a) included in the image sensor device 100 may include a plurality of memory cells. The plurality of memory cells may include a plurality of real memory cells connected to a plurality of bit lines. Among the plurality of real memory cells, a real memory cell (RMC) used to store a digital signal of a first digital pixel is connected to first and third word lines (WL1, WL3). A real memory cell (RMC) used to store a digital signal of a second digital pixel physically adjacent to the first digital pixel is connected to second and fourth word lines (WL2, WL4). In this case, the second word line (WL2) may be located between the first word line and the third word line (WL1, WL3), and the third word line (WL3) may be located between the second word line and the fourth word line (WL2, WL4). In this case, the word line contacts for the first and third word lines (WL1, WL3) are formed in the first peripheral region (PRA1), and the word line contacts for the second and fourth word lines (WL2, WL4) are formed in the second peripheral region (PRA2). Therefore, as the distance between the word line contacts increases, the complexity of the process for forming the word line contacts can be reduced.

[0149] 11A and 11B, since there are no dummy cells (DC) or dummy pattern areas (DPA) between the real memory cells (RMC), the total area occupied by the memory cell area (MCA-c) can be reduced. The reduced area is used for the area of ​​the peripheral areas (PRA1 to PRA4). Therefore, an image sensor device with reduced cost, improved reliability, and improved performance is provided.

[0150] 12 is a plan view illustrating an example of a memory cell region according to an embodiment of the present invention, and for the sake of convenience, detailed descriptions of previously described components will be omitted.

[0151] 12, the memory cell area (MCA-d) includes a plurality of memory cells, which may include real memory cells (RMC), dummy cells (DC), and shared dummy cells (sDC). The memory cell area (MCA-d) is divided into first to fourth sub-areas (sMCA1 to sMCA4). As described above, the memory cell area (MCA-d) is a memory cell area shared by four digital pixels, and the configuration of the real memory cells (RMC) used in each of the four digital pixels is similar to that described with reference to FIGS. 11A and 11B. That is, the real memory cells (RMC) in the memory cell area (MCA-d) may have a structure in which they share bit lines (BL1 to BL4). In other words, the real memory cells (RMC) connected to the first and third word lines (WL1, WL3) and the first to fourth bit lines (BL1 to BL4) can store a digital signal corresponding to a first digital pixel, and the real memory cells (RMC) connected to the second and fourth word lines (WL2, WL4) and the first to fourth bit lines (BL1 to BL4) can store a digital signal corresponding to a second digital pixel. In this case, the first digital pixel and the second digital pixel may be adjacent digital pixels located in the same row at the pixel array level.

[0152] 11A and 11B, the memory cell area (MCA-d) of Fig. 12 may have shared dummy cells (sDC) or shared dummy pattern areas (sPDA) between the real memory cells (RMC) arranged along the second direction (DR2). For example, the shared dummy cells (sDC) or shared dummy pattern areas (sPDA) may be present between the real memory cells (RMC) located in the first and second sub-areas (sMCA1, sMCA2) and the real memory cells (RMC) located in the third and fourth sub-areas (sMCA3, sMCA4).

[0153] 13 is a plan view illustrating an example of a memory cell region according to an embodiment of the present invention, and for the sake of convenience, detailed descriptions of previously described components will be omitted.

[0154] 13, the memory cell area (MCA-d) includes a plurality of memory cells, which may include real memory cells (RMC), dummy cells (DC), and shared dummy cells (sDC). The memory cell area (MCA-d) may be divided into first to fourth sub-areas (sMCA1 to sMCA4).

[0155] In this case, the real memory cells (RMC) connected to the first and third word lines (WL1, WL3) and the first and second bit lines (BL1, BL2) may be configured to store a digital signal generated from a first digital pixel, and the real memory cells (RMC) connected to the second and fourth word lines (WL2, WL4) and the third and fourth bit lines (BL3-BL4) may be configured to store a digital signal generated from a second digital pixel. In this case, the first digital pixel and the second digital pixel may be located in the same row at the pixel array level and may be adjacent digital pixels. That is, as described above, the real memory cells used in one digital pixel may be connected to non-adjacent word lines from the perspective of the memory cell area (MCA-e) (or memory cell array) and may be included in a sub-area corresponding to one digital pixel.

[0156] Although not shown in the drawings, as described with reference to FIG. 7A or FIG. 8, a shared dummy cell (sDC) or a shared dummy pattern area (sPDA) may exist between each of the first to fourth sub-areas (sMCA1 to sMCA4) of the memory cell area (MCA-e).

[0157] 14A and 14B are plan views illustrating exemplary layouts of a lower wafer and memory cell region according to embodiments of the present invention, and for convenience of explanation, detailed descriptions of previously described components are omitted.

[0158] 14A and 14B, the lower wafer (WF-df) may include a plurality of second pixel circuits (PXC12, PXC22, PXC32, PXC42, PXC52, PXC62). The plurality of second pixel circuits (PXC12 to PXC62) may share one memory cell array (MCA-f).

[0159] The memory cell array (MCA-f) includes a plurality of memory cells, which may include real memory cells (RMC) and dummy cells (DC). As described above, the memory cell area (MCA-f) may be divided into a plurality of sub-areas (sMCA1 to sMCA6). The real memory cells (RMC) of the memory cell area (MCA-f) may be connected to a plurality of word lines (WL1 to WL12) and a plurality of bit lines (BL1 to BL4). The correspondence between the real memory cells (RMC) and the digital pixels or second pixel circuits is similar to that described with reference to FIGS. 11A and 11B. That is, the real memory cells (RMC) of the memory cell area (MCA-f) may have a structure in which they share bit lines. This has been described above, so a detailed description thereof will be omitted.

[0160] Unlike the above description, the memory cell area (MCA-f) of Figures 14A and 14B may have no dummy cells (DC) or shared dummy cells (sDC) between the real memory cells (RMC) arranged along the second direction (DR2). The configuration in which no dummy cells (DC) or shared dummy cells (sDC) exist between the real memory cells (RMC) arranged along the second direction (DR2) has been described with reference to Figures 10A and 10B, so a detailed description thereof will be omitted.

[0161] Although not shown in the drawings, the sub-region of the second pixel circuit located in the edge region of the lower wafer (WF-df) may include dummy cells (DC) located on the second direction (DR2) side or the side opposite to the second direction (DR2), as described with reference to Figures 10A and 10B. This has been described with reference to Figures 10A and 10B, so a detailed description thereof will be omitted.

[0162] 15A and 15B are plan views illustrating exemplary layouts of an upper wafer and a lower wafer of an image sensor device according to an embodiment of the present invention. For ease of explanation, detailed descriptions of previously described components will be omitted. Referring to FIGS. 15A and 15B, the upper wafer (WF-u1) may include a plurality of first sub-pixel circuits (sPD11 to sPD41). Each of the plurality of first sub-pixel circuits (sPD11 to sPD41) may include a photodetector or photodiode configured to detect light incident from the outside. For example, each of the plurality of sub-pixel circuits (sPD11 to sPD41) may include a photodetector (PDT) or photodiode (PD) described with reference to FIGS. 3A to 3D. The plurality of sub-pixel circuits (sPD11 to sPD41) may be arranged along a row direction (i.e., a first direction (DR1)) and a column direction (i.e., a second direction (DR2)).

[0163] In an exemplary embodiment, photodetectors or photodiodes included in the same pixel group are configured to detect light of the same color. For example, the first subpixel circuits (sPD11) included in the first pixel group (PXG1) are configured to detect light of a first color (e.g., green (G)), the second subpixel circuits (sPD21) included in the second pixel group (PXG2) are configured to detect light of a second color (e.g., red (R)), the third subpixel circuits (sPD31) included in the third pixel group (PXG3) are configured to detect light of a third color (e.g., blue (B)), and the fourth subpixel circuits (sPD41) included in the fourth pixel group (PXG4) are configured to detect light of the first color (e.g., green (G)). However, the scope of the present invention is not limited thereto, and various color filter arrays (CFAs) may be formed on top of the subpixel circuits for various detection patterns.

[0164] The lower wafer (WF-d1) may include a plurality of second subpixel circuits (sPD12, sPD22, sPD32, sPD42). Each of the second subpixel circuits (sPD12 to sPD42) may be arranged to overlap a plurality of first subpixel circuits (sPD11 to sPD41) of the upper wafer (WF-u1). For example, each of the first subpixel circuits (e.g., sPD11) may be arranged to overlap a second subpixel circuit (e.g., sPD12). The remaining second subpixels (sPD22 to sPD42) are arranged in the same manner as described above, and therefore further description thereof will be omitted.

[0165] The plurality of first subpixel circuits (sPD11 to sPD41) and the plurality of second subpixel circuits (sPD12 to sPD42) are divided into a plurality of pixel groups (PXG1 to PXG4). For example, four first subpixel circuits (sPD11) and four second subpixel circuits (sPD12) can form one first pixel group (PXG1). One first pixel group (PXG1) can operate as one digital pixel (DP) as described with reference to FIGS. 3A to 3D. That is, detection signals or optical signals from four photodetectors (PDTs) or four photodiodes (PDs) can be combined into one signal, and one comparison signal corresponding to the four first subpixel circuits (sPD11) can be output via one comparator (COMP). In this case, one set of digital signals corresponding to the four first subpixel circuits (sPD11) can be stored in a memory circuit. The remaining sub-pixel circuits sPD21 to sPD41 ​​and the remaining pixel groups PXG2 to PXG4 are also similar to those described above, and therefore detailed description thereof will be omitted.

[0166] In this case, the size and pitch of each of one sub-first pixel circuit (e.g., sPD11) and one sub-second pixel circuit (e.g., sPD12) may be "L11." The size and pitch of one pixel group (e.g., PXG1) may be "L12." As described above, four sub-pixel circuits make up one pixel group, and one comparator is used in one pixel group. Therefore, the size and pitch of one comparator may be the same as "L12," which is the size or pitch of one pixel group.

[0167] That is, multiple photodetectors or multiple photodiodes are included in one pixel group that operates as one digital pixel, and one pixel group may include one comparator and one memory circuit. One comparator may be formed in a corresponding second subpixel circuit (e.g., four sPDs 12) on the lower wafer (WF-d1). Also, a portion of one comparator may be formed in a corresponding first subpixel circuit (e.g., four sPDs 11) on the upper wafer (WF-u1), and the remaining portion may be formed in a corresponding second subpixel circuit (e.g., four sPDs 12) on the lower wafer (WF-d1).

[0168] In an exemplary embodiment, four pixel groups (PXG1-PXG4) can share one memory cell area (MCA-1). For example, because each of the four pixel groups (PXG1-PXG4) operates as one digital pixel, each of the four pixel groups (PXG1-PXG4) requires one set of real memory cells (RMC). In this case, as described with reference to FIGS. 1-14B, four sets of real memory cells (RMC) are included in one memory cell area (MCA-1), and the four pixel groups (PXG1-PXG4) can share one memory cell area (MCA-1). While FIG. 15B illustrates an example of a portion of the memory cell area (MCA-1) (with a structure similar to the memory cell area (MCA) of FIG. 7A), the scope of the present invention is not limited thereto, and the memory cell area (MCA-1) can have the form of each of the memory cell areas having various structures and layouts described above, or a combination thereof.

[0169] As described above, according to embodiments of the present invention, an image sensor device may include a plurality of digital pixels. Each of the plurality of digital pixels may require a memory cell for storing a digital signal. In this case, according to embodiments of the present invention, at least two adjacent digital pixels may share one memory cell region. This reduces the area of ​​a dummy pattern region formed in the memory cell region, and the reduced area may be used as the area of ​​a peripheral region for forming other components. This may improve the reliability of components formed in the peripheral region, or allow components for other additional functions to be added. This provides an image sensor device with reduced costs, improved reliability, and improved performance.

[0170] 16A and 16B are perspective and plan views illustrating an example of the image sensor device of FIG. 1. In the example embodiment, with reference to FIGS. 16A and 16B, an example embodiment of an image sensor device 100 according to an embodiment of the present invention will be described in terms of its physical structure. That is, with reference to the following drawings, an embodiment of the present invention will be described based on a semiconductor wafer included in an image device according to an embodiment of the present invention. To facilitate explanation of the technical concept of the present invention, components illustrated in the following drawings are simplified and are not represented as actual semiconductor wafers, semiconductor chips, semiconductor dies, semiconductor packages, etc.

[0171] 1, 16A, and 16B, the image sensor device 100 may include first to third semiconductor wafers (WF1 to WF3), each of which may be manufactured using a different semiconductor process or from a different semiconductor wafer.

[0172] The first semiconductor wafer (WF1) can be electrically connected to the second semiconductor wafer (WF2) on the second semiconductor wafer (WF2). The second semiconductor wafer (WF2) can be electrically connected to the third semiconductor wafer (WF3) on the third semiconductor wafer (WF3). In other words, the second semiconductor wafer (WF2) can be located between the first semiconductor wafer and the third semiconductor wafer (WF1, WF3).

[0173] The first semiconductor wafer (WF1) may include a first pixel circuit area (PXCA1) and a first pad area (PA1). The first pixel circuit area (PXCA1) and the first pad area (PA1) may be physically separated from each other or may be separated by a predetermined distance.

[0174] The first pixel circuit area (PXCA1) may be an area for forming a portion of each of the plurality of digital pixels 110. For example, as described above, the first pixel circuit area (PXCA1) may include a first pixel circuit (e.g., a photodetector or a portion of a comparator) of each of the plurality of digital pixels (DP).

[0175] The first pad area (PA1) may be an area for forming a plurality of pads configured to be connected to the second pad area (PA2) of the second semiconductor wafer (WF2). The first pad area (PA1) may be connected to components of the first pixel circuit area (PXCA1) through a metal layer formed on the first semiconductor wafer (WF1).

[0176] The second semiconductor wafer (WF2) may include a second pixel circuit area (PXCA2), a second pad area (PA2), a pixel driver area (PDA), and a third pad area (PA3). The second pixel circuit area (PXCA2) may include a second pixel circuit (e.g., a portion of a comparator or remaining components of the pixel) for each of the plurality of digital pixels (PD). In an example embodiment, the second pixel circuit area (PXCA2) may include the memory cell area and peripheral area described with reference to FIGS. 1-15.

[0177] In an example embodiment, a first portion of the comparator 112 formed in the first pixel circuit region (PXCA1) of the first semiconductor substrate (WF1) and a second portion of the comparator 112 formed in the second pixel circuit region (PXCA2) of the second semiconductor substrate (WF2) may be bonded to each other via a bonding structure formed on a plane corresponding to the first pixel circuit region (PXCA1) or the second pixel circuit region (PXCA2). In an example embodiment, the bonding structure may be a component or material configured to bond between semiconductor wafers, such as Cu-to-Cu bonding, TSV, BVS, etc.

[0178] The pixel driver area (PDA) may be an area for forming the pixel driver 120 described above. In the pixel driver area (PDA), some analog circuits such as the counter 121, row driver 122, ramp generator 123, and voltage generator 124 described above may be formed.

[0179] The second pad area (PA2) may be an area for forming a plurality of pads connected to the first pad area (PA1). The plurality of pads in the second pad area (PA2) may be respectively connected to the plurality of pads in the first pad area (PA1) via connecting structures. In an example embodiment, the connecting structures may be components or materials configured to bond between semiconductor wafers, such as Cu-to-Cu bonding, TSV, BVS, etc.

[0180] The third pad area (PA3) may be an area for forming a plurality of pads connected to the third semiconductor wafer (WF3).

[0181] In an example embodiment, the various components included in each of the second pixel circuit area (PXCA2), the second pad area (PA2), the pixel driver area (PDA), and the third pad area (PA3) may be respectively coupled to each other via a metal layer of the second semiconductor wafer (WF2).

[0182] The third semiconductor wafer (WF3) may include a digital logic circuit area (DLA) and a fourth pad area (PA4). The digital logic circuit area (DLA) may be an area for forming the digital logic circuit 130 described above. The fourth pad area (PA4) may be an area for forming a plurality of pads. The plurality of pads in the fourth pad area (PA4) may be connected to the plurality of pads in the third pad area (PA3) via a connecting structure. In an example embodiment, the connecting structure may be a component or material configured to bond between semiconductor wafers, such as Cu-to-Cu bonding, TSV, BVS, etc.

[0183] In an example embodiment, a first pixel circuit area (PXCA1) of a first semiconductor wafer (WF1) and a second pixel circuit area (PXCA2) of a second semiconductor wafer (WF2) are arranged to overlap each other in the same planar area and may be areas for forming multiple digital pixels, such as pixel core areas.

[0184] The remaining areas of the first and second semiconductor wafers (WF1, WF2) excluding the first and second pixel circuit areas (PXCA1, PXCA2) may be used as peripheral areas (or peripheral circuit areas) for forming interconnect structures between semiconductor wafers, drive circuits, analog circuits, etc. In an example embodiment, circuits or physical components that operate based on digital signals in the image sensor device 10 may be formed on the third semiconductor wafer (WF3).

[0185] As described above, the image sensor device 100 according to the embodiment of the present invention can reduce the area occupied by the memory cell region by allowing multiple pixels to share one memory cell region. Because the reduced area of ​​the memory cell region can be used as a peripheral region, the reliability of components included in the peripheral region can be improved, and additional components for other functions of the image sensor device 100 can be added. Therefore, an image sensor device with reduced costs, improved reliability, and improved performance is provided.

[0186] 17 is a block diagram illustrating an example of an electronic device to which an image sensor device according to the present invention is applied. Referring to FIG. 17, an electronic device 1000 may include a touch panel 1100, a touch driver circuit 1102, a display panel 1200, a display driver circuit 1202, a system memory 1400, a storage device 1500, an image processor 1600, a communication block 1700, an audio processor 1800, and a main processor 1900. In an example embodiment, an electronic device 2000 may be any one of various electronic devices such as a portable communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smartphone, a tablet computer, a laptop computer, a wearable device, etc.

[0187] The touch drive circuit 1102 is configured to control the touch panel 1100. The touch panel 1100 is configured to detect touch input from a user under the control of the touch drive circuit 1102. The display drive circuit 1202 is configured to control the display panel 1200. The display panel 1200 is configured to display image information under the control of the display drive circuit 1202.

[0188] System memory 1400 stores data used in the operation of electronic device 1000. By way of example, system memory 1400 may temporarily store data that has been processed or is to be processed by main processor 1900. In an example embodiment, output data from image signal processor 1630 may be stored in system memory 1400.

[0189] The storage device 1500 can store data regardless of the power supply. For example, the storage device 1500 may include at least one of various non-volatile memories such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc. For example, the storage device 1500 may include embedded memory and / or removable memory of the electronic device 1000.

[0190] Image processor 1600 can receive optical signals via lens 1610. Image device 1620 and image signal processor 1630 included in image processor 1600 can generate image information about external objects based on the received optical signals. In an example embodiment, image signal processor 1630 can be an image sensor device as described with reference to FIGS. 1-16 or can operate according to the methods described with reference to FIGS. 1-16.

[0191] The communications block 1700 can exchange signals with external devices / systems via an antenna 1710. The transceiver 1720 and MODEM 2730 (Modulator / Demodulator) of the communications block 1700 can process signals exchanged with external devices / systems based on at least one of a variety of wireless protocols.

[0192] The audio processor 1800 can process audio signals using an audio signal processor 1810. The audio processor 1800 can receive audio input via a microphone 1820 and provide audio output via a speaker 1830.

[0193] The main processor 1900 may control the overall operation of the electronic device 1000. The main processor 1900 may control / manage the operation of the components of the electronic device 1000. The main processor 1900 may process various operations to operate the electronic device 1000. In an example embodiment, some of the components of FIG. 17 may be implemented in the form of a system-on-chip and provided as an application processor (AP) of the electronic device 1000.

[0194] The above-described content is a specific embodiment for carrying out the present invention. The present invention includes not only the above-described embodiment but also embodiments that can be simply modified or easily changed. The present invention also includes techniques that can be easily implemented by modifying the embodiment. Therefore, the scope of the present invention should not be limited to the above-described embodiment, but should be defined by the following claims as well as equivalents of the claims of the present invention.

Claims

1. 1. An image sensor device including a first substrate including a plurality of first pixel circuits and a second substrate including a plurality of second pixel circuits, the plurality of first pixel circuits include a first photodetector and a second photodetector; the plurality of second pixel circuits a first memory circuit including a first memory cell and a first dummy memory cell configured to store a first digital signal generated from the first photodetector; a second memory circuit including second memory cells and second dummy memory cells configured to store a second digital signal generated from the second photodetector; the first memory circuit is positioned immediately adjacent to the second memory circuit in a first direction; one first pixel circuit among the plurality of first pixel circuits and one second pixel circuit among the plurality of second pixel circuits constitute one digital pixel; the first memory cell is located immediately adjacent to the second memory cell; the first dummy memory cell and the second dummy memory cell are not disposed between the first memory cell and the second memory cell; the plurality of first pixel circuits further include a third photodetector; the plurality of second pixel circuits further include a third memory circuit, the third memory circuit including a third memory cell and a third dummy memory cell configured to store a third digital signal generated from the third photodetector; the third memory circuit is disposed immediately adjacent to the first memory cell in a second direction perpendicular to the first direction; the plurality of first pixel circuits further include a fourth photodetector; the plurality of second pixel circuits further include a fourth memory circuit, the fourth memory circuit including a fourth memory cell configured to store a fourth digital signal generated from the fourth photodetector and a fourth dummy memory cell; the fourth memory cell is disposed immediately adjacent to the second memory cell in the second direction; Image sensor device.

2. 2. The image sensor device of claim 1, wherein the one first pixel circuit of the plurality of first pixel circuits and the one second pixel circuit of the plurality of second pixel circuits are electrically connected via Cu-to-Cu bonding.

3. 3. The image sensor device of claim 2, wherein the one first pixel circuit of the plurality of first pixel circuits includes a portion of a comparator, and the one second pixel circuit of the plurality of second pixel circuits includes a remaining portion of the comparator.

4. the third memory circuit is disposed immediately adjacent to the fourth memory circuit in the first direction; The image sensor device of claim 1 , wherein the third dummy memory cell and the fourth dummy memory cell are not disposed between the third memory cell and the fourth memory cell.

5. 2. The image sensor device according to claim 1, wherein the first to fourth dummy memory cells surround the first to fourth memory cells.

6. 2. The image sensor device of claim 1, wherein the first to fourth memory cells are connected to a plurality of bit lines and a plurality of word lines.

7. The second substrate comprises: a counter configured to output a code; The image sensor device of claim 1 , further comprising: a row driver configured to control the plurality of first pixel circuits and the plurality of second pixel circuits.

8. 2. The image sensor device of claim 1, wherein the first to fourth photodetectors are connected to a first portion of a comparator.

9. further comprising a third substrate laminated on the second substrate; The image sensor unit of claim 1 , wherein the third substrate includes digital logic circuitry.

10. The image sensor device of claim 9 , wherein the second substrate and the third substrate are connected via Cu-to-Cu bonding.

11. The image sensor device of claim 9 , wherein the second substrate and the third substrate are connected via a TSV.

12. 1. An image sensor device including a first substrate and a second substrate, The first substrate comprises: a first pixel circuit including a first photodetector; a second pixel circuit including a second photodetector; The second substrate comprises: a first memory circuit including a first memory cell and a first dummy memory cell configured to store a first digital signal generated from the first photodetector; a second memory circuit including second memory cells and second dummy memory cells configured to store a second digital signal generated from the second photodetector; the first memory circuit is positioned immediately adjacent to the second memory circuit in a first direction; the first substrate is stacked on the second substrate such that the first photodetector and the first memory circuit overlap, and the second photodetector and the second memory circuit overlap; the first dummy memory cell and the second dummy memory cell are not disposed between the first memory cell and the second memory cell; the first substrate further includes a third photodetector; the second substrate further includes a third memory circuit, the third memory circuit including a third memory cell and a third dummy memory cell configured to store a third digital signal generated from the third photodetector; the third memory circuit is disposed immediately adjacent to the first memory cell in a second direction perpendicular to the first direction; the plurality of first pixel circuits further include a fourth photodetector; the plurality of second pixel circuits further include a fourth memory circuit, the fourth memory circuit including a fourth memory cell configured to store a fourth digital signal generated from the fourth photodetector and a fourth dummy memory cell; the fourth memory cell is disposed immediately adjacent to the second memory cell in the second direction perpendicular to the first direction; Image sensor device.

13. The image sensor device of claim 12 , further comprising a third substrate stacked on the second substrate, the third substrate including a digital logic circuit.

Images