Information processing device, information processing system, and information processing method

Abstract

To stably perform information processing using an SSD while reducing a delay time for memory access.SOLUTION: An information processing device 10a includes a first SSD drive 22a including a first NAND module 20a and a first flash controller 18a; and a second SSD drive 22a including a second NAND module 20b and a second flash controller 18b. Data required for a host unit 12 to execute information processing is stored to either the first SSD drive 22a or the second SSD drive 22b, which is set to be a read-only mode in which only a read request is received.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an information processing device equipped with a flash memory, an information processing system including the same, and an information processing method. [Background technology]

[0002] As the capacity of NAND flash memory increases, solid-state drives (SSDs) are increasingly being used as storage devices to replace conventional hard disk drives (HDDs). While SSDs offer the advantage of faster data access speeds and lower power consumption than HDDs, they are also characterized by lower durability against repeated data reads and rewrites. Therefore, when rewriting data to an SSD, a process is performed to distribute the areas to be rewritten. For example, when a rewrite request is made by the host CPU, the specified logical block address is replaced with a different physical address, thereby distributing the rewrite target across as many memory cells as possible (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] WO 2014 / 132346 A1 Publication Summary of the Invention [Problem to be solved by the invention]

[0004] As mentioned above, SSDs allow for high-speed access, allowing most of the data required for information processing to be read only when it is needed, thereby reducing the amount of system memory required. However, as access frequency increases, problems with management processes specific to SSDs become apparent. Examples of such management processes include the following: Since NAND flash memory cannot be overwritten, when data is written to various areas as described above, it is necessary at some stage to copy it to a contiguous area and erase the data in the freed area in preparation for future writes.

[0005] Furthermore, repeated reads can cause the charge in the element to leak, potentially destroying the data, so it is necessary to save the data to another area at some stage. Furthermore, to speed up writing, SLC (Single Level Cell), which stores one bit per memory cell, is used as a cache, and at a later time, the data is re-stored in TLC (Triple Level Cell), which can store three bits per memory cell. Giving priority to these management processes over requests from the host CPU can cause significant delays in information processing. On the other hand, if management processes are not performed at the appropriate time, it may not be possible to process requests from the host CPU.

[0006] The present invention has been made in view of these problems, and its purpose is to provide a technology that enables stable information processing using an SSD while reducing the delay time for memory access. [Means for solving the problem]

[0007] One aspect of the present invention relates to an information processing device, comprising: a host unit that executes information processing, a memory that stores data used in the information processing, and a memory controller that executes access to the memory in response to a request from the host unit, wherein the memory controller realizes a read-only mode that only accepts requests to read data stored in the memory.

[0008] Another aspect of the present invention relates to an information processing system including an information processing device that executes information processing and a server that provides data used in the information processing to the information processing device via a network, wherein the information processing device includes a plurality of device drives, each including a memory that stores the data provided by the server and a memory controller that accesses the memory in response to a request from a host unit, and the memory controller corresponding to the memory that has completed storing the data used in the information processing implements a read-only mode that only accepts requests to read the data stored in the memory.

[0009] Yet another aspect of the present invention relates to an information processing method, the information processing method including the steps of: storing data to be used for information processing in a memory; after the data storage is completed, realizing a read-only mode in the memory in which only a read request for the stored data is accepted; executing the read request to the memory; and executing information processing using the data read in accordance with the read request.

[0010] Any combination of the above components, and any transformation of the present invention into a method, device, system, computer program, or recording medium on which a computer program is recorded, are also valid aspects of the present invention. [Effects of the Invention]

[0011] According to the present invention, it is possible to stably perform information processing using an SSD while suppressing delay time for memory access. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram illustrating an example of a circuit configuration of a general information processing device. [Figure 2] 1 is a diagram illustrating a circuit configuration of an information processing device according to an embodiment of the present invention. [Figure 3] FIG. 10 is a diagram illustrating another example of the circuit configuration of the information processing device according to the present embodiment. [Figure 4] 1 is a diagram illustrating a configuration of an information processing system according to an embodiment of the present invention. [Figure 5] FIG. 10 is a diagram illustrating an example of the flow of access processing to an SSD drive in this embodiment. [Figure 6] 10 is a flowchart showing a procedure in which the information processing device according to the present embodiment downloads a necessary file from a storage server and performs information processing. [Figure 7] 7 is a flowchart showing in detail the procedures of the initial processing in S10 and the mounting processing in S12 in FIG. 6. [Figure 8] 7 is a flowchart showing in detail the procedure of the mounting process in read-only mode in S16 of FIG. 6. DETAILED DESCRIPTION OF THE INVENTION

[0013] First, to clarify the features of this embodiment, a general information processing device including an SSD will be described. Fig. 1 illustrates an example of the circuit configuration of a general information processing device. Here, the information processing device 110 is composed of a host unit 112 including a CPU, a system memory 114, and an SSD drive 122 including a NAND module 120 and a flash controller 118. In the SSD drive 122, the NAND module 120 includes multiple NAND flash memories, and stores data distributed across multiple channels, such as four or eight channels.

[0014] The host unit 112 includes a CPU, loads programs and data stored in the NAND module 120 into the system memory 114, and uses them to process information. The resulting data to be saved is then written appropriately to the NAND module 120. The host unit 112 also reads application programs and data from a recording medium driven by a recording medium drive (not shown), or downloads them from a server connected to the network by a network controller, and stores them in the NAND module 120.

[0015] In these processes, the host unit 112 issues an access request to the NAND module 120 to the flash controller 118. The flash controller 118 adds the issued access request to an access request queue provided in an internal memory or the like. The flash controller 118 then performs read / write processing on the NAND module 120 in accordance with the access requests sequentially read from the queue. Here, the access request includes the logical block address (LBA) of the access destination.

[0016] The host unit 112 uses LBA to realize random access to a continuous address space. The unit of random access that can be specified by LBA is, for example, 512 bytes. The flash controller 118 converts the LBA included in the access request into a physical address of the NAND module 120. For this reason, the flash controller 118 loads at least a part of the address conversion table originally stored in the NAND module 120 into an internal memory, the system memory 114, etc.

[0017] The flash controller 118 then reads or writes data by accessing an area of ​​the NAND module 120 that corresponds to the physical address obtained by referencing the address conversion table. Generally, data is read or written to the NAND module 120 in units defined by the file system, such as 4096 bytes.

[0018] On the other hand, NAND flash memory cannot overwrite data, so to update written data, the original data must be erased. In the case of recent large-capacity NAND flash memory, the data erasure unit is several tens of MiB (1 MiB = 2 20 The erase unit is often 1,000 times larger than the read or write unit, such as a byte. This means that even when rewriting small data, it is necessary to read and erase the entire large erase unit, and then write the read data back.

[0019] To avoid this, when data needs to be rewritten, the flash controller 118 allocates a new area in the NAND module 120 for the data to be rewritten. It then updates the address translation table so that the physical address corresponds to the same LBA as before the rewrite. This reduces the number of times large data such as that mentioned above needs to be erased. At this time, the flash controller 118 periodically erases used areas to prevent the newly allocated areas from becoming depleted even if rewrites occur frequently. This type of processing is generally called "garbage collection."

[0020] Another characteristic of NAND flash memory is its asymmetric read and write latencies. For SLC, which stores one bit of data per memory cell, typical read latencies are less than 50 μsec and write latencies are less than 500 μsec. For TLC, which stores three bits of data per memory cell, typical read latencies are less than 100 μsec and write latencies are less than 3 msec.

[0021] Furthermore, in the case of a write that involves erasing data, the latency is about 5 to 10 msec, and in the case of performing the above-mentioned garbage collection, the latency may be 1 second or more. Generally, the flash controller 118 uses firmware to implement a command scheduling function that assumes the characteristics of such NAND flash memory, thereby keeping the latency of reads and writes below a certain value as much as possible.

[0022] For example, TLC requires a complex write sequence, which means write operations take longer than SLC. Therefore, a portion of the NAND module 120 is typically reserved as an SLC area and used as a cache to speed up write operations. The flash controller 118 then copies data written to the SLC to the TLC at an appropriate time, separate from the execution of the write request. This complex command schedule, combined with the command processing latency of the firmware itself, makes it difficult to achieve the high-speed access performance inherent in NAND flash memory.

[0023] Therefore, in this embodiment, two or more SSD drives are provided, and mode switching is controlled so that at least one of them is read-only, thereby keeping data read latency below a certain value. Drives operating in read-only mode do not require complex command scheduling associated with writing, so sequential read processing can be performed without or with minimal firmware intervention, minimizing latency. Meanwhile, by providing drives that accept both read and write, necessary processing can be performed in the background, as before.

[0024] FIG. 2 shows the circuit configuration of an information processing device according to this embodiment. Here, the information processing device 10a may be any common information device, such as a portable game console, a personal computer, a mobile phone, a tablet terminal, or a PDA. In addition to a host unit 12 and a system memory 14, the information processing device 10a also includes a first SSD drive 22a consisting of a first NAND module 20a and a first flash controller 18a, and a second SSD drive 22b consisting of a second NAND module 20b and a second flash controller 18b. The information processing device 10a basically has the same functions as the information processing device 110 shown in FIG. 1. The following description will focus on the differences from the information processing device 110.

[0025] The host unit 12 is connected to the first SSD drive 22a and the second SSD drive 22b via a switch 24, for example, via PCI Express (PCIe). PCIe is a connection standard for expansion buses and expansion slots. This allows separate transmission bandwidths to be used for reading and writing data. Note that while the illustrated example uses two SSD drives, three or more SSD drives may also be provided. The host unit 12 loads device drivers for the first SSD drive 22a and the second SSD drive 22b, respectively, to individually recognize the SSD drives at different mounting positions.

[0026] The host unit 12 basically mounts an SSD drive (e.g., the first SSD drive 22a) that stores data for applications running in the foreground in read-only mode and reads various data from it to progress information processing and generate display images. To write data that must be saved, such as save data or additional patch data, that is generated or downloaded during information processing, a folder is created in another SSD drive (e.g., the second SSD drive 22b) that is mounted in read / write mode, and a link is established to set the write destination.

[0027] Here, "read-only mode" is a special mode that accepts only read requests, and "read / write mode" is a general mode that accepts both read and write requests. When a scene changes in an electronic game or when an application is terminated, the host unit 12 remounts the first SSD drive 22a, which was mounted in read-only mode, in read / write mode. The host unit 12 then copies to the first SSD drive 22a any additional data, such as save data and patch data, that has been written to the second SSD drive 22b and that needs to be read with low latency during subsequent application execution.

[0028] This allows the data and the data of the original application to be stored on the same SSD drive, enabling high-speed reading in read-only mode when processing is resumed. Also, the host unit 12 may progress information processing by reading data from the first SSD drive 22a in read-only mode, while downloading data of another application from a server and storing it on the second SSD drive 22b in read / write mode.

[0029] By executing various processes associated with writing save data, patch data, data of other applications, etc. in the background, necessary processes can be performed without affecting the progress of applications running in the foreground. When transitioning between read / write mode and read-only mode, the firmware used in the flash controller (e.g., first flash controller 18a) of the target SSD drive is also switched.

[0030] A typical flash controller is configured with multiple microcontrollers, which share the tasks of reading, writing, background jobs, etc. In this case, the overhead associated with synchronization between the microcontrollers can increase latency. Therefore, in this embodiment, as described above, the firmware is switched in read-only mode, and control is performed so that a single microcontroller immediately processes read requests received from the host unit 12.

[0031] In read-only mode, there is little need for complex scheduling or processing other than read processing, allowing for simple processing by a single microcontroller. When switching to read / write mode, the firmware is also restored. When switching firmware in this way, the program data is reloaded each time, thereby saving storage space within the flash controller.

[0032] The firmware may also be switched to optimize various settings within the flash controller. For example, in read-only mode, the flash controller may increase the frequency with which it polls for read requests from the host unit 12. Alternatively, the depth of the read request queue may be increased by using the storage area within the flash controller that is freed by switching from read / write mode. These setting switches can also reduce the processing latency for read requests.

[0033] 3 shows another example of the circuit configuration of an information processing device according to this embodiment. The information processing device 10b in the figure is similar to the information processing device 10a in FIG. 2 in that it includes, in addition to a host unit 12 and a system memory 14, a first SSD drive 22a consisting of a first NAND module 20a and a first flash controller 18a, and a second SSD drive 22b consisting of a second NAND module 20b and a second flash controller 18b.

[0034] 2 in that the information processing device 10b connects two SSD drives in series to the host unit 12 instead of in parallel. That is, the host unit 12 is connected only to the first flash controller 18a, and the first flash controller 18a is connected to the second flash controller 18b in a cascade connection. In this case, an access request issued by the host unit 12 is propagated between the flash controllers as necessary, and the flash controller corresponding to the request reads from or writes to the connected NAND module.

[0035] Even with this configuration, information processing can proceed with minimal latency, similar to the information processing device 10a in Figure 2. That is, by using an SSD drive (e.g., the first SSD drive 22a) that stores data for an application running in the foreground in read-only mode, data can be read and processing can be performed with guaranteed latency. Note that in this case, the number of SSD drives is not limited, and three or more SSD drives may be cascaded.

[0036] 4 shows the configuration of an information processing system according to this embodiment. The illustrated information processing system 30 has a configuration in which an information processing device 10c and a storage server 32 are connected via a network 34. However, the number of information processing devices 10c (also called computation nodes) connected to the storage server 32 is not particularly limited. The storage server 32 is included in a server that provides programs and data, such as game applications, necessary for information processing performed by the information processing device 10c, and may be a storage array made up of multiple storage devices.

[0037] 2, the information processing device 10c includes a host unit 12, a system memory 14, a first SSD drive 22a consisting of a first NAND module 20a and a first flash controller 18a, and a second SSD drive 22b consisting of a second NAND module 20b and a second flash controller 18b. In this example, the first flash controller 18a and the second flash controller 18b are each connected to the host unit 12 via a switch 24.

[0038] However, the first flash controller 18a and the second flash controller 18b may be cascade-connected, as in the information processing device 10b shown in Fig. 3. In either case, the number of SSD drives is not limited. The information processing device 10c further includes a network controller 26 that connects to the host unit 12 via a switch 24 and to the storage server 32 via a network 34.

[0039] The network 34 has a peak bandwidth equivalent to the write speed to the first SSD drive 22a and the second SSD drive 22b in the information processing device 10c. The information processing device 10c accesses the storage server 32 via the network 34 and downloads at least a portion of the data required for information processing to the first SSD drive 22a and the second SSD drive 22b for use. Game applications that include large textures, audio data, and 3D data have strict requirements for latency.

[0040] For this reason, in the past, the most recently used data was stored in the system memory of the information processing device as much as possible, and for data that could not be stored, an explicit loading screen was displayed and the data that would be needed was downloaded from the server, or the data that would be needed was predicted and pre-loaded from the server.For example, by controlling this in such a way that game titles that are popular with multiple users are downloaded to the information processing device in advance, and less popular game titles are downloaded only as needed, the server's load balancer distributes the load so that the write bandwidth to the SSD drive does not become congested.

[0041] By introducing the read-only mode in this embodiment, a latency of about 200 μsec, which is sufficiently shorter than the rendering time of one frame, can be guaranteed in the read process, and the read data can be used for the frame being rendered without pre-reading some of the data. Considering that the size of data that can be stored in a NAND module is several hundred gigabytes to several terabytes, it is entirely possible to load all of the data for one game title from the storage server 32 and use it to progress through the game with low latency.

[0042] For example, the information processing device 10c loads a game title selected by the user from the storage server 32 into the first NAND module 20a and then starts the game. As described above, while the game is running, the first SSD drive 22a is used in read-only mode. Meanwhile, the load balancer of the storage server 32 predicts the game title that is likely to be executed next on each computing node based on the game titles currently running on multiple computing nodes including the information processing device 10c and game titles that are waiting to be executed.

[0043] Based on this prediction, the information processing device 10c loads the next game title likely to be played from the storage server 32 in the background and stores it in the second NAND module 20b operating in read / write mode. By using different SSD drives for reading and writing in this way, the bandwidths used for each process are not affected by each other, and each peak bandwidth can be maintained. Furthermore, because the latency of each process is not affected by the other, latency below a certain value is guaranteed.

[0044] Figure 5 illustrates the flow of access processing for an SSD drive in this embodiment. (a) shows the transition of processing for an SSD driver in read-only mode, and (b) shows the transition of processing for an SSD driver in read / write mode. The horizontal direction of the figure represents the passage of time, and the length of the rectangle represents the time required for each process. Here, read processing is represented as "R," write processing as "W," and erasing data from a block as "Erase."

[0045] In this example, the SSD drive is configured with multiple channels (four channels in the figure), and data access is performed in parallel across these multiple channels. Also, by configuring each channel with multiple NAND devices and selecting devices with chip enable signals, the latency that occurs in read and write processes can be hidden.

[0046] The NAND device is used in SLC mode, the time required for data read is 40 μsec, the time required for write is 200 μsec, the interface speed between the flash controller and the NAND module is 1 GB / sec, and the time required for data erase is 5 msec. The unit of read and write is a page size of 16 KiB, with 32 KiB for two planes. Furthermore, the transfer bandwidth of the interface with the host unit 12 is 6.5 GB / sec on one side. However, this embodiment is not intended to be limited to these numerical values.

[0047] In the above numerical example, in the read-only mode shown in (a), the SSD driver processes read requests issued by the host unit 12 in 40 μsec cycles on each channel. The bandwidth for this read processing is 32768 / 40 = 819.2 MB / sec per channel. As shown in the figure, while data is being transferred on one channel, the next page is read on another channel, thereby hiding the time required for transmission. For example, with eight channels, the bandwidth is 6.5 GB / sec, making it possible to maximize the transfer bandwidth of the interface with the host unit 12.

[0048] On the other hand, in the read / write mode shown in (b), the SSD driver needs to execute background jobs such as erasing data in blocks of several tens of MiB and garbage collection in addition to handling write requests issued from the host unit 12. Of these, the bandwidth for write processing is 32768 / 200 = 163.84 MB / sec per channel. If four devices are provided on each of the eight channels, for a total of 32 devices, the total bandwidth becomes 5.2 GB / sec, and the transfer bandwidth of the interface with the host unit 12 can be utilized even for writes.

[0049] On the other hand, the worst-case latency estimate is as follows: For example, when a high-priority read request is interrupted on an SSD drive in read-only mode, the latency is approximately 120 μsec, including the read processing for the issued request, the read processing for the interrupting request, and the transmission time of the read data. Here, if the size of the data to be read increases, the number of requests issued simultaneously to each channel increases, and the latency for waiting for processing is added.

[0050] For example, when requesting 1 MiB of data from an 8-channel SSD drive, four requests are issued per channel, adding 120 μsec of processing time for three requests, for a total latency of 240 μsec. Using the same calculation, the latency when requesting 32 MiB of data is 5.2 msec. If the requested data size is 256 KiB or less, there will be one request per channel, so the latency is 120 μsec as mentioned above. When overhead such as waiting for processing completion in the host unit 12 is taken into account, a read latency of approximately 200 μsec can be achieved.

[0051] On the other hand, when a high-priority read request is interrupted on an SSD drive in read / write mode, a latency of several milliseconds can occur unless the issued write or data erase request is canceled. However, canceling a write or data erase request in this way can result in a very long latency for the write request. This eventually requires complex processing, such as putting the read request on hold for a long time before the write or data erase can proceed.

[0052] In this embodiment, by securing an SSD drive in read-only mode, read processing is released from such control. This makes it possible to stably guarantee peak performance when only read processing or only write processing is performed. Note that the SLC assumed in the above explanation allows high-speed access and is advantageous in that, compared to TLC, the frequency of data reads from the same area is reduced, resulting in less degradation due to applied voltage. However, this embodiment is not limited to SLC, and similar effects can be obtained with TLC.

[0053] Next, the operation of the information processing device realized by the above configuration will be described. Figure 6 is a flowchart showing the procedure by which the information processing device 10c downloads necessary files from the storage server 32 and performs information processing. In this example, the information processing device 10c is assumed to have two SSD drives, a first and a second. First, the information processing device 10c performs an initial process (S10), and then mounts the first SSD drive 22a and the second SSD drive 22b in read / write mode (S12).

[0054] The information processing device 10c then downloads data for application A, which the user has selected to run in the foreground, from the storage server 32 and stores it in the first SSD drive 22a (S14). Once all the necessary data has been stored, the information processing device 10c temporarily unmounts the first SSD drive 22a and then remounts it in read-only mode (S16). At this time, the first flash controller 18a of the first SSD drive 22a switches its internal configuration and settings by loading read-only firmware.

[0055] Then, the information processing device 10c starts application A, and progresses the processing while reading data from the first SSD drive 22a with guaranteed latency and performance (S18). Meanwhile, in the background, the information processing device 10c downloads data for application B, which is predicted to be executed next, from the storage server 32 and stores the data in the second SSD drive 22b, which remains in read / write mode (S20).

[0056] Until there is a need to switch to application B, application A continues processing in the foreground (N in S22), and when there is a need to switch (Y in S22), application A processing is stopped (S24). The information processing device 10c then temporarily unmounts the first SSD drive 22a and remounts it in read / write mode (S26). At this time, the first flash controller 18a of the first SSD drive 22a switches its internal configuration and settings by reloading the read / write firmware.

[0057] After setting the first SSD drive 22a to read / write mode, the information processing device 10c may copy additional data, such as save data and patch data, written to the second SSD drive 22b during execution of application A to the first SSD drive 22a as necessary.The information processing device 10c then temporarily unmounts the second SSD drive 22b, which stores the data of application B to be executed next, and remounts it in read-only mode (S28).At this time, the second flash controller 18b of the second SSD drive 22b switches its internal configuration and settings by loading read-only firmware.

[0058] Then, the information processing device 10c starts up application B, and progresses the processing while reading data from the second SSD 22b drive with guaranteed latency and performance (S30). Thereafter, the information processing device 10c switches the storage destination as needed, downloads the application data from the storage server 32, and progresses the processing while using the SSD drive where the data is stored in read-only mode.

[0059] During this time, the information processing device 10c may download data for application C, which is predicted to be executed next, from the storage server 32 as needed, and store the data in the first SSD drive 22a in the background (S20). Thereafter, similarly, the SSD drive storing at least the data of the application executed in the foreground is used for reading only, and the SSD drive in read / write mode performs necessary processing, including writing, in the background.

[0060] 7 is a flowchart showing in detail the procedures for the initialization process in S10 and the mounting process in S12 of FIG. 6. First, when the information processing device 10c is powered on (S40), the first flash controller 18a and the second flash controller 18b load read / write firmware from a storage device inside the information processing device 10c (S42). Here, the storage device may be the first NAND module 20a and the second NAND module 20b, or a separately prepared dedicated serial flash device for storing firmware. At this time, the host unit 12 also loads the BIOS from a storage device inside the information processing device 10c, such as a serial flash.

[0061] Next, the first flash controller 18a and the second flash controller 18b access the first NAND module 20a and the second NAND module 20b, respectively, using the loaded firmware to read various control information such as drive metadata and initialize the first SSD drive 22a and the second SSD drive 22b (S44). Next, the first flash controller 18a and the second flash controller 18b accept initialization processing from the host unit 12 (S46).

[0062] Specifically, the host unit 12 (BIOS) first loads a device driver for accessing the first SSD drive 22a and the second SSD drive 22b based on the PCIe device ID. The host unit 12 then uses the device driver to initialize the registers of the first SSD drive 22a and the second SSD drive 22b and perform various initialization processes, such as generating a command queue. Once the initialization is complete, the host unit 12 is able to access the first SSD drive 22a and the second SSD drive 22b, and the host unit 12 then performs the necessary initialization processes, such as loading the operating system (S48).

[0063] Figure 8 is a flowchart showing in detail the procedure for mounting in read-only mode in S16 of Figure 6. First, the host unit 12 waits for all data write processing by application A to be completed, and then unmounts the first SSD drive 22a (S50). Note that the firmware loaded in the first flash controller 18a at this point supports a special command for restarting the drive in read-only mode. The same applies to the firmware loaded in the second flash controller 18b.

[0064] As a result, the first flash controller 18a writes the status information of the first SSD drive 22a at the time of unmounting to the first NAND module 20a. Once the saving of the status information is complete, the first flash controller 18a loads read-only firmware from the internal storage device of the information processing device 10c (S52), and resets the first SSD drive 22a by accessing a soft reset function mapped to an internal register (S54).

[0065] When the drive is soft reset, the first flash controller 18a executes the loaded read-only firmware, loads the saved status information and various control information from the first NAND module 20a, and initializes the first SSD drive 22a (S56). Note that if the PCIe link is disconnected due to the soft reset of the first flash controller 18a in S54, the host unit 12 detects this and unloads the device driver.

[0066] Then, in S56, the drive is initialized by the read-only firmware, and when the PCIe connection is re-established, the host unit 12 scans the PCIe tree to read the device ID. This allows the host unit 12 to load the appropriate device driver again. On the other hand, if the PCIe link is not disconnected, the first SSD drive 22a can be continuously controlled regardless of mode switching by using a driver that supports both read / write and read-only.

[0067] The host unit 12 then initializes the first SSD drive 22a again in accordance with the read-only firmware (S58), allowing the host unit 12 to remount the first SSD drive 22a, which has a different configuration from the read / write mode and is configured for performance assurance, such as a read-only command queue.

[0068] Through the above process, application A and the file system that supports it can use the various functions provided by the read-only firmware to satisfy the bandwidth and latency required by application A. When remounting the SSD drive in read / write mode in S26 of Figure 6, the drive should be unmounted once, as in the procedure shown in Figure 8, and then initialized with the read / write firmware.

[0069] According to the embodiment described above, a read-only mode is provided in an SSD drive configured with a NAND module including a NAND flash memory and a flash controller in an information processing device. This frees read processing in this mode from the complex command scheduling inherent to NAND flash memory that accompanies data writing. Furthermore, the use of read-only firmware simplifies the configuration by eliminating unnecessary functions from the flash controller. As a result, read requests issued by the host unit can be processed in order, allowing information processing to proceed with minimal and stable latency.

[0070] In addition, multiple SSD drives are provided, and drives in read / write mode are also maintained. This allows various processes for write processing and memory management to be performed in the same way as before. Furthermore, because the SSD drives performing these processes are independent of the SSD drives in read-only mode, there is no impact on the latency or bandwidth of foreground processing. For example, large image data used in electronic games does not need to be updated, making it ideal for use in read-only mode. Furthermore, reducing latency reduces the need for read-ahead, saving on the memory space required to store read data, thereby lowering the manufacturing cost of the entire device.

[0071] The present invention has been described above based on the embodiments. The above embodiments are merely examples, and it will be understood by those skilled in the art that various modifications are possible in the combination of the respective components and treatment processes, and that such modifications are also within the scope of the present invention. [Explanation of symbols]

[0072] 10a Information processing device, 12 Host unit, 14 System memory, 18a First flash controller, 18b Second flash controller, 20a First NAND module, 20b Second NAND module, 22a First SSD drive, 22b Second SSD drive, 24 Switch, 26 Network controller, 32 Storage server, 34 Network.

Claims

1. a host unit that performs information processing; a memory for storing data used in the information processing; a memory controller that executes access to the memory in response to a request from the host unit; Equipped with The information processing device is characterized in that the memory controller realizes a read-only mode in which only read requests for data stored in the memory are accepted, and accordingly, the frequency of polling for read requests from the host unit is increased, and the depth of the queue that stores the read requests is increased in the memory area built into the memory controller.

2. the memory controller, in a read / write mode in which a write request to the memory is accepted together with the read request, switches the memory to the read-only mode after completing storage of the data to be used for the information processing; 2. The information processing apparatus according to claim 1, wherein the host unit issues a read request to the memory in the read-only mode, and uses the read data to progress information processing.

3. 3. The information processing apparatus according to claim 2, wherein the memory controller switches firmware that defines its own processing when switching from the read / write mode to the read-only mode.

4. 4. The information processing apparatus according to claim 3, wherein the host unit remounts a device drive including the memory controller whose firmware has been switched when switching from the read / write mode to the read-only mode.

5. a plurality of device drives including the memory and a memory controller that executes access to the memory; 5. The information processing device according to claim 2, wherein, during a certain period, one of the memory controllers realizes a read-only mode, while another memory controller realizes the read / write mode.

6. The system includes a plurality of SSDs including an SSD (Slid State Drive) that can be switched between a read-only mode that accepts only read requests and a read / write mode that accepts both read requests and write requests, the SSD in the read-only mode stores application data used for information processing; The SSD in the read / write mode writes data to be saved that has been generated or downloaded during the information processing, An information processing device characterized in that, upon switching to the read-only mode, the memory controller of the SSD increases the frequency of polling for the read requests and increases the depth of the queue that stores the read requests in the memory area built into the memory controller.

7. An information processing system including an information processing device that executes information processing, and a server that provides data used in the information processing to the information processing device via a network, The information processing device includes: a plurality of device drives each including a memory for storing data provided by the server and a memory controller for accessing the memory in response to a request from a host unit; An information processing system characterized in that the memory controller corresponding to the memory in which the storage of data used for the information processing has been completed realizes a read-only mode in which only read requests for data stored in that memory are accepted, and accordingly, the frequency of polling for read requests from the host unit is increased, and the depth of the queue that stores the read requests is increased in the memory area built into the memory controller.

8. The information processing system described in claim 7, characterized in that while the information processing device is progressing with information processing using data read from the memory in read-only mode, it obtains data from the server to be used for information processing that is expected to be executed in the future, and stores the obtained data in the memory of another device drive in read / write mode that accepts write requests to the memory as well as the read requests.

9. The information processing system described in claim 7 or 8, characterized in that the information processing device writes data to be saved that occurs during information processing using data read from the memory in read-only mode to the memory of another device drive in read / write mode that accepts write requests to the memory as well as read requests.

10. The information processing system according to claim 9, characterized in that the information processing device switches the device drive in the read-only mode to the read / write mode at a predetermined timing, and copies the data to be saved that has been written to the memory of the other device driver to the memory of the device driver after the mode switch.

11. 11. The information processing system according to claim 7, wherein the plurality of device drives are connected in parallel to the host unit via a switch.

12. 11. The information processing system according to claim 7, wherein the plurality of device drives are cascade-connected to the host unit.

13. storing data to be used for information processing in a memory; After the data storage is completed, the memory is put into a read-only mode in which only read requests for the stored data are accepted, and accordingly, the frequency of polling for the read requests is increased and the depth of a queue for storing the read requests is increased in a memory area included in the memory controller; executing a read request to the memory; performing information processing using the data read in accordance with the read request; 2. An information processing method by an information processing device, comprising:

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