Display device, display panel, and driving method thereof

Abstract

The present disclosure provides a display device, a display panel, and a driving method thereof. The display panel includes a base substrate, a pixel array provided on the base substrate, and including a pixel group having a plurality of pixels, and a plurality of pixel driving chips provided on the base substrate, configured to drive the pixel array to display, and including a data signal terminal for receiving a data signal and a control signal terminal for receiving a control signal, and a plurality of pixels in a pixel group are connected to the same pixel driving chip. One display frame of the display panel includes an address assignment step and a data signal transmission step. The driving method includes inputting a control signal to the control signal terminal and a first data signal to the data signal terminal in the address assignment step, and inputting a second data signal to the data signal terminal in the data signal transmission step. The present disclosure can reduce the number of signal lines and power consumption.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a display device, a display panel, and a driving method thereof. [Background technology]

[0002] With the continuous development of light-emitting diode (LED) technology, mini LEDs have been miniaturized to less than 300 microns in size, and thousands, tens of thousands, or even more mini LEDs are fixed on a substrate to achieve more precise local dimming, resulting in a display screen with high contrast and excellent color expression.Mini LED display devices use a passive matrix (PM) driving method, which consumes a lot of power. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present disclosure is to provide a display device, a display panel, and a driving method thereof that can reduce power consumption. [Means for solving the problem]

[0004] According to one aspect of the present disclosure, there is provided a display panel, comprising: A base substrate; a pixel array provided on the base substrate, the pixel array including a pixel group having a plurality of pixels; a plurality of pixel driving chips disposed on the base substrate, configured to drive the pixel array to display, the pixel driving chips including a data signal terminal for receiving a data signal and a control signal terminal for receiving a control signal; The pixels in the pixel group are connected to the same pixel drive chip.

[0005] Furthermore, the pixel group includes a plurality of the pixels located in different pixel rows of the pixel array.

[0006] Furthermore, the pixel group includes a plurality of the pixels located in different pixel columns of the pixel array.

[0007] Furthermore, the plurality of pixels in the pixel group are distributed along one direction.

[0008] Furthermore, the pixels in the pixel group are located in the same pixel row of the pixel array.

[0009] Furthermore, the pixels in the pixel group are located in the same pixel column in the pixel array.

[0010] Furthermore, the plurality of pixel driving chips include at least one chip column, which is parallel to the pixel columns in the pixel array, and which is located between two adjacent pixel columns.

[0011] Furthermore, two adjacent pixel columns form a plurality of pixel groups, and the plurality of pixel groups are distributed along the extension direction of the pixel columns, and the plurality of pixel driving chips in the chip column located between the two adjacent pixel columns are connected to the plurality of pixel groups in a one-to-one correspondence.

[0012] Furthermore, the plurality of pixel driving chips form a plurality of chip columns, and two of the pixel columns are present between two adjacent chip columns.

[0013] Furthermore, the pixel includes a first sub-pixel, and the display panel further includes a plurality of power supply signal lines; The first sub-pixels in the two pixel columns located between two adjacent chip columns are connected to the same power supply signal line.

[0014] Furthermore, the display panel further includes a power supply signal line connected to the pixel.

[0015] Furthermore, the pixel includes a sub-pixel, and the sub-pixel includes a light-emitting diode, the power signal line is connected to the positive electrode of the light-emitting diode, and the pixel driving chip is connected to the negative electrode of the light-emitting diode.

[0016] Furthermore, the display panel further includes data signal lines connected to the data signal terminals.

[0017] Furthermore, the number of the data signal lines is plural, the plurality of pixel driving chips include at least one chip column, and the data signal terminals of the plurality of pixel driving chips in the chip column are connected to the same data signal line.

[0018] Furthermore, the display panel further includes a control signal line connected to the control signal terminal.

[0019] Furthermore, the number of the control signal lines is plural, the plurality of pixel driving chips include at least one chip row, and the control signal terminals of the plurality of pixel driving chips in the chip row are connected to the same control signal line.

[0020] Furthermore, the display panel further comprises: a data signal line connected to the data signal terminal; a control chip connected to the control signal lines and the data signal lines, and used to provide control signals to the control signal lines and data signals to the data signal lines.

[0021] Furthermore, the display panel includes a display area and a peripheral area surrounding the display area, the pixel driving chip is located in the display area, and the control chip is located in the peripheral area.

[0022] In addition, the pixel driving chip further includes a power supply voltage terminal and / or a ground terminal.

[0023] Furthermore, the number of pixel rows and the number of pixel columns are both even numbers.

[0024] Furthermore, a plurality of the pixel driving chips are arranged in an array.

[0025] According to one aspect of the present disclosure, there is provided a display device including the above-described display panel.

[0026] According to one aspect of the present disclosure, there is provided a method for driving a display panel, the method including the above-described display panel, wherein one display frame of the display panel includes an address assignment step and a data signal transmission step, and the driving method includes: In the address assignment step, inputting a control signal to the control signal terminal and a first data signal to the data signal terminal; The data signal transmitting step includes inputting a second data signal to the data signal terminal.

[0027] In the display device, display panel and driving method thereof disclosed herein, during the driving process, a control signal is input to the control signal terminal of the pixel driving chip, a first data signal is input to the data signal terminal, and a second data signal is input to the data signal terminal of the pixel driving chip, so that each pixel driving chip provides a data signal to a corresponding pixel, thereby realizing an active matrix driving method. In addition, multiple pixels in a pixel group are connected to the same pixel driving chip, so that the number of signal lines on the base substrate is reduced, which makes the process easier, reduces the driving power consumption and driving costs of the entire display module, and significantly improves the competitiveness of the product. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a schematic diagram of the display area of ​​FIG. [Figure 3] FIG. 3 is a schematic diagram of the pixel array and pixel driving chip distribution in FIG. [Figure 4] FIG. 4 is a schematic diagram of the pixel group and pixel driving chip of FIG. [Figure 5]FIG. 5 is another schematic diagram of a pixel group and a pixel driving chip in a display panel according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is yet another schematic diagram of a pixel group and a pixel driving chip in a display panel according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a connection schematic diagram of a pixel driving chip without a power supply voltage terminal according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a sequence diagram corresponding to a method for driving a display panel according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a sequence diagram of the signal channel terminals of the pixel driving chip according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a schematic diagram of encoding a data signal according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0029] Exemplary embodiments are described in detail herein, examples of which are illustrated in the drawings. Where the following description is accompanied by drawings, like reference numerals in different drawings shall refer to like or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Rather, they are merely examples of devices consistent with certain aspects of the present disclosure as detailed in the appended claims.

[0030] The terms used in this disclosure are for the purpose of describing particular embodiments only and are not intended to limit the disclosure. Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. As used in the specification and claims of this disclosure, the words "first," "second," and similar words do not denote order, quantity, or importance, but are merely used to distinguish between different elements. Similarly, similar words such as "one" or "an" do not denote a quantitative limitation, but rather indicate the presence of at least one. The words "plurality" or "several" denote two or more. Unless otherwise specified, similar words such as "front," "rear," "lower," and / or "upper" are used for convenience of description only and are not limited to one location or one spatial orientation. Similar words such as "comprise" or "include" are intended to indicate that the elements or objects preceding "comprise" or "include" cover the elements or objects listed after "comprise" or "include" and equivalents thereof, and do not exclude other elements or objects. Similar terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in the specification of this disclosure and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. The term "and / or," as used herein, should also be understood to include any and all possible combinations of one or more of the associated listed items.

[0031] An embodiment of the present disclosure provides a display panel, which may include a base substrate, a pixel array, and a pixel driving chip 2, as shown in Figures 1 to 4 .

[0032] The pixel array is disposed on a base substrate. The pixel array includes a pixel group 8. The pixel group 8 includes a plurality of pixels 1. A plurality of the pixel driving chips 2 are provided. The plurality of pixel driving chips 2 are disposed on the base substrate and configured to drive the pixel array to display. The pixel driving chip 2 includes a data signal terminal 4 for receiving a data signal and a control signal terminal 3 for receiving a control signal. The plurality of pixels 1 in the pixel group 8 are connected to the same pixel driving chip 2.

[0033] In the display panel according to the embodiment of the present disclosure, during the driving process, a control signal is input to the control signal terminal 3 of the pixel driving chip 2, a first data signal is input to the data signal terminal 4 of the pixel driving chip 2, and a second data signal is input to the data signal terminal 4 of the pixel driving chip 2, so that each pixel driving chip 2 provides a data signal to a corresponding pixel 1, thereby realizing an active matrix driving method. In addition, multiple pixels 1 in a pixel group 8 are connected to the same pixel driving chip 2, so that the number of signal lines on the base substrate is reduced, which reduces the process difficulty and reduces the driving power consumption and driving costs of the entire display module, thereby significantly improving the competitiveness of the product.

[0034] Hereinafter, each component of the display panel according to the embodiment of the present disclosure will be described in detail.

[0035] The base substrate may be a rigid base substrate, and examples of materials include, but are not limited to, glass, quartz, PMMA (Polymethyl methacrylate), plastic, etc. in the embodiments of the present disclosure.

[0036] The pixel array is disposed on a base substrate. As shown in FIG. 1, the display panel may include a display area 10 and a peripheral area 11 surrounding the display area 10. The pixel array may be disposed in the display area 10 of the display panel. As shown in FIG. 3, the pixel array may include a plurality of pixel rows 300 and a plurality of pixel columns 100. The pixel rows 300 may extend along a first direction, and the pixel columns 100 may extend along a second direction. The first direction may be perpendicular to the second direction. The number of pixel rows 300 may be even, but the present disclosure is not limited thereto, and may be odd. The number of pixel columns 100 may be even, but the present disclosure is not limited thereto, and may be odd. The pixel row 300 may include a plurality of pixel 1s. The pixel column 100 may include a plurality of pixel 1s. As shown in FIG. 4, the pixel 1s may include a plurality of sub-pixels. The sub-pixels may emit light of different colors, or may emit light of the same color. Specifically, the plurality of subpixels may include a first subpixel 101, a second subpixel 102, and a third subpixel 103. The first subpixel 101 may be a red subpixel or a blue subpixel, but the present disclosure is not limited thereto, and may be a green subpixel. The second subpixel 102 may be a red subpixel or a blue subpixel, but the present disclosure is not limited thereto, and may be a green subpixel. The third subpixel 103 may be a red subpixel or a blue subpixel, but the present disclosure is not limited thereto, and may be a green subpixel. For example, when the plurality of subpixels emit light of different colors, the first subpixel 101 is a red subpixel that emits red light, the second subpixel 102 is a blue subpixel that emits blue light, and the third subpixel 103 is a green subpixel that emits green light. Each subpixel may include one or more light-emitting diodes. The light emitting diode may be a mini LED, and of course, the light emitting diode may be a micro LED, but the embodiments of the present disclosure are not limited thereto.For example, if a subpixel includes two light emitting diodes, the two light emitting diodes are connected in parallel and have the same color. The orthogonal projection of the light emitting diode on the base substrate may be a rectangle with a width of 70 μm to 100 μm and a length of 120 μm to 180 μm. The light emitting diode is a standalone component and can be mounted on the base substrate by surface mount technology (SMT) or mass transfer technology.

[0037] As shown in FIG. 1, the pixel array may include one pixel group 8, but of course the pixel array may also include multiple pixel groups 8, that is, the multiple pixels 1 in the pixel array may be divided into multiple pixel groups 8. At least one pixel group 8 in the multiple pixel groups 8 includes multiple pixels 1. When there are multiple pixel groups 8, the number of pixels 1 in the multiple pixel groups 8 may be the same, or

[0038] Of course, the number of pixels 1 in the two pixel groups 8 may be different. Multiple pixels 1 among the multiple pixels 1 in the pixel group 8 may be located in different pixel rows 300 in the pixel array. That is, at least two pixels 1 among the multiple pixels 1 in the pixel group 8 may be located in different pixel rows 300 in the pixel array. The different pixel rows 300 may be sequentially arranged pixel rows 300, but this is not particularly limited in the embodiments of the present disclosure. In an example where a pixel group 8 includes four pixels 1, two of the four pixels 1 are located in different pixel rows 300, one pixel 1 of the two pixels 1 is located in the n-th pixel row 300 and the other pixel 1 is located in the (n+1)-th pixel row 300, where n is an integer greater than or equal to 1, and the n-th pixel row 300 and the (n+1)-th pixel row 300 are sequentially arranged pixel rows 300. Of course, three of the four pixels 1 may be located in different pixel rows 300, or one of the three pixels 1 may be located in the n-th pixel row 300, another in the (n+1)-th pixel row 300, and the remaining one in the (n+2)-th pixel row 300. Furthermore, as shown in Figure 6, each pixel 1 of the four pixels 1 is located in a different pixel row 300, for example, the four pixels 1 are located in the same pixel column 100.

[0039] Of course, multiple pixels 1 among the multiple pixels 1 in the pixel group 8 can be located in different pixel columns 100 in the pixel array. That is, at least two pixels 1 among the multiple pixels 1 in the pixel group 8 can be located in different pixel columns 100 in the pixel array. The different pixel columns 100 may be sequentially arranged pixel columns 100, but this is not particularly limited in the embodiments of the present disclosure. In an example where the pixel group 8 includes four pixels 1, two of the four pixels 1 are located in different pixel columns 100, one pixel 1 of the two pixels 1 is located in the m-th pixel column 100 and the other pixel 1 is located in the (m+1)-th pixel column 100, where m is an integer greater than or equal to 1, and the m-th pixel column 100 and the (m+1)-th pixel column 100 are sequentially arranged pixel columns 100. Of course, three of the four pixels 1 may be located in different pixel columns 100, or one of the three pixels 1 may be located in the m-th pixel column 100, another in the (m+1)-th pixel column 100, and the remaining one in the (m+2)-th pixel column 100. Furthermore, as shown in FIG. 5 , each pixel 1 of the four pixels 1 is located in a different pixel column 100, for example, the four pixels 1 are located in the same pixel row 300.

[0040] The pixels 1 in the pixel group 8 may be distributed along the same direction. In one embodiment of the present disclosure, as shown in FIG. 5, the pixels 1 in the pixel group 8 are located in the same pixel row 300 in the pixel array, and the pixels 1 in the same pixel row 300 may be arranged sequentially. For convenience of explanation, the four pixels 1 in FIG. 5 are numbered sequentially from left to right, and the distance between the second pixel 1 closest to the pixel driving chip 2 and the third pixel 1 is slightly larger than the distance between the first pixel 1 and the second pixel 1 and the distance between the third pixel 1 and the fourth pixel 1. However, in an actual layout design, any two pixels 1 may be arranged at equal intervals in the row direction. However, the embodiment of the present disclosure is not limited to this, and in an actual design, it is based on the pixel driving chip 2 not affecting the display effect of all pixels 1. In another embodiment of the present disclosure, as shown in FIG. 6, the pixels 1 in the pixel group 8 are located in the same pixel column 100 in the pixel array, and the pixels 1 in the same pixel column 100 may be arranged sequentially. 6 are numbered sequentially from top to bottom, and the distance between the second pixel 1 closest to the pixel driving chip 2 and the third pixel 1 is slightly larger than the distance between the first pixel 1 and the second pixel 1 and the distance between the third pixel 1 and the fourth pixel 1. However, in an actual layout design, any two pixels 1 may be equally spaced in the column direction, but the embodiments of the present disclosure are not limited to this, and the actual design is based on the pixel driving chip 2 not affecting the display effect of all pixels 1.

[0041] As shown in FIG. 4, the pixel driving chip 2 is disposed on a base substrate. The pixel driving chip 2 and pixel 1 may be disposed on the same side of the base substrate, or they may be disposed on opposite sides of the base substrate. The pixel driving chip 2 is connected to pixel 1. Here, the pixel driving chip 2 may be connected to multiple sub-pixels within pixel 1. Specifically, the signal terminals of the pixel driving chip 2 include multiple signal channel terminals 7, and the multiple signal channel terminals 7 of the pixel driving chip 2 may be connected to multiple sub-pixels within pixel 1 in a one-to-one correspondence. For example, if a sub-pixel includes an LED, the signal channel terminal 7 may be connected to a first electrode of the LED. The first electrode may be a negative electrode, or the first electrode may be a positive electrode. The signal terminals of the pixel driving chip 2 include a data signal terminal 4 and a control signal terminal 3. The data signal terminal 4 is configured to receive a data signal, and the control signal terminal 3 is configured to receive a control signal. The data signal may include a first data signal and a second data signal. The signal terminals of the pixel driving chip 2 may further include a power supply voltage terminal 5 and / or a ground terminal 6. For example, if the number of signal terminals of the pixel driving chip 2 is X, the maximum number of signal terminals in the row direction is a, and the maximum number of signal terminals in the column direction is b, where a, b, and X are all integers and the product of a and b is less than or equal to X. In the pixel driving chip 2 according to the present disclosure, the absolute value of the difference between a and b is minimum. This prevents the pixel driving chip 2 from being too large in one direction, and solves the problem of the pixel driving chip 2 being too large in one direction, resulting in an excessively large pitch between multiple pixels 1. For example, if the pixel driving chip 2 has 16 signal terminals, the number of signal terminals in the row direction and the number of signal terminals in the column direction are both four.

[0042] The orthogonal projection of the pixel driving chip 2 on the base substrate may be a rectangle with a width of 350 μm to 450 μm and a length of 350 μm to 450 μm. The orthogonal projection of the pixel driving chip 2 on the base substrate may have the same length and width, but this is not particularly limited in the present invention. The area of ​​the orthogonal projection of the pixel driving chip 2 on the base substrate may be 8 to 15 times the area of ​​the light-emitting diode in the pixel 1 orthogonally projected on the base substrate. The pixel driving chip 2 is a standalone component and can be assembled on the base substrate by surface mount technology (SMT). Pads are provided on the base substrate, and when the pixel driving chip 2 is assembled on the base substrate by surface mount technology, the signal terminals of the pixel driving chip 2 are fixedly connected to the pads.

[0043] The number of pixel driving chips 2 is plural, and the plural pixel driving chips 2 cooperate to drive the pixel array to display. Here, as shown in FIGS. 1 and 4, plural subpixels 1 in a pixel group 8 are connected to the same pixel driving chip 2. That is, plural subpixels in plural pixels 1 are all connected to the same pixel driving chip 2. For example, if a pixel group 8 includes four pixels 1, and each pixel 1 includes three subpixels, all three subpixels in the four pixels 1 are all connected to the same pixel driving chip 2. That is, the pixel driving chip 2 is connected to 12 subpixels, and the pixel driving chip 2 may have 12 signal channel terminals 7, and the 12 signal channel terminals 7 are connected one-to-one to the first electrodes of the light-emitting diodes of each subpixel. When there are plural pixel groups 8, the plural pixel driving chips 2 correspond one-to-one to drive the plural pixel groups 8 to display.

[0044] As shown in FIG. 3 , multiple pixel driving chips 2 according to the present disclosure can be arranged in an array to form multiple chip columns 200 and multiple chip rows 400. The chip rows 400 may be parallel to the pixel rows 300 described above. The chip columns 200 may be parallel to the pixel columns 100 described above. The number of pixel driving chips 2 in the chip columns 200 may be equal to or less than the number of pixels 1 in the pixel columns 100. At least one of the multiple chip columns 200 is located between two adjacent pixel columns 100, and the chip column 200 located between the two adjacent pixel columns 100 is used to drive the two adjacent pixel columns 100 for display. Here, there is only one chip column 200 between the two adjacent pixel columns 100. The two adjacent pixel columns 100 may form multiple pixel groups 8, and the number of pixels 1 included in each pixel group 8 may be the same or different, and the multiple pixel groups 8 are distributed along the extension direction of the pixel columns 100. For example, if each pixel column 100 includes six rows of pixels 1 and each pixel group 8 includes four pixels 1, then for two adjacent pixel columns 100, two pixels 1 in the first row and two pixels 1 in the second row can form one pixel group 8, two pixels 1 in the third row and two pixels 1 in the fourth row can form another pixel group 8, and two pixels 1 in the fifth row and two pixels 1 in the sixth row can form yet another pixel group 8. Furthermore, the pixel driving chips 2 of the chip column 200 located between the two adjacent pixel columns 100 are connected to the pixel groups 8 in one-to-one correspondence.

[0045] Of course, the multiple pixel driving chips 2 according to the present disclosure do not have to be arranged in an array, and one pixel driving chip 2 can be connected to multiple pixels 1 in a pixel group 8 to reduce the number of signal lines on the base substrate. In one embodiment, the multiple pixel driving chips 2 are arranged in multiple chip rows 400 but not in multiple chip columns 200, and the number of pixel driving chips 2 in each chip row 400 may be the same. In another embodiment, the multiple pixel driving chips 2 are arranged in multiple chip columns 200 but not in multiple chip rows 400, and the number of pixel driving chips 2 in each chip column 200 may be the same.

[0046] As shown in FIGS. 1, 2, and 3, a display panel according to an embodiment of the present disclosure further includes a plurality of power signal lines. The power signal lines may be arranged parallel to a pixel column 100. The power signal lines are connected to pixels 1. Here, the power signal lines are connected to subpixels within pixels 1. Specifically, the power signal lines are connected to second electrodes of light-emitting diodes of the subpixels. For example, if the first electrode of the light-emitting diode is negative, the second electrode may be positive. Alternatively, if the first electrode of the light-emitting diode is positive, the second electrode may be negative. Here, for two pixel columns 100 located between two adjacent chip columns 200, the first subpixels 101 of the two pixel columns 100 are connected to the same power signal line, thereby reducing the number of power signal lines. Furthermore, as shown in FIGS. 1 and 4, the power signal lines may include a first power signal line VR and a second power signal line VGB. The red sub-pixel in each pixel 1 can be connected to a first power supply signal line VR, and the green and blue sub-pixels in each pixel 1 can both be connected to a second power supply signal line VGB.

[0047] 3, the (2k-1)th chip column 200 is provided between the (4k-3)th pixel column 100 and the (4k-2)th pixel column 100, and no chip column 200 exists between the (4k-2)th pixel column 100 and the (4k-1)th pixel column 100. The 2kth chip column 200 is provided between the (4k-1)th pixel column 100 and the 4kth pixel column 100, and the (4k-2)th pixel column 100 and the (4k-1)th pixel column 100 are provided between the (2k-1)th chip column 200 and the 2kth chip column 200. Here, the (2k-1)th chip column 200 is used to drive the (4k-3)th pixel column 100 and the (4k-2)th pixel column 100 for display, the 2kth chip column 200 is used to drive the (4k-1)th pixel column 100 and the 4kth pixel column 100 for display, and the first sub-pixel 101 of the (4k-2)th pixel column 100 and the first sub-pixel 101 of the (4k-1)th pixel column 100 can share a power signal line, and k is a positive integer. Furthermore, the distance between the (4k-3)th pixel column 100 and the (4k-2)th pixel column 100 may be greater than the distance between the (4k-2)th pixel column 100 and the (4k-1)th pixel column 100, and the distance between the (4k-1)th pixel column 100 and the 4kth pixel column 100 may be greater than the distance between the (4k-2)th pixel column 100 and the (4k-1)th pixel column 100.

[0048] That is, a pixel driving chip 2 is provided between some of the adjacent pixel rows 300, but no pixel driving chip 2 is provided between other parts of the adjacent pixel rows 300. The distance between two adjacent pixel rows 300 with a pixel driving chip 2 interposed therebetween is larger than the distance between two adjacent pixel rows 300 without a pixel driving chip 2 interposed therebetween. A pixel driving chip 2 is provided between some of the adjacent pixel columns 100, but no pixel driving chip 2 is provided between other parts of the adjacent pixel columns 100. The distance between two adjacent pixel columns 100 with a pixel driving chip 2 interposed therebetween is larger than the distance between two adjacent pixel columns 100 without a pixel driving chip 2 interposed therebetween. However, in an actual layout design, any two adjacent pixel rows 300 may be equally spaced apart in the column direction, or any two adjacent pixel columns 100 may be equally spaced apart in the row direction. The embodiments of the present disclosure are not limited to this, and the actual design is based on the assumption that the pixel driving chip 2 does not affect the display effect of any of the pixels 1.

[0049] As shown in FIGS. 1, 2, and 3, a display panel according to an embodiment of the present disclosure may further include a plurality of data signal lines DATA. The data signal lines DATA may be arranged parallel to the pixel column 100. The data signal lines DATA may be connected to the data signal terminals 4 of the pixel driving chips 2. The data signal terminals 4 of each pixel driving chip 2 in the chip column 200 may be connected to the same data signal line DATA, although the display panel according to the embodiment of the present disclosure is not limited thereto. The display panel according to the embodiment of the present disclosure may further include a plurality of control signal lines DE. The control signal lines DE may be arranged parallel to the pixel rows 300 in the pixel array. The control signal lines DE may be connected to the control signal terminals 3 of the pixel driving chips 2. The control signal terminals 3 of each pixel driving chip 2 in the chip row 400 may be connected to the same control signal line DE, although the embodiment of the present disclosure is not limited thereto. As shown in FIG. 1, a display panel according to an embodiment of the present disclosure may further include a control chip 9. The control chip 9 is connected to the control signal lines DE and the data signal lines DATA, and may provide control signals to the control signal lines DE and data signals to the data signal lines DATA. The control chip 9 can be located in the peripheral area 11 of the display panel.

[0050] As shown in FIGS. 1, 2, and 3, a display panel according to an embodiment of the present disclosure may further include a plurality of power supply voltage lines VCC. The power supply voltage line VCC may be arranged parallel to the pixel column 100. The power supply voltage line VCC may be connected to the power supply voltage terminal 5 of the pixel driving chip 2. The power supply voltage terminal 5 of each pixel driving chip 2 in the chip column 200 may be connected to the same power supply voltage line VCC, although this is not particularly limited in this embodiment. A display panel according to an embodiment of the present disclosure may further include a plurality of ground lines GND. The ground line GND may be arranged parallel to the pixel column 100. The ground line GND may be connected to the ground terminal 6 of the pixel driving chip 2. The ground terminal 6 of each pixel driving chip 2 in the chip column 200 may be connected to the same ground line GND, although this is not particularly limited in this embodiment. The power supply voltage terminal 5 according to the present disclosure is configured to receive a power supply voltage, and the control signal terminal 3 is configured to receive a control signal. By receiving the power supply voltage and the control signal separately through two signal ports, it is possible to prevent the pixel driving chip 2 from misreading the control signal, which would cause the pixel driving chip 2 to operate abnormally and affect the display effect.

[0051] In the present disclosure, signal lines such as the first power supply signal line VR, the second power supply signal line VGB, the control signal line DE, the data signal line DATA, the ground line GND, and the power supply voltage line VCC of the pixel driving chip 2 of the present invention may be formed directly on the base substrate, or may be manufactured by processes such as film formation and patterning. In the present disclosure, the pixel driving chip 2 can be assembled on the base substrate after the above-mentioned signal lines are formed by processes such as film formation and patterning. Here, there is an overlapping area between the orthogonal projection of the pixel driving chip 2 on the base substrate and the orthogonal projection of a partial region of the signal lines on the base substrate, which makes the most efficient use of wiring space and increases pixel layout density.

[0052] 7, the power supply voltage and the address signal may be input from the same signal terminal of the pixel driving chip 2, for example, the control signal terminal 3. As an example, in the present disclosure, the control function and the power supply function can be distinguished according to the amplitude of the signal received at the control signal terminal 3. For example, when the signal amplitude is higher than a certain preset level, the control function is performed, and when the signal amplitude is lower than a certain preset level, the power supply function is performed.

[0053] Taking a display panel with a resolution of 160×180 as an example, when the pixel driving chip 2 and the pixel 1 are connected in the configuration shown in FIG. 4 , the display panel requires 80 data signal lines DATA, 90 control signal lines DE, and 80 ground lines GND. Compared with a driving method in which a single pixel 1 is driven by a single pixel driving chip 2, the embodiment of the present disclosure can reduce the number of lines by half. The two pixel columns 100 located between two adjacent chip columns 200 can share the first power signal line VR and the second power signal line VGB. That is, in the display panel of FIG. 1, the left and right pixel columns 100 do not share the first power signal line VR and the second power signal line VGB with other pixel columns 100, but the pixel columns 100 located between the pixel columns 100 on both the left and right sides share the first power signal line VR and the second power signal line VGB. There are 81 first power signal lines VR and 81 second power signal lines VGB each. This significantly reduces the number of lines on the display panel, reduces manufacturing costs, and significantly improves product competitiveness.

[0054] Taking a display panel with a resolution of 160×180 as an example, when the pixel driving chip 2 and the pixels 1 are connected in the configuration shown in FIG. 5 , the display panel requires 40 data signal lines DATA, 180 control signal lines DE, 40 ground lines GND, 40 power supply voltage lines VCC, and 160 first power supply signal lines VR and 160 second power supply signal lines VGB.

[0055] Taking a display panel with a resolution of 160×180 as an example, when the pixel driving chip 2 and the pixels 1 are connected in the configuration shown in FIG. 6 , the display panel requires 160 data signal lines DATA, 45 control signal lines DE, 160 ground lines GND, 160 power supply voltage lines VCC, 160 first power supply signal lines VR, and 160 second power supply signal lines VGB.

[0056] An embodiment of the present disclosure further provides a display device. The display device may include a display panel according to any of the above-described embodiments. The display device may be applied to any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigation system. The display panel included in the display device is similar to the display panel in the above-described display panel embodiment, and therefore provides the same beneficial effects, and therefore a description thereof will be omitted here.

[0057] The embodiments of the present disclosure further provide a method for driving a display panel. The display panel may be any of the display panels according to the above embodiments. As an example, if each pixel driving chip 2 in the display panel is used to drive a pixel group 8, and each pixel group 8 includes four pixels 1, then 4M*N pixels 1 and pixel driving chips 2 are arranged in an array of N rows and M columns on the display panel, where M and N are both positive integers. When the display panel displays a frame, the display panel may include an address assignment step and a data signal transmission step. As shown in FIG. 8, the method for driving the display panel may include steps S1 and S3.

[0058] In step S1, an address is assigned to each pixel driving chip 2.

[0059] For example, the control signal terminals 3 of each pixel driving chip 2 in the same chip row 400 are connected to a single control signal line DE, and the data signal terminals 4 of each pixel driving chip 2 in the same chip column 200 are connected to a single data signal line DATA. As shown in Fig. 8 , in step S1, the control chip 9 inputs first data signals to the multiple chip columns 200 via the multiple data signal lines DATA, and the control chip 9 inputs control signals to the multiple chip rows 400 sequentially, row by row, via the multiple control signal lines DE, thereby controlling the data signal terminals 4 of the pixel driving chips 2 located in the same chip row 400 to simultaneously receive first data signals transmitted from different data signal lines. Specifically, the display panel includes N chip rows 400 and N control signal lines. As shown in FIG. 8, when the first control signal line DE1 transmits a control signal, the pixel driving chips 2 in the first chip row 400 are triggered, and the remaining chip rows 400 are not triggered. Each data signal line DATA simultaneously transmits a different first data signal to the pixel driving chips 2 located in different chip columns 200 in the first chip row 400, and the pixel driving chips 2 in each column in the first chip row 400 receive the first data signal. The control chip 9 transmits the Nth control signal line DE N When a control signal is transmitted via the DATA line, the pixel driving chip 2 in the Nth chip row 400 is triggered, and the remaining chip rows 400 are not triggered. Each data signal line DATA simultaneously transmits a different first data signal to the pixel driving chip 2 in a different chip column 200 in the Nth chip row 400, and the pixel driving chip 2 in each column of the Nth chip row 400 receives the first data signal. The first data signal may be a digital signal and may include a start command SoT, address information ID, interval command DCX, and end command EoT, which are sequentially set. The first data signal includes the address information ID, which can be used to set the address information ID in the pixel driving chip 2. The length of the first data signal may be 12 bits, where the start command SoT is 1 bit, the address information ID is 8 bits, the interval command DCX is 1 bit, and the end command EoT is 2 bits. After receiving the first data signal, each pixel driving chip 2 stores the address information ID therein.

[0060] It can be understood that before step S1, the pixel driving chip 2 of the present disclosure may be in a low-power operation mode or a sleep state, which is a non-operational state. A power supply voltage is input to the power supply voltage terminal 5 of the pixel driving chip 2 via the power supply voltage line VCC to wake up the pixel driving chip 2 from the sleep state, i.e., step S0 in FIG. 8 .

[0061] The step of inputting the second data signal to the data signal terminal 4 of the pixel driving chip 2 is step S3, which is also called a data signal transmission step.

[0062] 8, in step S3, the control chip 9 inputs second data signals to the plurality of chip rows 200 via the plurality of data signal lines DATA. Here, the present disclosure relates to simultaneously inputting the second data signals to the plurality of chip rows 200. Each second data signal includes a plurality of sub-data information Subdata_1, Subdata_2, ..., Subdata_N.

[0063] Each sub-data information includes address information ID and pixel data information. The sub-data information may be a digital signal, specifically including a start command SoT, address information ID, a data transmission command DCX, an interval command IoT, pixel data information, and an end command EoT. The pixel data information includes a plurality of sub-pixel data Rda1, Rda2, Rda3, Rda4, Gda1, Gda2, Gda3, Gda4, Bda1, Bda2, Bda3, and Bda4. When the data transmission command DCX is a set value, it indicates that data transmission is to be performed. For example, DCX=1 indicates data transmission. When the pixel driving chip 2 recognizes that the value of DCX is 1, it transmits the pixel data information in the sub-data information to the corresponding pixel. The subpixel data Rda1, Rda2, Rda3, and Rda4 indicate data information required for emitting light from the red subpixels of each of the four pixels 1 connected to the pixel driving chip 2, the subpixel data Gda1, Gda2, Gda3, and Gda4 indicate data information required for emitting light from the green subpixels of each of the four pixels 1 connected to the pixel driving chip 2, and the subpixel data Bda1, Bda2, Bda3, and Bda4 indicate data information required for emitting light from the blue subpixels of each of the four pixels 1 connected to the pixel driving chip 2.

[0064] In a specific implementation, the length of each sub-data information may be set to 63 bits, where the start command SoT occupies 1 bit, the address information ID occupies 8 bits, the data transmission command DCX occupies 1 bit, the interval command IoT occupies 1 bit, the sub-pixel data Rda1, Rda2, Rda3, and Rda4 occupy a total of 16 bits, the sub-pixel data Gda1, Gda2, Gda3, and Gda4 occupy a total of 16 bits, the sub-pixel data Bda1, Bda2, Bda3, and Bda4 occupy a total of 16 bits, and the end command EoT occupies 2 bits. The interval command IoT may also be set between any two adjacent sub-data information. One pixel driving chip 2 is configured to drive a total of four pixels 1 in one pixel group 8. The number relationship between the four pixels 1 connected to the pixel driving chip 2 can be realized by a digital logic circuit within the pixel driving chip, thereby accurately distributing each sub-pixel data in the pixel data information to a corresponding signal channel terminal 7.

[0065] That is, it can be understood that the address information ID in each sub-data information corresponds to the address information ID received by each pixel driving chip 2 in step S1, and the pixel data information includes a set of data information for each pixel 1 driven by the pixel driving chip 2.

[0066] Here, the multiple sub-data information may be arranged in a specific order (for example, the specific order may be the order in which the multiple pixel driving chips 2 in each chip column 200 are arranged along the column direction) to form the second data signal, or the multiple sub-data information may not be arranged in the specific order described above, but the present disclosure is not limited thereto.

[0067] The second data signal is transmitted to the pixel driving chips 2 in the same column via the data signal line DATA, and each pixel driving chip 2 decodes and aligns the address information ID in the plurality of sub-data information in the second data signal to selectively receive the sub-data information corresponding to the same address information ID received and stored in step S1, and obtains the pixel data information in the sub-data information.

[0068] Each signal channel terminal 7 of the pixel driving chip 2 forms a signal channel with a corresponding subpixel. Specifically, the pixel driving chip 2 is configured to drive four pixels 1, each of which includes three subpixels of different colors. Therefore, the pixel driving chip 2 includes 12 signal channel terminals 7, each connected to a different subpixel. After step S3, the pixel driving chip 2 receives and stores the data information of the four pixels 1 connected to it. The signal channel terminals 7 connected to the subpixels of different colors do not need to be turned on simultaneously, so that the subpixels of different colors are driven at different times. Specifically, as shown in FIGS. 4, 7, and 9, the signal channel terminals 7(R1), 7(R2), 7(R3), and 7(R4) connected to the red subpixels may all be turned on first. That is, in the time period when CH_R in FIG. 9 becomes an enabled level, the red subpixels are driven first, and the signal channel terminals 7(G1), 7(G2), 7(G3), and 7(G4) connected to the green subpixels may be turned on a few nanoseconds later than the signal channel terminals 7(R1), 7(R2), 7(R3), and 7(R4) connected to the red subpixels. That is, CH_G in FIG. 9 becomes an enabled level later than CH_R, and the green subpixels are driven in the time period when CH_G becomes an enabled level. Compared to the signal channel terminals 7(G1), 7(G2), 7(G3), and 7(G4) connected to the green subpixels, the signal channel terminals 7(B1), 7(B2), 7(B3), and 7(B4) connected to the blue subpixels may be turned on a few nanoseconds later. 9, CH_B becomes active later than CH_G, and the blue subpixel is driven during the time period when CH_B becomes active. This reduces the transient load capability and transient noise of the pixel driving chip 2, and although the subpixels of each color are driven with a delay of several nanoseconds from each other, this delay is barely noticeable to the human eye, and they are effectively brightened simultaneously, thereby achieving accurate full-color display.

[0069] 10 is a schematic diagram of encoding a first data signal and a second data signal according to the present disclosure. As shown in FIG. 10, in the present disclosure, the meaning of each bit in the first data signal and the second data signal can be represented by designing the duty ratio in the pulse sequence. For example, if the duty ratio of a pulse in the pulse sequence is 25%, that bit represents 0; if the duty ratio of a pulse is 75%, that bit represents 1; if the duty ratio of a pulse is 50%, that bit represents a start command SoT; and if the duty ratios of two consecutive pulses are both 50%, that is, if two consecutive SoTs occur, the meaning of these two bits is an end command EoT.

[0070] As shown in FIG. 8 , one display frame of the display panel according to the present disclosure may further include a current setting step S2 located between the address assignment step S1 and the data signal transmission step S3. In the current setting step S2, current setting information Co is input to the data signal terminal 4 of the pixel driving chip 2 to control the magnitude of the driving current of the pixel driving chip 2 and more accurately control the light emission brightness of the corresponding pixel 1. The length of the current setting information Co may be 63 bits, specifically including a 1-bit start command SoT, 8-bit address information ID, a 1-bit current setting command DCX, a 1-bit interval command IoT, 16-bit data consisting of a frame start command C and a control command (e.g., indicating a current amplitude correction coefficient that the signal channel terminal 7 needs to provide to the light emitting diode), a 1-bit interval command IoT, 16-bit reserved control command bits, a 1-bit interval command IoT, 16-bit reserved control command bits, and a 2-bit end command EoT. Here, a set value of the current setting command DCX indicates that current setting is to be performed, e.g., DCX = 0 indicates that current setting is to be performed.

[0071] It can be understood that in the process of displaying a screen for each frame, the display panel may need to perform steps S0, S1, S2, and S3 in order before displaying the first frame screen (i.e., the enable steps of CH_R, CH_G, and CH_B, the steps in which the corresponding pixels are driven), or before displaying the frame screen after the first frame, the display panel may only perform steps S2 and S3, or may only perform step S3.

[0072] The embodiments of the present disclosure are described in an example in which one pixel driving chip provides signals to a pixel group having four pixels. For example, a display panel including pixels in odd rows or odd columns can also be designed and driven using the embodiments of the present disclosure, in which some signal channel terminals of some pixel driving chips can be empty (i.e., not connected to any components), or a pixel driving chip that provides signals to a pixel group having an odd number of pixels can be provided in the display panel, and the present disclosure is not limited thereto.

[0073] The above is merely a preferred embodiment of the present disclosure and does not impose any formal limitations on the present disclosure. Although the present disclosure has been disclosed as a preferred embodiment as above, it is not used to limit the present disclosure, and any technical person familiar with the present disclosure can create an equivalent embodiment with equivalent changes by making some changes or modifications using the technical content of the above disclosure within the scope of the technical solution of the present disclosure, and any simple modifications, equivalent changes and modifications made to the above embodiment based on the technical substance of the present disclosure fall within the scope of the technical solution of the present disclosure, as long as they do not deviate from the technical solution of the present disclosure. [Explanation of symbols]

[0074] 1: Pixel 101: First sub-pixel 102: Second sub-pixel 103: Third sub-pixel 2: Pixel driving chip 3: Control signal terminal 4: Data signal terminal 5: Power supply voltage terminal 6: Ground terminal 7: Signal channel terminal 8: Pixel Group 9: Control chip 10:Display area 11: Surrounding area 100: pixel row 200: Chip row 300: pixel rows 400: Tip line

Claims

1. A base substrate; a pixel array provided on the base substrate, the pixel array including a pixel group having a plurality of pixels; a plurality of pixel driving chips provided on the base substrate, configured to drive the pixel array to display, the pixel driving chips including data signal terminals for receiving data signals and control signal terminals for receiving control signals; a plurality of the pixels in the pixel group are connected to the same pixel driving chip; the plurality of pixel driving chips form a plurality of chip columns, the chip columns being parallel to pixel columns in the pixel array, the chip columns being located between two adjacent pixel columns, and two pixel columns being present between the two adjacent chip columns; the pixel includes a first sub-pixel, and the display panel further includes a plurality of power supply signal lines; The first sub-pixels in the two pixel columns located between the two adjacent chip columns are connected to the same power supply signal line. A display panel characterized by:

2. The pixel group includes a plurality of the pixels located in different pixel rows of the pixel array.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

3. The pixel group includes a plurality of the pixels located in different pixel columns of the pixel array.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

4. Two adjacent pixel columns constitute a plurality of pixel groups, and the plurality of pixel groups are distributed along the extending direction of the pixel columns, and the plurality of pixel driving chips in the chip column located between the two adjacent pixel columns are connected to the plurality of pixel groups in one-to-one correspondence.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

5. The pixel includes a plurality of sub-pixels, the plurality of sub-pixels including the first sub-pixel, and each of the sub-pixels includes a light-emitting diode, the power supply signal line is connected to a positive electrode of the light-emitting diode, and the pixel driving chip is connected to a negative electrode of the light-emitting diode.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

6. The display panel further includes a data signal line connected to the data signal terminal.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

7. The number of the data signal lines is plural, and the data signal terminals of the pixel driving chips in the chip row are connected to the same data signal line.

7. The display panel according to claim 6, wherein the first and second electrodes are arranged parallel to each other.

8. The display panel further includes a control signal line connected to the control signal terminal.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

9. The number of the control signal lines is plural, the plural pixel driving chips include at least one chip row, and the control signal terminals of the plural pixel driving chips in the chip row are connected to the same control signal line.

9. The display panel according to claim 8.

10. The display panel further comprises: a data signal line connected to the data signal terminal; a control chip connected to the control signal lines and the data signal lines, the control chip being used to provide control signals to the control signal lines and data signals to the data signal lines.

9. The display panel according to claim 8.

11. The display panel includes a display area and a peripheral area surrounding the display area, the pixel driving chip is located in the display area, and the control chip is located in the peripheral area.

11. The display panel according to claim 10.

12. The pixel driving chip further includes a power supply voltage terminal and / or a ground terminal.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

13. The number of pixel rows and pixel columns is both even.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

14. A plurality of the pixel driving chips are arranged in an array.

2. The display panel according to claim 1, wherein the first and second electrodes are arranged parallel to each other.

15. A display panel according to any one of claims 1 to 14. A display device characterized by:

16. A method for driving a display panel using the display panel according to any one of claims 1 to 14, wherein one display frame of the display panel includes an address assignment step and a data signal transmission step, and the driving method comprises: In the address assignment step, inputting a control signal to the control signal terminal and a first data signal to the data signal terminal; The data signal transmitting step includes inputting a second data signal to the data signal terminal. A display panel driving method comprising:

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