electronic equipment

Abstract

The purpose of the present embodiment is to provide an electronic device in which the occurrence of lines can be suppressed, and a decrease in precision can be suppressed.　This electronic device comprises a first lower electrode connected to a first upper electrode, a second lower electrode connected to a second upper electrode, a third lower electrode connected to a third upper electrode, a fourth lower electrode connected to a fourth upper electrode, and a fifth lower electrode connected to a fifth upper electrode, the second lower electrode overlapping the first upper electrode and the second upper electrode, the third lower electrode overlapping the first upper electrode and the third upper electrode, the fourth lower electrode overlapping the second upper electrode, the third upper electrode, and the fourth upper electrode, and the fifth lower electrode overlapping the second upper electrode, the third upper electrode, and the fifth upper electrode.

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to an electronic device. [Background technology]

[0002] 2. Description of the Related Art Electronic devices equipped with small and thin imaging elements have been developed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-098758 Summary of the Invention [Problem to be solved by the invention]

[0004] The present embodiment provides an electronic device that can suppress the occurrence of streaks and the deterioration of accuracy. [Means for solving the problem]

[0005] An electronic device according to an embodiment includes: a first upper electrode; A second upper electrode; a third upper electrode; a fourth upper electrode; A fifth upper electrode; a first lower electrode connected to the first upper electrode; a second lower electrode connected to the second upper electrode; a third lower electrode connected to the third upper electrode; a fourth lower electrode connected to the fourth upper electrode; a fifth lower electrode connected to the fifth upper electrode; an insulating layer provided between the first upper electrode, the second upper electrode, the third upper electrode, the fourth upper electrode, and the fifth upper electrode, and between the first lower electrode, the second lower electrode, the third lower electrode, the fourth lower electrode, and the fifth lower electrode; a counter electrode facing the first upper electrode, the second upper electrode, the third upper electrode, the fourth upper electrode, the fifth upper electrode, the first lower electrode, the second lower electrode, the third lower electrode, the fourth lower electrode, and the fifth lower electrode; Equipped with the second lower electrode overlaps the first upper electrode and the second upper electrode; the third lower electrode overlaps the first upper electrode and the third upper electrode; the fourth lower electrode overlaps the second upper electrode, the third upper electrode, and the fourth upper electrode; The fifth lower electrode overlaps the second upper electrode, the third upper electrode, and the fifth upper electrode.

[0006] Moreover, the electronic device according to an embodiment includes: An upper electrode; A lower electrode; a region where the upper electrode and the lower electrode are not provided; Equipped with The upper electrode is a central electrode having a circular shape; a first peripheral electrode having an annular shape and surrounding the central electrode; a second peripheral electrode having an annular shape and surrounding the first peripheral electrode; a third peripheral electrode having an annular shape and surrounding the second peripheral electrode; a fourth peripheral electrode having an annular shape and surrounding the third peripheral electrode; and The central electrode, the first peripheral electrode, the second peripheral electrode, the third peripheral electrode, and the fourth peripheral electrode each include a plurality of segment electrodes. [Effects of the Invention]

[0007] According to this embodiment, it is possible to provide an electronic device that can suppress the occurrence of streaks and the deterioration of accuracy. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is an exploded perspective view showing an example of a schematic configuration of an electronic device to which the embodiment can be applied. [Figure 2] FIG. 2 is a cross-sectional view showing an example of a schematic configuration of the electronic device shown in FIG. [Figure 3] FIG. 3 is an exploded perspective view showing an outline of a partial configuration of the electronic device of this embodiment. [Figure 4] FIG. 4 is a diagram illustrating a method for measuring distance using a coded aperture. [Figure 5] FIG. 5 is a plan view showing an example of a schematic configuration of a part of a liquid crystal element. [Figure 6] FIG. 6 is a cross-sectional view of the liquid crystal element taken along line A1-A2 shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view showing an example of a schematic configuration of a liquid crystal element. [Figure 8A] FIG. 8A is a plan view of the liquid crystal element of Comparative Example 1. FIG. [Figure 8B] FIG. 8B is a plan view of the liquid crystal element of Comparative Example 1. FIG. [Figure 8C] FIG. 8C is a plan view of the liquid crystal element of Comparative Example 1. FIG. [Figure 8D] FIG. 8D is a plan view of the liquid crystal element of Comparative Example 1. FIG. [Figure 9A] FIG. 9A is a plan view of a liquid crystal element of Comparative Example 2. FIG. [Figure 9B] FIG. 9B is a plan view of the liquid crystal element of Comparative Example 2. FIG. [Figure 9C] FIG. 9C is a plan view of the liquid crystal element of Comparative Example 2. FIG. [Figure 9D] FIG. 9D is a plan view of the liquid crystal element of Comparative Example 2. FIG. [Figure 10A] FIG. 10A is a plan view showing the liquid crystal element of this embodiment. [Figure 10B] FIG. 10B is a plan view showing the liquid crystal element of this embodiment. [Figure 10C] FIG. 10C is a plan view showing the liquid crystal element of this embodiment. [Figure 10D] FIG. 10D is a plan view showing the liquid crystal element of this embodiment. [Figure 11] FIG. 11 is a partially enlarged view of FIG. [Figure 12] FIG. 12 is a plan view showing another example of the configuration of the liquid crystal element according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily conceive while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, etc. of each part schematically compared to the actual embodiment, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, elements similar to those described above with reference to the previous drawings may be designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] The embodiments described in this specification are not general but are embodiments that describe the same or corresponding special technical features of the present invention. Hereinafter, an electronic device according to an embodiment will be described in detail with reference to the drawings.

[0011] In this embodiment, the first direction X, the second direction Y, and the third direction Z are perpendicular to one another, but may intersect at an angle other than 90 degrees. The direction toward the tip of the arrow of the third direction Z is defined as up or upward, and the direction opposite to the direction toward the tip of the arrow of the third direction Z is defined as down or downward.

[0012] Furthermore, when the terms "second member above the first member" and "second member below the first member" are used, the second member may be in contact with the first member or may be located apart from the first member. In the latter case, a third member may be interposed between the first and second members. On the other hand, when the terms "second member above the first member" and "second member below the first member" are used, the second member is in contact with the first member.

[0013] Furthermore, the observation position for observing the electronic device is assumed to be at the tip of the arrow in the third direction Z, and viewing from this observation position toward the XY plane defined by the first direction X and the second direction Y is called planar view. Viewing a cross section of the electronic device in the XZ plane defined by the first direction X and the third direction Z, or in the YZ plane defined by the second direction Y and the third direction Z, is called cross-sectional view.

[0014] [Embodiment] Fig. 1 is an exploded perspective view showing an example of a schematic configuration of an electronic device applicable to the embodiment. The electronic device ERP shown in Fig. 1 includes an illumination device ILD, a display panel PNL, and an image sensor PA. The display panel PNL is a liquid crystal display panel and includes a liquid crystal element LCD, as will be described in detail later.

[0015] The illumination device ILD includes a light guide plate LG1, a light source EM1, and a housing CS. The illumination device ILD is configured to illuminate, for example, a display panel PNL, which is shown in simplified form by dashed lines in FIG.

[0016] The light guide plate LG1 is formed in the shape of a flat plate parallel to the XY plane defined by the first direction X and the second direction Y. The light guide plate LG1 faces the display panel PNL. The light guide plate LG1 has a side surface S1, a side surface S2 opposite to the side surface S1, and an opening OP1. The side surface S1 and the side surface S2 each extend along the first direction X. For example, the side surface S1 and the side surface S2 are surfaces parallel to the XZ plane defined by the first direction X and the third direction Z.

[0017] The opening OP1 is a through-hole that penetrates the light guide plate LG1 along the third direction Z. The opening OP1 is located between the side surface S1 and the side surface S2 in the second direction Y, and is closer to the side surface S2 than to the side surface S1.

[0018] The plurality of light sources EM1 are arranged at intervals along the first direction X. The light sources EM1 are mounted on the wiring board FPC1 and electrically connected to the wiring board FPC1.

[0019] The housing CS houses the light guide plate LG1 and the light source EM1. The housing CS has side walls W1 to W4, a bottom plate BP, an opening OP2, and a protrusion PP. The side walls W1 and W2 extend along the first direction X and face each other. The side walls W3 and W4 extend along the second direction Y and face each other. The openings OP2 are through holes that penetrate the bottom plate BP along the third direction Z.

[0020] The opening OP2 overlaps with the opening OP1 in the third direction Z. The protrusion PP protrudes from the bottom plate BP toward the display panel PNL along the third direction Z and is provided so as to surround the opening OP2.

[0021] 1 is provided so as to overlap the opening OP2 in the third direction Z. The imaging element PA is mounted on the wiring board FPC2 and electrically connected to the wiring board FPC2.

[0022] The display panel PNL overlaps the light guide plate LG1, and also overlaps the image sensor PA at the opening OP1.

[0023] Fig. 2 is a cross-sectional view showing an example of a schematic configuration of the electronic device shown in Fig. 1. Fig. 2 shows a cross-section of the electronic device ERP including a display panel PNL, an image sensor PA, and an illumination device ILD.

[0024] In the electronic device ERP, the opening OP2 of the housing CS of the lighting device ILD is located inside the opening OP1 of the light guide plate LG1, and the imaging element PA is located inside the openings OP1 and OP2.

[0025] The illumination device ILD further includes a light-shielding wall BW. The light-shielding wall BW is located inside the opening OP1. In the example shown in FIG. 2, the light-shielding wall BW is in contact with each of the reflective sheet RS, the light guide plate LG1, the diffusion sheet SS, the prism sheet PS1, and the prism sheet PS2, which will be described later, but it does not have to be in contact with them. The light-shielding wall BW is formed, for example, from a resin that is colored black. If not necessary, the light-shielding wall BW does not have to be provided.

[0026] The illumination device ILD further includes a reflective sheet RS, a diffusion sheet SS, a prism sheet PS1, and a prism sheet PS2. The reflective sheet RS, light guide plate LG1, diffusion sheet SS, prism sheet PS1, and prism sheet PS2 are arranged in this order along the third direction Z and housed in a housing CS. The housing CS includes a metal housing CS1 and a resin base CS2. The base CS2 forms a protrusion PP together with the housing CS1. The diffusion sheet SS, prism sheet PS1, and prism sheet PS2 each have an opening OP3 overlapping the opening OP1. The reflective sheet RS has an opening OP4 overlapping the opening OP1. The protrusion PP of the housing CS is located inside the openings OP1, OP3, and OP4.

[0027] The imaging element PA includes, for example, an optical system OPS including at least one lens, a sensor element IMS, and a housing HS. The sensor element IMS is an image sensor capable of detecting an image. The housing HS houses the optical system OPS and the sensor element IMS. The optical system OPS is located between the display panel PNL and the sensor element IMS. The sensor element IMS includes a plurality of sensor elements SX, which will be described later. The plurality of sensor elements SX are also called sensor pixels.

[0028] The polarizer PL1, the display panel PNL, the polarizer PL2, and the cover member CG are arranged in this order along the third direction Z, and form a liquid crystal element LCD that has an optical switching function for light traveling along the third direction Z.

[0029] A polarizing plate PL1 is provided in contact with the base material BA1 of the substrate SUB1. An adhesive or adhesive tape (not shown) is provided between the polarizing plate PL1 and the base material BA1 (substrate) to bond the polarizing plate PL to the base material BA1.

[0030] The adhesive tape TP2 is, for example, a transparent or white double-sided adhesive tape, and bonds the illumination device ILD and the liquid crystal element LCD together. The adhesive tape TP2 also bonds the polarizing plate PL1 to the protrusions PP, and the polarizing plate PL1 to the prism sheet PS2.

[0031] The polarizing plate PL2 is adhered to the base material BA2 with an adhesive or adhesive tape (not shown) The polarizing plate PL2 is adhered to the cover member CG with a transparent adhesive layer AD.

[0032] The cover member CG may be made of glass, for example.

[0033] The display panel PNL includes a display area DA that displays an image and a non-display area NDA that is adjacent to the display area DA and surrounds the display area DA. The display panel PNL includes a substrate SUB1, a substrate SUB2, a liquid crystal layer LC, and a seal SE. The seal SE is located in the non-display area NDA, bonds the substrates SUB1 and SUB2 together, and seals the liquid crystal layer LC. In other words, the display area DA is the area occupied by the substrates SUB1, SUB2, and the liquid crystal layer LC sandwiched between the substrates SUB1 and SUB2 that does not overlap with the seal SE.

[0034] The main parts of the substrates SUB1 and SUB2 will be described below. The substrate SUB1 includes a base material BA1 and an alignment film AL1. The substrate SUB2 includes a base material BA2, a color filter CF, a light-shielding layer BM, an insulating layer OC, and an alignment film AL2.

[0035] The base materials BA1 and BA2 are transparent substrates such as glass substrates, flexible resin substrates, etc. The alignment films AL1 and AL2 are in contact with the liquid crystal layer LC.

[0036] The color filter CF, the light-shielding layer BM, and the insulating layer OC are located between the base material BA2 and the liquid crystal layer LC. In the example shown in Fig. 2, the color filter CF is provided on the substrate SUB2, but it may be provided on the substrate SUB1.

[0037] The light-shielding layer BM is located in the non-display area NDA. The boundary LB between the display area DA and the non-display area NDA is defined, for example, by the inner edge (the edge on the display area DA side) of the light-shielding layer BM. The seal SE is provided at a position overlapping the light-shielding layer BM.

[0038] Although details of the color filter CF are omitted here, the color filter CF includes, for example, a red color filter disposed in the red pixel, a green color filter disposed in the green pixel, and a blue color filter disposed in the blue pixel. The color filter CF may also include a transparent resin layer disposed in the white pixel. An insulating layer OC covers the color filter CF and the light-shielding layer BM. The insulating layer OC is, for example, a transparent organic insulating layer.

[0039] In this embodiment, the imaging element PA is, for example, a camera. The imaging element PA may be, for example, a device that detects visible light, a device that detects infrared light, a proximity sensor that senses the proximity of a detection target, a detection element that detects infrared light reflected from a detection target, or a combination of these. The electronic device ERP may include a light-emitting element instead of or in addition to the imaging element PA. An example of the light-emitting element is a projection element that projects infrared light toward a detection target.

[0040] The imaging element PA is provided so as to overlap the opening OP2 of the housing CS, and is located inside the area surrounded by the protrusion PP. The imaging element PA overlaps the cover member CG, the display panel PNL, and the light guide plate LG2 in the third direction Z. A part or all of the imaging element PA overlaps the display area DA of the display panel PNL in the third direction Z. In other words, in an electronic device ERP having the display panel PNL and the imaging element PA, it is sufficient that the imaging element PA is provided on the back side of the display panel PNL as seen by a user of the electronic device ERP.

[0041] FIG. 3 is an exploded perspective view showing an outline of a partial configuration of an electronic device of this embodiment. The electronic device ERP includes a liquid crystal element LCE facing an image sensor PA. The liquid crystal element LCE displays an aperture pattern PT and is provided with a lens LNS. The lens LNS may be provided separately from the liquid crystal element LCE or may be included inside the liquid crystal element LCE. Although the lens LNS in FIG. 3 is shown separately from the image sensor PA, it is provided in the optical system OPS as described above. The image sensor PA has a sensor element SX facing the aperture pattern PT.

[0042] The electronic device ERP measures the distance between the image sensor PA and an object by using a coded aperture. In the coded aperture of this embodiment, a specific pattern that specifies whether or not light is transmitted is placed in front of the image sensor PA, allowing the distance of the object from the image sensor PA to be estimated. Here, using two or more types of coded aperture patterns can further improve accuracy. For example, a pair of coded aperture patterns is called a coded aperture pair (CAP).

[0043] FIG. 4 is a diagram illustrating a method for measuring distance using a coded aperture. An image IMG1 on the XY plane of the aperture pattern PT of the liquid crystal element LCE is formed on the imaging surface (uv plane) of the image sensor PA via the lens LNS. The formed image IMG2 is detected by the sensor element SX present on the imaging surface. Information on the light (image) detected by the image sensor PA includes information on the distance from the image sensor PA to the subject.

[0044] In this case, the image IMG3 at a position shifted from the focal point FC of the lens LNS will be blurred. By calculating the spread of this blur as a point spread function (PSF), distance (depth) can be obtained.

[0045] The coded aperture pattern can also be formed by a light-shielding layer made of, for example, a metal material, instead of a liquid crystal element. However, a light-shielding layer made of a metal material limits the types of coded aperture patterns. The electronic device ERP of this embodiment has the advantage that it is possible to use two or more types of coded aperture patterns by including a liquid crystal element LCE.

[0046] Fig. 5 is a plan view showing an example of a schematic configuration of a portion of a liquid crystal element. Fig. 6 is a cross-sectional view of the liquid crystal element taken along line A1-A2 shown in Fig. 5. The liquid crystal element LCE has a lower electrode LE1, a lower electrode LE2, a lower electrode LE3, a lower electrode LE4, and a lower electrode LE5, an upper electrode UE1, an upper electrode UE2, an upper electrode UE3, an upper electrode UE4, and an upper electrode UE5, and a contact hole CH.

[0047] The upper electrode UE1 has a square shape and is disposed near the center of the liquid crystal element LCE. The upper electrodes UE2, UE3, UE4, and UE5 are disposed surrounding the upper electrode UE1. The upper electrodes UE2, UE3, UE4, and UE5 form a hollow square electrode Q1. A gap GP is provided between the upper electrodes UE1, UE2, UE3, UE4, and UE5 to prevent them from contacting each other.

[0048] The upper electrode UE1 is a central electrode located at the center of these electrodes, and the upper electrodes UE2, UE3, UE4, and UE5, which are arranged around the upper electrode UE1, can also be considered to be peripheral electrodes surrounding the central electrode. The upper electrodes UE2, UE3, UE4, and UE5 can also be considered to be divided electrodes, which are peripheral electrodes divided by a gap GP.

[0049] The positional relationship between the upper electrodes UE2, UE3, UE4, and UE5 will be described. The upper electrode UE2 has an L-shape and is adjacent to the upper electrode UE5 in the first direction X. The upper electrode UE2 is adjacent to the upper electrode UE4 in the opposite direction to the second direction Y.

[0050] The upper electrode UE3 has an L-shape rotated 180°. The upper electrode UE3 is adjacent to the upper electrode UE4 in the direction opposite to the first direction X. The upper electrode UE3 is adjacent to the upper electrode UE5 in the second direction Y.

[0051] The upper electrode UE4 has a rectangular shape and is adjacent to the upper electrode UE3 in the first direction X. The upper electrode UE4 is adjacent to the upper electrode UE2 in the second direction Y.

[0052] The upper electrode UE5 has a rectangular shape and is adjacent to the upper electrode UE2 in the direction opposite to the first direction X. The upper electrode UE5 is adjacent to the upper electrode UE3 in the direction opposite to the second direction Y.

[0053] 5, the lower electrode LE1 has a rectangular electrode portion LE1a and a wiring portion LE1b, which are integrally formed. The electrode portion LE1a overlaps the upper electrode UE1 in plan view.

[0054] The lower electrode LE4 has two electrode portions LE4a and LE4b provided in the same layer. The wiring portion LE1b is provided between the electrode portion LE4a and the electrode portion LE4b in a plan view. The wiring portion LE1b is drawn out to the outside of the liquid crystal element LCE without contacting the electrode portion LE4a and the electrode portion LE4b provided in the same layer.

[0055] The lower electrode LE2 overlaps the ends of the upper electrode UE2 and the upper electrode UE1, and is provided so as to fill the gap GP between the upper electrode UE2 and the upper electrode UE1. In the region where the lower electrode LE2 and the upper electrode UE2 overlap, a contact hole CH is provided in an insulating layer INS, which will be described later.

[0056] The lower electrode LE3 overlaps the ends of the upper electrode UE3 and the upper electrode UE1, and is provided so as to fill the gap GP between the upper electrode UE3 and the upper electrode UE1. In the region where the lower electrode LE3 and the upper electrode UE3 overlap, a contact hole CH is provided in the insulating layer INS.

[0057] As described above, the lower electrode LE4 has the electrode portion LE4a and the electrode portion LE4b. The electrode portion LE4a overlaps the ends of the upper electrode UE4 and the upper electrode UE2, respectively, and is provided so as to fill the gap GP between the upper electrode UE4 and the upper electrode UE2. In the region where the electrode portion LE4a and the upper electrode UE4 overlap, a contact hole CH is provided in the insulating layer INS.

[0058] The electrode portion LE4b overlaps the ends of the upper electrode UE4 and the upper electrode UE3, respectively, and is provided so as to fill the gap GP between the upper electrode UE4 and the upper electrode UE3. In the region where the electrode portion LE4b and the upper electrode UE4 overlap, a contact hole CH is provided in the insulating layer INS.

[0059] The lower electrode LE5 overlaps the ends of the upper electrode UE5 and the upper electrode UE2, as well as the ends of the upper electrode UE5 and the upper electrode UE3. The lower electrode LE5 is provided so as to fill the gap GP between the upper electrode UE5 and the upper electrode UE2, and the gap GP between the upper electrode UE5 and the upper electrode UE3. Contact holes CH are provided in the insulating layer INS in the regions where the upper electrodes UE5 and the upper electrode UE2 overlap, and in the regions where the upper electrodes UE5 and the upper electrode UE3 overlap.

[0060] In this embodiment, the lower electrodes LE1, LE2, LE3, LE4, and LE5 are provided on an insulating layer HRC. The insulating layer HRC may be, for example, an organic resin layer, more specifically, an acrylic resin layer or a polyimide resin layer. The lower electrodes LE1, LE2, LE3, LE4, and LE5, as well as the upper electrodes UE1, UE2, UE3, UE4, and UE5, may be formed of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0061] 6, the lower electrode LE5 is covered with an insulating layer INS. The insulating layer INS may be made of an inorganic insulating material such as silicon nitride or silicon oxide. A contact hole CH overlapping the lower electrode LE5 is provided in the insulating layer INS.

[0062] An upper electrode UE2 and an upper electrode UE5 are provided on the insulating layer INS. The upper electrode UE5 is connected to the lower electrode LE5 through a contact hole CH. The upper electrode UE2 is not connected to the lower electrode LE5.

[0063] 6 shows the lower electrode LE5 and the upper electrode UE5, but the same applies to the other lower electrodes LE1, LE2, LE3, and LE4, as well as the upper electrodes UE1, UE2, UE3, and UE4. That is, the upper electrode UE1 is connected to the lower electrode LE1 via a contact hole CH. The upper electrode UE2 is connected to the lower electrode LE2 via a contact hole CH. The upper electrode UE3 is connected to the lower electrode LE4 via a contact hole CH. The upper electrode UE4 is connected to the lower electrode LE4 via a contact hole CH.

[0064] 7 is a cross-sectional view showing an example of a schematic configuration of a liquid crystal element LCE. The liquid crystal element LCE includes a base material BA3, a signal line SL, an insulating layer HRC, a lower electrode LE, an electrode LEX, an insulating layer INS, an upper electrode UE, a spacer PS, a liquid crystal layer LCY, a counter electrode CE, an insulating layer OC2, a light-shielding layer BM, and a base material BA4.

[0065] The substrate BA3, signal line SL, insulating layer HRC, lower electrode LE, electrode LEX, insulating layer INS, and upper electrode UE constitute the substrate SUB3. The counter electrode CE, insulating layer OC2, light-shielding layer BM, and substrate BA4 constitute the substrate SUB4.

[0066] In FIG. 7, the area surrounded by the dotted line corresponds to FIG.

[0067] The liquid crystal element LCE has a sensor area SA and an edge portion Ex. The sensor area SA mainly includes a lower electrode LE, an upper electrode UE, a liquid crystal layer LCY, and a counter electrode CE. The liquid crystal layer LCY is provided between the upper electrode UE, the lower electrode LE, and the counter electrode CE.

[0068] An electrode LEX is provided at the end Ex, which is connected to the signal line SL. The electrode LEX is electrically connected to an external driving element. However, the configuration of the end Ex is not limited to this, and wiring and electrodes for inputting a driving signal from an external driving element may also be provided.

[0069] The base material BA3 and the base material BA4 may be made of a transparent insulating material such as glass.

[0070] The signal line SL is provided on the base material BA3. The signal line SL may be made of a metal material, for example, a laminate in which aluminum is sandwiched between titanium layers.

[0071] An insulating layer HRC is provided to cover the base material BA3 and the signal lines SL, and functions as a planarizing layer.

[0072] The lower electrode LE and the electrode LEX are provided on the insulating layer HRC. The lower electrode LE and the electrode LEX are electrodes in the same layer. In other words, the lower electrode LE and the electrode LEX are formed of the same material and have the same configuration.

[0073] 7 shows the lower electrodes LE2 and LE5 of the lower electrodes LE. The lower electrode LE2 is connected to a signal line SL via a contact hole provided in the insulating layer HRC. Although not shown, the lower electrode LE5 is also connected to another signal line SL. A signal is input to the lower electrodes LE (lower electrodes LE2 and LE5) via the signal line SL, and the on / off state of the lower electrodes LE is controlled.

[0074] An insulating layer INS is provided over the lower electrode LE and the electrode LEX.

[0075] Upper electrodes UE are provided on the insulating layer INS. Of the upper electrodes UE, upper electrodes UE2 and UE5 are shown in FIG. 7. The upper electrode UE2 is connected to the lower electrode LE2 via a contact hole CH provided in the insulating layer INS. The upper electrode UE5 is connected to the lower electrode LE5 via a contact hole CH provided in the insulating layer INS.

[0076] A seal SAL, a spacer PS, a conductive member CM, and a liquid crystal layer LCY are provided on the insulating layer INS and the upper electrode UE.

[0077] The seal SAL is provided so as to surround the liquid crystal layer LCY. The area surrounded by the seal SAL and in which the liquid crystal layer LCY is provided becomes the sensor area SA. The seal SAL bonds the substrates SUB3 and SUB4 together and seals the liquid crystal layer LCY.

[0078] The spacers PS are disposed within the region where the liquid crystal layer LCY is provided. The spacers PS have the function of maintaining the thickness of the liquid crystal layer LCY. The spacers PS may be formed using an organic resin material.

[0079] A light-shielding layer BM is provided in contact with the base material BA4. The light-shielding layer BM is disposed in a position facing the spacers PS. Examples of materials for the light-shielding layer BM include metal materials and resin materials containing black pigments.

[0080] An insulating layer OC2 is provided to cover the base material BA4 and the light-shielding layer BM. The insulating layer OC2 is, for example, a transparent organic insulating layer.

[0081] A counter electrode CE is provided in contact with the insulating layer OC2. The counter electrode CE may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The counter electrode CE faces the upper electrode UE and the lower electrode LE.

[0082] When the liquid crystal element LCE is driven in the vertical electric field mode, the liquid crystal layer LCY is driven by a voltage applied between the upper electrode UE, the lower electrode LE, and the counter electrode CE. By applying this voltage, a region that displays white and a region that displays black are switched, and an opening pattern PT of the liquid crystal element LCE is formed.

[0083] Here, as a comparative example, an example in which the lower electrode LE is not provided will be considered. As comparative example 1, a case in which the lower electrode LE is not provided, that is, a case in which only the upper electrode UE is provided will be described.

[0084] 8A to 8D are plan views of the liquid crystal element of Comparative Example 1. In FIG. 8A, the upper electrodes UE3, UE4, and UE5 are in the ON state, and the upper electrodes UE1 and UE2 are in the OFF state. The area where the upper electrodes UE3, UE4, and UE5 are provided transmits light and displays what is called white. The area where the upper electrodes UE1 and UE2 are provided does not transmit light and displays what is called black.

[0085] In the gap GP between the upper electrodes UE1 and UE2, no electrodes for driving the liquid crystal layer LCY are arranged. Therefore, the liquid crystal layer LCY transmits light, resulting in a so-called white display. Therefore, the area corresponding to the gap GP between the upper electrodes UE1 and UE2 is detected as a white streak.

[0086] In Fig. 8B, the upper electrodes UE2, UE4, and UE5 are in the ON state, and the upper electrodes UE1 and UE3 are in the OFF state. In Fig. 8B as well, the area corresponding to the gap GP between the upper electrodes UE1 and UE3 is detected as a white streak.

[0087] In FIG. 8C, the upper electrodes UE1, UE2, UE3, UE4, and UE5 are all in the ON state. The areas where the upper electrodes UE1, UE2, UE3, UE4, and UE5 are provided, as well as the area corresponding to the gap GP, display white. This is the so-called all-white display state. No streaks are detected in FIG. 8C.

[0088] 8C, in Fig. 8D, the upper electrodes UE1, UE2, UE3, UE4, and UE5 are all in the OFF state. The areas where the upper electrodes UE1, UE2, UE3, UE4, and UE5 are provided do not transmit light and display black. This is the so-called all-black display state.

[0089] However, as described above, the liquid crystal layer LCY transmits light in the area corresponding to the gap GP, so the area corresponding to the gap GP displays all white, resulting in a noticeable white stripe.

[0090] In order to prevent the white streaks shown in Figures 8B to 8D, for example, it is possible to provide a light-shielding layer in the region corresponding to the gap GP. Figures 9A to 9D are plan views of a liquid crystal element of Comparative Example 2. In Comparative Example 2, a light-shielding layer is provided in the region corresponding to the gap GP.

[0091] 9A, the upper electrodes UE3, UE4, and UE5 are in the ON state, and the upper electrodes UE1 and UE2 are in the OFF state. The area where the upper electrodes UE3, UE4, and UE5 are provided transmits light and displays white. The area where the upper electrodes UE1 and UE2 are provided does not transmit light and displays black.

[0092] A light-shielding layer is provided in the gap GP between the upper electrode UE3 and the upper electrode UE4, and in the gap GP between the upper electrode UE3 and the upper electrode UE5, so light does not pass through, and therefore the gap GP is detected as a black streak.

[0093] In Fig. 9B, the upper electrodes UE2, UE4, and UE5 are in the ON state, and the upper electrodes UE1 and UE3 are in the OFF state. Also in Fig. 8B, the gap GP between the upper electrodes UE2 and UE4 and the area corresponding to the gap GP between the upper electrodes UE2 and UE5 are detected as black streaks.

[0094] 9C, the upper electrodes UE1, UE2, UE3, UE4, and UE5 are all in the on state. The area where the upper electrodes UE1, UE2, UE3, UE4, and UE5 are provided displays white, which is a so-called all-white display state.

[0095] The areas corresponding to the gaps GP are completely opaque to light, resulting in prominent black streaks.

[0096] In FIG. 9D, contrary to FIG. 8C, all of the upper electrodes UE1, UE2, UE3, UE4, and UE5 are in the OFF state. The areas where the upper electrodes UE1, UE2, UE3, UE4, and UE5 are provided, as well as the area corresponding to the gap GP, do not transmit light and display black. This is the so-called all-black display state. No streaks are detected in FIG. 9D.

[0097] If unwanted white or black streaks are detected by the sensor element SX, this can lead to a decrease in the accuracy of the electronic device ERP. Therefore, it is preferable to prevent the occurrence of such streaks. Even if there are areas where light escapes or areas where light does not pass through, if they are very small, they will not affect the detection by the sensor element SX. This makes it possible to prevent a decrease in accuracy.

[0098] 10A to 10D are plan views showing a liquid crystal element of this embodiment. In the liquid crystal element LCE of this embodiment, a lower electrode LE is provided, as explained in Fig. 5. The lower electrode LE is connected to the upper electrode UE, as explained in Fig. 6, and the same voltage is applied to them.

[0099] In Fig. 10A, the upper electrodes UE3, UE4, and UE5 are in the ON state, and the upper electrodes UE1 and UE2 are in the OFF state. The liquid crystal element LCE shown in Fig. 10A differs from the liquid crystal element LCE shown in Fig. 8A in that a lower electrode is provided so as to fill the gap GP between the upper electrodes UE1 and UE2 (see Fig. 5). The lower electrode LE2 is at the same potential as the upper electrode UE2, so the lower electrode LE2 is in the OFF state. As a result, the area corresponding to the gap GP also displays black, and no white stripe is detected.

[0100] In Fig. 10B, the upper electrodes UE2, UE4, and UE5 are in the ON state, and the upper electrodes UE1 and UE3 are in the OFF state. As shown in Fig. 5, the lower electrode LE3 is provided to fill the gap GP between the upper electrodes UE1 and UE3. Therefore, the lower electrode LE3 has the same potential as the upper electrode UE3, and is therefore in the OFF state. As a result, the area corresponding to the gap GP also displays black, and no white stripe is detected.

[0101] 10C, the upper electrodes UE1, UE2, UE3, UE4, and UE5 are all in the ON state. The lower electrodes LE1, LE2, LE3, LE4, and LE5 connected to them are also in the ON state, so that no black stripes are detected.

[0102] 10D, the upper electrodes UE1, UE2, UE3, UE4, and UE5 are all in the OFF state. The lower electrodes LE1, LE2, LE3, LE4, and LE5 are also all in the OFF state, so no white stripes are detected.

[0103] However, as shown in Fig. 5, there are locations where electrodes cannot be provided in order to separate the lower electrodes LE. Fig. 11 is a partial enlarged view of Fig. 5. As shown in Fig. 11, in region SP1 where the ends of lower electrode LE2, lower electrode LE3, lower electrode LE4a, and lower electrode LE4b are adjacent, and in region SP2 where the ends of lower electrode LE2, lower electrode LE3, and lower electrode LE5 are adjacent, neither lower nor upper electrodes are provided. When there is no need to particularly distinguish between region SP1 and region SP2, they are simply referred to as region SP.

[0104] In the region SP, no voltage can be applied to the liquid crystal layer LCY. Therefore, when the liquid crystal layer LCY displays black, the region SP may be detected as a white dot (see FIG. 10D). However, this is less likely to be detected than the streaks described in Comparative Examples 1 and 2.

[0105] Although not described above, the area SP also exists in Figures 10A and 10B. However, no streaks are formed, and the area SP is small compared to the area displayed in black, so it does not affect the accuracy of the electronic device ERP.

[0106] In this embodiment, both the upper electrode UE and the lower electrode LE are made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and therefore, no light-shielding layer is required, as shown in Figures 9A to 9D.

[0107] As described above, according to this embodiment, it is possible to provide an electronic device that can suppress the occurrence of streaks and the deterioration of accuracy.

[0108] <Configuration example 1> Fig. 12 is a plan view showing another example of the configuration of a liquid crystal element according to an embodiment. The example of the configuration shown in Fig. 12 differs from the example of the configuration shown in Fig. 5 in that the electrodes have a circular shape.

[0109] The liquid crystal element LCE includes an upper electrode VE1a, an upper electrode VE1b, an upper electrode VE2a, an upper electrode VE2b, an upper electrode VE3a, an upper electrode VE3b, an upper electrode VE4a, an upper electrode VE4b, an upper electrode VE5a, an upper electrode VE5b, an upper electrode VE6a, an upper electrode VE6b, an upper electrode VE7a, an upper electrode VE7b, an upper electrode VE8a, an upper electrode VE8b, an upper electrode VE9a, an upper electrode VE9b, an upper electrode VE10a, an upper electrode VE10b, an upper electrode VE1 1a, upper electrode VE11b, upper electrode VE12a, upper electrode VE12b, upper electrode VE13a, upper electrode VE13b, upper electrode VE14a, upper electrode VE14b, upper electrode VE15a, upper electrode VE15b, upper electrode VE16a, upper electrode VE16b, upper electrode VE17a, upper electrode VE17b, upper electrode VE18a, upper electrode VE18b, upper electrode VE19a, upper electrode VE19b, upper electrode VE20a, and upper electrode VE20b.

[0110] The upper electrodes VE1a, VE1b, VE2a, VE2b, VE3a, VE3b, VE4a, and VE4b are arranged adjacent to each other to form a circular electrode C1. A gap GP is provided between each of the upper electrodes VE1a, VE1b, VE2a, VE2b, VE3a, VE3b, VE4a, and VE4b.

[0111] Although not shown to make the drawings easier to understand, wiring is provided between the upper electrodes VE1a and VE1b, between the upper electrodes VE2a and VE2b, between the upper electrodes VE3a and VE3b, and between the upper electrodes VE4a and VE4b.

[0112] The upper electrodes VE5a, VE5b, VE6a, VE6b, VE7a, VE7b, VE8a, and VE8b are adjacently arranged to form a ring-shaped electrode C2. Electrode C2 is arranged in a position surrounding electrode C1. A gap GP is provided between each of the upper electrodes VE5a, VE5b, VE6a, VE6b, VE7a, VE7b, VE8a, and VE8b. A gap GP is also provided between electrode C1 and electrode C2.

[0113] Although not shown to make the drawings easier to understand, wiring is provided between the upper electrodes VE5a and VE5b, between the upper electrodes VE6a and VE6b, between the upper electrodes VE7a and VE7b, and between the upper electrodes VE8a and VE8b.

[0114] The upper electrodes VE9a, VE9b, VE10a, VE10b, VE11a, VE11b, VE12a, and VE12b are adjacently arranged to form a ring-shaped electrode C3. Electrode C3 is arranged to surround electrode C2. A gap GP is provided between each of the upper electrodes VE9a, VE9b, VE10a, VE10b, VE11a, VE11b, VE12a, and VE12b. A gap GP is also provided between electrode C2 and electrode C3.

[0115] Although not shown to make the drawings easier to understand, wiring is provided between the upper electrodes VE9a and VE9b, between the upper electrodes VE10a and VE10b, between the upper electrodes VE11a and VE11b, and between the upper electrodes VE12a and VE12b.

[0116] The upper electrodes VE13a, VE13b, VE14a, VE14b, VE15a, VE15b, VE16a, and VE16b are adjacently arranged to form a ring-shaped electrode C4. Electrode C4 is arranged in a position surrounding electrode C3. A gap GP is provided between each of the upper electrodes VE13a, VE13b, VE14a, VE14b, VE15a, VE15b, VE16a, and VE16b. A gap GP is also provided between electrodes C3 and C4.

[0117] Although not shown to make the drawings easier to understand, wiring is provided between the upper electrodes VE13a and VE13b, between the upper electrodes VE14a and VE14b, between the upper electrodes VE14a and VE14b, and between the upper electrodes VE15a and VE15b.

[0118] The upper electrodes VE17a, VE17b, VE18a, VE18b, VE19a, VE19b, VE20a, and VE20b are adjacently arranged to form a ring-shaped electrode C5. Electrode C5 is arranged in a position surrounding electrode C4. A gap GP is provided between each of the upper electrodes VE17a, VE17b, VE18a, VE18b, VE19a, VE19b, VE20a, and VE20b. A gap GP is also provided between electrode C4 and electrode C5.

[0119] The circular electrode C1 is a central electrode located at the center of the above-mentioned electrodes. The annular electrode C2, which is arranged to surround electrode C1, can also be considered a first peripheral electrode surrounding the central electrode. The upper electrodes VE5a, VE5b, VE6a, VE6b, VE7a, VE7b, VE8a, and VE8b can also be considered divided electrodes obtained by dividing the first peripheral electrode by a gap GP. Like electrode C2, electrodes C3, C4, and C5 can also be referred to as second, third, and fourth peripheral electrodes, respectively.

[0120] Although not shown to avoid complicating the drawing, the liquid crystal element LCE shown in Fig. 12 is provided with a lower electrode. As in Fig. 11, the liquid crystal element LCE also includes a region SP where neither a lower electrode nor an upper electrode is provided.

[0121] In Figure 12, region SP is provided at the end of upper electrode VE5b that is adjacent to electrode C1, the end of upper electrode VE6b that is adjacent to electrode C1, the end of upper electrode VE7b that is adjacent to electrode C1, and the end of upper electrode VE8b that is adjacent to electrode C1.

[0122] The region SP is provided at an end of the upper electrode VE8a that is adjacent to the electrode C3, and at an end of the upper electrode VE8b that is adjacent to the electrode C3.

[0123] The region SP is provided between the upper electrodes VE5b and VE9b, between the upper electrodes VE6b and VE10b, between the upper electrodes VE7b and VE11b, and between the upper electrodes VE8b and VE12b.

[0124] Region SP is provided at the end of upper electrode VE9a adjacent to electrode C4, the end of upper electrode VE9b adjacent to electrode C4, the end of upper electrode VE10a adjacent to electrode C4, the end of upper electrode VE10b adjacent to electrode C4, the end of upper electrode VE11a adjacent to electrode C4, the end of upper electrode VE11b adjacent to electrode C4, the end of upper electrode VE12a adjacent to electrode C4, and the end of upper electrode VE12b adjacent to electrode C4.

[0125] The region SP is provided between the upper electrode VE9b and the upper electrode VE13b, between the upper electrode VE10b and the upper electrode VE14b, between the upper electrode VE11b and the upper electrode VE15b, and between the upper electrode VE12b and the upper electrode VE16b.

[0126] Region SP is provided at the ends adjacent to the following electrodes C5, between upper electrodes VE13a and VE13b, at the end of upper electrode VE13b, at the end of upper electrode VE14a, at the end of upper electrode VE14b, between upper electrodes VE15a and VE15b, at the end of upper electrode VE15b, at the end of upper electrode VE16a, between upper electrodes VE16a and VE16b, and at the end of upper electrode VE16b.

[0127] The region SP is provided between the upper electrode VE14b and the upper electrode VE18b.

[0128] The regions SP provided between the upper electrode VE5b and the upper electrode VE9b, between the upper electrode VE6b and the upper electrode VE10b, between the upper electrode VE7b and the upper electrode VE11b, between the upper electrode VE8b and the upper electrode VE12b, between the upper electrode VE9b and the upper electrode VE13b, between the upper electrode VE10b and the upper electrode VE14b, between the upper electrode VE11b and the upper electrode VE15b, and between the upper electrode VE12b and the upper electrode VE16b have a pentagonal shape.

[0129] The remaining area SP has a square shape.

[0130] The regions SP between the upper electrodes VE13a and VE13b, the edge of the upper electrode VE13b, between the upper electrodes VE15a and VE15b, the edge of the upper electrode VE15b, the edge of the upper electrode VE16a, between the upper electrodes VE16a and VE16b, and the edge of the upper electrode VE16b are particularly referred to as regions SPb. Region SPb overlaps with wiring, so is shielded from light even in white display.

[0131] The region SPb has a lower electrode LE connected to electrodes C1, C2, and C3 arranged near the center, and is light-shielded in response to the lower electrode LE of the region SPb under conditions where the regions of electrodes C1, C2, and C3 are to be displayed in black.

[0132] For example, when area SPb occurs in the first quadrant (upper right area), second quadrant (upper left area), and fourth quadrant (lower right area) of the areas of electrodes C4 and C5, a light-blocking pattern is displayed over the entire third quadrant (lower left area) and electrodes C1, C2, and C3.

[0133] On the other hand, the region SP through which light passes is the region of the gap GP between the upper electrodes VE, and is also a region where there is no lower electrode LE for individually moving the electrodes near the center.

[0134] As described above, the areas SP other than the area SPb are not provided with either an upper or lower electrode, so light passes through even when the area SP is displayed in black. Therefore, although the area SP may be detected as a white dot, Since it is small compared to the area displayed in black, it does not affect the accuracy of electronic devices.

[0135] This configuration example also provides the same effects as the embodiment.

[0136] In this disclosure, the upper electrodes UE1, UE2, UE3, UE4, and UE5 are referred to as the first upper electrode, the second upper electrode, the third upper electrode, the fourth upper electrode, and the fifth upper electrode, respectively. The lower electrodes LE1, LE2, LE3, LE4, and LE5 are referred to as the first lower electrode, the second lower electrode, the third lower electrode, the fourth lower electrode, and the fifth lower electrode, respectively.

[0137] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0138] C1...electrode, C2...electrode, C3...electrode, C4...electrode, C5...electrode, CE...counter electrode, ERP...electronic device, GP...gap, INS...insulating layer, LCE...liquid crystal element, LCY...liquid crystal layer, LE...lower electrode, SP...region, SP1...region, SP2...region, SPb...region, SX...sensor element, UE...upper electrode, VE1a...upper electrode, VE2a...upper electrode.

Claims

1. a first upper electrode; A second upper electrode; a third upper electrode; a fourth upper electrode; A fifth upper electrode; a first lower electrode connected to the first upper electrode; a second lower electrode connected to the second upper electrode; a third lower electrode connected to the third upper electrode; a fourth lower electrode connected to the fourth upper electrode; a fifth lower electrode connected to the fifth upper electrode; an insulating layer provided between the first upper electrode, the second upper electrode, the third upper electrode, the fourth upper electrode, and the fifth upper electrode, and between the first lower electrode, the second lower electrode, the third lower electrode, the fourth lower electrode, and the fifth lower electrode; a counter electrode facing the first upper electrode, the second upper electrode, the third upper electrode, the fourth upper electrode, the fifth upper electrode, the first lower electrode, the second lower electrode, the third lower electrode, the fourth lower electrode, and the fifth lower electrode; Equipped with the second lower electrode overlaps the first upper electrode and the second upper electrode; the third lower electrode overlaps the first upper electrode and the third upper electrode; the fourth lower electrode overlaps the second upper electrode, the third upper electrode, and the fourth upper electrode; the fifth lower electrode overlaps the second upper electrode, the third upper electrode, and the fifth upper electrode; the first upper electrode has a square shape in a plan view, the second upper electrode, the third upper electrode, the fourth upper electrode, and the fifth upper electrode form hollow square electrodes surrounding the first upper electrode.

2. 2. The electronic device according to claim 1, wherein the first upper electrode, the second upper electrode, the third upper electrode, the fourth upper electrode, the fifth upper electrode, the first lower electrode, the second lower electrode, the third lower electrode, the fourth lower electrode, and the fifth lower electrode are each formed of a transparent conductive material.

3. The electronic device according to claim 1 , wherein a gap is provided between the first upper electrode, the second upper electrode, the third upper electrode, the fourth upper electrode, and the fifth upper electrode.

4. A counter electrode; A liquid crystal layer; Furthermore, the first upper electrode, the second upper electrode, the third upper electrode, the fourth upper electrode, and the fifth upper electrode are defined as upper electrodes, the first lower electrode, the second lower electrode, the third lower electrode, the fourth lower electrode, and the fifth lower electrode are defined as lower electrodes, The electronic device according to claim 1 , wherein the liquid crystal layer is disposed between the upper electrode, the lower electrode, and the counter electrode.

5. The electronic device according to claim 1 , further comprising an imaging element including a sensor element.

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