Terahertz beam steering antenna array

Abstract

A terahertz imaging system is disclosed. The terahertz imaging system includes a terahertz antenna array of a plurality of antenna elements. Each antenna element includes a patch antenna, a one-bit phase shifter, and a plurality of storage elements. The storage elements are used to store a plurality of phase states that are provided to the one-bit phase shifter. The one-bit phase shifter is configured to shift the phase of an incoming signal by either 90° or 270° depending on the value of the phase state. The one-bit phase shifter is also bidirectional, allowing for phase shifting of the transmitted and reflected signals. A plurality of these antenna elements are provided on a semiconductor device having an exposed top metal layer. The top metal layer is used to form the patch antennas.

Description

[Technical Field]

[0001] In this disclosure, a terahertz beam steering antenna array is described.

[0002] REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 310,624, filed February 16, 2022, the disclosure of which is incorporated herein by reference in its entirety. [Background technology]

[0003] The terahertz spectrum of electromagnetic waves, spanning frequencies from approximately 0.1 to 10 terahertz, has attracted increasing attention in scientific and engineering research communities for a number of reasons, including available bandwidth, relatively short wavelengths, and intriguing properties of wave-matter interactions, among others. Efficient generation and detection of terahertz waves has proven elusive. At the same time, THz systems have the potential to enable a wide range of applications, including communications, pathogen sanitation, and space applications, in addition to numerous imaging applications.

[0004] Terahertz imaging is an emerging technology that has seen increased research interest over the past decade. Terahertz imaging systems are finding practical applications in security, military, spectroscopy, nondestructive testing, medical imaging, and other applications. In such systems, terahertz waves are directed at a sample target, and the received signal reflected or transmitted through the target is acquired to form a pixel array. The most common approach generates a matrix of such pixels to produce an image. These systems rely almost exclusively on motorized beam steering, steering the radiation beam with approaches such as motorized reflecting mirrors, gimbaled sample stages, or actuated lenses. While effective, these approaches are typically large, heavy, expensive, power-hungry, slow in image acquisition, and have reliability issues associated with physical movement.

[0005] Therefore, terahertz antenna arrays with hundreds or even thousands of antenna elements employing phased array beam steering techniques would be beneficial for these applications. Summary of the Invention [Means for solving the problem]

[0006] A terahertz imaging system is disclosed. The terahertz imaging system includes a terahertz antenna array consisting of multiple antenna elements. Each antenna element includes a patch antenna, a one-bit phase shifter, and multiple storage elements. The storage elements are used to store multiple phase states that are supplied to the one-bit phase shifter. The one-bit phase shifter is configured to shift the phase of an incoming signal by either 90° or 270° depending on the value of the phase state. The one-bit phase shifter is also bidirectional, allowing for phase shifting of transmitted and reflected signals. A plurality of these antenna elements are mounted on a semiconductor device with an exposed top metal layer. This top metal layer is used to form patch antennas. The semiconductor device interface is designed to allow a plurality of these semiconductor devices to be mounted as an array on a wiring board.

[0007] According to one embodiment, a semiconductor device is disclosed, comprising: a semiconductor substrate; and a plurality of metal layers including an exposed upper metal layer, the upper metal layer being formed as a plurality of patch antennas, wherein a plurality of storage elements and a one-bit phase shifter are provided in the semiconductor substrate below each of the patch antennas, and the plurality of storage elements store a plurality of phase states provided to the one-bit phase shifter.

[0008] In some embodiments, the plurality of storage elements disposed beneath each individual patch antenna includes at least 1000 phase states. In some embodiments, the plurality of patch antennas are arranged as a grid having a first number of rows and a second number of columns. In some embodiments, each storage element of the plurality of storage elements comprises a shift register. In one embodiment, the semiconductor device has two modes: a load mode in which all of the shift registers in the semiconductor device are connected in series and data is loaded sequentially into all of the shift registers, and a circulate mode in which the output of each shift register is provided to the input of that shift register.

[0009] In some embodiments, the plurality of storage elements comprise random access memory (RAM). In some embodiments, each patch antenna is rectangular with two pairs of parallel sides and has three contacts: a first contact (P1); a second contact (P2) provided at the midpoint of the first side; and a third contact (P3) provided at the midpoint of the second side opposite the first side, where the first contact (P1) is provided at the midpoint of the side perpendicular to the first and second sides.

[0010] In some embodiments, the one-bit phase shifter comprises two field-effect transistors: a first transistor including a gate, a source, and a drain, wherein one of the source or the drain is electrically connected to the first contact (P1), the other of the source or the drain is electrically connected to the second contact (P2), and the gate is electrically connected to a control signal provided by the storage element; and a second transistor including a gate, a source, and a drain, wherein one of the source or the drain is electrically connected to the first contact (P1), the other of the source or the drain is electrically connected to the third contact (P3), and the gate is electrically connected to a signal complementary to the control signal.

[0011] According to another embodiment, a reflectarray is disclosed that includes a plurality of the semiconductor devices described above arranged in a tiled array. In some embodiments, the spacing between two adjacent patch antennas on the same semiconductor device is within 20% of the spacing between two adjacent patch antennas on different semiconductor devices. In some embodiments, the semiconductor devices are soldered onto a printed wiring board, and bonding wires are used to connect signals between adjacent semiconductor devices. In some embodiments, some signals are duplicated so that open circuits in isolated bonding wires do not affect operation.

[0012] According to another embodiment, a terahertz imaging system is disclosed, comprising the reflectarray described above, a transceiver including a transmitter, a directional coupler, a mixer, and a receiver, and a waveguide, wherein terahertz waves generated by the transmitter propagate through the directional coupler and the waveguide to an opening at the end of the waveguide, where the terahertz waves are directed toward the reflectarray, and waves reflected from an object are focused by the reflectarray toward the end of the waveguide, propagate through the waveguide, the directional coupler, and the mixer, and reach the receiver.

[0013] According to another embodiment, a method for performing a sweep across a frequency band using the terahertz imaging system described above is disclosed, the method including: computing a phase state for each patch antenna in a reflectarray at a plurality of frequencies within the frequency band; storing the computed phase states in a storage element associated with each individual patch antenna; transmitting at the plurality of frequencies within the frequency band using a transmitter; and modifying the phase state provided to each patch antenna to accommodate the frequencies transmitted by the transmitter.

[0014] According to another embodiment, a method for reducing side lobes associated with quantization errors using the terahertz imaging system described above is disclosed, the method including: calculating a first set of phase values ​​for each patch antenna in a reflectarray based on frequency; quantizing the first set of phase values ​​to obtain a first set of phase states; adding a constant phase offset to each phase value in the first set of phase values ​​to generate a second set of phase values; quantizing the second set of phase values ​​to obtain the second set of phase states; using the first set of phase states in a first integration; using the second set of phase states in a second integration; and summing or averaging the results of the integrations.

[0015] In some embodiments, the method includes adding a constant phase offset to each phase value of the second set of phase values ​​to generate a third set of phase values; quantizing the third set of phase values ​​to obtain a third set of phase states; adding a constant phase offset to each phase value of the third set of phase values ​​to generate a fourth set of phase values; quantizing the fourth set of phase values ​​to obtain a fourth set of phase states; using the third set of phase states in a third integral; using the fourth set of phase states in a fourth integral; and including the third integral and the fourth integral in summation or averaging.

[0016] According to another embodiment, a method for reducing reflections associated with passive structures using the terahertz imaging system described above is disclosed, the method including: calculating a first set of phase states for each patch antenna in the reflectarray; performing a first integration using the first set of phase states; inverting each phase state in the first set of phase states to generate a second set of phase states for each patch antenna in the reflectarray; performing a second integration using the second set of phase states; and subtracting a result of the second integration from a result of the first integration to cancel the reflections associated with the passive structures. [Brief explanation of the drawings]

[0017] For a better understanding of the present disclosure, reference is made to the accompanying drawings, in which like elements are numbered as follows: [Figure 1A] FIG. 1A illustrates a terahertz imaging system according to one embodiment. [Figure 1B] FIG. 1B illustrates the advantages of a bidirectional reflectarray. [Figure 2] FIG. 2 shows an implementation of a 1-bit phase shifter according to one embodiment. [Figure 3] Figure 3 shows the reflected wave based on the state of the phase shifter; [Figure 4] FIG. 4 shows a first embodiment of a storage element located below each patch antenna. [Figure 5] FIG. 5 shows a second embodiment of a storage element located below each patch antenna. [Figure 6] FIG. 6 shows one embodiment of a semiconductor device used as part of a terahertz antenna array. [Figure 7A] FIG. 7A shows the connections between semiconductor devices and to a printed wiring board. [Figure 7B] FIG. 7B shows the configuration of I / O signals for each semiconductor device according to one embodiment. [Figure 8] FIG. 8 shows an assembled terahertz antenna array according to one embodiment. [Figure 9] FIG. 9 shows details of a terahertz antenna array according to one embodiment. [Figure 10A] Figure 10A shows the result of the changing dynamic phase state in the beam squint. [Figure 10B] Figure 10B shows the result of the changing dynamic phase state in the beam squint. [Figure 11] FIG. 11 shows an algorithm for sidelobe mitigation. [Figure 12] FIG. 12 shows the results of the algorithm for sidelobe mitigation. [Figure 13] FIG. 13 shows a technique for removing unwanted reflections. DETAILED DESCRIPTION OF THE INVENTION

[0018] FIG. 1A illustrates a terahertz imaging system according to one embodiment. In this disclosure, the terahertz waves may be in the frequency range of approximately 0.1 THz to 10 THz. The terahertz imaging system includes a transceiver 20, which may be a frequency-modulated continuous wave (FMCW) transceiver or a stepped-frequency continuous wave (SFCW) transceiver. The transceiver 20 includes a transmitter 25. A signal (TX) transmitted by the transmitter 25 is fed to two drivers 21 and 22. The output of the first driver 21 passes through a directional coupler 23. The directional coupler 23 may be any common duplexing component that allows simultaneous use of the antenna in both transmit and receive modes. Other types of directional couplers include a Wilkinson power combiner, a rat-race coupler, or a circulator.

[0019] The output from directional coupler 23 enters waveguide 30, which directs the terahertz waves to terahertz antenna array 100, also known as a reflectarray. A distal end 31 of waveguide 30 defines an aperture through which the terahertz waves are emitted. Terahertz antenna array 100 may comprise a plurality of antenna elements 110. In some embodiments, there may be more than one hundred antenna elements. In certain embodiments, there may be more than one thousand antenna elements. The configuration of each antenna element is described in more detail below.

[0020] The terahertz waves from the terahertz antenna array 100 are directed toward a target, such as object 10, which reflects a portion of their energy back toward the terahertz antenna array 100. The received reflected waves are then focused back toward the distal end 31 of the waveguide 30. These reflected waves propagate through the waveguide 30 to the transceiver 20. The directional coupler 23 then directs the reflected waves to the mixer 24. The mixer 24 receives the reflected waves and the output from the second driver 22 to generate a received signal (RX), which can be analyzed and processed in the receiver 26.

[0021] By using the distal end 31 of the waveguide 30 as both the terahertz wave source and the destination for the reflected waves, an improved signal-to-noise ratio can be achieved. Figure 1B shows a comparison between a terahertz reflectarray using an omnidirectional receiver and a terahertz reflectarray using a transceiver, such that the waveguide 30 is used for both transmission and reception. Specifically, the terahertz reflectarray with an omnidirectional receiver exhibits an approximately 20 dB difference between the peak power at the main lobe and the nearest side lobe. Furthermore, the difference between the peak power and the background noise is 30–40 dB. Using a waveguide to also receive the reflected waves further compounds this effect, doubling the difference between the peak power at the main lobe and the nearest side lobe, as well as the difference between the peak power and the background noise.

[0022] The terahertz antenna array 100 is adapted to steer the signal from the waveguide 30 towards the target 10. Like a concave mirror, the antenna array, when illuminated by a signal radar source, applies an incident angle-dependent phase shift to the incident wave from the waveguide 30, refocusing it in the desired direction. The antenna array can generate a pencil beam 32 with a beamwidth of 1° in both directions.

[0023] This is achieved through the use of a one-bit phase shifter, as shown in FIG. 2. The antenna element 110 includes a patch antenna 111 constructed of a conductive material, such as metal, and may be disposed on an upper metal layer of a semiconductor device. The patch antenna 111 may be square or rectangular, with two pairs of parallel sides perpendicular to each other. The patch antenna 111 has three contacts, labeled P1, P2, and P3. Note that P1 is configured to receive and transmit signals having a different polarization than the signals received and transmitted from P2 and P3. Specifically, P2 and P3 utilize the same polarization but are 180° out of phase. Thus, P2 and P3 are located at the midpoints of the opposing parallel sides, while P1 is located at the midpoint of the side perpendicular to these two parallel sides. P1 is connected to P2 through a first transistor 120a, and P1 is connected to P3 through a second transistor 120b. In some embodiments, these transistors may be finFETs, although other geometries may also be used. Specifically, P3 is connected to the drain of the second transistor 120b, P2 is connected to the source of the first transistor 120a, and P1 is connected to the source of the second transistor 120b and the drain of the first transistor 120a. Note that these connections can be modified so that any of these connections are connected to the source or drain of each transistor. The gates of the first transistor 120a and the second transistor 120b are driven with complementary signals, such that when the first transistor 120a is enabled, the second transistor 120b is disabled. In some embodiments, these complementary signals are generated through the use of an inverter 125. Signal D, also referred to as a phase state, is used as an input to the inverter 125 and as an input to the gate of the first transistor 120a. However, it is understood that the complementary signals can be generated in other manners.

[0024] Thus, when the phase state (i.e., signal D) is asserted, contact P1 is connected to P2 and disconnected from P3. Conversely, when control signal D is deasserted, contact P1 is connected to P3 and disconnected from P2. This result can be seen in Figure 3. Assuming the incident wave is vertically polarized, it can be seen that the reflected wave will be a horizontally polarized signal, regardless of the value of control signal D. When control signal D is asserted, the reflected signal is radiated from the first side of patch antenna 111, which is the right side in Figure 2, as shown in the lower right. If control signal D is deasserted, the reflected signal is radiated from the opposite side of patch antenna 111, which is the left side in Figure 2, as shown in the upper right. In this way, the 1-bit phase shifter can introduce a phase shift of 0° or 180°. Note that because MOSFETs (metal-oxide-semiconductor field-effect transistors) are used as the first and second transistors, the current flow is omnidirectional. Thus, current flows from P1 to P2 or from P2 to P1 when control signal D is asserted, and flows from P1 to P3 or from P3 to P1 when control signal D is deasserted.

[0025] In a phased array antenna, two or more antennas are configured to radiate energy at the same frequency but with different phases. The phases are selected so that the individual radiation fields of each antenna interfere constructively and / or destructively in a desired direction in the aggregate far field, allowing solid-state control over radiation direction and shape. In practical systems, antenna phase control is often quantized to discrete values, with the desired phase shift value approximated to the nearest available quantized value. This quantization can be as extreme as 1-bit quantization, with two possible phase states and a step size of 180 degrees.

[0026] Returning to Figure 2, it can be seen that one or more storage elements 130 are disposed below the patch antenna 111. The one or more storage elements 130 may be registers, such as shift registers, or memory elements. These storage elements 130 may be used to store multiple values, each of which corresponds to the state of the control signal D at a particular time. In some embodiments, there may be more than 1000 bits associated with each patch antenna 111. In some embodiments, there may be more than 50,000 bits associated with each patch antenna 111.

[0027] As mentioned above, FIG. 2 illustrates storage elements 130 disposed beneath each patch antenna 111. These storage elements 130 can be configured in several ways. In one embodiment, as shown in FIG. 4, storage elements 130a, 130b, ... 130n are arranged as shift registers. While FIG. 4 illustrates two shift registers 136, 137, it is understood that any number of shift registers can be employed, with the number of shift registers typically equaling the number of antenna elements 110. In this configuration, the input and output paths of the shift registers 136, 137 can be connected via multiplexers to enable two different modes. The input multiplexer 132 is used to select the output between the last storage element 130n in the shift register 137 and the last storage element 130n in the previous shift register 136. The output multiplexer 135 is used to direct the output from the last storage element 130n to either the input multiplexer 132 of the shift register 136 or the input multiplexer 132 of the next shift register 137. In a first, or load, mode, the output multiplexer 135 is configured to select the output of the last storage element 130n in the shift register of one antenna element 110 as the input to the first storage element 130a in the shift register of an adjacent antenna element 110. In a second, or cyclic, mode, the output of the last storage element 130n in the shift register of one antenna element 110 serves as the input to the first register in that antenna element's 110 shift register and also serves as the control signal D that controls the phase of the antenna element 110. In this way, the pattern stored in the shift register can be repeatedly applied to the antenna elements 110, if desired. The mode selection can be determined using two multiplexers: the input multiplexer 132 and the output multiplexer 135. Furthermore, in the load mode, the output multiplexer 135 also serves to isolate the antenna elements 110 from the loaded data, since no signal is provided to the patch antenna 111 in this mode.

[0028] Thus, in load mode, all of the shift registers are connected in series and data can be loaded into all of them sequentially. In circular mode, the shift registers are configured so that the output from each shift register is fed back to the input of its respective shift register.

[0029] FIG. 5 illustrates another embodiment. In this embodiment, the storage element 130 is a memory device 145. The memory device 145 may be 1 bit wide, such as 100K x 1 bit, or other configurations. To minimize the number of signals passed between each antenna element 110, each antenna element 110 may have a counter 140 that is used to provide an address to the memory device 145. For example, upon initialization, all counters 140 may be reset. Each clock pulse increments the counter 140, and a different location is written to or read from the memory device 145. The output of the memory device 145 may then serve as the control signal D shown in FIG. 2.

[0030] Thus, in Figure 4, input multiplexer 132 functions as control logic that allows the shift register to be preloaded in a first mode and cyclically provided to the 1-bit phase shifter in a second mode. In Figure 5, counter 140, read signal, and write signal function as control logic that preloads data into memory device 145 and then sequentially provides it to the 1-bit phase shifter.

[0031] FIG. 6 illustrates one embodiment of a semiconductor device 150 including multiple antenna elements, each antenna element having an individual patch antenna 111 and an associated storage element 130. The patch antenna 111 is disposed on an upper metal layer of the semiconductor device 150. The semiconductor device further includes a semiconductor substrate disposed below the metal layer. Active components, including a one-bit phase shifter (i.e., first transistor 120a, second transistor 120b, and inverter 125) and a storage element 130, are formed on the semiconductor substrate. Some of the lower metal layer are used as ground layers to provide interconnections between these active components. The upper metal layer is reserved for use as the patch antenna 111. Furthermore, the semiconductor device 150 is not packaged, leaving the upper metal layer exposed. In this embodiment, the semiconductor device 150 includes 49 antenna elements arranged in a 7-by-7 grid. Of course, grids of other dimensions can also be used. Each antenna element 110 includes a patch antenna 111, a one-bit phase shifter disposed below the patch antenna 111, and a storage element 130.

[0032] The patch antennas 111 are spaced apart in both the horizontal and vertical directions such that there is a spacing of approximately 0.5 wavelengths between each patch antenna 111 and its adjacent antenna. Importantly, because the terahertz antenna array 100 includes a plurality of these semiconductor devices 150, the patch antennas 111 are spaced apart such that the spacing between two patch antennas on the same semiconductor device 150 is the same as the spacing between adjacent patch antennas 111 on different semiconductor devices 150.

[0033] As described above, the terahertz antenna array 100 includes a tiled array of multiple semiconductor devices 150 connected by multiple bond wires. Given the size and complexity of such an assembly, the risk of defects in chip manufacturing or assembly is high. Therefore, the I / O architecture of the array is designed to be robust so that the most likely failure modes, such as an open circuit in an isolated bond wire, have little or no effect on the operation of the array.

[0034] For example, in one embodiment shown in FIG. 7B , clock and data signals for programming and cycling phase states are provided to adjacent semiconductor devices 150 in a row. Additionally, each semiconductor device 150 may include multiple bond wires for power, ground, data, and clock signals. In this manner, open circuits in wire bonds may be tolerated without affecting the functionality of the terahertz antenna array 100. Specifically, if one of the bond wires carrying a clock signal is not properly connected, a second, redundant bond wire can carry the clock signal.

[0035] FIG. 7A shows several semiconductor devices 150 attached to a printed wiring board 160. Each semiconductor device 150 includes multiple antenna elements 110. Additionally, signals such as clock, data, power, and ground are connected to each other using bond wires 161. Additionally, bond wires 161 attach from the semiconductor devices 150 to the printed wiring board 160 along the edges of the terahertz antenna array 100. Preferably, adjacent semiconductor devices 150 are spaced apart so that the patch antennas are evenly spaced across the array. Thus, the spacing between adjacent patch antennas 111 on the same semiconductor device 150 is approximately the same as the spacing between adjacent patch antennas 111 on adjacent semiconductor devices. In some embodiments, these spacings may be within 20% of each other. Although not shown, the printed wiring board 160 may include other circuitry, such as power conditioning circuitry, clock generation circuitry, debug circuitry, and connections to external components. FIG. 7B shows that the clock, data, power, and ground signals all include multiple bond wires. Furthermore, as shown in FIG. 7B, power, ground, data, and clock signals are located on opposite sides of the semiconductor device. In this manner, there is little routing requirement on the underlying printed wiring board because the semiconductor device 150 is responsible for routing these signals from one side of the device to the other, as shown in FIG. 7A. For example, a clock signal is provided as an input on a first side and exits the semiconductor device 150 on the opposite second side. Data, ground, and power signals are similarly configured. In this manner, clock and data signals are routed horizontally. In addition, control signals and additional power and ground signals are provided as inputs on a third side of the semiconductor device and exit the semiconductor device 150 on the opposite fourth side. In this manner, control signals are routed vertically in the tiled array. For redundancy, power and ground signals are routed along both the horizontal and vertical directions of the tiled array. Of course, the direction of the various signals is a design choice, and signals may be interchanged without departing from the spirit of this disclosure.For example, data and clock signals may be routed vertically, while control signals may be provided horizontally.

[0036] FIG. 8 shows an assembled terahertz antenna array 100 according to one embodiment.

[0037] FIG. 9 shows a more detailed view of the assembled terahertz antenna array 100 shown in FIG. 8. An array of semiconductor devices 150 is disposed on a printed wiring board 160. As described in FIG. 7B, the semiconductor devices 150 can be configured so that some signals propagate horizontally from one semiconductor device 150 to an adjacent device and other signals propagate vertically from one device to an adjacent device. In this diagram, a clock generation circuit 173 is used to generate clock signals for all of the semiconductor devices 150. Input data for the array can be provided by data circuits 170. The data and clock signals propagate horizontally. Power conditioning circuits 174 can be located on the periphery of the array. In some embodiments, column selection circuits 171 and row selection circuits 172 can be used to individually address the semiconductor devices 150 in the array.

[0038] Thus, the terahertz antenna array includes a plurality of semiconductor devices 150, each of which includes a plurality of antenna elements 110. Each antenna element 110 includes a patch antenna 111 disposed on a top metal layer of the semiconductor device 150. Each antenna element 110 also includes a one-bit phase shifter in communication with its respective patch antenna 111. Each antenna element 110 also includes a storage element 130 disposed below its respective patch antenna 111 for storing multiple phase states (also referred to as signals D) provided to the one-bit phase shifter. The storage element 130 also includes control logic that enables data to be loaded into the storage element 130 and later accessed. In some embodiments, the control logic enables data stored in the storage element 130 to be provided sequentially, and optionally cyclically, to the one-bit phase shifter associated with the patch antenna 111.

[0039] The semiconductor devices 150 are unpackaged, exposing the top metal layers. These bare semiconductor devices are soldered to a printed wiring board 160, and wire bonding is used to connect signals between the devices. Wire bonding is also used to connect signals from the array to the printed wiring board and back.

[0040] Terahertz antenna array 100 constructed in accordance with the teachings of the present disclosure enables a variety of different applications and tuning algorithms.

[0041] One such algorithm involves beam squint. Beam squint is an effect that degrades the performance of wideband frequency-modulated continuous wave (FMCW) phased array radars and stepped-frequency continuous wave phased array radars. This effect arises from the fact that in phased array antennas, the beamforming phase is set based on the operating frequency, often the center frequency of the frequency sweep. During radar operation, the phased array experiences instantaneous frequency changes during the frequency sweep, also known as chirps. Any difference between the instantaneous frequency and the frequency assumed during the beamforming phase calculations leads to errors that manifest as beam squint. For example, a 10 GHz bandwidth in a classic phased array system with a single set of phases can result in a beam squint of more than 3 degrees in typical applications. This increases the effective beamwidth seen during one chirp of radar operation, reducing the effective resolution of the resulting radar image, especially at wide angles from the bore sight.

[0042] However, the present antenna array mitigates this problem. For example, the frequency sweep, or chirp, can include 10 GHz. The phase of each antenna element 110 in the antenna array can be calculated for multiple different frequencies within the frequency band. In one embodiment, the phase of each antenna element 110 in the antenna array is computed at every integral GHz frequency. Thus, for this frequency band, there are 10 different phase states calculated for each antenna element. These 10 phase states are then stored in a storage element associated with each antenna element 110. When the transceiver 20 changes frequency, the data provided to the 1-bit phase shifter can be changed to accommodate the new frequency. This pattern can be repeated as the transceiver 20 sweeps through the frequency range. To accomplish this, this technique requires synchronization of the antenna array's clock signal with the low-frequency signal used to vary the FMCW signal to adjust the phase states programmed during the chirp sequence. In other words, as the frequency transmitted by transceiver 20 is changed, the phase state provided to each of the one-bit phase shifters of the multiple antenna elements may also be updated. This occurs with each change in transmit frequency, which may change at regular intervals, such as every GHz. In certain embodiments, the transceiver is an FMCW transceiver, while in other embodiments, the transceiver is an SFCW transceiver. This approach is workable with both types of transceivers. In all embodiments, the phase state provided to each patch antenna is changed multiple times during a frequency sweep. In some embodiments, only two phase states may be used during a frequency sweep. In other embodiments, ten or more phase states may be used during a frequency sweep.

[0043] 10A-10B illustrate the benefits of synchronizing the phase state to the frequency of the transceiver 20. In FIG. 10A, normalized power is shown as a function of azimuth angle for three different frequencies. Note that in FIG. 10A, the phase state does not change as the frequency changes. As a result, the peak power at the center frequency (265 GHz) occurs at an azimuth angle of −45°. However, the peak power at the lower frequency (260 GHz) occurs at an azimuth angle of approximately −47°, and the peak power at the higher frequency (270 GHz) occurs at an azimuth angle of approximately −44°. However, as shown in FIG. 10B, by changing the phase state relative to the frequency transmitted by the transceiver 20, the peak power for all three frequencies is shifted (centered) to the −45° center. This improves the effective resolution of the resulting radar image compared to the configuration shown in FIG. 10A.

[0044] Another issue with quantized phase shifters that can be addressed in the reflectarrays described in this disclosure relates to the generation of sidelobes. In imaging radar systems, large sidelobes, combined with a non-sparse environment, can result in erroneous reflections that are indistinguishable from reflections in the desired direction. As shown in FIG. 11, a 1-bit phase shifter results in quantization error. To mitigate this quantization error and reduce the magnitude of the associated sidelobes, a time dithering algorithm can be used. Specifically, a phase value can be calculated for each of the antenna elements 110 using known techniques. These calculated phase values ​​are shown as φ and φ in FIG. 11. A phase offset term, Δφ, is added to the calculated phase values ​​(e.g., φ and φ) of all antenna elements 110 before quantization. This phase offset term is constant across the entire array at each instant in time but changes over time over the course of multiple integrations of the radar imager. The integral is defined as one sweep across the frequency band. The inclusion of this phase offset term, Δφ, changes the quantized state of each antenna element, inverting the phase of some antenna elements from 0° to 180°, and vice versa. This can reduce the side lobes. Figure 12 shows that an unreduced 1-bit phase shifter can produce many side lobes with normalized powers greater than -35°. This is in contrast to an ideal phase shifter, where the side lobes exponentially decrease with distance from the main lobe.

[0045] Thus, in this embodiment, a phase state is calculated for each antenna element using the time dithering algorithm described above. These phase states are then stored in individual storage elements 130. A clock signal is used to cycle the antenna elements through various phase states to achieve the desired pattern. In one test, two values ​​(which could be 0° and 90°) were assigned to the term Δφ, and the phase state of each antenna element was calculated at these two values. The two phase states are then used in two integration steps. In a second test, four values ​​(which could be 0°, 45°, 90°, and 135°) were assigned to the term Δφ, and the phase state of each antenna element was calculated at these four values. The four phase states are then used in four integration steps. Of course, any number of values ​​can be assigned to the phase offset term Δφ, and the phase state associated with each different phase offset term Δφ can be stored in individual storage elements. The results of the various integrations can then be summed or averaged. The values ​​associated with the main lobe are summed coherently, and the values ​​associated with the various side lobes are summed incoherently. Note that using this time dithering algorithm, the magnitude of the side lobes is reduced by approximately 5 dB.

[0046] This time dithering algorithm, and the beam squint algorithm described above, are possible due to the dedicated storage elements in the 1-bit phase shifters of each antenna element.

[0047] This configuration of the terahertz array also enables other advanced features. For example, in some embodiments, the terahertz beam directed at the reflectarray also contacts passive structures, creating unwanted reflections that interfere with the beamformed field. These unwanted reflections can reduce the signal-to-noise ratio (SNR). This effect can be mitigated using the technique shown in Figure 13. As shown on the left side of the figure, a first integration is performed. This integration includes contributions from the beamformed image (top left) and unwanted passive reflections (center left). The result is shown as the total IF. A second integration is then performed. During this second integration, the value of each 1-bit phase shifter is changed across the entire terahertz antenna array, so that all "1s" become "0s" and all "0s" become "1s." This has the effect of shifting the phase of the formed beam by 180° compared to the first integration (top right). However, this phase state reversal does not affect the unwanted passive reflection component (center right). Therefore, the total IF from the second integration is shown in the bottom right. The result of the second integration is then subtracted from the result of the first integration to give the final output shown in the bottom part of Figure 13. Note that since the component from passive reflections is constant, this component is removed by subtracting the two results, leaving only the reflections due to the beamformed field.

[0048] The disclosed system has several applications. For example, the system can be used for real-time imaging, where a beam focused by a reflectarray is sequentially directed to multiple points in a two-dimensional array. Additionally, the system can be used in communications systems, where phase states can be calculated to move a focused beam to track a moving communication target, such as a satellite.

[0049] The present system has many advantages. The reflectarray comprises a large number of antenna elements. Each antenna element utilizes a plurality of storage elements configured to provide multiple phase states to a one-bit phase shifter associated with the individual antenna element. In some embodiments, over 1000 phase states can be stored for each antenna element. This allows the reflectarray to perform functions and algorithms not previously possible. Additionally, the semiconductor device architecture containing these antenna elements can be designed so that they can be arranged in large numbers in a two-dimensional array on a printed wiring board, enabling the formation of very large reflectarrays.

[0050] The present disclosure is not limited in scope by the specific embodiments described herein. Indeed, various other embodiments and modifications of the present disclosure, in addition to those described herein, will be apparent to those skilled in the art from the foregoing description and accompanying drawings. Accordingly, such other embodiments and modifications are intended to be included within the scope of the present disclosure. Moreover, while the present disclosure has been described herein in the context of particular implementations in particular environments for particular purposes, those skilled in the art will recognize that its utility is not limited thereto, and that the present disclosure may be beneficially implemented in any number of environments for any number of purposes. Accordingly, the claims set forth below should be construed in light of the full scope and spirit of the present disclosure as described herein.

Claims

1. a semiconductor substrate; and a plurality of metal layers including an exposed top metal layer; the upper metal layer is formed as a plurality of patch antennas; a plurality of storage elements and one-bit phase shifters are provided on the semiconductor substrate below each of the patch antennas; The semiconductor device, wherein the plurality of storage elements store a plurality of phase states to be supplied to the 1-bit phase shifter.

2. 2. The semiconductor device of claim 1, wherein the plurality of storage elements disposed beneath each individual patch antenna include at least 1000 phase states.

3. 2. The semiconductor device according to claim 1, wherein the plurality of patch antennas are arranged as a lattice having a first number of rows and a second number of columns.

4. The semiconductor device of claim 1 , wherein each storage element of said plurality of storage elements comprises a shift register.

5. 5. The semiconductor device according to claim 4, wherein the semiconductor device has two modes: a load mode in which all shift registers in the semiconductor device are connected in series and data is loaded sequentially into all shift registers, and a circulation mode in which the output of each shift register is provided to the input of that shift register.

6. The semiconductor device of claim 1 , wherein the plurality of storage elements comprises random access memory (RAM).

7. 2. The semiconductor device according to claim 1, wherein each patch antenna is rectangular having two pairs of parallel sides and has three contacts: a first contact (P1); a second contact (P2) provided at the midpoint of the first side; and a third contact (P3) provided at the midpoint of a second side opposite the first side, and the first contact (P1) is provided at the midpoint of a side perpendicular to the first side and the second side.

8. 8. The semiconductor device according to claim 7, wherein the one-bit phase shifter comprises two field-effect transistors: a first transistor including a gate, a source, and a drain, wherein one of the source or the drain is electrically connected to the first contact (P1), the other of the source or the drain is electrically connected to the second contact (P2), and the gate is electrically connected to a control signal provided by the storage element; and a second transistor including a gate, a source, and a drain, wherein one of the source or the drain is electrically connected to the first contact (P1), the other of the source or the drain is electrically connected to the third contact (P3), and the gate is electrically connected to a signal complementary to the control signal.

9. A reflectarray in which the semiconductor devices according to claim 1 are arranged in a tiled array.

10. 10. The reflectarray according to claim 9, wherein a distance between two adjacent patch antennas provided on the same semiconductor device is within 20% of a distance between two adjacent patch antennas provided on different semiconductor devices.

11. The reflect array according to claim 9 , wherein the semiconductor devices are soldered onto a printed wiring board, and wire bonding is used to connect signals between adjacent semiconductor devices.

12. The reflectarray according to claim 11, wherein some of the signals are duplicated so that open circuits in isolated bond wires do not affect operation.

13. The reflectarray according to claim 9; A transceiver comprising a transmitter, a directional coupler, a mixer, and a receiver; and a waveguide; the terahertz waves generated by the transmitter propagate through the directional coupler and the waveguide to an opening at the end of the waveguide; the terahertz waves are directed toward the reflectarray; A terahertz imaging system, wherein waves reflected from an object are focused by the reflectarray toward the end of the waveguide, propagate through the waveguide, the directional coupler, and the mixer, and reach the receiver.

14. 14. A method of performing a sweep across a frequency band using the terahertz imaging system of claim 13, comprising: calculating a phase state for each patch antenna in the reflectarray at a plurality of frequencies within the frequency band; storing the calculated phase states in the storage elements associated with each individual patch antenna; transmitting at a plurality of frequencies in the frequency band using the transmitter; and changing the phase state provided to each patch antenna to accommodate the frequency transmitted by the transmitter.

15. 14. A method for reducing side lobes associated with quantization errors using a terahertz imaging system according to claim 13, comprising: calculating a first set of phase values ​​for each patch antenna in the reflectarray based on frequency; quantizing the first set of phase values ​​to obtain a first set of phase states; adding a constant phase offset to each phase value of the first set of phase values ​​to generate a second set of phase values; quantizing the second set of phase values ​​to obtain a second set of phase states; using the first set of phase states in a first integration; using the second set of phase states in a second integration; adding or averaging the results of said integrations.

16. 16. The method of claim 15, further comprising: adding a constant phase offset to each phase value of the second set of phase values ​​to generate a third set of phase values; quantizing the third set of phase values ​​to obtain a third set of phase states; adding a constant phase offset to each phase value of the third set of phase values ​​to generate a fourth set of phase values; quantizing the fourth set of phase values ​​to obtain a fourth set of phase states; using the third set of phase states in a third integration; using the fourth set of phase states in a fourth integration; The method further comprising including the third integral and the fourth integral in a summation or averaging.

17. 14. A method of reducing reflections associated with passive structures using a terahertz imaging system according to claim 13, comprising: calculating a first set of phase states for each patch antenna in the reflectarray; performing a first integration using the first set of phase states; inverting each phase state in the first set of phase states to generate a second set of phase states for each patch antenna in the reflectarray; performing a second integration using the second set of phase states; and subtracting a result of the second integration from a result of the first integration to cancel reflections associated with the passive structure.

Images