Error rate measuring device and signal detection method

Abstract

To provide an error rate measurement device and a signal detection method capable of detecting a specific pattern, such as a sequence block, in real time and notifying a user of the detection.SOLUTION: An error rate measurement device includes an internal signal generation circuit 22 that generates an internal signal composed of a specific pattern expected to be output from a DUT in accordance with a state of an LTSSM, a reference signal holding unit 23 that holds a part of the beginning of the internal signal as a reference signal, a beginning detection unit 24 that compares the reference signal with an input signal from the DUT to detect a beginning of the specific pattern in the input signal, a detection signal output unit 25 that outputs a detection signal synchronized with a timing at which the beginning of the specific pattern is detected by the beginning detection unit 24, a latch unit 26 that holds the detection signal, and a display unit that displays a detection notification image indicating that the specific pattern has been detected by the beginning detection unit 24 during a period in which the detection signal is held by the latch unit 26.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an error rate measurement device and a signal detection method, and more particularly to an error rate measurement device and a signal detection method for detecting the beginning of a pattern in an input signal. [Background technology]

[0002] Protocols such as PCIe (registered trademark) (Peripheral Component Interconnect Express) and USB (registered trademark) require sequence operations to control the Link Training and Status State Machine (LTSSM) and switch device states. By sending multiple specified data patterns (hereafter referred to as "sequence blocks") to a device in the correct order, it becomes possible to arbitrarily change the device state.

[0003] For example, PCIe has standards such as Gen1 to Gen6, and the communication speed varies depending on the standard, ranging from 2.4GT / s to 32GT / s. All PCIe devices are backward compatible and can switch communication speeds. State switching is also used to switch this communication speed.

[0004] For example, in PCIe, the state transition diagram of the LTSSM is as shown in Figure 6, and the states defined are L0, L0s, L1, L2, Detect, Polling, Configuration, Disabled, Hot Reset, Loopback, and Recovery.

[0005] Developers of PCIe and USB devices, as well as those of their controllers, need to verify during device development testing whether their devices are correctly transmitting and receiving sequence blocks. This verification is typically performed using a logic analyzer or protocol analyzer. However, these measurement devices lack real-time capabilities and often cannot simultaneously acquire and analyze data. Furthermore, some sequence blocks contain patterns with extremely long cycles, which can take a long time to analyze using these measurement devices.

[0006] An error rate measuring device is known as a measuring device that can simultaneously acquire and analyze data in real time (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 7132964 Summary of the Invention [Problem to be solved by the invention]

[0008] Device manufacturers must verify that the devices they develop perform the correct state transitions according to the sequence blocks they input. Because the data output from a device is determined according to its state, the device state can be determined by determining the data output from the device.

[0009] However, although existing error rate measurement devices are capable of measuring the error rate of continuous data, they do not have a mechanism for detecting instantaneous data of about 1 ms and notifying the user of the detection.

[0010] Since an error rate measurement device does not measure an error rate unless it detects data, it is possible for a user to know that data has been detected based on whether an error rate measurement is being performed. However, since the update period of the GUI (Graphical User Interface) of conventional error rate measurement devices is about 100 ms, there is a problem that a user cannot visually recognize the detection of data unless the data is several hundred ms or longer. Furthermore, even if the data is several hundred ms or longer, if the entire sequence is long, it is not realistic for a user to check when the period of several hundred ms was displayed.

[0011] The present invention has been made to solve the above-mentioned conventional problems, and aims to provide an error rate measuring device and a signal detection method that can detect specific patterns such as sequence blocks in real time and notify the user. [Means for solving the problem]

[0012] In order to solve the above-mentioned problems, the error rate measurement device according to the present invention is an error rate measurement device (100) that measures the error rate of an input signal from a device under test (200) equipped with a link state management mechanism, and is configured to include: an internal signal generation circuit (22) that generates an internal signal consisting of a specific pattern that is expected to be output from the device under test (200) in accordance with the state of the link state management mechanism; a reference signal holding unit (23) that holds a part of the beginning of the internal signal as a reference signal; a beginning detection unit (24) that compares the reference signal with the input signal to detect the beginning of the specific pattern in the input signal; a detection signal output unit (25) that outputs a detection signal synchronized with the timing at which the beginning of the specific pattern is detected by the beginning detection unit; a latch unit (26) that holds the detection signal; and a display unit (40) that displays a detection notification image (61) that indicates that the beginning of the specific pattern has been detected by the beginning detection unit during the period in which the detection signal is held by the latch unit.

[0013] With this configuration, when the error rate measurement device according to the present invention detects the beginning of a specific pattern such as a sequence block in the input signal, it displays on the display unit that the specific pattern has been detected, thereby enabling the error rate measurement device according to the present invention to detect specific patterns such as sequence blocks in real time and notify the user.

[0014] In other words, the present invention is configured by adding a function for detecting sequence blocks such as PCIe and USB to an error rate measurement device capable of measuring error rates in real time, allowing users to instantly confirm the presence of specific sequence blocks without spending time on analysis, thereby improving usability.

[0015] Furthermore, the error rate measuring device according to the present invention may be configured such that the display unit further displays a hold release instruction unit (62) for releasing the hold of the detection signal by the latch unit.

[0016] With this configuration, the error rate measurement device of the present invention can release the retention of the detection signal by the latch unit by operating the retention release instruction unit, so that it can start detecting a new specific pattern.

[0017] Furthermore, the error rate measurement device according to the present invention may further include a delay circuit (27) that delays the input signal in which the head of the specific pattern has been detected by the head detection unit, thereby synchronizing the internal signal output from the internal signal generation circuit with the specific pattern in the input signal, and an error rate measurement unit (28) that measures the error rate of the specific pattern in the input signal by sequentially comparing the internal signal output from the internal signal generation circuit with the input signal output from the delay circuit, and the internal signal generation circuit may be configured to generate the internal signal using the detection signal as a trigger.

[0018] With this configuration, the error rate measurement device according to the present invention can measure the error rate of a specific pattern in an input signal by synchronizing the internal signal output from the internal signal generation circuit with the specific pattern in the input signal.

[0019] The error rate measurement apparatus according to the present invention may further comprise a pulse pattern generator (21) for transmitting a sequence block for causing the link state management mechanism to transition to an arbitrary state to the device under test.

[0020] With this configuration, the error rate measurement device according to the present invention is equipped with a pulse pattern generator, which makes it possible to transmit sequence blocks for error rate measurement and check their operation in a single device. As a result, the error rate measurement device according to the present invention can reduce the time and cost required for the test process related to error rate measurement, thereby making the test process more efficient.

[0021] Furthermore, a signal detection method according to the present invention is a signal detection method executed by an error rate measurement device (100) that measures the error rate of an input signal from a device under test (200) equipped with a link state management mechanism, and includes an internal signal generation step (S3) of generating an internal signal consisting of a specific pattern that is expected to be output from the device under test (200) in accordance with the state of the link state management mechanism, a reference signal holding step (S4) of holding a part of the beginning of the internal signal as a reference signal, a head detection step (S6) of comparing the reference signal with the input signal to detect the beginning of the specific pattern in the input signal, a detection signal output step (S7) of outputting a detection signal synchronized with the timing at which the beginning of the specific pattern is detected in the head detection step, a latch step (S8) of holding the detection signal in a latch unit (26), and a display step (S9) of displaying a detection notification image (61) indicating that the beginning of the specific pattern has been detected in the head detection step during the period in which the detection signal is held by the latch unit. [Effects of the Invention]

[0022] The present invention provides an error rate measuring device and a signal detection method that can detect specific patterns such as sequence blocks in real time and notify the user of the detected patterns. [Brief explanation of the drawings]

[0023] [Figure 1] 1 is a block diagram showing a configuration of an error rate measurement device according to an embodiment of the present invention; [Figure 2] 1 is a block diagram showing the functional configuration of an FPGA included in an error rate measurement device according to an embodiment of the present invention. [Figure 3] FIG. 10 is a diagram showing an example of a result display screen displayed on a display unit provided in the error rate measurement device according to the embodiment of the present invention. [Figure 4] FIG. 10 is a diagram showing an example of a pattern setting screen displayed on a display unit provided in the error rate measurement apparatus according to the embodiment of the present invention. [Figure 5] 1 is a flowchart showing the processing of a signal detection method using an error rate measurement device according to an embodiment of the present invention. [Figure 6] FIG. 10 is a diagram illustrating state transitions of the LTSSM. DETAILED DESCRIPTION OF THE INVENTION

[0024] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An error rate measurement device and a signal detection method according to embodiments of the present invention will be described below with reference to the accompanying drawings.

[0025] As shown in FIG. 1, the error rate measurement device 100 according to this embodiment measures the error rate of an input signal from a device under test (DUT) 200, and includes a signal processing unit 10, an FPGA 20, a data storage unit 30, a display unit 40, an operation unit 41, and a control unit 42.

[0026] The control unit 42 is composed of a control device such as a computer including, for example, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and an HDD (Hard Disk Drive), and is configured to control the display unit 40 and operation unit 41, as well as the FPGA 20, using control software 43.

[0027] The control unit 42 also includes firmware 44 that acts as an intermediary between the FPGA 20 and the control software 43. The control software 43 has a GUI, and processes inputs from the user on the operation unit 41 and displays to the user on the display unit 40.

[0028] The display unit 40 is composed of various display screens and display devices such as an LCD (Liquid Crystal Display) that displays GUIs such as soft keys.

[0029] The operation unit 41 is used to accept operation inputs from the user, and is composed of user interfaces such as operation knobs, various keys, switches, and buttons provided on the main body of the error rate measurement device 100, as well as a touch panel, mouse, or keyboard for operating the GUI of the display unit 40.

[0030] The DUT 200 is equipped with an LTSSM, and when the LTSSM transitions to one of the states shown in Fig. 6, it outputs a data pattern such as a sequence block corresponding to that state as an input signal to the error rate measurement device 100. For example, when the DUT 200 transitions to the loopback state "LOOPBACK_ACTIVE_MASTER", it outputs (loops back) an output signal from a pulse pattern generator (PPG) 21, which will be described later, as an input signal to the error rate measurement device 100. Examples of standards that the DUT 200 supports include PCIe Gen1 to 6 and USB 1.0 to 4.

[0031] The signal processing unit 10 converts the input signal from the DUT 200 from an analog signal to a digital signal, and also converts the output signal from the FPGA 20 from a digital signal to an analog signal.

[0032] The data storage unit 30 is configured with a memory such as a RAM, and stores a specific pattern that is expected to be output from the DUT 200 when the LTSSM of the DUT 200 transitions to an arbitrary state. The data storage unit 30 also stores the specific pattern in advance on a file-by-file basis.

[0033] The specific pattern is, for example, a sequence block that controls state transitions between multiple states managed by the LTSSM of the DUT 200. The data storage unit 30 stores, in file units, known sequence blocks that are output when the DUT 200 transitions to each state.

[0034] For example, if the standard is PCIe Gen5 and the state of the DUT 200 is "LOOPBACK_ENTRY_MASTER_TS1", the sequence block output from the DUT 200 is recorded in a file with the file name "PCIe5_LOOPBACK_ENTRY_MASTER_TS1". Note that the file naming method is not limited to the above, and any name that makes it easy for the user to understand the combination of standard and state may be used.

[0035] Alternatively, the specific pattern may be a PRBS (Pseudo Random Binary Sequence) pattern or an arbitrary data pattern set by the user.

[0036] For example, when the state of the DUT 200 is "LOOPBACK_ACTIVE_MASTER", the data storage unit 30 may store information in file units for causing the PPG 21 and the internal signal generation circuit 22 described later to generate known patterns such as a PRBS pattern or an arbitrary data pattern set by the user.

[0037] As shown in FIG. 2, the FPGA 20 includes a PPG 21, an internal signal generating circuit 22, a reference signal holding unit 23, a head detection unit 24, a detection signal output unit 25, a latch unit 26, a delay circuit 27, and an error rate measurement unit 28.

[0038] The PPG 21 is configured to transmit a sequence block for transitioning the LTSSM of the DUT 200 to an arbitrary state as an output signal to the DUT 200. Furthermore, when the state of the DUT 200 is "LOOPBACK_ACTIVE_MASTER," the PPG 21 reads data of a specific pattern stored in the data storage unit 30 from the data storage unit 30, performs appropriate encoding processing on the read data of the specific pattern, generates a test signal consisting of a repetition of the specific pattern, and transmits the test signal as an output signal to the DUT 200. The specific pattern read by the PPG 21 from the data storage unit 30 is set on a pattern setting screen 70, which will be described later.

[0039] The internal signal generation circuit 22 is a circuit that reads out, from the data storage unit 30, data of a specific pattern that is expected to be output from the DUT 200 in accordance with the state of the LTSSM of the DUT 200, performs appropriate encoding processing on the read data of the specific pattern, and generates an internal signal consisting of a repetition of the specific pattern. The specific pattern that is read out from the data storage unit 30 by the internal signal generation circuit 22 is set on a pattern setting screen 70, which will be described later.

[0040] The internal signal generating circuit 22 generates an internal signal using a detection signal output from a detection signal output unit 25 (described later) as a trigger, and outputs the generated internal signal to an error rate measuring unit 28 at the subsequent stage.

[0041] When the state of the DUT 200 is "LOOPBACK_ACTIVE_MASTER", the control unit 42 controls the PPG 21 and the internal signal generating circuit 22 to generate the same specific pattern.

[0042] The reference signal holding unit 23 holds a portion of the beginning of an internal signal consisting of a specific pattern set on a pattern setting screen 70 described later, for example, the first several tens of bits of the specific pattern, as a reference signal.

[0043] The head detection unit 24 compares the reference signal held by the reference signal holding unit 23 with the input signal from the DUT 200 that has been signal processed by the signal processing unit 10, and detects the head of a specific pattern in the input signal.

[0044] The detection signal output unit 25 outputs a detection signal synchronized with the timing at which the head of the specific pattern is detected by the head detection unit 24 to the internal signal generation circuit 22. The detection signal output unit 25 also outputs to the delay circuit 27 the pattern of the input signal at which the head of the specific pattern is detected by the head detection unit 24.

[0045] The latch unit 26 is configured to hold the detection signal output from the detection signal output unit 25. Note that the latch unit 26 is configured to release the held detection signal when the error rate measured by the error rate measurement unit 28 (described later) exceeds a predetermined value. This is because the input signal may contain the same data as the beginning of the specific pattern at a location different from the specific pattern. In such a case, the subsequent bits of the input signal will no longer match the specific pattern, resulting in a high error rate.

[0046] The latch unit 26 also releases the held detection signal when a "History Reset" button 62 is pressed on a result display screen 60 (described later). After the latch unit 26 releases the held detection signal, the head detection unit 24 again detects the head of the specific pattern contained in the input signal.

[0047] The delay circuit 27 is a circuit that delays the input signal in which the head of the specific pattern has been detected by the head detector 24, and synchronizes the internal signal output from the internal signal generating circuit 22 with the specific pattern in the input signal.

[0048] That is, the internal signal generating circuit 22 generates an internal signal using the detection signal as a trigger, and the delay circuit 27 delays the input signal in which the beginning of the specific pattern is detected, so that an internal signal synchronized with the input signal is output to the error rate measuring unit 28 in the subsequent stage.

[0049] The error rate measurement unit 28 measures the error rate of a specific pattern in the input signal by sequentially comparing the internal signal output from the internal signal generation circuit 22 with the input signal output from the delay circuit 27. The error rate in this embodiment is a bit error rate (BER) when the input signal is a non-return to zero (NRZ) signal, and is a symbol error rate (SER) when the input signal is a pulse amplitude modulation 4 (PAM4) signal.

[0050] FIG. 3 shows a result display screen 60 that is displayed by the display unit 40 when the "Result" tab 51a is pressed by the operation unit 41 in the screen selection tabs 51 on the main display screen 50 that is displayed by the display unit 40.

[0051] The result display screen 60 includes an image 61 of “SyncGain”, a button 62 of “History Reset”, and a text box 63 .

[0052] The "SyncGain" image (hereinafter also referred to as a "detection notification image") 61 on the result display screen 60 is an image that resembles an LED.

[0053] The detection notification image 61 changes from a black, off state to a green, on state when the beginning of a specific pattern set on the pattern setting screen 70, which will be described later, is detected consecutively the number of times set in the text box 63. Here, the text box 63 is used to set the number of detections required for the detection notification image 61 to change from the off state to the on state, and is located on the result display screen 60, for example, near the detection notification image 61.

[0054] When the "History Reset" button 62 is pressed by the operation unit 41, the detection notification image 61 turns black and turns off, and at this time the detection signal held by the latch unit 26 is released. The "History Reset" button 62 constitutes a hold release instruction unit for releasing the hold of the detection signal by the latch unit 26.

[0055] That is, the detection notification image 61 lights up in green to indicate that the head of a specific pattern has been detected by the head detection unit 24 during the period in which the detection signal is held by the latch unit 26. The colors of the detection notification image 61 are not limited to the above-mentioned black and green, and may be any combination of colors.

[0056] Furthermore, the latch unit 26 can release the detection signal from being held not only by pressing the "History Reset" button 62 on the operation unit 41, but also by using a remote command from an external control device.

[0057] Furthermore, the result display screen 60 may have a text box 64 near the detection notification image 61 that indicates the number of detections, which indicates how many times the detection signal has been detected consecutively by the latch unit 26.

[0058] Furthermore, the detection notification image 61 may be configured to change from a black, off state to a green, lit state when the error rate of the specific pattern measured by the error rate measurement unit 28 falls below a predetermined error rate during the period in which the detection signal is held by the latch unit 26. This has the advantage of increasing the reliability of the detection of the specific pattern. For this purpose, the result display screen 60 may have a text box 65 for setting the predetermined error rate at which the detection notification image 61 turns green.

[0059] Depending on the error rate set in the text box 65, it may take more than 1 ms from the time the detection signal is held by the latch unit 26 until the detection notification image 61 turns green (for example, at least 1E9 bits of data are required to confirm that the error rate is 1E-9 or less).

[0060] In practice, the error rate measurement apparatus 100 according to this embodiment will detect sequence blocks of, for example, 1 ms or more, but synchronization by the delay circuit 27 is completed within tens to hundreds of μs, which is less than 1 ms, from the input of the input signal from the DUT 200. This is the delay time from the input of the input signal to synchronization. However, since the final method of notifying the user is through a GUI display on the display unit 40, the update period of the GUI on the display unit 40 actually becomes the final delay time.

[0061] FIG. 4 shows a pattern setting screen 70 that is displayed when the "Pattern" tab 51b is pressed by the operation unit 41 in the screen selection tabs 51 on the main display screen 50 of the display unit 40.

[0062] The pattern setting screen 70 is a screen for setting a specific pattern, and includes a "Test Pattern" pull-down menu 71, an Edit button 72, and an "Edit File Name" label 73.

[0063] The "Test Pattern" pull-down menu 71 allows a specific pattern, such as a sequence block, a PRBS pattern, or an arbitrary data pattern, to be selected using the operation unit 41. Fig. 4 shows the state in which "HSSB Data," which indicates the data of a sequence block, has been selected.

[0064] The Edit button 72 is used to specify a file in which a specific pattern selected in the "Test Pattern" pull-down menu 71 is recorded, from among multiple files stored in the data storage unit 30. When the Edit button 72 is pressed using the operation unit 41, a separate screen (not shown) opens, allowing the user to load, save, and edit the file in bit units.

[0065] The "Edit File Name" label 73 displays the file name of the file specified by the Edit button 72 among the multiple files stored in the data storage unit 30. In other words, the specific pattern recorded in the file displayed here is set in the PPG 21 and the internal signal generation circuit 22. FIG. 4 shows a state in which the file name "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" is displayed.

[0066] As shown in FIGS. 3 and 4, the main display screen 50 has a measurement start button 53 for specifying the start of measurement, and a measurement stop button 54 for specifying the stop of measurement.

[0067] When the measurement start button 53 is pressed by the operation unit 41, the PPG 21 sequentially outputs sequence blocks that control the state transition of the DUT 200 to the DUT 200. Thereafter, when the DUT 200 sequentially transitions through its states and outputs the specific pattern recorded in the file displayed in the "Edit File Name" label 73, the head detection unit 24 detects the head of this specific pattern, and the detection signal output unit 25 outputs a detection signal.

[0068] For example, as shown in Figure 4, if "HSSB Data" is selected in the "Test Pattern" pull-down menu 71 and "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" is specified in the "Edit File Name" label 73, when the DUT 200 reaches the PCIe Gen5 "LOOPBACK_ENTRY_MASTER_TS1" state and outputs a sequence block for this state, the head detection unit 24 detects the head of this sequence block and the detection signal output unit 25 outputs a detection signal.

[0069] An example of the signal detection method using the error rate measurement apparatus 100 of this embodiment will be described below with reference to the flowchart in Fig. 5. Note that descriptions that overlap with the description of the configuration of the error rate measurement apparatus 100 described above will be omitted as appropriate.

[0070] First, the control unit 42 displays the main display screen 50 on the display unit 40 (step S1).

[0071] Next, the user selects a file with the file name "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" on the pattern setting screen 70 via the operation unit 41, thereby setting a specific pattern to be detected (step S2).

[0072] Next, when the user presses the measurement start button 53 via the operation unit 41, the internal signal generation circuit 22 generates an internal signal consisting of a sequence block that is a specific pattern recorded in the file "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" (internal signal generation step S3).

[0073] Next, the reference signal holding unit 23 holds a part of the beginning of the sequence block recorded in the file "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" as a reference signal (reference signal holding step S4).

[0074] Next, the PPG 21 sequentially transmits sequence blocks that control state transitions to the DUT 200 (step S5).

[0075] Next, when the head detection unit 24 compares the reference signal with the input signal from the DUT 200 and detects the head of the sequence block recorded in the file "PCIe5_LOOPBACK_ENTRY_MASTER_TS1" in the input signal (head detection step S6: YES), the detection signal output unit 25 outputs a detection signal synchronized with the timing at which the head of the above sequence block is detected in the head detection step S6 to the internal signal generation circuit 22 (detection signal output step S7).

[0076] Next, the latch section 26 holds the detection signal output from the detection signal output section 25 (latch step S8).

[0077] Next, the display unit 40 changes the detection notification image 61 on the result display screen 60 from an off state to an on state during the period in which the detection signal is held by the latch unit 26, thereby indicating that the beginning of the specific pattern has been detected in the beginning detection step S6 (display step S9).

[0078] Next, when the user presses the "History Reset" button 62 via the operation unit 41 (step S10: YES), the latch unit 26 releases the detection signal from being held (step S11).

[0079] Next, the display unit 40 changes the detection notification image 61 on the result display screen 60 from a lit state to an unlit state (step S12).

[0080] Next, when the user presses the measurement stop button 54 via the operation unit 41 (step S13: YES), the processing of this flowchart ends. On the other hand, if the user does not press the measurement stop button 54 via the operation unit 41 (step S13: NO), the processing from step S6 onwards is executed again.

[0081] As described above, when the error rate measurement apparatus 100 according to this embodiment detects the beginning of a specific pattern such as a sequence block in an input signal, it displays a message that the specific pattern has been detected on the display unit 40. This allows the error rate measurement apparatus 100 according to this embodiment to detect specific patterns such as sequence blocks in real time and notify the user.

[0082] In other words, the present invention is configured by adding a function for detecting sequence blocks such as PCIe and USB to an error rate measurement device capable of measuring error rates in real time, allowing users to instantly confirm the presence of specific sequence blocks without spending time on analysis, thereby improving usability.

[0083] Furthermore, in the error rate measurement device 100 according to this embodiment, when the user presses the "History Reset" button 62, which serves as a hold release instruction section, the latch section 26 releases the retention of the detection signal, so that detection of a new specific pattern can be started.

[0084] Furthermore, the error rate measurement apparatus 100 according to this embodiment can measure the error rate of a specific pattern in an input signal by synchronizing the internal signal output from the internal signal generation circuit 22 with the specific pattern in the input signal.

[0085] Furthermore, the error rate measurement apparatus 100 according to this embodiment includes the pulse pattern generator 21, which makes it possible to transmit sequence blocks for error rate measurement and check their operation in a single device. As a result, the error rate measurement apparatus 100 according to this embodiment can reduce the time and cost required for the test process related to error rate measurement, thereby making the test process more efficient. [Explanation of symbols]

[0086] 20 FPGA 21 PPG 22 Internal signal generation circuit 23 Reference signal holding unit 24 Head detection unit 25 Detection signal output section 26 Latch section 27 Delay Circuit 28 Error rate measurement unit 30 Data storage unit 40 Display section 41 Operation section 42 Control Unit 43 Control Software 44 Firmware 50 Main display screen 60 Results display screen 61 Detection notification image 62 buttons 63~65 Text box 70 Pattern setting screen 71 Drop-down menu 72 Edit button 73 Label 100 Error rate measuring device 200 DUT

Claims

1. An error rate measurement device (100) for measuring an error rate of an input signal from a device under test (200) equipped with a link state management mechanism, an internal signal generating circuit (22) that generates an internal signal having a specific pattern that is expected to be output from the device under test in accordance with the state of the link state management mechanism; a reference signal holding unit (23) that holds a part of the beginning of the internal signal as a reference signal; a head detection unit (24) that compares the reference signal with the input signal to detect the head of the specific pattern in the input signal; a detection signal output unit (25) that outputs a detection signal synchronized with the timing at which the head of the specific pattern is detected by the head detection unit; a latch unit (26) for holding the detection signal; and a display unit (40) that displays a detection notification image (61) indicating that the beginning of the specific pattern has been detected by the beginning detection unit during the period in which the detection signal is held by the latch unit.

2. 2. The error rate measuring device according to claim 1, wherein the display unit further displays a hold release instruction unit (62) for releasing the hold of the detection signal by the latch unit.

3. a delay circuit (27) that delays the input signal in which the head of the specific pattern has been detected by the head detection unit, thereby synchronizing the internal signal output from the internal signal generation circuit with the specific pattern in the input signal; an error rate measurement unit (28) that measures an error rate of the specific pattern in the input signal by sequentially comparing the internal signal output from the internal signal generation circuit with the input signal output from the delay circuit, 2. The error rate measuring device according to claim 1, wherein the internal signal generating circuit generates the internal signal using the detection signal as a trigger.

4. 3. The error rate measuring device according to claim 1, further comprising a pulse pattern generator (21) for transmitting to the device under test a sequence block for causing the link state management mechanism to transition to an arbitrary state.

5. A signal detection method executed by an error rate measurement device (100) that measures the error rate of an input signal from a device under test (200) equipped with a link state management mechanism, comprising: an internal signal generating step (S3) of generating an internal signal having a specific pattern expected to be output from the device under test in accordance with the state of the link state management mechanism; a reference signal holding step (S4) of holding a part of the beginning of the internal signal as a reference signal; a head detection step (S6) of comparing the reference signal with the input signal to detect the head of the specific pattern in the input signal; a detection signal output step (S7) of outputting a detection signal synchronized with the timing at which the head of the specific pattern is detected by the head detection step; a latch step (S8) of holding the detection signal by a latch unit (26); a display step (S9) of displaying a detection notification image (61) indicating that the beginning of the specific pattern has been detected by the beginning detection step during the period in which the detection signal is held by the latch unit.

Images