Error correction method and error correction circuit

Abstract

An error correction method and an error correction circuit are provided that suppress increases in circuit size and power consumption even when the code length is large in error correction processing in a digital coherent optical transmission system. [Solution] The error correction method of the present invention performs multiple error corrections, and in some error corrections, only the latter half of the code is corrected. For the bits in the latter half of the code, error correction is performed using the LLR (log-likelihood ratio) input from the previous circuit, and for the bits in the first half of the code, error correction is performed using the fixed maximum value that the LLR can take.

Description

[Technical Field]

[0001] The present invention relates to an error correction method and an error correction circuit for a digital coherent optical transmission system. [Background technology]

[0002] Error correction is a technology for correcting bit errors that occur in a transmission path. The transmitter adds an error-correcting code (parity bit) to the code (information bit) to be transmitted and transmits it. The receiver then uses the received error-correcting code (parity bit) to correct errors in the received code (information bit). To further increase the capacity and speed of optical communications, long-distance transmission of signals exceeding 100 Gbps is required, and digital coherent optical transmission systems are expected to be utilized. Transmission of signals exceeding 100 Gbps requires advanced error correction because the effects of transmission path noise become significant. Digital coherent optical transmission achieves high error correction capabilities by using soft decision and iterative decoding in addition to conventional hard decision (see Patent Document 1).

[0003] When error correction processing is performed on the receiving side, LLR (Log-Likelihood Ratio) is used as soft decision information that is input to the error correction decoding circuit. This LLR is a value derived from the coordinate shift of the received symbol, and is calculated as the ratio of the probability that the transmitted signal is 0 to the probability that it is 1. The absolute value of the LLR indicates the likelihood of the 1 / 0 decision result of the received code.

[0004] Conventional error correction technology requires the storage of LLRs for the code length for error correction processing, which poses the problem of increased circuit size and power consumption when processing error correction with long code lengths. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 7241851 Summary of the Invention [Problem to be solved by the invention]

[0006] The present invention has been made to solve the above-mentioned problems, and has as its object to provide an error correction method and an error correction circuit that can reduce power consumption in error correction processing with a large code length. [Means for solving the problem]

[0007] The error correction method of the present invention is an error correction method for a digital coherent optical transmission system, comprising: The error correction method includes a first step of calculating an LLR for each bit of a code to be error corrected, and a second step of performing error correction processing using the LLR, updating the LLR based on the result of the error correction processing, and outputting the LLR to a subsequent circuit, wherein at least some of the second steps, which are performed a plurality of times, are determined in advance to perform error correction processing using an LLR input from a previous circuit for only the latter bits of a codeword consisting of a multi-bit code due to a known difference in residual error rate depending on the code position, and to update the LLR for the latter bits based on the result of the error correction processing and output the LLR to the subsequent circuit, and are determined in advance not to perform error correction processing for the first bits, but to update the LLR for the first bits to a fixed maximum value that can be taken, and output the LLR to the subsequent circuit, and wherein each of the second steps, which are performed a plurality of times, does not perform error correction processing for the bit for which the LLR input from the previous circuit is the maximum value. It is characterized by the above.

[0008] Furthermore, the error correction circuit of the present invention is configured to perform error correction processing in a digital coherent optical transmission system, The present invention comprises a soft decision circuit that calculates an LLR for each bit of a code from a coordinate shift of a received symbol and outputs the LLR to a subsequent circuit, and a plurality of cascaded soft decision decoding circuits that perform error correction processing using the LLR calculated or updated by the previous circuit and update the LLR based on the result of the error correction processing, wherein at least some of the soft decision decoding circuits are determined in advance to perform error correction processing using the LLR input from the previous circuit for only the latter bits of a codeword consisting of a multi-bit code due to a known difference in residual error rate depending on the code position, and update the LLR for the latter bits based on the result of the error correction processing and output the LLR to the subsequent circuit, and are determined in advance not to perform error correction processing for the first bits, but to update the LLR for the first bits to a fixed maximum value that can be taken and output the LLR to the subsequent circuit, and each of the plurality of soft decision decoding circuits does not perform error correction processing for the bit for which the LLR input from the previous circuit is the maximum value. It is characterized by the above.

[0009] Moreover, one example of the configuration of the error correction circuit of the present invention is as follows: The soft-decision decoding circuit at the final stage among the plurality of soft-decision decoding circuits is determined in advance to perform error correction processing on only the latter bits of a codeword consisting of a code of multiple bits using the LLR input from the previous stage circuit, and not to perform error correction processing on the first bits. It is characterized by the above. Moreover, one example of the configuration of the error correction circuit of the present invention is as follows: All of the soft-decision decoding circuits are determined in advance to perform error correction processing on only the latter bits of a codeword consisting of a multi-bit code using the LLR input from a previous circuit, update the LLR for the latter bits based on the result of the error correction processing, and output the updated LLR to a subsequent circuit, and are determined in advance to not perform error correction processing on the first bits, update the LLR for the first bits to a fixed maximum value that can be taken, and output the updated LLR to a subsequent circuit. It is characterized by the above. Moreover, one example of the configuration of the error correction circuit of the present invention is as follows: Some of the soft-decision decoding circuits are determined in advance to perform error correction processing on only the latter bits of a codeword consisting of a multi-bit code using the LLR input from a previous circuit, update the LLR for the latter bits based on the result of the error correction processing, and output the updated LLR to a subsequent circuit, and are determined in advance to not perform error correction processing on the first bits, update the LLR for the first bits to a fixed maximum value that can be taken, and output the updated LLR to a subsequent circuit. It is characterized by the above. [Effects of the Invention]

[0010] According to the present invention, in the error correction process of a digital coherent optical transmission system, multiple error corrections are performed, and in some error corrections, only the latter half of the code is corrected, thereby making it possible to suppress increases in circuit size and power consumption. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing the configuration of a transmitting device in a digital coherent optical transmission system according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing a configuration of a receiving device of a digital coherent optical transmission system according to an embodiment of the present invention. [Figure 3] FIG. 3 is a block diagram showing the configuration of a soft decision circuit and an error correction decoding circuit according to an embodiment of the present invention. [Figure 4] FIG. 4 is a flowchart illustrating the operation of the soft decision circuit and the error correction decoding circuit according to the embodiment of the present invention. [Figure 5] FIG. 5 is a diagram illustrating the overall arrangement of codes in oFEC and the placement of each code. [Figure 6] FIG. 6 is a diagram illustrating code overlap in oFEC. [Figure 7] FIG. 7 is a diagram illustrating code overlap in oFEC. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a transmitting device in a digital coherent optical transmission system according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a receiving device in a digital coherent optical transmission system according to an embodiment of the present invention. The transmitting device 1 encodes and modulates transmission data to generate a transmission signal. The transmission signal is received by the receiving device via a wired or wireless transmission path. The receiving device demodulates and decodes the received signal to generate received data.

[0013] The transmitting device 1 includes an error correction coding circuit 10, a symbol mapping circuit 11, a modulation circuit 12, and a DA conversion circuit 13. The error correction coding circuit 10 generates coded data by performing, for example, BCH (Bose-Chaudhuri-Hocquenghem) coding or LDPC (Low Density Parity Check) coding on the transmission data.

[0014] The symbol mapping circuit 11 performs carrier modulation by allocating the coded data output from the error correction coding circuit 10 to symbol points such as QPSK (Quadrature Phase Shift Keying) and 16QAM (Quadrature Amplitude Modulation). The modulation circuit 12 performs, for example, OFDM (Orthogonal Frequency Division Multiplexing) modulation on the data carrier-modulated by the symbol mapping circuit 11, thereby generating a modulated signal.

[0015] The DA conversion circuit 13 converts the modulated signal from a digital signal to an analog signal to generate a transmission signal, which is converted into an optical signal by an optical transmission module (not shown) and sent to an optical fiber transmission line.

[0016] The receiving device 2 includes an AD conversion circuit 20, a demodulation circuit 21, a symbol demapping circuit 22, a soft decision circuit 23, and an error correction decoding circuit 24.

[0017] An optical receiving module (not shown) of the receiving device 2 converts an optical signal received from an optical fiber transmission line into an analog received signal. The AD conversion circuit 20 converts the analog received signal into a digital signal. The demodulation circuit 21 performs demodulation processing on the signal output from the AD conversion circuit 20, corresponding to the OFDM modulation performed on the transmitting device 1 side, and outputs the demodulated received signal to the symbol demapping circuit 22.

[0018] The symbol demapping circuit 22 outputs a bit string corresponding to an ideal signal point that is closest to the received signal (received symbol) by hard decision from the received signal output from the demodulation circuit 21. The soft decision circuit 23 calculates and outputs an LLR (Log Likelihood Ratio) for each bit based on the coordinate shift of the received symbol. The error correction decoding circuit 24 performs error correction processing on the bit string output from the soft decision circuit 23 based on the LLR (Log Likelihood Ratio) for each bit generated by the soft decision circuit 23 .

[0019] 3 is a block diagram showing the configurations of the soft decision circuit 23 and the error correction decoding circuit 24 of this embodiment. The error correction decoding circuit 24 is made up of a plurality of cascaded soft decision decoding circuits (SD-DEC: Soft Decision Decoders) 240-1 to 240-k (k is an integer of 2 or more).

[0020] The soft-decision decoding circuits 240-1 to 240-k include error correction units 241-1 to 241-k that perform error correction processing based on the LLR calculated or updated in the previous circuit. Also, the soft-decision decoding circuits 240-1 to 240-(k-1) include LLR update units 242-1 to 242-(k-1) that update the LLR (Log-Likelihood Ratio) based on the result of the error correction processing.

[0021] The configuration in Fig. 3 is an example of a configuration including a soft decision circuit 23 and k-stage soft decision decoding circuits 240-1 to 240-k. The number of stages of the soft decision decoding circuits 240-1 to 240-k is not limited, and any number of stages of soft decision decoding circuits may be provided depending on the required error tolerance. Although not shown in Fig. 3, a hard decision decoder (HD-DEC: Hard Decision Decoder) may be provided subsequent to the soft decision decoding circuit 240-k.

[0022] 4 is a flowchart illustrating the operation of the soft decision circuit 23 and the error correction decoding circuit 24 in this embodiment. The soft decision circuit 23 calculates an LLR (Log Likelihood Ratio) indicating the likelihood of each bit of the data (symbol) output from the symbol demapping circuit 22 (step S100 in FIG. 4). A method for calculating the LLR (Log Likelihood Ratio) is disclosed in, for example, Patent Document 1.

[0023] The first-stage soft-decision decoding circuit 240-1 uses the LLR (Log-Likelihood Ratio) supplied from the soft-decision circuit 23 to perform error correction processing on the bit string output from the soft-decision circuit 23 and update the LLR (steps S101 and S102 in FIG. 4). The soft-decision decoding circuit 240-1 outputs the bit string after error correction and the updated LLR.

[0024] The second-stage soft-decision decoding circuit 240-2 uses the LLR (Log-Likelihood Ratio) supplied from the soft-decision decoding circuit 240-1 to perform error correction processing on the bit string output from the soft-decision decoding circuit 240-1 and update the LLR (steps S103 and S104 in FIG. 4). The soft-decision decoding circuit 240-2 outputs the bit string after error correction and the updated LLR.

[0025] The soft-decision decoding circuit 240-3 in the third stage uses the LLR (Log-Likelihood Ratio) supplied from the soft-decision decoding circuit 240-2 to perform error correction processing on the bit string output from the soft-decision decoding circuit 240-2 and update the LLR (steps S105 and S106 in FIG. 4). The soft-decision decoding circuit 240-3 outputs the bit string after error correction and the updated LLR.

[0026] The (k-1)th stage soft-decision decoding circuit 240-(k-1) uses the LLR (Log-Likelihood Ratio) supplied from the soft-decision decoding circuit 240-(k-2) to perform error correction processing on the bit string output from the soft-decision decoding circuit 240-(k-2) and update the LLR (steps S107 and S108 in FIG. 4). The soft-decision decoding circuit 240-(k-1) outputs the bit string after error correction and the updated LLR.

[0027] The k-th stage soft-decision decoding circuit 240-k uses the LLR (Log-Likelihood Ratio) supplied from the soft-decision decoding circuit 240-(k-1) to perform error correction processing on the bit string output from the soft-decision decoding circuit 240-(k-1) (step S109 in FIG. 4). The soft-decision decoding circuit 240-k outputs the bit string after error correction. Among the 2nd to kth soft decision decoding circuits 240-2 to 240-k, some soft decision decoding circuits perform error correction processing with the LLR of the first half bits set to the maximum.

[0028] The overall code arrangement and the placement of each code in oFEC are shown in Figure 5. Each code consists of 256 bits (16 bits x 16), and all 256 bits that make up one code are simultaneously subjected to error correction processing. Of the 256 bits that make up a code, the first 128 bits are arranged in a vertical column of 16 bits in a 16x16 block. The 16x16 blocks where the first 128 bits are arranged are located every 16 rows, shifted by 16 columns. Of the 256 bits that make up a code, the last 128 bits are arranged in a horizontal row of 16 bits in a 16x16 block. The 16x16 blocks where the last 128 bits are arranged are located every 16 columns in the same row. For example, the first half (bits 0-127) of the code (20,0) is arranged in column 0 (c=0) in the 16x16 block where (R,C)=(1,0)(3,1)(5,2)(7,3)(9,4)(11,5)(13,6)(15,7). The second half of the code (20,0) (bits 128-255) is located in row 0 (r=0) of the 16x16 block (R,C) = (20,0) to (20,7). Similarly, the first half of the code (20,15) (bits 0-127) is located in column 15 (c=15) of the 16x16 block (R,C) = (1,1) (3,1) (5,2) (7,3) (9,4) (11,5) (13,6) (15,7). The second half of the code (20,15) (bits 128-255) is located in row 15 (r=15) of the 16x16 block (R,C) = (20,0) to (20,7).

[0029] A more detailed explanation follows. Repeating the error correction process improves the error correction capability. Figures 6 and 7 are diagrams explaining the overlap of codes in oFEC. In Figures 6 and 7, 200a and 200b represent code A, 201a and 201b represent code P, 202a and 202b represent code Q, and 203a and 203b represent code Z. In this document, the codes arranged vertically, such as 200a, 201a, 202a, and 203a, are referred to as "vertically long 16 bits," and the codes arranged horizontally, such as 200b, 201b, 202b, and 203b, are referred to as "horizontally long 16 bits."

[0030] The first 128 bits of the eight "vertical 16 bits" of code Z in the 16x16 blocks (R,C) = (20,0), (22,1), (24,2), ..., (34,7) in Figures 6 and 7 have already undergone a first error correction as another code when the error correction process for code Z is performed, and are then subjected to a second error correction as code Z. For example, when performing error correction for code Z, the 256 bits in (20,0) have already undergone one error correction process using codes A to P. Because the bits to be corrected by the "horizontal 16 bits" of codes A to P and the "vertical 16 bits" of code Z overlap, the "vertical 16 bits" of code Z undergo two error corrections. On the other hand, when performing error correction for code Z, the eight "horizontal 16 bits" of code Z in (39,0) to (39,7) undergo their first error correction. In this way, at a certain point in time, the latter 128 bits have more residual errors than the first 128 bits because the latter 128 bits have been subjected to fewer error corrections than the first 128 bits.

[0031] In this embodiment, such a characteristic is utilized. For example, in the soft-decision decoding circuit 240-3, when LLRs (Log-Likelihood Ratios) are calculated only for the latter 128 bits of the 256 bits to be error corrected and a fixed maximum value that the LLRs (Log-Likelihood Ratios) can take is output for the first 128 bits, a circuit for calculating and storing the LLRs (Log-Likelihood Ratios) is required for the latter 128 bits, but the circuit for calculating and storing the LLRs (Log-Likelihood Ratios) is not required for the first 128 bits, and therefore it is possible to reduce the circuit size and power consumption.

[0032] For example, when the third-stage soft-decision decoding circuit 240-3 performs processing with the LLR (log-likelihood ratio) of the first 128 bits as the maximum value, the soft-decision decoding circuit 240-3 performs the same processing as the soft-decision decoding circuits 240-1 and 240-2 on data arranged as described in Figure 7, but since the LLR (log-likelihood ratio) of the first 128 bits is the maximum value, the error correction judgment results in "no error correction" and error correction processing is not performed.

[0033] As described above, in this embodiment, by utilizing the difference in residual error rate depending on the code position that occurs after multiple error corrections, only the code positions with a high residual error rate are efficiently corrected. As a result, in this embodiment, it is possible to suppress the increase in circuit size and power consumption that accompanies an increase in the number of repeated error corrections.

[0034] In this embodiment, the 256-bit code of open FEC (oFEC) is used for the explanation. However, if the error correction method generates a difference in the residual error rate due to code overlap, it is possible to reduce the power consumption and circuit size by utilizing the difference in the residual error rate. For details about oFEC, see the literature "Open ROADM MSA 3.01 W-Port Digital Specification," June 25, 2019. <https: / / view.officeapps.live.com / op / view.aspx?src=https%3A%2F%2F0201.nccdn.net%2F1_2%2F000%2F000%2F141%2Fb6c%2FOpenROADM_MSA3.01-W-Port-Digital-Specification.docx&wdOrigin=BROWSELINK> " is disclosed in

[0035] For the oFEC bit array shown in Figure 5, error correction processing is performed sequentially in increasing row order. Error correction processing is performed simultaneously on 256 bits of the same code. The code processing order is from top to bottom in Figure 5. When this embodiment is applied to oFEC, some soft-decision decoding circuits 240-X perform error correction processing on the first 128 bits of the 256 bits to be error corrected, assuming that the LLR (log-likelihood ratio) is the fixed maximum value (LLR=1) that the LLR can take, and perform error correction processing on the last 128 bits based on the LLR (log-likelihood ratio) from the previous circuit.

[0036] In this embodiment, for the sake of simplicity, the configuration is assumed to have k stages of soft-decision decoding circuits. In an actual circuit, the optimal number of error corrections is determined in consideration of the balance between power consumption and error correction performance. The number of stages of the soft-decision decoding circuits that maximize the LLR (Log-Likelihood Ratio) and provide the characteristic configuration of the present invention can also be determined in consideration of the balance between power consumption and error correction performance.

[0037] Each of the transmitting device 1 and receiving device 2 described in this embodiment can be configured with hardware logic such as an ASIC (application specific integrated circuit) or an FPGA (field-programmable gate array). Also, at least a part of each of the transmitting device 1 and receiving device 2 may be realized by a computer. In this case, the CPU of each device executes the processing described in this embodiment according to a program stored in memory. [Explanation of symbols]

[0038] 1...transmitting device, 2...receiving device, 10...error correction coding circuit, 11...symbol mapping circuit, 12...modulation circuit, 13...DA conversion circuit, 20...AD conversion circuit, 21...demodulation circuit, 22...symbol demapping circuit, 23...soft decision circuit, 24...error correction decoding circuit, 240-1 to 240-k...soft decision decoding circuits, 241-1 to 241-k...error correction unit, 242-1 to 242-(k-1)...LLR update unit.

Claims

1. In the error correction process of a digital coherent optical transmission system, A first step of calculating an LLR for each bit of a code to be error corrected; a second step of performing an error correction process using the LLR, updating the LLR based on a result of the error correction process, and outputting the LLR to a subsequent circuit; at least some of the second steps that are performed a plurality of times are determined in advance to perform error correction processing using LLRs input from a previous-stage circuit only for latter bits of a code word consisting of a multi-bit code, due to known differences in residual error rate depending on code position, and update the LLRs for the latter bits based on the results of the error correction processing and output them to a subsequent-stage circuit, and to not perform error correction processing on the first-stage bits, but to update the LLRs for the first-stage bits to a fixed maximum value that can be taken and output them to a subsequent-stage circuit, An error correction method, characterized in that in each of the second steps that are performed a plurality of times, error correction processing is not performed on the bit whose LLR input from the preceding circuit is the maximum value.

2. In the error correction process of a digital coherent optical transmission system, a soft decision circuit that calculates an LLR for each bit of the code from the coordinate shift of the received symbol and outputs the LLR to a subsequent circuit; a plurality of cascaded soft-decision decoding circuits that perform error correction processing using the LLR calculated or updated by the preceding circuit and update the LLR based on the result of the error correction processing; at least some of the soft decision decoding circuits are determined in advance to perform error correction processing using LLRs input from a previous circuit only for latter bits of a codeword consisting of a multi-bit code, due to a known difference in residual error rate depending on code position, and update the LLRs for the latter bits based on the result of the error correction processing, and output the updated LLRs to a subsequent circuit, and are determined in advance not to perform error correction processing on the first half bits, but to update the LLRs for the first half bits to a fixed maximum value that can be taken, and output the updated LLRs to a subsequent circuit, 10. An error correction circuit, wherein each of the plurality of soft-decision decoding circuits does not perform error correction processing on a bit whose LLR input from a preceding circuit has the maximum value.

3. 3. The error correction circuit according to claim 2, an error correction circuit, characterized in that a soft-decision decoding circuit at a final stage among the plurality of soft-decision decoding circuits is determined in advance to perform error correction processing on only the latter bits of a codeword consisting of a code of multiple bits using LLRs input from a circuit at a previous stage, and not to perform error correction processing on the first bits.

4. 3. The error correction circuit according to claim 2, all of the plurality of soft-decision decoding circuits are determined in advance to perform error correction processing on only latter bits of a codeword consisting of a multi-bit code using LLRs input from a previous-stage circuit, update the LLRs for the latter bits based on the results of the error correction processing, and output the updated LLRs to a subsequent-stage circuit; and the error correction circuit is determined in advance to not perform error correction processing on the first-stage bits, but update the LLRs for the first-stage bits to a fixed maximum possible value, and output the updated LLRs to a subsequent-stage circuit.

5. 3. The error correction circuit according to claim 2, an error correction circuit, characterized in that some of the soft-decision decoding circuits are determined in advance to perform error correction processing on only latter bits of a codeword consisting of a multi-bit code using LLRs input from a previous-stage circuit, update the LLRs for the latter bits based on the results of the error correction processing, and output the updated LLRs to a subsequent-stage circuit, and do not perform error correction processing on former bits, but update the LLRs for the former bits to a fixed maximum possible value, and output the updated LLRs to a subsequent-stage circuit.

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