FPGA-based approximate log-likelihood ratio calculation method, apparatus and system

Abstract

This invention relates to an FPGA-based method, apparatus, and system for calculating the approximate log-likelihood ratio (ALLR). The method includes: receiving a communication data frame via a receiver; performing a conjugate multiplication of the training sequence symbols in the communication data frame with local training sequence symbols to obtain the conjugate multiplication result; using a first FPGA circuit to obtain the signal amplitude and noise power based on the conjugate multiplication result; obtaining a calculation formula for the approximate log-likelihood ratio based on the signal amplitude and noise power using the max-log-map algorithm; and using a second FPGA circuit to obtain the approximate log-likelihood ratio result of the communication data frame based on the signal amplitude, noise power, and the calculation formula, thereby decoding the data sequence in the communication data frame according to the approximate log-likelihood ratio result. This approach fully considers the impact of signal amplitude and noise power on the ALLR, helping to improve the accuracy of the ALLR calculation and enabling the decoder to achieve optimal decoding performance.

Description

Technical Field

[0001] This invention belongs to the field of satellite communication technology, specifically relating to an approximate log-likelihood ratio calculation method, device, and system based on FPGA. Background Technology

[0002] In wireless communication employing channel coding and modulation cascades, the output of a digital demodulator can be either hard-decision decoding or soft-decision decoding. Hard-decision decoding outputs either 0 or 1 to the decoder; soft-decision decoding outputs the log-likelihood ratio to the decoder. Because soft-decision decoding fully utilizes the information in the channel output signal, it offers a 2-3 dB gain over hard-decision decoding. Therefore, wireless communication receivers frequently employ soft-decision decoding.

[0003] The output of soft-decision decoding is the Log-Likelihood Ratio (LLR), which is also the input to the next stage decoder. Its basic definition is the logarithm of the probability of a bit being 1 divided by the probability of that bit being 0. A higher probability of a bit being 1 results in a positive LLR; conversely, a lower probability of a bit being 0 results in a negative LLR. When the probability of a bit being 1 equals the probability of 0, the LLR is 0. There are two main algorithms for calculating the LLR: the log-map algorithm and the max-log-map algorithm. The log-map algorithm is the optimal soft demodulation algorithm, obtaining the most accurate soft information, but it involves logarithmic operations, which is not conducive to engineering implementation. The max-log-map algorithm is the most commonly used simplified version of the log-map algorithm. It uses a maximal function to approximate the logarithmic function, thereby reducing complexity. The result obtained using this method is called the Approximate Log-Likelihood Ratio (ALLR).

[0004] The accuracy of the approximate log-likelihood ratio (ALLR) directly affects the performance of the decoder. The more accurate the ALLR, the better the noise immunity of the decoder. As a real-time communication receiver platform, FPGA is a topic worthy of study in terms of how to calculate ALLR simply and accurately. The literature (Zhang Hongshuang, Research on Soft Demodulation in LTE System [J], Electronic Testing, June 2010, No. 6) and (Gao Shihhan, Xiong Tao, Yang Bishui, A 16APSK Soft Demodulation Method for Satellite Communication [J], Radio Communication Technology, 2021, 47(3):4) have studied the amplitude in the max-log-map algorithm and obtained the amplitude-related ALLR results; however, the max-log-map algorithm is also related to noise power. Calculating ALLR without using noise power will introduce a large error and reduce the performance of the decoder. Summary of the Invention

[0005] This invention provides an FPGA-based approximate log-likelihood ratio calculation method, apparatus, and system, aiming to solve the problem that the calculation of ALLR in the prior art introduces large errors, leading to a decrease in decoder performance.

[0006] The technical solution of this invention relates to an FPGA-based approximate log-likelihood ratio calculation method, comprising: receiving a communication data frame through a receiver, and performing conjugate multiplication of the training sequence symbols in the communication data frame with the local training sequence symbols to obtain the conjugate multiplication result; applying a first FPGA circuit to obtain the signal amplitude and noise power based on the conjugate multiplication result; obtaining the calculation formula for the approximate log-likelihood ratio based on the signal amplitude and the noise power using the max-log-map algorithm; applying a second FPGA circuit to obtain the approximate log-likelihood ratio result of the communication data frame based on the signal amplitude, the noise power, and the calculation formula, so as to decode the data sequence in the communication data frame based on the approximate log-likelihood ratio result.

[0007] Further, the training sequence symbols in the communication data frame are multiplied by the local training sequence symbols to obtain the conjugate multiplication result, including: mapping the local training sequence according to the transmitted training sequence constellation diagram, and taking the conjugate of the mapping result; performing time and frequency synchronization processing on the communication data frame through the receiver to obtain the training sequence symbols in the communication data frame; and performing a complex multiplication operation on the training sequence symbols and the conjugate local training sequence symbols to obtain the conjugate multiplication result.

[0008] Further, performing a complex multiplication operation between the training sequence symbol and the conjugate local training sequence symbol to obtain a conjugate multiplication result includes: normalizing the conjugate local training sequence symbol; and performing a complex multiplication operation between the training sequence symbol and the normalized local training sequence symbol to obtain a conjugate multiplication result.

[0009] Furthermore, the first FPGA circuit includes a first summation circuit, a first right-shift circuit connected to the first summation circuit, a square calculation circuit, a second summation circuit connected to the square calculation circuit, and a second right-shift circuit connected to the second summation circuit. The step of obtaining the signal amplitude and noise power using the first FPGA circuit based on the conjugate multiplication result includes: determining a preset number based on the number of symbols in the training sequence; summing the real part of the conjugate multiplication result using the first summation circuit, and then applying the preset number of bits to the first right-shift circuit to obtain the signal amplitude; squaring the imaginary part of the conjugate multiplication result using the square calculation circuit, summing the square calculation result using the second summation circuit, and then applying the preset number of bits to the second right-shift circuit to obtain the noise power.

[0010] Furthermore, determining the preset quantity based on the number of training sequence symbols includes: rounding up the number of training sequence symbols to determine the smallest power of 2 integer; and determining the preset quantity as the power of 2 corresponding to the power integer.

[0011] Furthermore, the second FPGA circuit includes a division circuit, a first multiplication circuit and a second multiplication circuit connected to the division circuit, and a first left shift circuit and a second left shift circuit connected to the first multiplication circuit and the second multiplication circuit, respectively. The step of obtaining an approximate log-likelihood ratio result using the second FPGA circuit based on the signal amplitude, the noise power, and the calculation formula includes: calculating the ratio of the signal amplitude to the noise power using the division circuit; calculating a first product of the ratio and the real part of the data sequence in the communication data frame using the first multiplication circuit; calculating a second product of the ratio and the imaginary part of the data sequence using the second multiplication circuit; and shifting the first product and the second product left by 2 bits using the first left shift circuit and the second left shift circuit, respectively, to obtain the approximate log-likelihood ratio result.

[0012] The technical solution of the present invention also relates to an FPGA-based approximate log-likelihood ratio calculation device, comprising: a conjugate multiplication unit, used to receive a communication data frame through a receiver and perform conjugate multiplication of the training sequence symbols in the communication data frame with the local training sequence symbols to obtain a conjugate multiplication result; a first FPGA circuit, used to obtain the signal amplitude and noise power according to the conjugate multiplication result; a relational determination unit, used to obtain a calculation relational formula for the approximate log-likelihood ratio based on the signal amplitude and the noise power using the max-log-map algorithm; and a second FPGA circuit, used to obtain the approximate log-likelihood ratio result according to the calculation relational formula, so as to decode the data sequence in the communication data frame according to the approximate log-likelihood ratio result.

[0013] The technical solution of the present invention also relates to an FPGA-based decoding system, comprising: a decoder and the aforementioned FPGA-based approximate log-likelihood ratio calculation device connected to the decoder, wherein the FPGA-based approximate log-likelihood ratio calculation device is used to obtain the approximate log-likelihood ratio result of a received communication data frame, and the decoder is used to decode the data sequence in the communication data frame according to the approximate log-likelihood ratio result.

[0014] The present invention also relates to an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the aforementioned method.

[0015] The present invention also relates to a computer storage medium storing at least one executable instruction, which causes a processor to execute the aforementioned method.

[0016] The beneficial effects of this invention are as follows: This invention provides an FPGA-based approximate log-likelihood ratio (ALLR) calculation method, apparatus, and system. The method involves receiving a communication data frame via a receiver, performing a conjugate multiplication of the training sequence symbols in the communication data frame with the local training sequence symbols to obtain the conjugate multiplication result; using a first FPGA circuit to obtain the signal amplitude and noise power based on the conjugate multiplication result; obtaining the approximate log-likelihood ratio calculation formula based on the signal amplitude and noise power using the max-log-map algorithm; and using a second FPGA circuit to obtain the approximate log-likelihood ratio result of the communication data frame based on the signal amplitude, noise power, and the calculation formula. This allows for the decoding of the data sequence in the communication data frame based on the approximate log-likelihood ratio result. This approach fully considers the impact of signal amplitude and noise power on ALLR, simplifies the calculation process, improves accuracy, and enables the decoder to achieve optimal decoding performance. It is of great significance for improving the bit error rate (BER) of wireless communication receivers and has significant engineering value. Attached Figure Description

[0017] Figure 1 A flowchart illustrating the approximate log-likelihood ratio calculation method based on FPGA according to an embodiment of the present invention is shown.

[0018] Figure 2 A schematic diagram of the data frame structure according to an embodiment of the present invention is shown;

[0019] Figure 3 A schematic diagram of a BPSK modulation constellation according to an embodiment of the present invention is shown;

[0020] Figure 4 A schematic diagram of a QPSK modulation constellation according to an embodiment of the present invention is shown;

[0021] Figure 5 A schematic diagram of conjugate multiplication according to an embodiment of the present invention is shown;

[0022] Figure 6 A schematic diagram of the structure of the first FPGA circuit according to an embodiment of the present invention is shown;

[0023] Figure 7 This diagram illustrates the location of data symbols in a communication data frame according to an embodiment of the present invention.

[0024] Figure 8 A schematic diagram of the structure of the second FPGA circuit according to an embodiment of the present invention is shown;

[0025] Figure 9A schematic diagram of the timing synchronization device of a satellite communication system according to another embodiment of the present invention is shown;

[0026] Figure 10 A schematic diagram of an electronic device according to an embodiment of the present invention is shown. Detailed Implementation

[0027] The following will provide a clear and complete description of the concept, specific structure, and technical effects of the present invention in conjunction with the embodiments and accompanying drawings, so as to fully understand the purpose, solution, and effects of the present invention.

[0028] It should be noted that, unless otherwise specified, when a feature is referred to as "fixed" or "connected" to another feature, it can be directly fixed or connected to the other feature, or indirectly fixed or connected to the other feature. The singular forms "a," "described," and "the" used herein are also intended to include the plural forms, unless the context clearly indicates otherwise. Furthermore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and not for limiting the invention. The term "and / or" as used herein includes any combination of one or more of the associated listed items.

[0029] It should be understood that although the terms first, second, third, etc., may be used in this disclosure to describe various elements, these elements should not be limited to these terms. These terms are only used to distinguish elements of the same type from one another. For example, a first element may also be referred to as a second element without departing from the scope of this disclosure, and similarly, a second element may also be referred to as a first element. Any and all instances or exemplary language (“e.g.,” “such as,” etc.) provided herein are intended only to better illustrate embodiments of the invention and, unless otherwise required, do not impose a limitation on the scope of the invention.

[0030] Since the accuracy of the approximate log-likelihood ratio (ALLR) directly affects the decoding performance of the decoder, how to implement a simple and accurate ALLR in an FPGA is an important research problem. This invention performs conjugate multiplication of the training sequence symbols received by the receiver with the local training sequence symbols, sums the real parts of the multiplication results, and takes the average as the amplitude of the received signal; it also squares the imaginary parts of the multiplication results, sums them, and takes twice the average as the noise power of the received signal; the transmitted data symbol constellation diagram is segmented according to bit positions, and after receiving a data symbol, the max-log-map algorithm is used to derive the ALLR expression for each bit in the corresponding symbol; then, the amplitude and noise power in the ALLR expression are replaced with the amplitude and noise power calculated from the training sequence to obtain the ALLR result required by the decoder. This ALLR result is then input into the decoder for decoding. This method can be implemented in an FPGA with fewer resources, has a simple computation process, and produces accurate results, enabling the decoder to achieve optimal decoding performance and improving the bit error rate of the wireless communication receiver, thus possessing significant engineering value.

[0031] In some embodiments, the present invention provides an approximate log-likelihood ratio calculation method based on FPGA, applied to servers, such as... Figure 1 As shown, it includes at least the following steps:

[0032] S11: Receive communication data frames through a receiver, and perform conjugate multiplication between the training sequence symbols in the communication data frames and the local training sequence symbols to obtain the conjugate multiplication result.

[0033] In wireless communication systems, the structure of transmitted data frames is generally as follows: Figure 2 As shown, its header is a training sequence of Binary Phase Shift Keying (BPSK) modulation used for time and frequency synchronization and channel estimation, followed by the data sequence of Quadrature Phase Shift Keying (QPSK) modulation. The constellation diagrams for BPSK and QPSK modulation are shown below. Figure 3 and Figure 4 As shown, b0 and b1 represent the bit sequences before mapping. Wireless communication systems typically use training sequences for receiver time-frequency synchronization and channel estimation; these are a segment of known symbols preceding the transmitted data frame.

[0034] In this embodiment of the application, when performing conjugate multiplication, optionally, the local training sequence is first mapped according to the transmitted training sequence constellation diagram, and the mapping result is conjugate. Specifically, the symbols of the local training sequence are mapped according to the BPSK modulation constellation diagram, and the mapped symbols are conjugate. The conjugate result is represented by p(n), as shown in relation (1):

[0035]

[0036] In the formula, n represents the symbol number after the training sequence is mapped, and b0 represents the training sequence bits.

[0037] Then, the receiver performs time and frequency synchronization processing on the communication data frame to obtain the training sequence symbols in the communication data frame. After the receiver completes the time and frequency synchronization processing, it can obtain the received training sequence symbols r. p (n) and the received data sequence symbol r s (n), whose expressions are shown in relation (2) and relation (3) respectively:

[0038] r p (n)=i(n)+jq(n) (2)

[0039] r s (n)=x(n)+jy(n) (3)

[0040] Where n represents the received symbol number, in relation (2) the real part i(n) represents the in-phase component of the received training sequence symbol, the imaginary part q(n) represents the quadrature component of the received training sequence symbol, and in relation (3) the real part x(n) represents the in-phase component of the received data sequence symbol, and the imaginary part y(n) represents the quadrature component of the received data sequence symbol.

[0041] Finally, the training sequence symbols are multiplied by complex numbers with the conjugate local training sequence symbols to obtain the conjugate multiplication result. Specifically, the conjugate local training sequence symbols are first normalized; then, the training sequence symbols are multiplied by complex numbers with the normalized local training sequence symbols to obtain the conjugate multiplication result.

[0042] Will receive training sequence symbol r p Multiplying (n) by the local training sequence symbol p(n) yields the conjugate multiplication result, denoted by R(n), as shown in relation (4):

[0043] R(n) = r p (n)·p(n) (4)

[0044] In FPGA implementation, directly using relation (4) for multiplication would require a complex multiplier. To save resources, the local training sequence symbol p(n) is normalized, that is, the real and imaginary parts of p(n) are multiplied by... (represented by c, i.e.) Adjust the amplitude value of p(n) in relation (1) to 1, as shown in relation (5):

[0045]

[0046] Thus, the multiplication operation of relation (4) can be converted into an operation containing only adders and subtractors, such as Figure 5 The expression for R(n) is shown in the figure. Figure 5 It also shows that the FPGA internal implementation can select the output R(n) based on the condition p(n). That is, if p(n) = 1 - j1, then R(n) = [i(n) + q(n)] + j[q(n) - i(n)]. If p(n) = -1 + j1, then R(n) = [-i(n) - q(n)] + j[-q(n) + i(n)].

[0047] S12: The first FPGA circuit is used to obtain the signal amplitude and noise power based on the conjugate multiplication result.

[0048] go through Figure 5 After the processing shown, the conjugate multiplication result R(n) has had its modulation phase information removed. At this point, the amplitude A and noise power N0 can be calculated. The signal amplitude A is calculated by summing the real parts of R(n) and taking the average value. The noise power N0 is calculated by squaring the imaginary parts of R(n), summing them, and finally taking the average value, as shown in equations (6) and (7).

[0049]

[0050] Where N is the number of symbols in the training sequence.

[0051] When implementing equations (6) and (7) on an FPGA, a divider is needed for both amplitude A and noise power N0, for a total of two dividers, which consumes a significant amount of FPGA resources. Therefore, to save FPGA resources, the division operation can be converted into a right shift operation.

[0052] In the embodiments of this application, see Figure 6The first FPGA circuit used to calculate the signal amplitude A and noise power N0 includes a first accumulator circuit 101, a first right-shift circuit 102 connected to the first accumulator circuit 101, a square calculation circuit 103, a second accumulator circuit 104 connected to the square calculation circuit 103, and a second right-shift circuit 105 connected to the second accumulator circuit 104. In step S12, optionally, a preset quantity is first determined based on the number of symbols in the training sequence. The number of symbols in the training sequence is rounded up to determine the smallest power of 2 integer; the preset quantity is determined to be the power of 2 corresponding to the power integer. That is, N is replaced by a smallest power of 2 integer M greater than N, where M = 2. m and ( (This indicates an up-rounding operation), thus converting division by N into a right shift of m bits.

[0053] Then, the real part of the conjugate multiplication result is summed by the first accumulation and summing circuit 101, and the signal amplitude is obtained by applying a preset number of bits to the first right shift circuit 102; the imaginary part of the conjugate multiplication result is squared by the square calculation circuit 103, the square calculation result is summed by the second accumulation and summing circuit 104, and the noise power is obtained by applying a preset number of bits to the second right shift circuit 105.

[0054] S13: Based on the signal amplitude and the noise power, obtain the approximate log-likelihood ratio calculation formula using the max-log-map algorithm.

[0055] After calculating the signal amplitude A and noise power N0, the ALLR expression for the bits contained in the received data symbol is derived.

[0056] The ALLR expression obtained using the max-log-map algorithm is shown in relation (8):

[0057]

[0058] Where L(b) is the log-likelihood ratio of bit b, δ 2 This is the noise power. S0 is the set of constellation points where bit b is determined to be 0, S1 is the set of constellation points where bit b is determined to be 1, and s x It is the in-phase component of the constellation point, s y y is the orthogonal component of the constellation point, x is the in-phase component of the received data symbol, and y is the orthogonal component of the received data symbol.

[0059] S14: Based on the signal amplitude, the noise power, and the calculation formula, the second FPGA circuit is used to obtain the approximate log-likelihood ratio result of the communication data frame, so as to decode the data sequence in the communication data frame according to the approximate log-likelihood ratio result.

[0060] Figure 2 The data sequence in the display data frame is QPSK modulated. Each data symbol in QPSK modulation contains 2 bits b1b0, such as... Figure 4 As shown. When the received data symbol x+jy is located at Figure 7 At the position shown, derive the ALLR expression for bit b1b0 contained in the QPSK modulation symbol.

[0061] First, derive the ALLR expression for b0. Observe... Figure 7 The relationship between the constellation points and the received data symbols is used to determine the coordinates s of the constellation point that takes the minimum value of set S0 in relation (8). 0x +js 0y The coordinates of the constellation point s that take the minimum value of set S1. 1x +js 1y As shown in relation (9):

[0062]

[0063] Because the received QPSK modulation symbol contains the transmit gain, the signal amplitude is A. The signal amplitude A is introduced into s. 0x +js 0y and s 1x +js 1y Then relation (9) is expressed as relation (10):

[0064]

[0065] Substituting relation (10), the received data symbol x+jy, and the noise power N0 into relation (8), we can obtain the ALLR expression for the bit b0 contained in the received data symbol:

[0066]

[0067] When the received data symbol is located in other positions, the same processing method is used, and the resulting expression relation (11) is the same.

[0068] When calculating the amplitude A and noise power N0, c and M factors are introduced. These two factors are eliminated in relation (11) to obtain the final expression of ALLR for bit b0, as shown in relation (12):

[0069]

[0070] The process of solving the ALLR expression for bit b1 in the received data symbol is similar to that for bit b0, and its ALLR expression is shown in relation (13):

[0071]

[0072] Based on the ALLR expressions of relations (12) and (13), the ALLR calculation of bits b0 and b1 can be implemented in the FPGA. In order to avoid introducing large rounding errors when calculating the final ALLR, a divider and two multipliers are used to complete the ALLR result calculation when implementing the calculation of relations (12) and (13).

[0073] In the embodiments of this application, see Figure 8 The second FPGA circuit includes a division circuit 201, a first multiplication circuit 202 and a second multiplication circuit 203 connected to the division circuit 201, and a first left shift circuit 204 and a second left shift circuit 205 connected to the first multiplication circuit 201 and the second multiplication circuit 202, respectively. In step S14, optionally, the division circuit 201 is used to calculate the ratio of the signal amplitude to the noise power; the first multiplication circuit 202 calculates a first product of the ratio with the real part of the data sequence in the communication data frame; the second multiplication circuit 203 calculates a second product of the ratio with the imaginary part of the data sequence; and the first left shift circuit 204 and the second left shift circuit 205 shift the first product and the second product left by 2 bits respectively to obtain an approximate log-likelihood ratio result.

[0074] In an embodiment of the present invention, according to Figure 8 The second FPGA circuit shown calculates the ALLR result of bits b0 and b1 in the received data symbol, and then inputs the result into the decoder for decoding to obtain the original transmitted information bits b0 and b1.

[0075] The ALLR calculation method based on FPGA in this invention consists of four main processing steps. First, conjugate multiplication is performed: the local training sequence is mapped according to the transmitted training sequence constellation diagram, and the mapping result is conjugate and saved. After the receiver completes signal synchronization processing, it obtains the received training sequence symbols, and then performs a complex multiplication operation with the locally saved training sequence symbols to obtain the conjugate multiplication result. Second, signal amplitude and noise power are calculated: the real parts of the conjugate multiplication result are summed and the average value is calculated to obtain the signal amplitude; the imaginary parts of the conjugate multiplication result are squared, summed, and the average value is calculated, with twice the sum taken as the noise power. Third, the ALLR expression for each bit in the received data symbol is derived according to the max-log-map algorithm. Finally, the calculated signal amplitude and noise power are substituted into the ALLR expression to obtain the ALLR result required by the decoder. The ALLR result is then input into the decoder for accurate decoding. This method fully considers the influence of signal amplitude and noise power on ALLR. The calculation process is simple and the result is accurate. It can enable the decoder to obtain the best decoding performance, which is of great significance for improving the bit error rate index of wireless communication receivers and has important engineering value.

[0076] In summary, this embodiment of the invention receives communication data frames via a receiver, performs conjugate multiplication of the training sequence symbols in the communication data frames with the local training sequence symbols to obtain the conjugate multiplication result, uses a first FPGA circuit to obtain the signal amplitude and noise power based on the conjugate multiplication result, obtains an approximate log-likelihood ratio calculation formula based on the signal amplitude and noise power using the max-log-map algorithm, and uses a second FPGA circuit to obtain the approximate log-likelihood ratio result of the communication data frames based on the signal amplitude, noise power, and the calculation formula. This allows for the decoding of the data sequence in the communication data frames based on the approximate log-likelihood ratio result. This approach fully considers the impact of signal amplitude and noise power on ALLR, helps improve the accuracy of ALLR calculation, and enables the decoder to achieve optimal decoding performance.

[0077] Based on the same concept, embodiments of the present invention also provide an approximate log-likelihood ratio calculation device based on FPGA, applied to servers, such as... Figure 9 As shown, it includes: a conjugate multiplication unit, a first FPGA circuit, a relation determination unit, and a second FPGA circuit. Among them,

[0078] The conjugate multiplication unit is used to receive communication data frames through a receiver, and perform conjugate multiplication between the training sequence symbols in the communication data frames and the local training sequence symbols to obtain the conjugate multiplication result;

[0079] The first FPGA circuit is used to obtain the signal amplitude and noise power based on the conjugate multiplication result;

[0080] The relation determination unit is used to obtain the approximate log-likelihood ratio calculation relation based on the signal amplitude and the noise power using the max-log-map algorithm;

[0081] The second FPGA circuit is used to obtain an approximate log-likelihood ratio result based on the calculation formula, and to decode the data sequence in the communication data frame based on the approximate log-likelihood ratio result.

[0082] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing the embodiments of the present invention, the functions of each module can be implemented in one or more software and / or hardware.

[0083] The apparatus of the above embodiments is applied to the corresponding method in the previous embodiment and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0084] Based on the same concept, embodiments of the present invention also provide an FPGA-based decoding system, including: a decoder and the aforementioned FPGA-based approximate log-likelihood ratio calculation device connected to the decoder, wherein the FPGA-based approximate log-likelihood ratio calculation device is used to obtain the approximate log-likelihood ratio result of a received communication data frame, and the decoder is used to decode the data sequence in the communication data frame according to the approximate log-likelihood ratio result.

[0085] Based on the same inventive concept, embodiments of the present invention also provide an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the method described in any of the above embodiments.

[0086] This invention provides a non-volatile computer storage medium storing at least one executable instruction that can execute the method described in any of the above embodiments.

[0087] Figure 10 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1001, a memory 1002, an input / output interface 1003, a communication interface 1004, and a bus 1005. The processor 1001, memory 1002, input / output interface 1003, and communication interface 1004 are interconnected internally via the bus 1005.

[0088] The processor 1001 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present invention.

[0089] The memory 1002 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1002 can store the operating system and other application programs. When the technical solution provided by the method embodiment of the present invention is implemented by software or firmware, the relevant program code is stored in the memory 1002 and is called and executed by the processor 1001.

[0090] The input / output interface 1003 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0091] The communication interface 1004 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0092] Bus 1005 includes a pathway for transmitting information between various components of the device (e.g., processor 1001, memory 1002, input / output interface 1003, and communication interface 1004).

[0093] It should be noted that although the above-described device only shows the processor 1001, memory 1002, input / output interface 1003, communication interface 1004, and bus 1005, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of the present invention, and need not include all the components shown in the figures.

[0094] It should be understood that the method steps in the embodiments of the present invention can be implemented or carried out by computer hardware, a combination of hardware and software, or by computer instructions stored in a non-transitory computer-readable storage medium. The method can use standard programming techniques. Each program can be implemented in a high-level procedural or object-oriented programming language to communicate with the computer system. However, if necessary, the program can be implemented in assembly or machine language. In any case, the language can be a compiled or interpreted language. Furthermore, for this purpose, the program can run on a programmed application-specific integrated circuit (ASIC).

[0095] Furthermore, the procedures described herein may be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by the context. The procedures described herein (or variations and / or combinations thereof) may be executed under the control of one or more computer systems configured with executable instructions, and may be implemented by hardware or a combination thereof as code (e.g., executable instructions, one or more computer programs, or one or more applications) that commonly executes on one or more processors. The computer program comprises a plurality of instructions executable by one or more processors.

[0096] Furthermore, the method can be implemented and is operatively connected to any suitable type of computing platform, including but not limited to personal computers, minicomputers, mainframes, workstations, networked or distributed computing environments, standalone or integrated computer platforms, or communication with charged particle tools or other imaging devices, etc. Aspects of the invention can be implemented as machine-readable code stored on a non-transitory storage medium or device, whether removable or integrated into a computing platform, such as a hard disk, optical read and / or write storage medium, RAM, ROM, etc., such that it is readable by a programmable computer, and when the storage medium or device is read by the computer, it can be used to configure and operate the computer to perform the processes described herein. Furthermore, the machine-readable code, or portions thereof, can be transmitted via wired or wireless networks. The invention described herein includes these and other different types of non-transitory computer-readable storage media when such media comprises instructions or programs that implement the steps described above in conjunction with a microprocessor or other data processor. When programmed according to the methods and techniques described in the invention, the invention may also include the computer itself.

[0097] A computer program can be applied to input data to perform the functions described herein, thereby transforming the input data to generate output data stored in non-volatile memory. The output information can also be applied to one or more output devices, such as a display. In a preferred embodiment of the invention, the transformed data represents physical and tangible objects, including specific visual depictions of physical and tangible objects generated on the display.

[0098] The above description is merely a preferred embodiment of the present invention. The present invention is not limited to the above-described embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, as long as they achieve the technical effects of the present invention by the same means, should be included within the scope of protection of the present invention. Within the scope of protection of the present invention, the technical solutions and / or implementation methods can have various modifications and variations.

Claims

1. A method for calculating the approximate log-likelihood ratio based on FPGA, characterized in that, The approximate log-likelihood ratio calculation method includes: The receiver receives communication data frames and performs conjugate multiplication between the training sequence symbols in the communication data frames and the local training sequence symbols to obtain the conjugate multiplication result. The first FPGA circuit is used to obtain the signal amplitude and noise power based on the conjugate multiplication result. The approximate log-likelihood ratio is calculated based on the signal amplitude and the noise power using the max-log-map algorithm. The second FPGA circuit is used to obtain the approximate log-likelihood ratio of the communication data frame based on the signal amplitude, the noise power, and the calculation formula, so as to decode the data sequence in the communication data frame based on the approximate log-likelihood ratio. The step of performing conjugate multiplication between the training sequence symbols in the communication data frame and the local training sequence symbols to obtain the conjugate multiplication result includes: Map the local training sequence according to the constellation diagram of the sent training sequence, and take the conjugate of the mapping result; The receiver performs time and frequency synchronization processing on the communication data frame to obtain the training sequence symbols in the communication data frame. Perform a complex multiplication operation between the training sequence symbol and the local training sequence symbol after taking the conjugate, to obtain the conjugate multiplication result; The first FPGA circuit includes a first summation circuit, a first right-shift circuit connected to the first summation circuit, a square calculation circuit, a second summation circuit connected to the square calculation circuit, and a second right-shift circuit connected to the second summation circuit. The step of applying the first FPGA circuit to obtain the signal amplitude and noise power based on the conjugate multiplication result includes: The preset quantity is determined based on the number of symbols in the training sequence; The real part of the conjugate multiplication result is accumulated and summed by the first accumulation and summing circuit, and then the signal amplitude is obtained by applying the first right shift circuit with a preset number of bits. The imaginary part of the conjugate multiplication result is squared by the square calculation circuit, the square calculation result is summed by the second accumulation and summation circuit, and then the noise power is obtained by applying the second right shift circuit for a preset number of bits. The second FPGA circuit includes a division circuit, a first multiplication circuit and a second multiplication circuit connected to the division circuit, and a first left shift circuit and a second left shift circuit connected to the first multiplication circuit and the second multiplication circuit, respectively. The step of applying the second FPGA circuit to obtain an approximate log-likelihood ratio result based on the signal amplitude, the noise power, and the calculated relationship includes: The division circuit is used to calculate the ratio of the signal amplitude to the noise power; The first multiplication circuit calculates the first product of the ratio and the real part of the data sequence in the communication data frame, and the second multiplication circuit calculates the second product of the ratio and the imaginary part of the data sequence. By shifting the first product and the second product to the left by 2 bits using the first left shift circuit and the second left shift circuit respectively, an approximate log-likelihood ratio result is obtained.

2. The method according to claim 1, characterized in that, The step of performing a complex multiplication operation between the training sequence symbol and the conjugate local training sequence symbol to obtain the conjugate multiplication result includes: Normalize the symbols of the local training sequence after taking the conjugation. The training sequence symbols are multiplied by a complex number with the normalized local training sequence symbols to obtain the conjugate multiplication result.

3. The method according to claim 1, characterized in that, The step of determining the preset quantity based on the number of symbols in the training sequence includes: Round up the number of symbols in the training sequence to determine the smallest power of 2 integer; The preset quantity is determined to be the power of 2 corresponding to the integer power.

4. An approximate log-likelihood ratio calculation device based on FPGA, characterized in that, include: The conjugate multiplication unit is used to receive communication data frames through a receiver, and perform conjugate multiplication between the training sequence symbols in the communication data frames and the local training sequence symbols to obtain the conjugate multiplication result; The first FPGA circuit is used to obtain the signal amplitude and noise power based on the conjugate multiplication result; The relation determination unit is used to obtain the approximate log-likelihood ratio calculation relation based on the signal amplitude and the noise power using the max-log-map algorithm; The second FPGA circuit is used to obtain an approximate log-likelihood ratio result according to the calculation formula, so as to decode the data sequence in the communication data frame according to the approximate log-likelihood ratio result; The step of performing conjugate multiplication between the training sequence symbols in the communication data frame and the local training sequence symbols to obtain the conjugate multiplication result includes: Map the local training sequence according to the constellation diagram of the sent training sequence, and take the conjugate of the mapping result; The receiver performs time and frequency synchronization processing on the communication data frame to obtain the training sequence symbols in the communication data frame. Perform a complex multiplication operation between the training sequence symbol and the local training sequence symbol after taking the conjugate, to obtain the conjugate multiplication result; The first FPGA circuit includes a first summation circuit, a first right-shift circuit connected to the first summation circuit, a square calculation circuit, a second summation circuit connected to the square calculation circuit, and a second right-shift circuit connected to the second summation circuit. The step of applying the first FPGA circuit to obtain the signal amplitude and noise power based on the conjugate multiplication result includes: The preset quantity is determined based on the number of symbols in the training sequence; The real part of the conjugate multiplication result is accumulated and summed by the first accumulation and summing circuit, and then the signal amplitude is obtained by applying the first right shift circuit with a preset number of bits. The imaginary part of the conjugate multiplication result is squared by the square calculation circuit, the square calculation result is summed by the second accumulation and summation circuit, and then the noise power is obtained by applying the second right shift circuit for a preset number of bits. The second FPGA circuit includes a division circuit, a first multiplication circuit and a second multiplication circuit connected to the division circuit, and a first left shift circuit and a second left shift circuit connected to the first multiplication circuit and the second multiplication circuit, respectively. The step of applying the second FPGA circuit to obtain an approximate log-likelihood ratio result based on the signal amplitude, the noise power, and the calculated relationship includes: The division circuit is used to calculate the ratio of the signal amplitude to the noise power; The first multiplication circuit calculates the first product of the ratio and the real part of the data sequence in the communication data frame, and the second multiplication circuit calculates the second product of the ratio and the imaginary part of the data sequence. By shifting the first product and the second product to the left by 2 bits using the first left shift circuit and the second left shift circuit respectively, an approximate log-likelihood ratio result is obtained.

5. An FPGA-based decoding system, characterized in that, include: The decoder and the FPGA-based approximate log-likelihood ratio calculation device as described in claim 4, connected to the decoder, wherein the FPGA-based approximate log-likelihood ratio calculation device is used to obtain the approximate log-likelihood ratio result of the received communication data frame, and the decoder is used to decode the data sequence in the communication data frame according to the approximate log-likelihood ratio result.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1-3.

7. A computer storage medium, characterized in that, The storage medium stores at least one executable instruction that causes the processor to perform the method as described in any one of claims 1-3.

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