Decoding circuit, reception device, and decoding method

Abstract

This decoding circuit comprises: a likelihood calculation unit that, on the basis of a decoding metric obtained by demodulating transmission data transmitted from a transmission device, calculates log-likelihood ratios in first to dth lanes, the likelihood calculation unit calculating, as the log-likelihood ratios in second to dth lanes, a log-likelihood ratio for a case in which the bit of the decoded first lane is 0 and a log-likelihood ratio for a case in which the bit of the decoded first lane is 1; a first decoding unit that, on the basis of the log-likelihood ratio of the second to dth lanes, calculates bits of the second to dth lanes for a case in which the bit of the decoded first lane is 0 and a case in which the bit of the decoded first lane is 1; a second decoding unit that calculates the bit of the first lane on the basis of the log-likelihood ratio in the first lane; and a selector that selects the calculated bits of the second to dth lanes on the basis of the calculated bit of the first lane.

Description

Decoding circuit, receiving device, and decoding method

[0001] The present invention relates to a decoding circuit, a receiving device, and a decoding method.

[0002] Forward Error Correction (FEC), a bit error correction method for achieving highly reliable communication in optical transmission, requires careful consideration of the trade-off between power and decoding characteristics. As an FEC method, channel-polarized multilevel coding (CP-MLC) has been proposed, which enables a reduction in FEC decoding computation amount that is independent of modulation level and code (see Non-Patent Document 1). CP-MLC converts the communication channel into a total of d subchannels: one low-reliability subchannel and (d-1) high-reliability subchannels. By applying soft-decision (SD) FEC (SD-FEC) to the low-reliability subchannel, the computation amount is reduced.

[0003] Kakizaki, Takeshi, et al. "Low-complexity channel polarized multilevel coding for modulation-format-independent forward error correction." 2021 European Conference on Optical Communication (ECOC). IEEE, 2021 (2021).

[0004] In the (d-1) lanes that bypass the SD-FEC, it is necessary to maintain the log-likelihood ratio (LLR) for each lane. Therefore, the increased circuit size and power consumption when implementing the signal processing circuit become a problem.

[0005] In view of the above circumstances, the present invention aims to provide a technology that enables the realization of a decoding circuit with low power consumption.

[0006] One aspect of the present invention is a decoding circuit comprising: a likelihood calculation unit that calculates log-likelihood ratios in lanes 1 to d based on a decoding metric obtained by demodulating transmitted data transmitted from a transmitting device, the likelihood calculation unit that calculates the log-likelihood ratios in lanes 2 to d when the bit of the decoded first lane is 0 and when it is 1; a first decoding unit that calculates the bits of lanes 2 to d in the cases where the bit of the decoded first lane is 0 and 1 based on the log-likelihood ratios in lanes 2 to d; a second decoding unit that calculates the bit of the first lane based on the log-likelihood ratio in the first lane; and a selector that selects the calculated bits of lanes 2 to d based on the calculated bits of the first lane.

[0007] One aspect of the present invention is a likelihood calculation unit that calculates log-likelihood ratios in lanes 1 to d based on a decoding metric obtained by demodulating transmitted data transmitted from a transmitting device, comprising: a likelihood calculation step of calculating the log-likelihood ratios in lanes 2 to d when the bit of the decoded first lane is 0 and when it is 1; a first decoding step of calculating the bits of lanes 2 to d in the cases where the bit of the decoded first lane is 0 and 1 based on the log-likelihood ratios in lanes 2 to d; a second decoding step of calculating the bit of the first lane based on the log-likelihood ratio of the first lane; and a selection step of selecting the calculated bits of lanes 2 to d based on the calculated bits of the first lane.

[0008] This invention makes it possible to realize a decoding circuit with low power consumption.

[0009] This figure shows an example configuration of the optical communication system 100 according to this embodiment. This is a flowchart showing the operation of the decoding circuit 22 according to this embodiment.

[0010] Embodiments of the present invention will be described in detail below with reference to the drawings. Figure 1 is a diagram showing an example configuration of the optical communication system 100 according to this embodiment. The optical communication system 100 comprises a transmitting device 1 and a receiving device 2.

[0011] Transmitter 1 and receiver 2 are connected via a communication channel. The communication channel is used to transmit optical signals, such as an optical fiber. Transmitter 1 transmits data to be transmitted (hereinafter referred to as "transmitted data") to receiver 2. Transmitter 1 encodes the original data to be transmitted using HD-FEC (Hard-Decision FEC) technology, divides the encoded data into a predetermined number of divisions d (where d is an integer of 2 or more), encodes the divided data using error correction codes, converts the divided data into a series of data in one lane by parallel-serial conversion, assigns gray labeling to the series of data in one lane to generate the transmitted data, and transmits the transmitted data to receiver 2.

[0012] The receiving device 2 comprises a receiving unit 20, a symbol demapper 21, and a decoding circuit 22.

[0013] The receiving unit 20 receives the transmission data sent from the transmitting device 1 via the communication channel.

[0014] The symbol demapper 21 demodulates the transmitted data received by the receiving unit 20 using a demodulation method corresponding to the modulation scheme and obtains a decoding metric. The decoding metric is, for example, LLR.

[0015] The decoding circuit 22 includes a likelihood calculation unit 220, a first decoding unit 221, a second decoding unit 222, a selector 223, a d:1 converter 224, and an HD-FEC decoding unit 225.

[0016] The likelihood calculation unit 220 receives the value demapped by the symbol demapper 21. The value demapped by the symbol demapper 21 is received from the received signal l ｊ :=(l ｊ １ ,l ｊ ２ ,…,l ｊ ｄ The likelihood calculation unit 220 calculates the received signal l by equation (1).ｊ Based on this, the LLR λ in the first lane is calculated. ｊ １ Calculate.

[0017] The calculation symbol in Equation (1) is defined by Equation (2).

[0018] The likelihood calculation unit 220 outputs the calculated λ ｊ １ to the second decoder 222 via the first lane.

[0019] The likelihood calculation unit 220 calculates the LLR λ in the second lane to the d-th lane ｊ ｉ (i = 2,..., d). Here, the likelihood calculation unit 220 is z ｊ １ is the LLR when it is 0, λ ｊ ｉ (0, l) and the LLR when it is 1, λ ｊ ｉ (1, l) is calculated. λ ｊ ｉ (z ｊ １ , l) (z ｊ １ = 0 or 1) is calculated by Equation (3).

[0020] z ｊ ｉ is the j-th bit of the bit sequence of the i-th lane after correction by SD-FEC. z ｊ １ is determined to be 0 or 1 by the calculation of the second decoder 222 described later. The likelihood calculation unit 220 calculates the calculated λ ｊ ｉ (0, l) and λ ｊ ｉ (1, l) (i = 2,..., d) to the first decoder 221 via the i-th lane (i = 2,..., d). The likelihood calculation unit 220 calculates the calculated λ ｊ ｉ (0, l) and λ ｊ ｉ (1, l) and outputs them to the first decoder 221 as binary information in each lane.

[0021] The first decoding unit 221 processes z from the second lane to the d lane. ｊ ｉ (i = 2, ..., d) is calculated. Here, the first decoding unit 221 calculates z ｊ １ z when z is 0 ｊ ｉ (λ ｊ ｉ z when (0, l) and 1 ｊ ｉ (λ ｊ ｉ The (1, l)) is calculated. The likelihood calculation unit 220 calculates z according to equation (4). ｊ ｉ (i=2, ..., d) to z ｊ １ We will perform calculations for both the case where the value is 0 and the case where it is 1.

[0022] The first decoding unit 221 calculates z ｊ ｉ (λ ｊ ｉ (0, l) and z ｊ ｉ (λ ｊ ｉ (1, l))(i=2, ..., d) are output to selector 223 via each of the d lanes from the second lane.

[0023] The second decoding unit 222 calculates λ calculated by the likelihood calculation unit 220. ｊ １ Based on z ｊ １ The second decoding unit 222 calculates z according to equation (5). ｊ １ Calculate.

[0024] The second decoding unit 222 calculates z ｊ １ The first lane outputs the result to the d:1 converter 224. The second decoding unit 222 then calculates the z ｊ １ Output to selector 223.

[0025] The selector 223 is z calculated by the second decoding unit 222 ｊ１ Based on the value of, two z's calculated in each lane from the second lane to the d-th lane ｊ ｉ which is z ｊ ｉ (λ ｊ ｉ (0, l)) and z ｊ ｉ (λ ｊ ｉ (1, l)) are selected. The selector 223 selects z ｊ １ when the value of z calculated by the second decoder 222 is 0 ｊ ｉ (λ ｊ ｉ (0, l)). The selector 223 selects z ｊ １ when the value of z calculated by the second decoder 222 is 1 ｊ ｉ (λ ｊ ｉ (1, l)). The selector 223 outputs the selected z ｊ ｉ to the d:1 converter 224 via each of the second lane to the d-th lane.

[0026] The d:1 converter 224 converts z ｊ ｉ (i = 1,..., d) into data of a one-lane series by performing a parallel-to-serial conversion. The d:1 converter 224 outputs the data of the one-lane series to the HD-FEC decoder 225.

[0027] The HD-FEC decoder 225 decodes the data of the one-lane series output from the d:1 converter 224 using a decoding technique corresponding to the encoding performed by the transmission device 1.

[0028] FIG. 2 is a flowchart showing the operation of the decoder circuit 22 according to the present embodiment. The likelihood calculation unit 220 calculates λ ｊ which is the LLR in the first lane, based on the received signal l ｊ １ and calculates λ ｊ ｉ which are the LLRs in the second lane to the d-th lane (0, l) and λｊ ｉ (1, l)(i=2, ..., d) is calculated (step S10). The first decoding unit 221 calculates λ ｊ ｉ Based on (0, l) (i = 2, ..., d), z ｊ ｉ (λ ｊ ｉ Calculate (0, l) (i = 2, ..., d), and λ ｊ ｉ Based on (1, l) (i = 2, ..., d), z ｊ ｉ (λ ｊ ｉ (1, l) (i = 2, ..., d) is calculated (step S11). The second decoding unit 222 calculates λ ｊ １ Based on z ｊ １ The calculation is performed (step S12). Since step S11 is a calculation in the second lane to the d-th lane, and step S12 is a calculation in the first lane, steps S11 and S12 may be performed in parallel.

[0029] Selector 223 is z ｊ １ Depending on whether the value is 0 or 1, the two z calculated in lanes 2 through d are ｊ ｉ One of z (i=2, ..., d) ｊ ｉ (i = 2, ..., d) is selected (step S13). The d:1 converter 224 converts the values ​​input from the second decoding unit 222 or selector 223 via the first to d lanes into a single-lane sequence of data by performing a parallel-serial conversion (step S14). The HD-FEC decoding unit 225 decodes the single-lane sequence of data output from the d:1 converter 224 (step S15).

[0030] In the conventional CP-MLC method, the received signal l has d values ​​in lanes 2 through d. ｊIt is necessary to maintain the value z. Therefore, the required space complexity in each lane from the second to the dth lane is O(d). In contrast, in this embodiment, two values ​​z are required in lanes from the second to the dth lane. ｊ ｉ (λ ｊ ｉ (0, l) and z ｊ ｉ (λ ｊ ｉ It is sufficient to maintain (1, l), and the required space computation time from the second lane to the d-th lane is O(2). As a result, the decoding circuit 22 in this embodiment can be realized with low power and with reduced space computation time.

[0031] While embodiments of this invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs and the like that do not depart from the spirit of this invention.

[0032] Some of the functional components (for example, the decoding circuit 22) of the receiving device 2 in the above-described embodiment may be implemented using a computer. In that case, the program for implementing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be loaded into a computer system and executed. The term "computer system" as used herein includes hardware such as an operating system and peripheral devices.

[0033] Furthermore, "computer-readable recording media" refers to portable media such as flexible disks, magneto-optical disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into computer systems. In addition, "computer-readable recording media" may also include those that dynamically hold programs for a short period of time, such as communication lines used when transmitting programs over networks such as the Internet or communication lines such as telephone lines, and those that hold programs for a certain period of time, such as volatile memory inside computer systems that act as servers or clients in such cases. Moreover, the above-mentioned programs may be for the purpose of realizing some of the functions described above, or they may be able to realize the above-mentioned functions in combination with programs already recorded in the computer system, or they may be realized using programmable logic devices such as FPGAs (Field Programmable Gate Arrays).

[0034] 100 Optical communication system, 1 Transmitter, 2 Receiver, 20 Receiver section, 21 Symbol demapper, 22 Decoding circuit, 220 Likelihood calculation unit, 221 First decoding unit, 222 Second decoding unit, 223 Selector, 224 d:1 converter, 225 HD-FEC decoding unit

Claims

1. A likelihood calculation unit that calculates log-likelihood ratios in lanes 1 through d (where d is an integer of 2 or more) based on a decoding metric obtained by demodulating transmitted data transmitted from a transmitting device, comprising: a likelihood calculation unit that calculates the log-likelihood ratios in lanes 2 through d when the bit of the decoded first lane is 0 and when it is 1; a first decoding unit that calculates the bits of lanes 2 through d in the cases where the bit of the decoded first lane is 0 and 1 based on the log-likelihood ratios in lanes 2 through d; a second decoding unit that calculates the bits of the first lane based on the log-likelihood ratio in the first lane; and a selector that selects the calculated bits of lanes 2 through d based on the calculated bits of the first lane.

2. The decoding circuit according to claim 1, further comprising: a converter that converts the bits from the first lane to the d-th lane into a sequence of data in one lane by performing a parallel-to-serial conversion; and a decoding unit that decodes the sequence of data in one lane.

3. A receiving device comprising: a decoding circuit according to claim 1 or 2; a receiving unit that receives the transmission data from the transmitting device; and a symbol demapper that demodulates the transmission data using a demodulation method corresponding to the transmitting device and obtains a decoding metric.

4. A likelihood calculation unit for calculating log-likelihood ratios in lanes 1 through d based on a decoding metric obtained by demodulating transmitted data transmitted from a transmitting device, comprising: a likelihood calculation step of calculating the log-likelihood ratios in lanes 2 through d when the bits of the decoded first lane are 0 and when they are 1; a first decoding step of calculating the bits of lanes 2 through d in the cases where the bits of the decoded first lane are 0 and 1 based on the log-likelihood ratios in lanes 2 through d; a second decoding step of calculating the bits of the first lane based on the log-likelihood ratio in the first lane; and a selection step of selecting the calculated bits of lanes 2 through d based on the calculated bits of the first lane.

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