Semiconductor device and motor drive system

Abstract

To reduce cost.SOLUTION: A semiconductor device according to an embodiment comprises first through fifth terminals, an amplifier circuit, and a switching section. A first end of a first resistor that is provided in an outside is connected to a first terminal P1. A second end of the first resistor is connected to a second terminal P2. A first end of a second resistor that is provided in an outside is connected to a third terminal P3. A second end of the second resistor is connected to a fourth terminal P4. The amplifier circuit has a first input terminal, a second input terminal, and an output terminal. The output terminal of the amplifier circuit is connected to a fifth terminal P9. The switching section switches between a first state in which the first input terminal is connected to the first terminal P1 and the second input terminal is connected to the second terminal P2, and a second state in which the first input terminal is connected to the third terminal P3 and the second input terminal is connected to the fourth terminal P4.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a semiconductor device and a motor drive system. [Background technology]

[0002] Semiconductor devices for detecting current are known. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2006 / 55352 [Patent Document 2] Japanese Patent Application Laid-Open No. 2003-18900 [Patent Document 3] US Patent Application Publication No. 2009 / 256504 Summary of the Invention [Problem to be solved by the invention]

[0004] Keep costs down. [Means for solving the problem]

[0005] The semiconductor device according to the embodiment includes first to fifth terminals, an amplifier circuit, and a switching unit. The child , a first switch, and a first end of a first resistor provided externally to Connected to the second terminal The child , a second switch, and Second end of the first resistor to Connected to the third terminal The child , The third switch, and a first end of a second resistor provided externally to Connected to the fourth terminal The child , The fourth switch, and Second end of the second resistor to The amplifier circuit is connectable to the first terminal via the first switch and connectable to the third terminal via the third switch The first input terminal and , connectable to the second terminal via the second switch and connectable to the fourth terminal via the fourth switch; The second input terminal 、The fifth terminal is connected to the output terminal of the amplifier circuit. During a first period, the first switch and the second switch are each in a connected state, and the third switch and the fourth switch are each in a disconnected state, First state Switch to , During a second period different from the first period, the first switch and the second switch are each in a non-connected state, and the third switch and the fourth switch are each in a connected state, Second state to It is configured to switch. A first voltage developed across the first resistor is out of phase with a second voltage developed across the second resistor. In the first state, the first input is connected to the first terminal and isolated from the third terminal, and the second input is connected to the second terminal and isolated from the fourth terminal. In the second state, the first input is connected to the third terminal and isolated from the first terminal, and the second input is connected to the fourth terminal and isolated from the second terminal. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram illustrating an example of the configuration of a motor drive system according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of a driver unit according to the first embodiment. [Figure 3] 2 is a circuit diagram showing a current detection unit, a part of a driver unit, and a microcontroller of the semiconductor device according to the first embodiment. [Figure 4] 4 is a table for explaining the operation of a decoder according to the first embodiment. [Figure 5] 4 is a diagram for explaining the operation of a current detection unit according to the first embodiment. [Figure 6] FIG. 10 is a circuit diagram showing a current detection section, a part of a driver unit, and a microcontroller of a semiconductor device according to a second embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a current detection section, a part of a driver unit, and a microcontroller of a semiconductor device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the description, components having substantially the same functions and configurations are designated by the same reference numerals. The embodiments shown below are merely examples of technical ideas. The embodiments do not specify the materials, shapes, structures, arrangements, etc. of the components. Various modifications can be made to the embodiments.

[0008] [1] First embodiment The semiconductor device according to the first embodiment will be described.

[0009] [1-1] Configuration [1-1-1] Overall configuration of the motor drive system SYS including the semiconductor device 1 1 is a block diagram illustrating an example of the configuration of a motor drive system according to a first embodiment. The motor drive system SYS is a system that drives a vehicle's power steering with a motor. The motor drive system SYS includes a semiconductor device 1, a driver unit 2, a motor 3, and a microcontroller 4.

[0010] The semiconductor device 1 is an IC (Integrated Circuit) chip. The semiconductor device 1 includes a pre-driver 11 and a current detection unit 12. The pre-driver 11 drives the driver unit 2 based on a signal from the microcontroller 4. The current detection unit 12 detects the current flowing through the driver unit 2 and outputs a voltage to the microcontroller 4.

[0011] The driver unit 2 is a drive unit including a plurality of power semiconductors (not shown). The driver unit 2 is driven by the pre-driver 11 to generate a drive current and drive the motor 3. The drive current is a three-phase AC current.

[0012] The motor 3 is a three-phase AC motor. The motor 3 is driven by the driver unit 2 and drives a power steering load (not shown).

[0013] The microcontroller 4 is an IC chip. The microcontroller 4 controls the semiconductor device 1. The microcontroller 4 includes a logic circuit 41 and an AD converter (ADC) 42. The logic circuit 41 generates signals necessary for controlling the semiconductor device 1. The logic circuit 41 transmits control signals to the pre-driver 11 and the current detection unit 12. The ADC 42 measures the input voltage and converts it into a digital value.

[0014] [1-1-2] Driver unit 2 configuration 2 is a circuit diagram showing an example of the configuration of a driver unit according to Embodiment 1. The driver unit 2 includes power supply lines PL and GL, transistors 21 to 26, and resistors R1 to R3.

[0015] A power supply voltage is applied to the power supply line PL, and the power supply line GL is grounded.

[0016] The drain of transistor 21 is connected to the power supply line PL. The source of transistor 21 is connected to node N1. The drain of transistor 22 is connected to node N1. The source of transistor 22 is connected to a first end of resistor R1. The second end of resistor R1 is connected to the power supply line GL.

[0017] The drain of transistor 23 is connected to the power supply line PL. The source of transistor 23 is connected to node N2. The drain of transistor 24 is connected to node N2. The source of transistor 24 is connected to a first end of resistor R2. The second end of resistor R2 is connected to the power supply line GL.

[0018] The drain of transistor 25 is connected to the power supply line PL. The source of transistor 25 is connected to node N3. The drain of transistor 26 is connected to node N3. The source of transistor 26 is connected to a first end of resistor R3. The second end of resistor R3 is connected to the power supply line GL.

[0019] The gates of the transistors 21 to 26 are each independently connected to the pre-driver 11. The transistors 21 to 26 are each individually turned on and off by the pre-driver 11, thereby generating a driving current. The first and second ends of the resistors R1 to R3 are each independently connected to the current detection unit 12. The nodes N1, N2, and N3 are each connected to the motor 3. The nodes N1, N2, and N3 are each an output node of the driver unit 2.

[0020] The voltage across resistor R1 is called voltage V1, the voltage across resistor R2 is called voltage V2, and the voltage across resistor R3 is called voltage V3.

[0021] Each of the resistors R1 to R3 is a resistor for current detection. The resistance value of each of the resistors R1 to R3 is known to the microcontroller 4. The first and second terminals of each of the resistors R1 to R3 and the current detection unit 12 are connected by independent wiring, as described above. By wiring in this manner, the influence of parasitic resistance components of the wiring is suppressed. The connection between the resistors R1 to R3 and the current detection unit 12 will be described in detail later.

[0022] [1-1-3] Configuration of current detection unit 12 FIG. 3 is a circuit diagram showing a current detection section, a part of a driver unit, and a microcontroller of the semiconductor device according to the first embodiment.

[0023] The semiconductor device 1 further includes terminals P1 to P9, which are configured to electrically connect the inside and outside of the semiconductor device 1.

[0024] The terminal P1 is connected to a first end of the resistor R1. The terminal P2 is connected to a second end of the resistor R1. The terminal P3 is connected to a first end of the resistor R2. The terminal P4 is connected to a second end of the resistor R2. The terminal P5 is connected to a first end of the resistor R3. The terminal P6 is connected to a second end of the resistor R3. The terminals P7 and P8 are each connected to the logic circuit 41. The terminal P9 is connected to the ADC 42.

[0025] The current detection unit 12 includes an operational amplifier 121, a decoder 122, resistors R11 to R18, resistors R21 to R24, switches SW1 to SW8, and a voltage source PS1.

[0026] The operational amplifier 121 is an operational amplifier that amplifies an input signal and outputs the amplified signal. The operational amplifier 121 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The voltage source PS1 is a constant voltage source. The voltage output by the voltage source PS1 is the voltage Vref. The voltage Vref is a reference voltage that determines the operating point of the operational amplifier 121. The voltage Vref is, for example, a DC voltage that is half the magnitude of the power supply voltage (not shown) of the operational amplifier 121.

[0027] A first end of the resistor R11 is connected to the terminal P1. The switch SW1 electrically connects the second end of the resistor R11 and the first end of the resistor R21 in the connected state and electrically insulates them in the disconnected state. A first end of the resistor R12 is connected to the terminal P2. The switch SW2 electrically connects the second end of the resistor R12 and the first end of the resistor R22 in the connected state and electrically insulates them in the disconnected state. A first end of the resistor R13 is connected to the terminal P3. The switch SW3 electrically connects the second end of the resistor R13 and the first end of the resistor R21 in the connected state and electrically insulates them in the disconnected state. A first end of the resistor R14 is connected to the terminal P4. The switch SW4 electrically connects the second end of the resistor R14 and the first end of the resistor R22 in the connected state and electrically insulates them in the disconnected state. A first end of the resistor R15 is connected to the terminal P5. The switch SW5 electrically connects the second end of the resistor R15 and the first end of the resistor R21 in the connected state and electrically insulates them in the disconnected state. The first end of the resistor R16 is connected to the terminal P6. The switch SW6 electrically connects the second end of the resistor R16 and the first end of the resistor R22 in the connected state and electrically insulates them in the disconnected state. The first end of the resistor R17 is grounded. The switch SW7 electrically connects the second end of the resistor R17 and the first end of the resistor R21 in the connected state and electrically insulates them in the disconnected state. The first end of the resistor R18 is grounded. The switch SW8 electrically connects the second end of the resistor R18 and the first end of the resistor R22 in the connected state and electrically insulates them in the disconnected state.

[0028] A second terminal of the resistor R21 is connected to the non-inverting input terminal of the operational amplifier 121. A second terminal of the resistor R22 is connected to the inverting input terminal of the operational amplifier 121. A first terminal of the resistor R23 is connected to the non-inverting input terminal of the operational amplifier 121. A second terminal of the resistor R23 is connected to the positive output terminal of the voltage source PS1. The negative output terminal of the voltage source PS1 is grounded. A first terminal of the resistor R24 ​​is connected to the inverting input terminal of the operational amplifier 121. A second terminal of the resistor R24 ​​is connected to the output terminal of the operational amplifier 121. The output terminal of the operational amplifier 121 is connected to the terminal P9. The signal output from the output terminal of the operational amplifier 121 is called the signal VOUT.

[0029] The decoder 122 sets each of the switches SW1 to SW8 to a connected or disconnected state based on the received signal. The decoder 122 receives signals from the logic circuit 41 via terminals P7 and P8. Specifically, the decoder 122 receives the signal SEL1 via terminal P7. The decoder 122 receives the signal SEL2 via terminal P8. Each of the signals SEL1 and SEL2 is a signal having one bit of information. In other words, the signals SEL1 and SEL2 transmit a total of two bits of information. The decoder 122 controls each of the switches SW1 to SW8 in accordance with the received signals SEL1 and SEL2.

[0030] [1-2] Operation Fig. 4 is a table for explaining the operation of the decoder according to the first embodiment. In Fig. 4, the signals SEL1 and SEL2 are each shown as being at an "H" level or an "L" level. Also, in Fig. 4, the connected state of each of the switches SW1 to SW8 is indicated by an "O" mark, and the non-connected state is indicated by an "X" mark.

[0031] The decoder 122 controls the switches SW1 to SW8 to one of four states, from a first state to a fourth state, in accordance with the signals SEL1 and SEL2.

[0032] When signal SEL1 is at L level and signal SEL2 is at H level, the decoder controls switches SW1 to SW8 to a first state. In the first state, switches SW1 and SW2 are connected. In the first state, switches SW3, SW4, SW5, SW6, SW7, and SW8 are disconnected. That is, in the first state, operational amplifier 121 amplifies and outputs voltage V1.

[0033] When signal SEL1 is at H level and signal SEL2 is at L level, the decoder controls switches SW1 to SW8 to the second state. In the second state, switches SW3 and SW4 are connected. In the second state, switches SW1, SW2, SW5, SW6, SW7, and SW8 are disconnected. That is, in the second state, operational amplifier 121 amplifies and outputs voltage V2.

[0034] When signal SEL1 is at H level and signal SEL2 is at H level, the decoder controls switches SW1 to SW8 to a third state. In the third state, switches SW5 and SW6 are connected. In the third state, switches SW1, SW2, SW3, SW4, SW7, and SW8 are disconnected. That is, in the third state, operational amplifier 121 amplifies and outputs voltage V3.

[0035] When signal SEL1 is at an L level and signal SEL2 is at an L level, the decoder controls switches SW1 to SW8 to a fourth state. In the fourth state, switches SW7 and SW8 are connected. In the fourth state, switches SW1, SW2, SW3, SW4, SW5, and SW6 are disconnected. That is, in the fourth state, the input terminal of operational amplifier 121 is grounded via a resistor. In the fourth state, the output of operational amplifier 121 is a DC voltage equal to the sum of voltage Vref and an offset voltage Voff of operational amplifier 121. The offset voltage Voff is a voltage generated by an error in manufacturing operational amplifier 121.

[0036] FIG. 5 is a diagram illustrating the operation of the current detection unit according to the first embodiment. FIG. 5 shows voltages V1, V2, and V3, signals SEL1 and SEL2, and signal VOUT. Also, FIG. 5 uses dashed lines to show voltage GV1 obtained when operational amplifier 121 amplifies voltage V1, voltage GV2 obtained when operational amplifier 121 amplifies voltage V2, and voltage GV3 obtained when operational amplifier 121 amplifies voltage V3, superimposed on signal VOUT. The densest dashed line represents voltage GV1, and the coarsest dashed line represents voltage GV3.

[0037] During the period T0, the signal SEL1 is at the L level and the signal SEL2 is at the L level, so the switches SW1 to SW8 are controlled to be in the fourth state. Therefore, during the period T0, the signal VOUT becomes a DC voltage equal to the voltage Vref plus the offset voltage Voff.

[0038] During the period T1, the signal SEL1 is at the L level and the signal SEL2 is at the H level, so the switches SW1 to SW8 are controlled to be in the first state. Therefore, during the period T1, the signal VOUT becomes equal to the voltage GV1.

[0039] During the period T2, the signal SEL1 is at the H level and the signal SEL2 is at the L level, so the switches SW1 to SW8 are controlled to be in the second state, and therefore, during the period T2, the signal VOUT becomes equal to the voltage GV2.

[0040] During the period T3, the signal SEL1 is at the H level and the signal SEL2 is at the H level, so the switches SW1 to SW8 are controlled to be in the third state. Therefore, during the period T3, the signal VOUT becomes equal to the voltage GV3.

[0041] Thereafter, signals SEL1 and SEL2 change to alternately switch between the first state, the second state, and the third state, and signal VOUT switches to be equal to voltages GV1, GV2, and GV3, respectively. In the final period shown in FIG. 5, signals SEL1 and SEL2 enter the fourth state, and signal VOUT becomes a DC voltage equal to voltage Vref plus offset voltage Voff.

[0042] In this way, the semiconductor device 1 according to the first embodiment can switch voltages so that multiple voltages can be measured with one ADC 42. Furthermore, the semiconductor device 1 according to the first embodiment can also ground the input terminal of the operational amplifier 121 and output a DC voltage equal to the voltage Vref plus the offset voltage Voff.

[0043] [1-3] Effects The semiconductor device 1 according to the embodiment includes a decoder 122, switches SW1 to SW8, and an operational amplifier 121. The decoder 122 switches the states of the switches SW1 to SW8 based on signals SEL1 and SEL2, so that three types of voltages can be amplified using one operational amplifier 121.

[0044] That is, in the semiconductor device 1 according to the embodiment, one operational amplifier 121 is shared by multiple inputs. This reduces the circuit size and chip area compared to when an operational amplifier 121 is provided for each voltage to be measured, thereby reducing manufacturing costs.

[0045] Furthermore, the reduced circuit scale also reduces the time required for product testing, thereby reducing testing costs.

[0046] Furthermore, in the semiconductor device 1 according to the embodiment, the input terminal of the operational amplifier 121 can be grounded by controlling the switches SW1 to SW8 to the fourth state. The output of the operational amplifier 121 includes an offset voltage Voff. The offset voltage Voff can be calculated by grounding the input terminal of the operational amplifier 121 and comparing the measured value of the signal VOUT with the design value. Specifically, the offset voltage Voff can be calculated by subtracting the magnitude of the voltage Vref from the measured value of the signal VOUT in the fourth state. Then, for example, the microcontroller 4 can subtract the calculated offset voltage Voff from the measured value of the signal VOUT obtained in the first to third states, thereby suppressing the influence of the offset voltage Voff on the measurement result.

[0047] [2] Second embodiment The configuration of the semiconductor device according to the second embodiment is different from that of the semiconductor device according to the first embodiment in the configuration of the current detection unit. The following describes the differences between the semiconductor device according to the second embodiment and the first embodiment.

[0048] [2-1] Configuration [2-1-1] Configuration of semiconductor device 1a 6 is a circuit diagram showing a current detection unit, a part of a driver unit, and a microcontroller of a semiconductor device according to the second embodiment. The semiconductor device 1a according to the second embodiment has a configuration in which the current detection unit 12 of the semiconductor device 1 described in the first embodiment is replaced with a current detection unit 12a.

[0049] Compared to the current detection unit 12, the current detection unit 12a further includes an offset adjustment circuit 123 and variable resistance circuits 124 and 125, but does not include the resistors R23 and R24.

[0050] The offset adjustment circuit 123 has a function of adjusting the offset of the signal Vout. Specifically, the offset adjustment circuit 123 reduces the offset of the signal Vout by adjusting the offset of the voltage input to the operational amplifier 121. The offset adjustment circuit 123 is provided between each of the switches SW1, SW3, SW5, and SW7 and a first end of the resistor R21, and between each of the switches SW2, SW4, SW6, and SW8 and a first end of the resistor R22. In addition, the output of the operational amplifier 121 is connected to the offset adjustment circuit 123.

[0051] The variable resistance circuits 124 and 125 have the function of changing the resistance value to a plurality of different values. The variable resistance circuit 124 is provided to replace the resistor R23 of the current detection unit 12. The variable resistance circuit 125 is provided to replace the resistor R24 ​​of the current detection unit 12. Other configurations of the current detection unit 12a are similar to those of the current detection unit 12.

[0052] The semiconductor device 1a has the same configuration as the semiconductor device 1 except for the current detection unit 12a.

[0053] [2-2] Operation The operations of the offset adjustment circuit 123 and the variable resistance circuits 124 and 125 will be described in turn.

[0054] The offset adjustment circuit 123 performs an offset adjustment operation when the switches SW1 to SW8 are in the fourth state. Specifically, the offset adjustment circuit 123 adjusts the offset so that the offset voltage Voff included in the output voltage of the operational amplifier 121 approaches 0 V. After completing the offset adjustment operation, the offset adjustment circuit 123 holds the adjustment result until another offset adjustment operation is performed. As a result, the offset voltage Voff is suppressed even when the switches SW1 to SW8 change between the first state, the second state, and the third state.

[0055] The variable resistance circuits 124 and 125 change their resistance values ​​in response to commands from outside the semiconductor device 1a. As a result, the amount of negative feedback of the operational amplifier 121 changes, and the gain of the current detection unit 12a changes. In this way, the variable resistance circuits 124 and 125 make it possible to change the gain. The variable resistance circuits 124 and 125 can also be called gain change circuits.

[0056] [2-3] Effects The semiconductor device 1a according to the second embodiment can reduce manufacturing costs and test costs, similarly to the semiconductor device 1 according to the first embodiment.

[0057] The semiconductor device 1a according to the second embodiment includes an offset adjustment circuit 123 and variable resistance circuits 124 and 125. The offset adjustment circuit 123 and variable resistance circuits 124 and 125 are circuits used in combination with an operational amplifier 121. Therefore, the configuration of the second embodiment in which one operational amplifier 121 is shared by multiple inputs can further reduce the circuit size and the increase in chip area compared to the case in which an operational amplifier 121 is provided for each voltage to be measured. In other words, the manufacturing cost can be further reduced.

[0058] Furthermore, the reduced circuit scale also reduces the time required for product testing, thereby reducing testing costs.

[0059] [3] Modifications, etc. In the above embodiment, the current detection unit includes switches SW1 to SW8. The switches may be configured to switch between at least two types of voltage. Fig. 7 is a circuit diagram showing a current detection unit, a part of a driver unit, and a microcontroller of a semiconductor device according to a modified example.

[0060] The motor drive system according to the modified example differs from the motor drive system SYS according to the first embodiment in that the semiconductor device 1 is replaced with a semiconductor device 1b and the microcontroller 4 is replaced with a microcontroller 4a.

[0061] The microcontroller 4a is an IC chip. The microcontroller 4a controls the semiconductor device 1b. The microcontroller 4a includes a logic circuit 41a and ADCs 42a and 42b. The logic circuit 41a generates signals necessary for controlling the semiconductor device 1b. The logic circuit 41a transmits control signals to the pre-driver 11 (not shown) and the current detection unit 12b. Each of the ADCs 42a and 42b measures an input voltage and converts it into a digital value.

[0062] The semiconductor device 1b is an IC chip. The semiconductor device 1b includes a pre-driver 11 (not shown), a current detection unit 12b, and terminals P11 to P19. The pre-driver 11 (not shown) drives the driver unit 2 based on a signal from the microcontroller 4a. The current detection unit 12b detects the current flowing through the driver unit 2 and outputs a voltage to the microcontroller 4a. The terminals P11 to P19 are configured to electrically connect the inside and outside of the semiconductor device 1b.

[0063] The terminal P11 is connected to a first end of the resistor R1. The terminal P12 is connected to a second end of the resistor R1. The terminal P13 is connected to a first end of the resistor R2. The terminal P14 is connected to a second end of the resistor R2. The terminal P15 is connected to a first end of the resistor R3. The terminal P16 is connected to a second end of the resistor R3. The terminal P17 is connected to the logic circuit 41a. The terminal P18 is connected to the ADC 42a. The terminal P19 is connected to the ADC 42b.

[0064] The current detection unit 12b includes operational amplifiers 121a and 121b, an inverter 126, resistors R31 to R36, resistors R41 to R48, switches SW11 to SW14, and voltage sources PS1a and PS1b.

[0065] The operational amplifiers 121a and 121b are operational amplifiers that amplify and output an input signal. Each of the operational amplifiers 121a and 121b has a non-inverting input terminal, an inverting input terminal, and an output terminal. The inverter 126 is an inverter circuit that inverts and outputs an input signal. The voltage sources PS1a and PS1b are constant voltage sources. The voltages output by the voltage sources PS1a and PS1b are voltages Vref.

[0066] A first end of the resistor R31 is connected to the terminal P11. The switch SW11 electrically connects the second end of the resistor R31 and the first end of the resistor R41 in the connected state and electrically insulates them in the disconnected state. A first end of the resistor R32 is connected to the terminal P12. The switch SW12 electrically connects the second end of the resistor R32 and the first end of the resistor R42 in the connected state and electrically insulates them in the disconnected state. A first end of the resistor R33 is connected to the terminal P13. The switch SW13 electrically connects the second end of the resistor R33 and the first end of the resistor R41 in the connected state and electrically insulates them in the disconnected state. A first end of the resistor R34 is connected to the terminal P14. The switch SW14 electrically connects the second end of the resistor R34 and the first end of the resistor R42 in the connected state and electrically insulates them in the disconnected state.

[0067] A first end of resistor R35 is connected to terminal P15. A second end of resistor R35 is connected to a first end of resistor R45. A first end of resistor R36 is connected to terminal P16. A second end of resistor R36 is connected to a first end of resistor R46.

[0068] A second terminal of the resistor R41 is connected to the non-inverting input terminal of the operational amplifier 121a. A second terminal of the resistor R42 is connected to the inverting input terminal of the operational amplifier 121a. A first terminal of the resistor R43 is connected to the non-inverting input terminal of the operational amplifier 121a. A second terminal of the resistor R43 is connected to the positive output terminal of the voltage source PS1a. The negative output terminal of the voltage source PS1a is grounded. A first terminal of the resistor R44 is connected to the inverting input terminal of the operational amplifier 121a. A second terminal of the resistor R44 is connected to the output terminal of the operational amplifier 121a. The output terminal of the operational amplifier 121a is connected to the terminal P18.

[0069] The second terminal of resistor R45 is connected to the non-inverting input terminal of operational amplifier 121b. The second terminal of resistor R46 is connected to the inverting input terminal of operational amplifier 121b. The first terminal of resistor R47 is connected to the non-inverting input terminal of operational amplifier 121b. The second terminal of resistor R47 is connected to the positive output terminal of voltage source PS1b. The negative output terminal of voltage source PS1b is grounded. The first terminal of resistor R48 is connected to the inverting input terminal of operational amplifier 121b. The second terminal of resistor R48 is connected to the output terminal of operational amplifier 121b. The output terminal of operational amplifier 121b is connected to terminal P19.

[0070] Each of the switches SW11 and SW12 operates based on a signal SEL3 applied to a terminal P17. The signal SEL3 is a signal having one bit of information. The inverter 126 inverts the signal SEL3 applied to the terminal P17 and outputs the inverted signal to each of the switches SW13 and SW14. Each of the switches SW13 and SW14 operates based on the signal received from the inverter 126.

[0071] The other configurations of the motor drive system according to the modified example are the same as those of the motor drive system SYS according to the first embodiment.

[0072] The operation of each of the switches SW11 to SW14 will now be described.

[0073] When the signal SEL3 is at H level, the switches SW11 and SW12 are connected, and the switches SW13 and SW14 are disconnected. That is, when the signal SEL3 is at H level, the operational amplifier 121a amplifies and outputs the voltage V1.

[0074] When the signal SEL3 is at L level, the switches SW11 and SW12 are in a non-connected state, and the switches SW13 and SW14 are in a connected state. That is, when the signal SEL3 is at L level, the operational amplifier 121a amplifies and outputs the voltage V2.

[0075] In this way, the semiconductor device 1b according to the modified example can switch the circuit so that the ADC 42a can measure two types of voltage.

[0076] That is, in the semiconductor device 1b according to the modification, one operational amplifier 121a is shared by two inputs. This allows the circuit size to be reduced compared to when an operational amplifier 121a is provided for each voltage to be measured, and the increase in chip area can be suppressed. In other words, manufacturing costs can be suppressed. Furthermore, the reduced circuit size also shortens the time required for product testing, and the testing costs can be suppressed.

[0077] Note that voltage sources that output the same voltage may be combined into a single voltage source. For example, in a current detection unit 12b according to a modified example, the voltage sources PS1a and PS1b output the same voltage. Therefore, for example, the voltage source PS1b may be omitted, and the second end of the resistor R47 may be connected to the positive output end of the voltage source PS1a. With this configuration, the operational amplifiers 121a and 121b operate based on the voltage source PS1a. By distributing the voltage from a single voltage source to multiple operational amplifiers, costs can be reduced compared to when a voltage source is provided for each operational amplifier.

[0078] Furthermore, multiple resistors included in the current detection unit may be combined into one resistor as long as the gain of the current detection unit does not change. For example, in the current detection unit 12b according to the modified example, the resistors R35 and R45 may be combined into one resistor whose resistance value is equal to the sum of the resistance values ​​of the resistors R35 and R45. Similarly, the resistors R36 and R46 may be combined into one resistor whose resistance value is equal to the sum of the resistance values ​​of the resistors R36 and R46. Multiple resistors connected in series via switches may also be combined into one resistor as long as the gain of the current detection unit does not change. For example, in the current detection unit 12b according to the modified example, the resistance value of the resistor R31 may be increased by the resistance value of the resistor R41, the resistance value of the resistor R33 may be increased by the resistance value of the resistor R41, and the resistor R41 may be omitted. Alternatively, if the resistance values ​​of resistors R31 and R33 are equal, the resistance value of resistor R41 may be increased by the same amount, and resistors R31 and R33 may be omitted. Similarly, for resistors R32, R34, and R42, the resistance value of resistor R32 may be increased by the same amount as resistor R42, and the resistance value of resistor R34 may be increased by the same amount as resistor R42, and resistor R42 may be omitted. Alternatively, if the resistance values ​​of resistors R32 and R34 are equal, the resistance value of resistor R42 may be increased by the same amount as resistor R32, and resistors R32 and R34 may be omitted.

[0079] In the embodiment and modified examples, the motor 3 is a three-phase AC motor. The motor included in the system is not limited to a three-phase AC motor. The motor included in the system may be, for example, a DC motor, a combination of a DC motor and a single-phase motor, or multiple single-phase motors. The drive current generated by the driver unit 2 is changed to correspond to the connected motor.

[0080] In this specification, "connection" refers to being electrically connected, and does not exclude, for example, the presence of another element therebetween. Furthermore, "electrically connected" may be achieved through an insulator, provided that it is possible for the element to function in the same manner as an electrically connected element.

[0081] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0082] 1, 1a, 1b... semiconductor device, 2... driver unit, 3... motor, 4, 4a... microcontroller, 11... pre-driver, 12, 12a, 12b... current detection unit, 21 to 26... transistor, 41, 41a... logic circuit, 42... AD converter, 121, 121a, 121b... operational amplifier, 122... decoder, 123... offset adjustment circuit, 124, 125... variable resistor circuit, 126... inverter, GL... power supply line, P1 to P9, P11 to P19... terminal, PL... power supply line, PS1, PS1a, PS1b... voltage source, R1 to R3, R11 to R18, R21 to R24, R31 to R36, R41 to R48... resistor, SW1 to SW8, SW11 to SW14... switch, SYS... motor drive system

Claims

1. A first terminal connected to a first switch and a first end of an externally provided first resistor; a second terminal connected to a second switch and a second end of the first resistor; a third terminal connected to a third switch and a first end of a second resistor provided externally; a fourth terminal connected to a fourth switch and the second end of the second resistor; an amplifier circuit having a first input terminal connectable to the first terminal via the first switch and connectable to the third terminal via the third switch, a second input terminal connectable to the second terminal via the second switch and connectable to the fourth terminal via the fourth switch, and an output terminal; a fifth terminal to which the output terminal of the amplifier circuit is connected; during a first period, the first switch and the second switch are each set to a connected state, and the third switch and the fourth switch are each set to a disconnected state, thereby switching to a first state; During a second period different from the first period, the first switch and the second switch are each brought into a non-connected state, and the third switch and the fourth switch are each brought into a connected state, thereby switching to a second state. A switching unit configured as follows: Equipped with a first voltage developed across the first resistor is out of phase with a second voltage developed across the second resistor; In the first state, the first input end is connected to the first terminal and insulated from the third terminal, and the second input end is connected to the second terminal and insulated from the fourth terminal; In the second state, the first input terminal is connected to the third terminal and insulated from the first terminal, and the second input terminal is connected to the fourth terminal and insulated from the second terminal.

2. A sixth terminal connected to a fifth switch and a first end of a third resistor provided externally; a seventh terminal connected to a sixth switch and the second end of the third resistor; Furthermore, a third voltage generated across the third resistor is out of phase with both the first voltage and the second voltage; the switching unit is further configured to switch to a third state by bringing each of the first switch, the second switch, the third switch, and the fourth switch into a non-connected state and bringing each of the fifth switch and the sixth switch into a connected state during a third period different from either the first period or the second period; In the third state, the first input terminal is connected to the sixth terminal and insulated from the first terminal and the third terminal, and the second input terminal is connected to the seventh terminal and insulated from the second terminal and the fourth terminal; the switching unit further switches between the first state and the second state by setting each of the fifth switch and the sixth switch to a non-connected state; In each of the first state and the second state, the first input terminal is insulated from the sixth terminal and the second input terminal is insulated from the seventh terminal. The semiconductor device according to claim 1 .

3. A seventh switch; The 8th switch and Furthermore, the switching unit is further configured to switch to a fourth state by bringing each of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch into a non-connected state and bringing each of the seventh switch and the eighth switch into a connected state during a fourth period different from any of the first period, the second period, and the third period; In the fourth state, the first input terminal is grounded and insulated from the first terminal, the third terminal, and the sixth terminal, and the second input terminal is grounded and insulated from the second terminal, the fourth terminal, and the seventh terminal. The semiconductor device according to claim 2 .

4. The semiconductor device further comprises an eighth terminal to which a first signal having an information amount of 1 bit is applied from outside the semiconductor device, and a ninth terminal to which a second signal having an information amount of 1 bit is applied from outside the semiconductor device; the switching unit is configured to switch a connection state of the first input terminal and the second input terminal among the first state, the second state, the third state, and the fourth state based on the first signal and the second signal. The semiconductor device according to claim 3 .

5. The semiconductor device further includes a tenth terminal to which a third signal having an information amount of 1 bit is applied from outside the semiconductor device; the switching unit is configured to switch a connection state of the first input terminal and the second input terminal between the first state and the second state based on the third signal. The semiconductor device according to claim 1 .

6. the amplifier circuit has an offset adjustment circuit connected between the first terminal and the third terminal and the first input terminal, and between the second terminal and the fourth terminal and the second input terminal; The semiconductor device according to claim 1 .

7. the amplifier circuit has a gain change circuit; The semiconductor device according to claim 6.

8. a first power line; A second power supply line; a first transistor having a first end connected to the first power supply line and a second end connected to a first node; a second transistor having a first end connected to the first node; a first resistor having a first terminal connected to the second terminal of the second transistor and a second terminal connected to the second power supply line; a third transistor having a first end connected to the first power supply line and a second end connected to a second node; a fourth transistor having a first end connected to the second node; a second resistor having a first terminal connected to the second terminal of the fourth transistor and a second terminal connected to the second power supply line; a driver unit including: a pre-driver that controls the first transistor, the second transistor, the third transistor, and the fourth transistor; a first terminal connected to a first switch and the first end of the first resistor; a second terminal connected to a second switch and the second end of the first resistor; a third terminal connected to a third switch and the first end of the second resistor; a fourth terminal connected to a fourth switch and the second end of the second resistor; an amplifier circuit having a first input terminal connectable to the first terminal via the first switch and connectable to the third terminal via the third switch, a second input terminal connectable to the second terminal via the second switch and connectable to the fourth terminal via the fourth switch, and an output terminal; a fifth terminal to which the output terminal of the amplifier circuit is connected; during a first period, the first switch and the second switch are each set to a connected state, and the third switch and the fourth switch are each set to a disconnected state, thereby switching to a first state; During a second period different from the first period, the first switch and the second switch are each brought into a non-connected state, and the third switch and the fourth switch are each brought into a connected state, thereby switching to a second state. A switching unit configured as follows: a semiconductor device including: a microcontroller that controls the pre-driver and is connected to the fifth terminal; a motor connected to each of the first node and the second node; Equipped with a first voltage developed across the first resistor is out of phase with a second voltage developed across the second resistor; In the first state, the first input end is connected to the first terminal and insulated from the third terminal, and the second input end is connected to the second terminal and insulated from the fourth terminal; In the second state, the first input terminal is connected to the third terminal and insulated from the first terminal, and the second input terminal is connected to the fourth terminal and insulated from the second terminal.

9. The driver unit includes: a fifth transistor having a first end connected to the first power supply line and a second end connected to a third node; a sixth transistor having a first end connected to the third node; a third resistor having a first terminal connected to the second terminal of the sixth transistor and a second terminal connected to the second power supply line; further comprising The semiconductor device includes: a sixth terminal connected to a fifth switch and the first end of the third resistor; a seventh terminal connected to a sixth switch and the second end of the third resistor; Furthermore, a third voltage generated across the third resistor is out of phase with both the first voltage and the second voltage; the switching unit is further configured to switch to a third state by bringing each of the first switch, the second switch, the third switch, and the fourth switch into a non-connected state and bringing each of the fifth switch and the sixth switch into a connected state during a third period different from either the first period or the second period; In the third state, the first input terminal is connected to the sixth terminal and insulated from the first terminal and the third terminal, and the second input terminal is connected to the seventh terminal and insulated from the second terminal and the fourth terminal; the switching unit further switches between the first state and the second state by setting each of the fifth switch and the sixth switch to a non-connected state; In each of the first state and the second state, the first input terminal is insulated from the sixth terminal and the second input terminal is insulated from the seventh terminal. The motor drive system according to claim 8 .

10. The semiconductor device A seventh switch; The 8th switch and further comprising the switching unit is further configured to switch to a fourth state by bringing each of the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch into a non-connected state and bringing each of the seventh switch and the eighth switch into a connected state during a fourth period different from any of the first period, the second period, and the third period; In the fourth state, the first input terminal is grounded and insulated from the first terminal, the third terminal, and the sixth terminal, and the second input terminal is grounded and insulated from the second terminal, the fourth terminal, and the seventh terminal. The motor drive system of claim 9.

11. the semiconductor device further includes an eighth terminal to which a first signal having an amount of information of 1 bit is applied from the microcontroller, and a ninth terminal to which a second signal having an amount of information of 1 bit is applied from the microcontroller; the switching unit is configured to switch a connection state of the first input terminal and the second input terminal among the first state, the second state, the third state, and the fourth state based on the first signal and the second signal. The motor drive system of claim 10.

12. the semiconductor device further includes a tenth terminal to which a third signal having one bit of information is applied from the microcontroller; the switching unit is configured to switch a connection state of the first input terminal and the second input terminal between the first state and the second state based on the third signal. The motor drive system according to claim 8 .

13. the amplifier circuit has an offset adjustment circuit connected between the first terminal and the third terminal and the first input terminal, and between the second terminal and the fourth terminal and the second input terminal; 13. The motor drive system according to any one of claims 8 to 12.

14. the amplifier circuit has a gain change circuit; 14. The motor drive system of claim 13.

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