Method for evaluating a gate-source leakage current in a transistor device, circuit arrangement with a transistor device and electronic circuit

Abstract

A process that exhibits: Discharging a gate-source capacitance (C GS ) of a transistor device (1) from a first voltage level (V1) to a second voltage level (V2) when a first resistor (21) is connected in parallel to the gate-source capacitance (C GS ) is switched on, and measuring a first discharge time (T1) in connection with the discharge; Discharge of the gate-source capacitance (C GS ) from the first voltage level (V1) to the second voltage level (V2) when the first resistor (21) and a second resistor (22) are connected in parallel to the gate-source capacitance (C GS ) are switched on, and measuring a second discharge time (T2) in connection with the discharge; Comparing the ratio between the first discharge time (T1) and the second discharge time (T2) with a predefined threshold; and Detecting a fault based on comparison.

Description

[0001] This description generally relates to a method and an electronic circuit for evaluating a gate-source leakage current or a gate-source resistance in a transistor device, in particular a MOS transistor device.

[0002] A MOS transistor device, such as a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor), is a voltage-controlled transistor device that is either on (conducting) or off (blocking) depending on the charge level of an internal capacitance. This internal capacitance is connected between a control node (gate node) and a load node (source node) and is commonly referred to as the gate-source capacitance. When the transistor is on, leakage currents can occur, discharging the gate-source capacitance. Excessive leakage currents can indicate that the transistor is faulty.

[0003] One approach to evaluating gate-source leakage current involves applying a voltage between the gate and source nodes that is higher than the drive voltage applied between them during normal operation, and measuring the current flowing between the gate and source nodes. The transistor is considered defective if the current exceeds a predefined threshold. However, applying a high test voltage places a stress on the transistor, which can reduce its lifespan. Therefore, a gentler method for evaluating gate-source leakage current is desirable.

[0004] ERTURK, F.; AKIN, B.: A Method for Online Ageing Detection in SiC MOSFETs. In: 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), 26 - 30 March 2017, pp. 3576 - 3581, describes a method in which the determination of a gate-source leakage current of a SiC MOSFET involves measuring a voltage across a gate resistor connected between a gate driver and a gate terminal of the MOSFET.

[0005] One embodiment relates to a method according to claim 1. The method comprises discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level when a first resistor is connected in parallel with the gate-source capacitance, and measuring a first discharge time associated with the discharge; and discharging the gate-source capacitance from the first voltage level to the second voltage level when a first resistor and a second resistor are connected in parallel with the gate-source capacitance, and measuring a second discharge time associated with the discharge. The method further comprises comparing a ratio between the first discharge time and the second discharge time with a predetermined threshold and detecting a fault based on the comparison.

[0006] Another embodiment relates to a circuit arrangement according to claim 8. The circuit arrangement comprises a transistor device with a gate node, a source node, a gate-source capacitance between the gate node and the source node, and a gate-source resistor between the gate node and the source node, and an electronic circuit connected between the gate node and the source node, comprising a control circuit, a first resistor connected between the gate node and the source node, and a second resistor.The control circuit is configured to measure, in a first test cycle, the discharge time associated with discharging the gate-source capacitance from a first voltage level to a second voltage level. In a second test cycle, it connects the second resistor between the gate node and the source node and measures a second discharge time associated with discharging the gate-source capacitance from the first voltage level to the second voltage level. The control circuit is further configured to compare the ratio between the first and second discharge times with a predefined threshold and to detect a fault based on this comparison.

[0007] Another embodiment relates to an electronic circuit according to claim 18. The electronic circuit is configured to be connected to a gate node and a source node of a transistor device and comprises a first resistor and a second resistor, each configured to be connected between the gate node and the source node, and a control circuit.The control circuit is configured to measure, in a first test cycle, the first discharge time associated with discharging the gate-source capacitance from a first voltage level to a second voltage level when the first resistor is connected between the gate node and the source node. In a second test cycle, it is configured to measure the second discharge time associated with discharging the gate-source capacitance from the first voltage level to the second voltage level when the first and second resistors are connected between the gate node and the source node. The control circuit is further configured to compare the ratio between the first and second discharge times with a predefined threshold and to detect a fault based on this comparison.

[0008] Examples are explained below using drawings. The drawings serve to illustrate certain principles, so only aspects necessary for understanding these principles are shown. The drawings are not to scale. In the drawings, the same reference symbols denote the same features. Fig. Figure 1 shows an equivalent circuit diagram of a transistor component according to an example; Fig. 2A to 2C show various examples of how the transistor component can be used as an electronic switch; Fig. Figure 3 shows an example of an electronic circuit with a transistor component and an electronic circuit designed to evaluate a gate-source leakage current; Fig. Figure 4 is a flowchart illustrating an example of a procedure for evaluating the gate-source leakage current; Fig. Figure 5 shows signal waveforms of a gate-source voltage; Fig. Figure 6 illustrates a relationship between a discharge time ratio, which is used in the Fig. The 4 illustrated methods were calculated, and a resistance value ratio between a resistance value of one at which in Fig. The 4 illustrated methods used a first resistance and an internal gate-source resistance value; Fig. Figure 7 shows an example of the electronic circuit in more detail; Fig. Figure 8 shows an electronic circuit with a transistor component, an electronic circuit and a control circuit; Fig. Figure 9 shows an example of a control circuit that includes an electronic circuit; and Fig. Figure 10 shows signal waveforms that illustrate the operation of the system in Fig. The control circuit shown in section 9 illustrates this.

[0009] The following detailed description refers to the accompanying drawings. The drawings form part of the description and illustrate examples of how the invention can be used and implemented. Naturally, the features of the various embodiments described herein can be combined unless explicitly stated otherwise.

[0010] Fig. Figure 1 illustrates an example of a transistor device 1, in particular a MOS (Metal Oxide Semiconductor) transistor device, which can also be referred to as an IG (Insulated Gate) transistor device. The transistor device comprises a control node G, which is subsequently referred to as the gate node, a first load node S, which is subsequently referred to as the source node, and a second load node D, which is subsequently referred to as the drain node. The diagram shown is for illustrative purposes only. Fig. The transistor device shown in Figure 1 is a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), specifically an n-type enhancement MOSFET. However, this is only one example. The following description and explanation apply equally to any other type of MOSFET, such as a p-type enhancement MOSFET, an n-type or p-type depletion MOSFET, or an IGBT (Insulated Gate Bipolar Transistor).

[0011] A transistor component of the in Fig. The transistor of type shown in section 1 can be used as an electronic switch in various types of electronic circuits. Some examples of how the transistor component can be used as an electronic switch are given in the following. Fig. 2A to 2C illustrated. Referring to Fig. 2A The transistor component 1 can be used as a low-side switch. In this case, a load path DS between the drain node D and the source node S of the transistor component 1 is connected between a load Z and a circuit node where a negative supply potential or ground GND is available. A series connection consisting of the load path DS of the transistor component 1 and the load Z is connected between a circuit node for a positive supply potential V+ and the circuit node for the negative supply potential or ground GND.

[0012] Referring to Fig. 2B, the electronic circuit can be used as a high-side switch. In this example, the load path DS of transistor element 1 is connected between the circuit nodes for the positive supply potential V+ and the load Z. According to another example, which is described in Fig. As shown in Figure 2C, the load section DS is connected between two loads Z1, Z2, with a series circuit comprising the loads Z1, Z2 and the load section DS being connected between circuit nodes for the positive supply potential V+ and the negative supply potential or ground GND.

[0013] The in Fig. The transistor component shown is a voltage-controlled transistor component that depends on a gate-source voltage V. GS The transistor device is in a conducting state (on state) or a blocking state (off state) between the gate node G and the source node S. Internally, the transistor includes a capacitance between the gate node G and the source node S, which is commonly referred to as the gate-source capacitance C. GS This gate-source capacity is described in the Fig. The circuit diagram shown in 1 is represented by a capacitor connected between the gate node G and the source node S. A capacitor in the diagram shown in Fig. In the circuit diagram shown, the resistor connected between the gate node G and the source node S represents a leakage current path. Typically, the resistance value R is... GS The leakage current path must have a resistance of at least a few megaohms (MΩ) or at least a few tens of MΩ. In a fault-free transistor, this results in a leakage current I. GS of less than a few microamperes (µA), for example when the gate-source voltage V GS The on-state voltage is approximately 10 volts (V). A low gate-source resistance value R GS This can be an indication that the transistor component is defective. It is therefore advisable to check the gate-source resistance value R. GS or the leakage current I GS to evaluate in order to detect a defect in transistor component 1.

[0014] Fig. Figure 3 shows an example of an electronic circuit designed to measure the gate-source resistance value R. GS or the gate-source current I GSto evaluate. The electronic circuit 2 comprises a first node configured to be connected to the gate node G, and a second node configured to be connected to the source node S of the transistor device 1. The electronic circuit 2 also comprises a first resistor 21 connected between the first and second nodes, such that the first resistor 21 is connected between the gate node G and the source node S when the transistor device 1 is connected to the electronic circuit 2. A second resistor 22 is connected in series with an electronic switch 23, forming a series connection between the first and second nodes, and thus in parallel with the first resistor 21.The electronic switch 23 is controlled by a control circuit 3, wherein the second resistor 22 is connected in parallel to the first resistor 21 when the control circuit 3 turns on the electronic switch 23, and is disconnected from the gate node G and the source node S when the control circuit 3 turns off the electronic switch 23. The control circuit 3 is connected to the gate node and the source node S to control the gate-source voltage V. GS to detect. Furthermore, the control circuit 3 is designed to detect a status signal S. STATUS to output a signal representing a test result. For example, the control circuit is configured to output the status signal S. STATUS to output a pass level and a failure level, where the pass level indicates that the gate-source resistance value R GS has passed the test, and the error level indicates that the gate-source resistance value R GSfailed the test.

[0015] An example of a method for evaluating the gate-source resistance value R GS through the in Fig. The electronic circuit shown in section 3 is in Fig. 4 illustrates. Fig. Figure 4 shows a flowchart of the procedure. In a first step, or test cycle 101, the procedure involves discharging the gate-source capacitance C. GS from a first voltage level V1 to a second voltage level V2, when the first resistor 21 is connected in parallel to the gate-source capacitance C GS is connected and if the second resistor 22 is not in parallel with the gate-source capacitance C GSThe process involves switching off the electronic switch 23 and measuring an initial discharge time T1 in connection with the discharge. In the first process step 101, the control circuit 3 switches off the electronic switch 23 to disconnect the second resistor 22 from the gate node and the source node S. In a second process step or test cycle 102, the procedure includes discharging the gate-source capacitance C. GS from the first voltage level V1 to the wide voltage level V2, when the first resistor 21 and the second resistor 22 are connected in parallel to the gate-source capacitance C GS are switched, and a second discharge time T2 is measured in connection with the discharge. Naturally, the gate-source capacitance is recharged to the first voltage level V1 or higher between the first step 101 and the second step 102. This recharging is shown in the flowchart according to Fig. 4, however, not explicitly shown. Referring to Fig. 4 The procedure also includes in step 103 comparing a ratio T1 / T2 between the first discharge time T1 and the second discharge time T2 with a predefined threshold to detect a fault or excessive leakage current.

[0016] Discharging the gate-source capacitance C GS in the first step 101 and the second step 102 is in Fig. 5 illustrates. Fig. Figure 5 shows a first curve 201, which represents the gate-source voltage V GS In the first step, 101 is represented, and a second curve 202 represents the gate-source voltage V. GS In the second step, 102 is represented. The gate-source voltage V GS is essentially equal to the voltage across the gate-source capacitance C GS "That the gate-source voltage V GS essentially equal to the voltage across the gate-source capacitance C GS "is" means that a (parasitic) gate resistor R G(the one in Fig. 1 (shown in dashed lines), which is between the gate-source capacitance C GS and the gate node G is significantly smaller than either of the first and second resistors 21, 22. "Significantly smaller" means that this gate resistance R G is smaller than 0.01-(10 -2 )-times or even smaller than 0.001-(10 -3 ) times the resistance value R21 of the first resistor 21 or the resistance value R22 of the second resistor R22.

[0017] Basically, each of the first and second curves 201, 202 is an exponential curve, meaning that the gate-source capacitance is discharged exponentially in the first and second steps 101, 102. In this process, the first discharge time T1 is given by T1=R1⋅CGS⋅ln(V1V2) where C GSThe gate-source capacitance is denoted. ln(.) denotes the natural logarithm, and R1 denotes a resistance value of the parallel circuit with the first resistor 21 and the gate-source capacitance R. GS , That means, R1=1 / (1RGS+1R21) where R GS R21 denotes the gate-source resistance value, and R21 denotes the resistance value of the first resistor 21. The second discharge time T2 can be expressed as: T2=R2⋅CGS⋅ln(V1V2) where C GS The gate-source capacitance is denoted, and R1 represents the resistance value of a parallel circuit consisting of the first resistor 21, the second resistor 22, and the gate-source resistance value R. GS that is, R2=1 / (1RGS+1R21+1R22)

[0018] R1 and R2 are subsequently referred to as the first and second resistance values, respectively. Based on equations (1a) and (1b), the ratio r between the first discharge time T1 and the second discharge time T2 is given by: r=T1T2=R1⋅CGS⋅ln(V1V2)R2⋅CGS⋅ln(V1V2)=R1R2

[0019] According to one example, the first resistor 21 is chosen such that its resistance value R21 in a fault-free state of the transistor element 1 is significantly smaller than the gate-source resistance value R. GS For example, the resistance value R21 of the first resistor is chosen to be less than 5%, less than 1%, or even less than 0.1% of the gate-source resistance value R. GS in the fault-free state of transistor component 1. In this case, the first resistance value R1 is determined by the resistance value R21 of the first resistor 21, such that R1≈R21

[0020] According to one example, the second resistor 22 is also chosen such that its resistance value R22 is significantly smaller than the gate-source resistance value R. GS Furthermore, the resistance value R22 of the second resistor is m times the resistance value R21 of the first resistor, that is, R22 = m·R21. According to an example, m is selected from between 0.01 (10 -2 ) and 10, in particular from between 0.01 (10 -2 ) and 1. If the resistance values ​​R21 and R22 of the first and second resistors are significantly smaller than the gate-source resistance value R GS , these resistance values ​​R21, R22 determine the second resistance value R2, such that the second resistance value R2 is approximately given by R2≈R21⋅R22R21+R22=mm+1⋅R21

[0021] Based on equations (4a) and (4b), the ratio r between the first discharge time T1 and the second discharge time T2 in the fault-free state of transistor element 1 is r=m+1m

[0022] For example, if m=1, such that R21=R22, the ratio r in the fault-free state is 2 (r=2), meaning the first discharge time T1 is twice the second discharge time T2. The ratio r increases when the resistance value R22 decreases relative to the resistance value R21. For example, if R22 is 0.5 times R21, then r=3. This means the first discharge time T1 is three times the second discharge time T2.

[0023] If, on the other hand, the transistor component is defective, such that the gate-source resistance value R GS Since the gate-source resistance value R is significantly smaller than in the fault-free state, the ratio r is smaller than in the fault-free state, that is, smaller than (m+1) / m. GSAs the resistance decreases, the ratio r approaches 1. This can be easily seen from equations (2a), (2b), and (3). Referring to equations (2a) and (2b), the first resistance value R1 and the second resistance value R2 each approach the gate-source resistance value R. GS on, when the gate-source resistance value R GS becomes significantly smaller than the resistance values ​​R21, R22 of the first and second resistors 21, 22, so that, with reference to equation (3), the ratio r approaches 1. This is also true in Fig. Figure 6 illustrates how the ratio r depends on a ratio R21 / R GS between the resistance value R21 of the first resistor and the gate-source resistance value R GS shows. The in Fig. The curve shown in section 6 was obtained based on m=1. As shown by Fig. As can be seen in Figure 6, the ratio r is essentially defined by equation (5), where the gate-source resistance value R GSgreater than 100 times R21, that is, when R21 is less than 1% of the gate-source resistance value R GS is. Since the gate-source resistance value R GS As the ratio r decreases relative to R21, it falls below (m+1) / m and decreases towards 1.

[0024] According to one example, a fault in transistor element 1 is detected when the ratio r falls below a predefined threshold. According to another example, this predefined threshold is chosen based on (m+1) / m. According to yet another example, this threshold is selected from between 0.8 times (m+1) / m and 0.999 times (m+1) / m, specifically from between 0.9 times (m+1) / m and 0.99 times (m+1) / m.

[0025] Fig. Figure 7 shows an example of control circuit 3 in more detail. Referring to Fig. The control circuit 3 comprises a controller 31, configured to control the operation of the control circuit 3, a current source 32, and a voltage source 34. A series connection of the current source 32 and the voltage source 34 is connected between the first and second nodes of the electronic circuit 2. The current source 32 is controlled by the controller 31. Referring to Fig. 7. Controlling the power source 32 by the controller 31 can include controlling an electronic switch 33 connected in series with the power source 32, wherein the power source 32 drives a charging current into the gate node G when the controller 31 turns on the electronic switch 33, and no charging current into the gate node G when the controller 31 turns off the electronic switch 33. Controlling the power source 32 by controlling the electronic switch 33 is only one example. Other ways of enabling or disabling the power source 32 by the controller 31 can also be implemented.

[0026] Referring to Fig. The control circuit 3 also includes a first reference voltage source 351, configured to generate a first voltage V1 with a first voltage level, and a second reference voltage source 352, configured to generate a second voltage V2 with a second voltage level. A first comparator 361 compares the first voltage V1 with the gate-source voltage V. GS and a second comparator 362 compares the second voltage V2 with the gate-source voltage V GS An output signal S361 of the first comparator 361 is received by the controller 31 and indicates whether the gate-source voltage V GS above or below the first voltage level V1, and an output signal S362 of the second comparator 362 is received by the controller 31 and indicates whether the gate-source voltage V GS above or below the second voltage level V2. In the case of the Fig. The example shown in section 7 compares the first voltage V1 with the gate-source voltage V. GS The first comparator achieves this by connecting its first input node to the first reference voltage source 351 and its second input node to the gate node G. Similarly, the first input node of the second comparator 362 is connected to the second reference voltage source 352 and its second input node is connected to the gate node G. In this example, the circuit nodes of the first and second reference voltage sources 351 and 352 that face away from the first and second comparators 361 and 362 are connected to the second node of the electronic circuit 2.

[0027] To determine the gate-source resistance value R GS to evaluate is the operation of the in Fig. Control circuit 3 shown in section 7 is as follows. Before discharging the gate-source capacitance C GS The first step, 101, which is based on Fig. As explained in section 4, the controller 31 switches on the electronic switch 33, so that the gate-source capacitance C GS is charged by the power source 32. For example, the controller 31 switches on the electronic switch 33 long enough so that the gate-source voltage V GS can rise above the first voltage level V1. For example, the controller 31 switches on the electronic switch 33 long enough so that the gate-source voltage V GS to a voltage level V SUP a supply voltage provided by the supply voltage source 34 can increase. According to another (in Fig. In the example shown in dashed lines (7), the control circuit 3 includes a further reference voltage source 350, which provides a reference voltage with a voltage level V0, where this voltage level V0 is between the first voltage level V1 and the supply voltage level V SUP In this example, controller 31 monitors the gate-source voltage V. GS , when the electronic switch 33 is turned on, and turns the electronic switch 33 off when the gate-source voltage V GS The third voltage level V0 has been reached. After the controller 31 has switched off the electronic switch 33, the gate-source capacitance C GS through the parallel circuit with the first resistor 21 and the gate-source resistance value R GS discharged. Controller 31 monitors the gate-source voltage V. GS and begins measuring the first discharge time T1 when the gate-source voltage V GSThe first voltage level V1 has been reached. Controller 31 also monitors the gate-source voltage V. GS and ends the measurement when the gate-source voltage V GS The voltage has dropped to the second voltage level V2. The time between the beginning and end of this measurement is the first discharge time T1.

[0028] After the first discharge time T1 has been measured, the controller 31 switches the electronic switch 33 back on to increase the gate-source capacitance C. GS to reload. After the gate-source capacity C GS Once recharged, the controller 31 switches off the electronic switch 33 and switches on the electronic switch 23 (which may already be switched on before recharging), which is connected in series with the second resistor 22, so that the gate-source capacitance C GSnow through the parallel circuit with the first resistor 21, the second resistor 22 and the gate-source resistance value R GS is discharged. Controller 31 again measures the time between the point at which the gate-source voltage V is reached. GS the first voltage level V1 is reached (crosses), and the time at which the gate-source voltage V GS The second voltage V2 is reached (crosses). This time is equal to the second discharge time T2.

[0029] Inevitably, delays can occur between the times at which the gate-source voltage V is applied. GS The first and second voltage levels V1, V2 are reached, and there are times when the controller begins and ends measuring the first discharge time T1 and the second discharge time T2. However, since these delays occur in the same way at the beginning and end of the measurement, they do not negatively affect the measurement of the first and second discharge times T1, T2.

[0030] According to one example, electronic circuit 2 is a dedicated circuit used solely to determine the gate-source resistance value R. GS to evaluate. In this case, with reference to Fig. 8. A control circuit 5 is connected to the gate node G and the source node S of the transistor element 1. This control circuit 5 can be configured to control the transistor element 1 by charging or discharging the gate-source capacitance C. GS depending on an input signal S IN to turn on or off.

[0031] According to another example, which is in Fig. As shown in Figure 9, the electronic circuit is not only designed to control the gate-source capacitance C. GS to evaluate, but is further designed to control the transistor element 1 depending on an input signal S INto switch on or off. In this example, the electronic circuit 3 is configured to switch on or off depending on an operating mode signal S. MODE to operate in one of two modes: a test mode and a control mode. In test mode, the electronic circuit 3 evaluates the gate-source resistance value R. GS in the manner described above. In control mode, the electronic circuit 3 controls the transistor element 1 based on the input signal S. IN to.

[0032] At the in Fig. In example 9, the controller 31 receives the input signal S IN and the operating mode signal S MODE and operates the electronic circuit 3 either in test mode or in control mode. Except for those based on Fig. In addition to the components described in Figure 7, the control circuit 3 also includes a further current source 52, which is coupled between the first and second nodes, such that the second current source 55 is connected between the gate node G and the source node S of the transistor element 1 when the latter is connected to the electronic circuit 2. The controller 31 is configured to control this further current source 52. The controller can control (activate or deactivate) the further current source 52 by controlling another electronic switch 53, which is connected in series with the further current source 52 (as shown in Figure 7). Fig. 9 shown), or in any other way.

[0033] The additional current source 52 is used in control mode to determine the gate-source capacitance C. GSto discharge and switch off transistor element 1. Optionally, current source 32 and / or the additional current source 52 are adjustable current sources. This means that the current level of a current supplied by the respective current source 32, 52 can be adjusted by the controller 31. In test mode, the Fig. 9 shown electronic circuit 2 in the same way as the one in Fig. The electronic circuit shown in Figure 7 operates. In control mode, the controller 31 activates or deactivates the current sources 32, 52, for example by switching the associated switches 33, 53 on or off, depending on the input signal S. IN The controller 31 specifically activates the power source 32 and deactivates the other power source 52 when the input signal S IN indicates that it is desired to switch on transistor element 1. If the input signal S INWhen the signal indicates that transistor element 1 should be switched off, controller 31 deactivates current source 32 and activates the other current source 52. The latter discharges the gate-source capacitance C. GS , to switch off transistor element 1. In drive mode, the first resistor 21 fulfills a safety function. The first resistor 21 discharges the gate-source capacitance C. GS , if the other power source 52 is defective and the gate-source capacitance C GS does not discharge. Resistor 21 discharges the gate-source capacitance C. GS However, it is significantly slower than the current source 52, so that the resistor 21 does not significantly affect the control of the transistor component 1 by the current source 32 and the further current source 52, if the electronic circuit 2 is working correctly.

[0034] According to an example, at least one of the reference voltage levels V0, V1, and V2 is used by the electronic circuit 2 in control mode. This is demonstrated by Fig. 10 explained. Fig. Figure 10 shows signal waveforms of the input signal S IN , of a gate current I G and the gate-source voltage V GS In this example, controller 31 adjusts the gate current I. G , which is driven into the gate node G, by adjusting the current level of the current supplied by the current source 32 depending on the gate-source voltage V GS on. At the one in Fig. In example 10, t1 denotes a time at which a signal level of the input signal S IN from an output level (which is in Fig. 10 is represented by a low signal level) to a one-level (which is in Fig. 10 (represented by a high signal level) changes. When the signal level of the input signal S INWhen the controller 31 switches from the off level to the on level, it controls the current source 32 so that it supplies a gate current I G with a first current level I1. When the gate-source voltage V GS When the second voltage level V2 is reached, the controller 31 reduces the current level of the gate current I by controlling the current source 32. G to a second level I2, which is lower than the first level I1, until the gate-source voltage V GS the first voltage level V1 is reached. After the gate-source voltage V GS Once the first voltage level V1 has been reached, the controller 31 increases the current level of the gate current I by controlling the current source 32. G to a third level I3, which is higher than the second level I2. The third level I3 can be equal to the first level I1 or it can differ from the first level I1. Optionally, the controller 31 reduces the current level of the gate current I. Gto a fourth level I4, as is the case in Fig. Figure 10 shows when the gate-source voltage V GS the third level V0 is reached. According to an example, the second voltage level V2 is chosen such that it is essentially equal to the threshold voltage of transistor element 1. Due to the in Fig. The control sequence shown in 10 determines the gate-source capacitance C. GSThe transistor is rapidly charged by the first current level I1 until transistor 1 switches on and enters the Miller phase. During the Miller phase, the current is reduced to the second level I2 and then increased again (to the third level I3) after the Miller phase. In this example, the end of the Miller phase is represented by the first voltage level V1. For example, the second voltage level V2 is selected from a range between 0.5V and 1.5V, and the first voltage level V1 is selected from a range between 2V and 5V. The optional third voltage level V0 is selected, for example, from a range between 7V and 12V. The fourth current level I4 can be chosen to match the gate-source voltage V1. GS at the third level V0. In particular, this fourth current level I4 is chosen such that it prevents the discharge of the gate-source capacitance C. GS compensated by the first resistance 21.

[0035] If the signal level of the input signal S IN switching from the on level to the off level, as is the case at time t2 in Fig. As shown in Figure 10, the controller 31 deactivates the power source 32 and activates the other power source 52. Referring to Fig. 10 can include switching off the transistor element: a rapid discharge of the gate-source capacitance C GS after time t2 and until the gate-source capacitance C GS the first voltage level V1 is reached, the discharge of the gate-source capacitance C slows down GS , if the gate-source voltage V GS between the first voltage level V1 and the second voltage level V2, and a renewed rapid discharge of the gate-source capacitance C GS , if the gate-source voltage V GS below the second voltage level V2 and until the gate-source voltage V GS zero reached. In Fig. 10 represent the negative current levels of the current IG After time t2, the current level of the discharge current flows in a direction opposite to the direction of the charging current. The magnitudes of the discharge current levels in the different phases of the discharge process can be equal to the magnitude of the charging current in the different phases of the charging process, that is, (1) the magnitude of the gate current I G in the first phase of the charging process, when the gate-source voltage V GS The voltage between zero and the second voltage level V2 can be equal to the magnitude of the gate current in a third phase of the discharge process when the gate-source voltage V GS also between zero and the second voltage level V2; (2) the magnitude of the gate current I G in the second phase of the discharge process, when the gate-source voltage V GSThe difference between the second voltage level V2 and the first voltage level V1 can be equal to the magnitude of the gate current in a second phase of the discharge process when the gate-source voltage V GS also between the second voltage level V2 and the first voltage level V1; and (3) the magnitude of the gate current I G in the third phase of the charging process, when the gate-source voltage V GS The difference between the first voltage level V1 and the third voltage level V0 can be equal to the amount of gate current in a first phase of the discharge process when the gate-source voltage V GS also between the first voltage level V1 and the third voltage level V0.

[0036] However, this is just one example of the same number of phases in the charging and discharging processes, and the same current level in the corresponding phases. The discharging process can have more or fewer phases than the charging process, and these phases can be defined by voltage levels that differ from the first, second, and third levels V1, V2, V0 that define the charging process. Furthermore, the gate current levels in the corresponding phases can differ, even if the same number of phases are present in both the charging and discharging processes and the phases are defined by the same voltage levels.

[0037] Referring to the information in the Fig. 9 and Fig. In the 10 examples shown, the first and second voltage levels V1, V2 can be chosen such that the transistor element 1 is in the on state when the gate-source voltage V GS between these voltage levels. According to another example, these voltage levels V1 and V2 are each chosen such that they are below the threshold voltage of the transistor component. This allows testing of transistor component 1 without switching it on. In an electronic circuit of the in Fig. In this example, of the type shown, which can operate in test mode and in drive mode, additional reference voltage sources and comparators can be used: reference voltage sources and comparators used for testing the transistor device, and reference voltage sources and comparators used for driving the transistor device.

[0038] It should be noted that features explained with reference to specific figures can be combined with features of other figures, even in cases where this is not explicitly mentioned. Furthermore, the methods of the invention can be achieved as pure software implementations using suitable processor instructions or as hybrid implementations that use a combination of hardware logic and software logic to achieve the same results.

[0039] Spatially relative terms such as "under," "below," "lower," "above," "upper," and similar terms are used to simplify the description and describe the positioning of one element relative to another. These terms are intended to encompass various orientations in addition to those described in the figures. Furthermore, terms like "first," "second," and similar terms are also used to designate different elements, areas, sections, etc., and should not be considered restrictive. Identical features refer to identical elements within the description.

[0040] The terms used herein, such as "containing," "encompassing," "exhibiting," and similar expressions, are open terms that indicate the presence of the designated element or feature but do not exclude additional elements or features. The articles "a" and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise.

Claims

[1] Method which features: Discharging a gate-source capacitance (C GS ) of a transistor device (1) from a first voltage level (V1) to a second voltage level (V2) when a first resistor (21) is connected in parallel to the gate-source capacitance (C GS ) is switched on, and measuring a first discharge time (T1) in connection with the discharge; Discharge of the gate-source capacitance (C GS ) from the first voltage level (V1) to the second voltage level (V2) when the first resistor (21) and a second resistor (22) are connected in parallel to the gate-source capacitance (C GS ) are switched on, and measuring a second discharge time (T2) in connection with the discharge; Comparing the ratio between the first discharge time (T1) and the second discharge time (T2) with a predefined threshold; and Detecting a fault based on comparison. [2] Method according to claim 1, where the first resistor (21) has a first resistance value and the second resistor (22) has a second resistance value, where the second resistance value is m times the first resistance value and where an error is detected if the ratio is less than 0.999 times (m+1) / m. [3] Method according to claim 2, wherein a fault is detected when the ratio is less than 0.9 times (m+1) / m. [4] Method according to any one of the preceding claims, wherein at least one of the first voltage level (V1) and the second voltage level (V2) is below a threshold voltage of the transistor element (1). [5] Method according to claim 4, wherein the first voltage level (V1) and the second voltage level (V2) are each below the threshold voltage of the transistor device. [6] Method according to any one of the preceding claims, wherein the transistor device (1) is an IGBT or a MOSFET. [7] A method according to any one of the preceding claims, further comprising: Charging the gate-source capacity (C GS ) to a voltage level that is higher than the initial voltage level (V1) before each discharge. [8] Circuit arrangement which includes: a transistor device (1) with a gate node (G), a source node (S), a gate-source capacitance (C) GS ) between the gate node (G) and the source node (S) and a gate-source resistor (R) GS ) between the gate node (G) and the source node (S); an electronic circuit (2) which is connected between the gate node (G) and the source node (S) and which has a control circuit (3), a first resistor (21) connected between the gate node (G) and the source node (S) and a second resistor (22), wherein the control circuit (3) is designed to in a first test cycle, an initial discharge time (T1) in connection with a discharge of the gate-source capacitance (C) GS ) to measure from a first voltage level (V1) to a second voltage level (V2), in a second test cycle to connect the second resistor (22) between the gate node (G) and the source node (S) and a second discharge time (T2) in connection with a discharge of the gate-source capacitance (C) GS ) to measure from the first voltage level (V1) to the second voltage level (V2), to compare a ratio between the first discharge time (T1) and the second discharge time (T2) with a predefined threshold and to detect an error based on comparison. [9] Circuit arrangement according to claim 8, further comprising an electronic switch (23) in series with the second resistor (22), wherein a series circuit with the electronic switch (23) and the second resistor (22) is connected between the gate node (G) and the source node (S) and where the switching of the second resistor (22) in parallel with the gate-source capacitance (C GS ) by the control circuit (3) the switching on of the electronic switch (23). [10] Circuit arrangement according to claim 8 or 9, where the first resistor (21) has a first resistance value and the second resistor (22) has a second resistance value, where the first resistance value is m times the second resistance value and where the control circuit is designed to detect a fault when the ratio is less than 0.999 times (m+1) / m. [11] Circuit arrangement according to any one of claims 8 to 10, wherein the control circuit (3) comprises: a first current source (32) configured to supply the gate-source capacitance (C GS ) to load; a comparator arrangement (351, 352, 361, 362) configured to apply a gate-source voltage (V GS ) to compare the first voltage level (V1) and the second voltage level (V2) between the gate node (G) and the source node (S) and to generate at least one comparator signal (S361, S362) based on the comparison; and a controller (31) designed to receive the at least one comparator signal (S361, S362) and to measure the first and second discharge time (T1, T2) based on the at least one comparator signal (S361, S362). [12] Circuit arrangement according to claim 11, wherein the first current source (32) is connected between the gate node (G) and a supply node at which a supply potential (V34) is available. [13] Electronic circuit according to any one of claims 8 to 12, wherein the electronic circuit (2) further comprises: a second power source (52) which is connected between the gate node (G) and the source node (S). [14] Circuit arrangement according to claim 13, in which the controller (31) is trained to operate in a test mode and a control mode, and in which the controller (31) is trained in test mode to select the first current source (32) and the second current source (52) based on an input signal (S IN ) to head towards. [15] Circuit arrangement according to claim 14, wherein the controller is configured to operate in control mode to activate the first current source (32) and deactivate the second current source (52) when the input signal (S IN ) has a first signal level, and to deactivate the first current source (32) and activate the second current source (52) when the input signal (S IN ) has a second signal level. [16] Circuit arrangement according to claim 14 or 15, wherein the controller (31) is configured to adjust a current provided by the first current source (32) in control mode based on a comparison of a voltage (V GS) between the gate node (G) and the source node (S) with at least one of a first voltage level and a second voltage level. [17] Circuit arrangement according to any one of claims 8 to 16, wherein the transistor element (1) is an IGBT or a MOSFET. [18] Electronic circuit designed to be connected to a gate node (G) and a source node (S) of a transistor device (1) and comprising: a first resistor (21) and a second resistor (22), each configured to be connected between the gate node (G) and the source node (S), and a control circuit (3), wherein the control circuit (3) is configured to in a first test cycle, an initial discharge time (T1) in connection with a discharge of the gate-source capacitance (C) GS) to measure from a first current level (V1) to a second current level (V2) when the first resistor (21) is connected between the gate node (G) and the source node (S), in a second test cycle a second discharge time (T2), in connection with a discharge of the gate-source capacitance (C) GS ) to measure from the first voltage level (V1) to the second voltage level (V2) when the first resistor (21) and the second resistor (22) are connected between the gate node (G) and the source node (S), to compare a ratio between the first discharge time (T1) and the second discharge time (T2) with a predefined threshold, and to detect an error based on comparison.

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