Multilayer ceramic capacitors

Abstract

The present invention provides a multilayer ceramic capacitor that has improved moisture resistance reliability. and that can suppress the occurrence of cracks in external electrodes. This multilayer ceramic capacitor (1) comprises: metal layers (41a, 41b) in which external electrodes are disposed on a first end face (E1) and a second end face (E2) to cover an internal electrode drawn out to the first end face (E1) and an internal electrode drawn out to the second end face (E2); glass films (42a, 42b) disposed on the first end face (E1) and the second end face (E2), adjacent to the metal layers (41a, 41b) and around the metal layers (41a, 41b); baked layers (43a, 43b) containing glass and metal and disposed to cover the metal layers (41a, 41b); and plating films (44a, 44b) disposed to cover the baked layers (43a, 43b). The baked layers (43a, 43b) have voids, and a plating material is present in at least a portion of the voids.

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] 2. Description of the Related Art Multilayer ceramic capacitors are known that include a laminate in which dielectric layers and internal electrodes are alternately stacked, and external electrodes that are electrically connected to the internal electrodes and are provided on the surfaces of the laminate. Patent Document 1 describes a method for forming external electrodes on a multilayer ceramic capacitor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-266208 Summary of the Invention [Problem to be solved by the invention]

[0004] Multilayer ceramic capacitors with external electrodes have the problem of insufficient moisture resistance reliability, and one of the causes of this is the occurrence of cracks in the external electrodes.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks in external electrodes and has improved moisture resistance reliability. [Means for solving the problem]

[0006] The multilayer ceramic capacitor of the present invention comprises: a laminate in which a plurality of dielectric layers and internal electrodes are alternately stacked; a pair of external electrodes provided on a surface of the laminate and electrically connected to the internal electrodes drawn out to the surface of the laminate; The laminate is a first main surface and a second main surface that face each other in a thickness direction, which is a lamination direction of the dielectric layers and the internal electrodes; a first end surface and a second end surface on which the pair of external electrodes are provided, the first end surface and the second end surface facing each other in a longitudinal direction, which is a direction in which the pair of external electrodes are opposed to each other; a first side surface and a second side surface that face each other in a width direction perpendicular to the thickness direction and the length direction; The external electrode is a metal layer disposed on the first end face and the second end face so as to cover the internal electrodes extended to the first end face and the internal electrodes extended to the second end face; a glass film disposed on the first end surface and the second end surface adjacent to and surrounding the metal layer; a baking layer including glass and metal and disposed over the metal layer; a plating film disposed so as to cover the baked layer, The baked layer has voids, The plating material is present in at least a portion of the gap. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can suppress the occurrence of cracks in the external electrodes and has improved moisture resistance reliability. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view of a multilayer ceramic capacitor according to the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line II in FIG. [Figure 3] FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 5] FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] An example of an embodiment of the present invention will be described below with reference to the accompanying drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0010] <External view of multilayer ceramic capacitor> The outline of the appearance of the multilayer ceramic capacitor 1 will be described with reference to Fig. 1. Fig. 1 is a perspective view showing the multilayer ceramic capacitor 1 of this embodiment. 1, the multilayer ceramic capacitor 1 includes a laminate 2 and external electrodes 4 (4a, 4b). The external electrodes 4 include a first external electrode 4a and a second external electrode 4b.

[0011] <Direction definition> 1 to 5 show the L direction, W direction, and T direction. The L direction is the length direction L of the multilayer ceramic capacitor 1. The W direction is the width direction W of the multilayer ceramic capacitor 1. The T direction is the stacking direction of the multilayer ceramic capacitor 1, i.e., the thickness direction T. Therefore, the cross sections shown in Figures 2 and 4 are called LT cross sections, and the cross sections shown in Figures 3 and 5 are called WT cross sections. The length direction L, width direction W, and thickness direction T do not necessarily have to be perpendicular to each other, but may be intersecting each other.

[0012] <External shape of laminate> As shown in FIG. 1, the laminate 2 has a substantially rectangular parallelepiped shape. The laminate has two end faces, two main faces and two side faces. The end faces are surfaces facing the length direction L. The main faces are surfaces facing the thickness direction T. The side faces are surfaces facing the width direction W. The two end faces are referred to as a first end face E1 and a second end face E2. The two main faces are referred to as a first main face M1 and a second main face M2. The two side faces are referred to as a first side face S1 and a second side face S2.

[0013] It is preferable that the corners and ridges of the laminate 2 are rounded. A corner is a portion where three surfaces of the laminate 2 intersect. A ridge is a portion where two surfaces of the laminate 2 intersect.

[0014] <Size of laminate> The size of the laminate 2 can be, for example, as follows. The length in the length direction L of the laminate 2 can be 200 μm or more and 2000 μm or less. The length in the thickness direction of the laminate 2 can be 100 μm or more and 1000 μm or less. The length in the width direction W of the laminate 2 can be 100 μm or more and 1000 μm or less. The length of each portion of the laminate 2 can be measured using a micrometer or an optical microscope.

[0015] <Internal structure of laminate> The internal structure of the laminate 2 will be described with reference to FIGS. Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor taken along line II in Fig. 1. Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor taken along line III-III in Fig. 1.

[0016] 2, the laminate 2 has a plurality of dielectric layers 7 (7a, 7b) and a plurality of internal electrodes 8 (8a, 8b). The plurality of dielectric layers 7 and the plurality of internal electrodes 8 are stacked on top of each other in the thickness direction T.

[0017] <Dielectric layer> As shown in FIG. 2, the dielectric layer 7 includes an outer dielectric layer 7a and an inner dielectric layer 7b. <Outer dielectric layer> The outer dielectric layers 7a are the dielectric layers 7 located on the first principal surface M1 side and the second principal surface M2 side of the laminate 2. In other words, the outer dielectric layers 7a are the dielectric layers 7 located on both outer sides of the laminate 2 in the thickness direction T. Specifically, the outer dielectric layer 7a is a dielectric layer 7 located between the first main surface M1 and the internal electrode 8 closest to the first main surface M1, and between the second main surface M2 and the internal electrode 8 closest to the second main surface M2. <Inner dielectric layer> The inner dielectric layer 7b is a dielectric layer 7 located between the internal electrodes 8. Specifically, the inner dielectric layer 7b is a dielectric layer 7 located between a first inner electrode 8a and a second inner electrode 8b, which will be described below.

[0018] <Internal electrode> 2, the internal electrodes 8 include a first internal electrode 8a and a second internal electrode 8b. The first internal electrode 8a is an internal electrode connected to the first external electrode 4a. The second internal electrode 8b is an internal electrode connected to the second external electrode 4b. The first inner electrode 8a extends from the first end face E1 toward the second end face E2, and the second inner electrode 8b extends from the second end face E2 toward the first end face E1.

[0019] <Facing part and pull-out part> The first internal electrode 8a and the second internal electrode 8b each have an opposing portion and an extended portion. The facing portion is a portion where the first inner electrode 8a and the second inner electrode 8b face each other. The extended portions are portions extended from the opposing portions to the end faces E1, E2 of the laminate 2. Specifically, the extended portion of the first inner electrode 8a is a portion extended from the opposing portion to the first end face E1 of the laminate 2. The extended portion of the second inner electrode 8b is a portion extended from the opposing portion to the second end face E2 of the laminate 2. The opposing portions of the first internal electrodes 8a and the second internal electrodes 8b face each other with the inner dielectric layer 7b interposed therebetween, thereby forming capacitance at the opposing portions, and the multilayer ceramic capacitor 1 functions as a capacitor.

[0020] <Length direction gap> The region from the tip of the first inner electrode 8a on the second end face E2 side to the second end face E2 is defined as a longitudinal gap LG, as shown in Fig. 2. Similarly, the region from the tip of the second inner electrode 8b on the first end face E1 side to the first end face E1 is defined as a longitudinal gap LG. The length in the longitudinal direction L of the longitudinal gap LG can be set to, for example, 5 μm or more and 30 μm or less.

[0021] <Width direction gap> The region from the end of the internal electrode 8 in the width direction W to the first side surface S1 is defined as a widthwise gap WG, as shown in Fig. 3. Similarly, the region from the end of the internal electrode 8 in the width direction W to the second side surface S2 is defined as a widthwise gap WG. The length of the width direction W of the widthwise gap WG can be set to, for example, 5 μm or more and 30 μm or less.

[0022] <Number of dielectric layers> The number of dielectric layers 7 stacked in the laminate 2 can be, for example, from 10 to 1000. This number of dielectric layers 7 includes the number of outer dielectric layers 7a and the number of inner dielectric layers 7b.

[0023] <Thickness of dielectric layer> Of the dielectric layers 7, the outer dielectric layer 7a may have a thickness of, for example, 10 μm or more and 100 μm or less, and the inner dielectric layer 7b may have a thickness of, for example, 0.3 μm or more and 5.0 μm or less.

[0024] <Dielectric layer material> The material of the dielectric layer 7 can be, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3. The material of the dielectric layer 7 may be the above-mentioned dielectric ceramic to which a Mn compound, an Fe compound, a Cr compound, a Co compound, an Ni compound, or the like has been added.

[0025] <Number of internal electrodes> The number of the internal electrodes 8 can be, for example, from 10 to 1000. This number of the internal electrodes 8 includes the number of the first internal electrodes 8a and the number of the second internal electrodes 8b.

[0026] <Internal electrode thickness> The thickness of the internal electrode 8 can be, for example, 0.3 μm or more and 5.0 μm or less. If the thickness of the internal electrode 8 is 0.5 μm or more, a plating film tends to grow easily when a metal layer is formed by plating. The metal layer will be described later.

[0027] <Internal electrode material> The material of the internal electrodes 8 can be, for example, metals such as Ni, Cu, Ag, Pd, and Au, or alloys of Ni and Cu, alloys of Ag and Pd, etc. In addition, the material of the internal electrodes 8 may contain dielectric particles having the same composition as the ceramic contained in the dielectric layers 7.

[0028] <External electrode> As explained based on FIG. 1, the external electrodes include the first external electrode 4a and the second external electrode 4b. <First external electrode> The first external electrode 4a is an external electrode disposed on the first end face E1 of the laminate 2, as shown in FIG. The first external electrode 4a extends from the first end face E1 to parts of the two main faces and parts of the two side faces. Of the first external electrode 4a, the portion arranged on the first end face E1 of the laminate 2 is referred to as an end face external electrode 4Ea. Of the first external electrode 4a, the portion arranged on a part of the first main face M1 or a part of the second main face M2 is referred to as a main face external electrode 4Ma. Of the first external electrode 4a, the portion arranged on a part of the first side face S1 or a part of the second side face S2 is referred to as a side face external electrode 4Sa. As shown in FIG. 2, the first outer electrode 4a is electrically connected to the first inner electrode 8a.

[0029] <Second external electrode> The second external electrode 4b is an external electrode disposed on the second end face E2 of the laminate 2. The second external electrode 4b has a configuration similar to that of the first external electrode 4a. That is, the second external electrode 4b extends from the second end face E2 to parts of the two main faces and parts of the two side faces. Of the second external electrode 4b, the portion arranged on the second end face E2 of the laminate 2 is referred to as an end face external electrode 4Eb. Of the second external electrode 4b, the portion arranged on a part of the first main face M1 or a part of the second main face M2 is referred to as a main face external electrode 4Mb. Of the second external electrode 4b, the portion arranged on a part of the first side face S1 or a part of the second side face S2 is referred to as a side face external electrode 4Sb. As shown in FIG. 2, the second outer electrode 4b is electrically connected to the second inner electrode 8b.

[0030] <Layer structure of external electrodes> The layer structure of the external electrode 4 will be described with reference to FIG. 2, the first external electrode 4a has a metal layer 41a, a glass film 42a, a baking layer 43a, and a plating film 44a. The second external electrode 4b has a metal layer 41b, a glass film 42b, a baking layer 43b, and a plating film 44b. Each layer of the external electrode 4 will be described using the first external electrode 4a as an example. Each layer of the second external electrode 4b has the same configuration as each layer of the first external electrode 4. Therefore, the explanation about the first external electrode 4a also applies to the second external electrode 4b.

[0031] <Metal layer> An end portion of the first inner electrode 8a is exposed from the end face E1. The metal layer 41a is a metal layer provided on the first end face E1 so as to cover the exposed end portion of the first inner electrode 8a. The metal layer 41a is formed from a material containing at least one metal selected from, for example, Cu, Ni, Ag, Pd, and Au, etc. The metal layer 41a may also be formed from an alloy such as an alloy of Cu and Ni or an alloy of Ag and Pd, for example. A part of the material forming the metal layer 41a may be diffused into the first internal electrode 8a that is in contact with the metal layer 41a. By mixing and intermixing the material forming the metal layer 41a and the material forming the first internal electrode 8a, the bonding strength between the metal layer 41a and the first internal electrode 8a can be increased.

[0032] The metal layer 41a can be formed by, for example, plating.

[0033] <Thickness of metal layer> In FIG. 2, the thickness of the metal layer 41a is indicated by d1. The thickness d1 of the metal layer 41a can be set to, for example, not less than 0.1 μm and not more than 15.0 μm. If the thickness d1 of the metal layer 41a is less than 0.1 μm, the continuity of the metal layer 41a is likely to decrease, which may result in a decrease in the bonding strength between the metal layer 41a and the first inner electrode 8a and a decrease in the conductivity of the metal layer 41a. If the thickness d1 of the metal layer 41a exceeds 15.0 μm, the internal stress in the metal layer 41a is likely to increase, which may cause the metal layer 41a to peel off from the first inner electrode 8a.

[0034] <Baking layer> The baking layer 43a is a layer disposed so as to cover at least a part of the metal layer 41a. The baking layer 43a includes glass and metal. The baking layer 43a is formed from a material containing at least one metal selected from, for example, Cu, Ni, Ag, Pd, Au, etc. The baking layer 43a may be a single layer or may include multiple layers.

[0035] The baking layer 43a can be formed, for example, as follows: First, a conductive paste is applied onto the metal layer 41a. The conductive paste contains glass and metal. Next, the applied conductive paste is fired. This allows the baking layer 43a to be formed. This firing, in other words, baking, can be carried out simultaneously with the firing of the laminate 2. Alternatively, the baking layer 43a can be fired after the laminate 2 has been fired. The baked layer 43a will be described in more detail later.

[0036] <Glass membrane> The glass film 42a is a film made mainly of glass and is disposed around the metal layer 41a. 2, the glass film 42a is disposed around the metal layer 41a so as to be adjacent to the metal layer 41a and surround the metal layer 41a. Specifically, the glass film 42a is in contact with the end 5 of the metal layer 41a. The glass film 42a extends from a portion of the first end face E1 to a portion of the first main surface M1 of the laminate 2. Similarly, the glass film 42a extends from a portion of the first end face E1 to a portion of the second main surface M2 of the laminate 2. Although not shown in FIG. 2, the glass film 42a extends from a part of the first end face E1 of the laminate 2 to a part of the first side face S1 and a part of the second side face S2.

[0037] The glass film 42a is formed together with the baking layer 43a during the formation of the baking layer 43. During the formation of the baking layer 43a, a conductive paste is applied to the first end face E1. This conductive paste contains glass. During the baking process, this glass moves to the portion where the dielectric layer 7 is exposed. The portion where the dielectric layer 7 is exposed is the portion of the laminate 2 where the metal layer 41a is not disposed. The glass moves to a portion of the first end face E1, a portion of the first main face M1, a portion of the second main face M2, a portion of the first side face S1, and a portion of the second side face S2. In this way, the glass that has moved to the portion where the dielectric layer 7 is exposed forms a glass film 42a after baking is completed.

[0038] As described above, during baking, the glass contained in the conductive paste migrates to the exposed portion of the dielectric layer 7. Therefore, the glass content of the glass film 42a becomes higher than the glass content of the baking layer 43a.

[0039] In particular, it is preferable that the surface of the baking layer 43a has a low glass content. This is because the adhesion of the plating film 44a, which will be described later, to the surface of the baked layer 43a is improved, and also because the adhesion between the surface of the baked layer 43a and the plating film 44a is improved.

[0040] Here, the metal portion of the baking layer 43a is referred to as a metal portion, and the glass portion of the baking layer 43a is referred to as a glass portion. On the surface of the baking layer 43a facing the plating film 44a, the area of ​​the metal portion is preferably 10 times or more larger than the area of ​​the glass portion. This can sufficiently improve the adhesion of the plating film 44a to the baked layer 43a, and also the adhesion between the baked layer 43a and the plating film 44a.

[0041] The glass film 42a does not have to be made of glass alone. The glass film 42a may contain other materials, such as metal materials, in addition to glass. However, it is preferable that the glass film 42a contain a higher percentage of glass. This is because a higher percentage of glass is more effective in suppressing moisture penetration into the interior of the laminate 2, as will be described later.

[0042] As described above, the glass film 42a is in contact with the end 5 of the metal layer 41a and is disposed adjacent to the metal layer 41a so as to surround the periphery of the metal layer 41a. In other words, the end 5 of the metal layer 41a is buried and sealed with the glass film 42a. This makes it possible to prevent moisture from entering the interface between the dielectric layer 7 and the internal electrode 8 from around the metal layer 41a.

[0043] From the viewpoint of suppressing the penetration of moisture, it is preferable that the glass film 42a be in contact with the end 5 without any breaks around the entire periphery of the metal layer 41a, and further cover the entire periphery of the metal layer 41a.

[0044] Whether or not the glass film 42a is formed on the surface of the laminate 2 can be determined by appropriately polishing the laminate 2 and performing elemental analysis on the polished portion using a field emission wavelength dispersive X-ray spectrometer.

[0045] <Plating film> The plating film 44a is a film made of metal and formed by plating. The plating film 44a is disposed so as to cover the baked layer 43a. The plating film 44a is formed from a material containing at least one metal selected from the group consisting of Cu, Ni, Ag, Pd, and Au. The plating film 44a may be formed from an alloy such as an alloy of Ag and Pd. The plating film 44a does not include glass.

[0046] The plating film 44a includes a lower-layer plating film and an upper-layer plating film. The upper-layer plating film is a plating film formed on the lower-layer plating film. The lower plating film is formed from a material containing at least one metal selected from the group consisting of Cu, Ni, Ag, Pd, an alloy of Ag and Pd, and Au. The upper layer plating film is formed using, for example, Sn as a material. By using Sn as the material for the upper layer plating film, the wettability of the solder to the first external electrode 4a can be improved. The thickness of the upper plating film can be set to, for example, 1 μm or more and 10 μm or less, and the thickness of the plating films 44a and 44b can also be set to, for example, 1 μm or more and 10 μm or less.

[0047] The above description of the first external electrode 4a also applies to the second external electrode 4b, because the first external electrode 4a and the second external electrode 4b are the same except for the surfaces on which they are provided. Therefore, the metal layer 41b, glass film 42b, baked layer 43b, and plated film 44b of the second external electrode 4b are the same as the respective members described for the first external electrode 4a.

[0048] <Size of multilayer ceramic capacitor> The length in the length direction L of the entire multilayer ceramic capacitor 1, including the laminate 2 and the external electrodes 4, can be, for example, 0.2 mm or more and 2.0 mm or less. The length in the thickness direction T of the entire multilayer ceramic capacitor 1 can be, for example, 0.1 mm or more and 1.2 mm or less. The length in the width direction W of the entire multilayer ceramic capacitor 1 can be, for example, 0.1 mm or more and 1.2 mm or less.

[0049] <Details of external electrodes> The external electrode 4 will be described in detail with reference to FIG. As mentioned above, Fig. 2 is a cross-sectional view taken along line II in Fig. 1. Here, the cross-sectional view taken along line II is a cross-sectional view taken along line LT at the center position in the width direction W of the multilayer ceramic capacitor 1. 3 shows the center position in the width direction W. The position of line I in FIG. 3 is the center position in the width direction W of the multilayer ceramic capacitor 1. FIG. 3 is a cross-sectional view taken along III-III in FIG. 1. FIG. 3 is a view showing a WT cross section of the multilayer ceramic capacitor 1. The LT cross section at the center position in the width direction W of the multilayer ceramic capacitor 1 shown in FIG. 2 is defined as a 1 / 2 LT cross section.

[0050] The external electrode 4 will be described below using the first external electrode 4a as an example. The second external electrode 4b has a similar configuration to the first external electrode 4a. Therefore, the following description also applies to the second external electrode 4b.

[0051] <Metal layer and glass film> 2, a metal layer 41a is disposed over almost the entire first end face E1. However, on the first end face E1, a glass film 42a is disposed in place of the metal layer 41a in the vicinity of the first main surface M1 and the second main surface M2. The glass film 42a contacts the end 5 of the metal layer 41a. 2, the glass film 42a is also disposed on the first end face E1 in the vicinity of the first side face S1 and in the vicinity of the second side face S2. The glass film 42a also contacts the end 5 of the metal layer 41a. As described above, the glass film 42a is disposed so as to cover the periphery of the metal layer 41a.

[0052] More specifically, the glass film 42a on the first end face E1 extends from the end 5 of the metal layer 41a to a part of the first main surface M1 and a part of the second main surface M2. Further, although not shown in FIG. 2, this glass film 42a extends from the end portion 5 of the metal layer 41a to a part of the first side surface S1 and a part of the second side surface S2. That is, the glass film 42a is disposed so as to cover the ridge line portion of the laminate 2 between the first end surface and both main surfaces and both side surfaces.

[0053] <Baked layer> The baked layer 43a is disposed over the entire area of the first end surface E1 at the central position in the width direction W, i.e., the 1 / 2LT cross section. Further, the baked layer 43a extends from the first end surface E1 to a part of the first main surface M1 and a part of the second main surface M2. Furthermore, although not shown in FIG. 2, the baked layer 43a extends from the first end surface E1 to a part of the first side surface S1 and a part of the second side surface S2.

[0054] Further, the baked layer 43a is disposed so as to cover the entire metal layer 41a and the glass film 42a. Therefore, at the central position in the width direction W of the multilayer ceramic capacitor 1, neither the metal layer 41a nor the glass film 42a is exposed from the baked layer 43a.

[0055] <Plated film> The plated film 44a is disposed so as to cover the entire baked layer 43a. That is, the plated film 44a is disposed on the first end surface E1 and a part of the two main surfaces beyond the range where the baked layer 43a is disposed. Further, although not shown in FIG. 2, the plated film 44a is also disposed on a part of the two side surfaces, similar to the two main surfaces.

[0056] <WT cross section> Based on the WT cross-sectional view of the multilayer ceramic capacitor 1, the arrangement of the first external electrode 4a will be described. FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1 as described above. FIG. 3 is a view showing the WT cross section at the line L1 in FIG. 2. As shown in FIG. 3, outside the laminate 2, a glass film 42a is disposed so as to surround the entire periphery of the laminate 2. A baking layer 43a is disposed on the outside of the glass film 42a so as to surround the entire periphery of the glass film 42a. Furthermore, a plating film 44a is disposed on the outside of the baked layer 43a so as to surround the entire periphery of the baked layer 43a.

[0057] <Gaps in the baked layer> The voids 6 in the baked layer 43a will be described with reference to Fig. 2. Fig. 2 is a diagram showing a ½ LT cross section of the multilayer ceramic capacitor 1. In the multilayer ceramic capacitor 1 of this embodiment, voids 6 are formed in the baked layer 43a. The voids 6 are portions of the baking layer 43a that are not filled with glass or metal. The glass and metal here refer to the glass and metal contained in the conductive paste used to form the baking layer 43a.

[0058] <Location of the gap> As shown in FIG. 2, the voids 6 are formed throughout the thickness of the baked layer 43a. However, it is preferable that the gap 6 is formed at least in a portion close to the metal layer 41a. Specifically, it is preferable that at least one of the voids 6 is formed in a range closer to the metal layer 41a than half the thickness d2 of the baked layer 43a from the surface of the baked layer 43a. 2 indicates the thickness d2 of the baked layer 43a. Also, the distance d3 shown in Fig. 2 indicates half the thickness d2 of the baked layer 43a from the surface of the metal layer 41a. At least one of the voids 6 is preferably located within a distance d3 from the surface of the metal layer 41a.

[0059] The thickness d2 of the baking layer 43a can be set to, for example, 1.0 μm or more and 100.0 μm or less, and this thickness is the thickness of the thickest part of the baking layer 43a.

[0060] <Filling of plating material> A plating film 44a is formed on the outside of the baked layer 43a, and therefore, the plating material is present in at least a part of the gap 6. This is because the plating material enters the gap 6 when the plating film 44a is formed.

[0061] <Void ratio> The ratio of the voids 6 in the baked layer 43a is not particularly limited, but is preferably within the following range. As described above, plating material is present in at least a portion of the voids 6. Therefore, the ratio of the voids 6 in the baked layer 43a is defined by the area ratio of the plating material in the WT cross section. Specifically, in the baked layer 43a of the first end face E1, a plane parallel to the first end face E1 is viewed from the surface of the baked layer 43a at a position 3 / 4 of the thickness d2 of the baked layer 43a. That is, the WT cross section is viewed at a position half the distance d3 from the surface of the metal layer 41a. In this WT cross section, the ratio of the area of ​​the plated material to the area of ​​the entire baked layer 43a is preferably 20% or more and 90% or less.

[0062] <1 / 2LT cross section and side end LT cross section> The external electrode 4 in the vicinity of the widthwise gap WG will be described with reference to FIGS. Fig. 4 is a cross-sectional view taken along line II-II in Fig. 1. Fig. 5 is a cross-sectional view taken along line IV-IV in Fig. 1. In the multilayer ceramic capacitor 1 of this embodiment, the arrangement of the external electrodes 4 differs between the central position in the width direction W and positions close to the side surfaces in the width direction W. In other words, the shape of the external electrodes 4 differs between the LT cross section taken along line I in FIG. 3 and the LT cross section taken along line II in FIG. 3.

[0063] The above description of the LT cross section based on Fig. 2 was about the central position in the width direction W. Below, a position close to the side surface in the width direction W will be described based on Fig. 4. 4 is a diagram showing an LT cross section at the position of the end face on the first side surface S1 side of the internal electrode 8. FIG. 4 is a diagram showing an LT cross section at line II in FIG. Hereinafter, the position of the end face of the internal electrode 8 on the first side surface S1 side will be referred to as the side end position.

[0064] As described above, the LT cross section at the center position in the width direction W shown in Fig. 2 is defined as a 1 / 2LT cross section. In contrast, the LT cross section at the side edge position shown in Fig. 4 is defined as a side edge LT cross section.

[0065] As shown in FIG. 4, in the cross section of the side end LT in FIG. 4, the thickness of the baked layer 43a on the first end face E1 is thinner than in the cross section of ½ LT in FIG. The distance d2 and the distance d3 shown in FIG. 4 are the same as the distance d2 and the distance d3 shown in FIG. As shown in Fig. 2, the thickness of the baking layer 43a is d2 at the center position in the width direction W. In contrast, as shown in Fig. 4, the thickness of the baking layer 43a at the side edge positions is thinner than d3, which is half of d2.

[0066] Thus, the baked layer 43a is not formed with a uniform thickness on the surface of the metal layer 41a. The thickness of the baking layer 43a is greater near the center of the metal layer 41a than near the edges of the metal layer 41a. In other words, the thickness of the baking layer 43a decreases from near the center of the metal layer 41a toward the edges of the metal layer 41a.

[0067] <Ridge> The thickness of the baked layer 43a decreases from near the center of the metal layer 41a toward the ridges of the laminate 2. The thickness of the baked layer 43a also decreases from near the center of the metal layer 41a toward the corners of the laminate 2. First, the decrease towards the ridgeline will be explained. The thickness of the baked layer 43a decreases toward the four ridges of the first end face E1. The four ridges are defined by the first end face E1 and the first main face M1, the first end face E1 and the second main face M2, the first end face E1 and the first side face S1, and the first end face E1 and the second side face S2. As described above, the ridges are defined as the intersections of two faces of the laminate 2.

[0068] Furthermore, the thickness of the baking layer 43a also decreases from the center of the first end face E1 toward the four corners of the first end face E1. The four corners are formed by the first end face E1, the first main face M1, and the first side face S1; the first end face E1, the first main face M1, and the second side face S2; the first end face E1, the second main face M2, and the first side face S1; and the first end face E1, the second main face M2, and the second side face S2. As described above, the corners are the intersections of three faces of the laminate 2.

[0069] <Exposed metal layer> In this way, the thickness of the baked layer 43a decreases toward the four corners, so that at the side edge positions, the end portions 5 of the metal layer 41a are exposed from the baked layer 43a. 4 shows a state in which the end 5 of the metal layer 41a is not covered with the baked layer 43a at two locations in the thickness direction T. The end 5 of the metal layer 41a is also not covered with the baked layer 43a at the remaining two corners not shown in FIG. The following description will be based on the WT cross section of the multilayer ceramic capacitor 1.

[0070] Fig. 5 is a cross-sectional view taken along line IV-IV in Fig. 1. Fig. 5 shows a cross-section taken along line L2 in Fig. 4, taken along line WT. 5, a baking layer 43a is disposed around the metal layer 41a, but no baking layer 43a is disposed near the four corners of the metal layer 41a. As a result, the four ends 5 of the metal layer 41a are exposed from the baked layer 43a near the four corners where the end faces, the main face, and the side faces intersect.

[0071] <Effects> The multilayer ceramic capacitor 1 of this embodiment can prevent cracks from occurring in the external electrodes 4. Furthermore, the multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with improved moisture resistance reliability. <Conventional multilayer ceramic capacitors> In conventional multilayer ceramic capacitors in which metal layers are disposed on the external electrodes, cracks can occur in the metal layers. One cause of cracks in the metal layers is stress applied from other components. One such component is the baked layer. The baked layer is a layer disposed in contact with the metal layer. Changes in environmental temperature or humidity can cause stress in the baked layer, which is then applied to the metal layer, causing cracks in the metal layer. If cracks occur in the metal layer, the function of the metal layer to prevent moisture penetration is impaired. Furthermore, it is not easy to suppress moisture penetration by using other layers such as a baked layer, because the density of the other layers is inferior to that of the metal layer. Therefore, it is necessary to suppress the occurrence of cracks.

[0072] <Gaps in the baked layer> In the multilayer ceramic capacitor 1 of this embodiment, the baked layer 43a has voids 6. The baked layer 43a has voids 6, which reduces the stress of the baked layer 43a. As a result, the occurrence of cracks in the metal layer 41a can be suppressed.

[0073] In particular, when at least one of the voids 6 is located in a range closer to the metal layer 41a than 1 / 2 the thickness d2 of the baked layer 43a from the surface of the baked layer 43a, the occurrence of cracks in the metal layer 41a can be further suppressed. This is because the voids 6 are located in the vicinity of the metal layer 41a, which makes it easier to alleviate the stress that the metal layer 41a receives from the baked layer 43a.

[0074] Furthermore, when the voids 6 are located near the metal layer 41a, the stress in the baked layer 43a can be further reduced. As will be explained later, the baked layer 43a is formed by baking a conductive paste. Baked layer 43a that is baked more than necessary is likely to develop large stress. Furthermore, during the baking process, as the baking progresses, the voids 6 tend to disappear from the portion of the baked layer 43a that is close to the metal layer 41a. In the multilayer ceramic capacitor 1 of this embodiment, the voids 6 are present in the baked layer 43a in a portion close to the metal layer 41a. In other words, the baked layer 43a is not baked more than necessary. This makes it difficult for large stresses to be generated in the baked layer 43a. As a result, it is possible to further suppress the occurrence of cracks in the metal layer 41a.

[0075] <Exposed metal layer> In the multilayer ceramic capacitor 1 of this embodiment, at least a portion of the metal layer 41a is exposed from the baked layer 43a. Specifically, when the metal layer 41a is viewed from the longitudinal direction L, the baked layer 43a is not disposed near the four corners of the metal layer 41a, and as a result, the areas near the four corners of the metal layer 41a are exposed from the baked layer 43a.

[0076] In the multilayer ceramic capacitor 1 of this embodiment, at least a portion of the metal layer 41a is exposed from the baked layer 43a, which can further prevent cracks from occurring in the metal layer 41a.

[0077] Since the metal layer 41a is exposed from the baked layer 43a, the exposed portion of the metal layer 41a is subjected to a weaker stress from the baked layer 43a, which makes it possible to prevent cracks from occurring in the metal layer 41a.

[0078] Furthermore, the exposed portions of the metal layer 41a are portions where the baked layer 43a is discontinued. The presence of discontinued portions in the baked layer 43a weakens the bonding in the planar direction of the baked layer 43a. This reduces the stress in the baked layer 43a. As a result, it is possible to prevent cracks from occurring in the metal layer 41a.

[0079] <Manufacturing method for multilayer ceramic capacitors> A general method for manufacturing the multilayer ceramic capacitor 1 will now be outlined. (1) Ceramic green sheets for the dielectric layers 7 and conductive paste for the internal electrodes 8 are prepared. (2) An internal electrode pattern is formed on the ceramic green sheet. The pattern can be formed by printing a conductive paste in a predetermined pattern on the ceramic green sheet. This printing can be performed by, for example, screen printing or gravure printing. (3) A plurality of ceramic green sheets for the outer dielectric layers, on which no internal electrode patterns are formed, are stacked. Ceramic green sheets on which internal electrode patterns are printed are stacked in turn on top of these. A plurality of ceramic green sheets for the outer dielectric layers are stacked on top of these. This produces a laminated sheet. (4) The laminated sheet is pressed in the thickness direction using a hydrostatic press or the like, thereby producing a laminated block. (5) The laminated block is cut to a predetermined size, thereby cutting out laminated chips. (6) The corners and ridges of the laminated chip are rounded by barrel polishing or the like. (7) The laminated chip is fired to obtain a fired laminate. (8) A metal layer is formed on the end surface of the fired laminate. Specifically, a metal layer is formed on the end surface so as to cover the internal electrodes drawn out to the end surface of the laminate. The metal layer can be formed by, for example, plating. The plating can be performed by electrolytic plating or electroless plating, and the plating method can be, for example, barrel plating. (9) A conductive paste for the baked layer is applied onto the metal layer. (10) The conductive paste is dried. After drying, baking is performed. As a result, baking layers 43a and 43b are formed. Furthermore, the glass contained in the conductive paste for baking layers 43a and 43b migrates to the surface of dielectric layer 7. This migrated glass then migrates to the surface of dielectric layer 7. This migrated glass becomes glass films 42a and 42b. (11) A plating film is formed on the baked layers 43a and 43b. Specifically, first, Ni plating is performed so as to cover the baked layers 43a and 43b. This forms a lower-layer plating film. Sn plating is performed thereon. This forms an upper-layer plating film.

[0080] <Features of the manufacturing method> In addition to the general method for manufacturing a multilayer ceramic capacitor described above, the manufacturing method of the multilayer ceramic capacitor 1 of this embodiment has the following features.

[0081] In the multilayer ceramic capacitor 1 of this embodiment, the baked layer 43a has voids 6. To form the voids 6, the baking temperature and baking time are optimized. Specifically, baking is performed at a temperature of 600°C or higher and 750°C or lower for 5 minutes or longer and 15 minutes or shorter. The temperature is more preferably 650°C or higher and 700°C or lower. The baking time is more preferably shorter than 15 minutes. This baking can be performed in an inert gas atmosphere such as nitrogen gas. The baking temperature is lower than the general baking temperature, and the baking time is shorter than the general baking time. In other words, the baking is slower than the general baking. By firing under these conditions, voids 6 can be formed in the fired layer 43a.

[0082] However, the above-mentioned firing does not form the glass film 42a. As described above, the glass film 42a is formed by the glass contained in the conductive paste for forming the baking layer 43a migrating to the portion where the dielectric layer 7 is exposed. In the above-mentioned firing, the glass does not move sufficiently, and therefore the glass film 42a is not formed. Therefore, in addition to the above-mentioned firing, firing is performed in an air atmosphere. This firing can be carried out in an air atmosphere at, for example, 700° C. for 5 minutes. By this firing in the air atmosphere, a baked layer 43a can be formed. Firing in the air atmosphere oxidizes metal particles such as Cu contained in the baking layer 43a. Glass then spreads over the surfaces of the oxidized metal particles, facilitating glass migration. The glass then spreads over the surface of the dielectric layer 7, which is made of an oxide such as BaTiO3, forming a glass film 42a.

[0083] <How to measure length> The length of each part of the multilayer ceramic capacitor 1 can be measured, for example, by observing the cross section of the laminate exposed by polishing with a scanning electron microscope. Each value can be the average value of measurements taken at multiple locations corresponding to the part to be measured.

[0084] <Moisture resistance reliability test> As a durability test, a humidity resistance reliability test was conducted. The samples and test conditions are as follows: (sample) Length in the length direction L: 0.6 mm Width W: 0.3 mm Length in thickness direction T: 0.3 mm Capacity: 2.2μF Thickness of inner dielectric layer 7b: 0.65 μm Thickness of internal electrode 8: 0.43 μm Number of internal electrodes 8: 280 Thickness of metal layers 41a and 141b: 5 μm (Moisture resistance reliability test) Temperature, humidity: 85℃ and 85%RH Voltage: 6.3V Voltage application time: 120 hours Criteria: A sample whose logarithmic value (log IR) of insulation resistance (IR) immediately after the start of the humidity reliability test was lowered by two or more orders of magnitude was judged to have IR degradation.

[0085] A moisture resistance reliability test was conducted using 72 samples according to the embodiment of the present invention and 72 conventional samples. The sample of the embodiment is a sample in which the baked layer 43a has voids 6. On the other hand, the conventional sample is a sample in which the baked layer 43a does not have voids. The results of the humidity resistance reliability test are as follows. In the samples of the embodiment, no IR degradation was observed in any of the 72 samples. On the other hand, among the 72 conventional samples, IR degradation was observed in 3 samples.

[0086] It is believed that in the conventional sample, cracks occurred in the metal layer during the humidity resistance reliability test, resulting in IR degradation. In contrast, in the sample of the embodiment, no cracks occurred in the metal layer during the moisture resistance reliability test, and as a result, it is believed that no IR degradation occurred.

[0087] The above test results show that the multilayer ceramic capacitor of this embodiment is capable of suppressing the occurrence of cracks in the external electrodes and is a multilayer ceramic capacitor with improved moisture resistance reliability.

[0088] The above explanation has been mainly based on the first external electrode 4a. As mentioned above, the explanation about the first external electrode 4a also applies to the second external electrode 4b. This is because the first external electrode 4a and the second external electrode 4b are the same except for the surfaces on which they are provided.

[0089] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various changes and modifications are possible.

[0090] <1> a laminate in which a plurality of dielectric layers and internal electrodes are alternately stacked; a pair of external electrodes provided on a surface of the laminate and electrically connected to the internal electrodes drawn out to the surface of the laminate; The laminate is a first main surface and a second main surface that face each other in a thickness direction, which is a lamination direction of the dielectric layers and the internal electrodes; a first end surface and a second end surface on which the pair of external electrodes are provided, the first end surface and the second end surface facing each other in a longitudinal direction, which is a direction in which the pair of external electrodes are opposed to each other; a first side surface and a second side surface that face each other in a width direction perpendicular to the thickness direction and the length direction; The external electrode is a metal layer disposed on the first end face and the second end face so as to cover the internal electrodes extended to the first end face and the internal electrodes extended to the second end face; a glass film disposed on the first end surface and the second end surface adjacent to and surrounding the metal layer; a baking layer including glass and metal and disposed over the metal layer; a plating film disposed so as to cover the baked layer, The baked layer has voids, A plating material is present in at least a portion of the void. Multilayer ceramic capacitor.

[0091] <2> At least one of the voids is located in a range closer to the metal layer than half the thickness of the baked layer from the surface of the baked layer. <1> The multilayer ceramic capacitor according to claim 1.

[0092] <3> At least a portion of the metal layer is exposed from the baked layer. <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0093] <4> The baked layer on the first end surface or the second end surface, The area ratio of the plated material at a position 3 / 4 of the thickness of the baked layer from the surface of the baked layer is 20% or more and 90% or less. <1> from <3> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes.

[0094] <5> The thickness of the metal layer is 0.1 μm or more and 15.0 μm or less. <1> from <4> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes.

[0095] <6> The thickness of the baking layer is 1.0 μm or more and 100.0 μm or less. <1> from <5> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes.

[0096] <7> A glass film is disposed around the metal layer and in contact with an end of the metal layer. <1> from <6> 10. The multilayer ceramic capacitor according to claim 9, wherein the first and second electrodes are electrically connected to the first and second electrodes. [Explanation of symbols]

[0097] 1. Multilayer ceramic capacitors 2. Laminate 4a First outer electrode 4b Second external electrode 4Ma, 4Mb main surface external electrode 4Ea, 4Eb Edge external electrode 4Sa, 4Sb side external electrode 41a, 41b metal layer 42a, 42b Glass membrane 43a, 43b Baking layer 44a, 44b Plating film 5 Edge of metal layer 6. Voids in the baked layer 7a Outer dielectric layer 7b Inner dielectric layer 8a First internal electrode 8b Second internal electrode M1 First main surface M2 Second main surface E1 First end face E2 Second end face S1 First aspect S2 Second Aspect L lengthwise T thickness direction W width direction

Claims

1. a laminate in which a plurality of dielectric layers and internal electrodes are alternately stacked; a pair of external electrodes provided on a surface of the laminate and electrically connected to the internal electrodes drawn out to the surface of the laminate; The laminate is a first main surface and a second main surface facing each other in a thickness direction, which is a lamination direction of the dielectric layers and the internal electrodes; a first end surface and a second end surface that face each other in a longitudinal direction, which is a direction in which the pair of external electrodes face each other, and on which the external electrodes are provided; a first side surface and a second side surface that face each other in a width direction perpendicular to the thickness direction and the length direction, The external electrode is a metal layer disposed on the first end face and the second end face so as to cover the internal electrodes extended to the first end face and the internal electrodes extended to the second end face; a glass film disposed on the first end surface and the second end surface adjacent to and surrounding the metal layer; a baking layer including glass and metal and disposed over the metal layer; a plating film disposed so as to cover the baked layer, The baked layer has voids, A plating material is present in at least a portion of the void. Multilayer ceramic capacitor.

2. At least one of the voids is located in a range closer to the metal layer than half the thickness of the baked layer from the surface of the baked layer. The multilayer ceramic capacitor according to claim 1 .

3. At least a portion of the metal layer is exposed from the baked layer.

3. The multilayer ceramic capacitor according to claim 1.

4. The baked layer on the first end surface or the second end surface, an area ratio of the plated material at a position three-quarters of the thickness of the baked layer from the surface of the baked layer is 20% or more and 90% or less; 3. The multilayer ceramic capacitor according to claim 1.

5. The thickness of the metal layer is 0.1 μm or more and 15.0 μm or less.

3. The multilayer ceramic capacitor according to claim 1.

6. The thickness of the baking layer is 1.0 μm or more and 100.0 μm or less.

3. The multilayer ceramic capacitor according to claim 1.

7. A glass film is disposed around the metal layer and in contact with an end of the metal layer.

3. The multilayer ceramic capacitor according to claim 1.

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