Self-Test Method for Phases of Three-Level ANPC Converter with LC Filters

Abstract

A method for testing an inverter having a bridge is disclosed. The bridge includes a first switch (T1) arranged between a positive connection (DC+) and a positive internal connection (PI) of a splitter link circuit having a center point (M), a second switch (T2) arranged between the positive internal connection (PI) and a bridge output (BR), a third switch (T3) arranged between the bridge output (BR) and a negative internal connection (NI), a fourth switch (T4) arranged between the negative internal connection (NI) and a negative connection (DC-) of the splitter link circuit, a fifth switch (T5) arranged between the center point (M) and the positive internal connection (PI), and a sixth switch (T6) arranged between the center point (M) and the negative internal connection (NI). A power supply filter having a filter inductor (LF) and a filter capacitor (CF) is connected to the bridge output (BR). The method includes the steps of applying a link circuit voltage to a split link circuit while a bridge output (BR) connected to a power supply filter is isolated from the connected grid, fully discharging a filter capacitor (CF), closing a first switch (T1) and a sixth switch (T6) and opening a fourth switch (T4) and a fifth switch (T5), followed by clocking a second switch (T2) using a plurality of short pulses, the duty cycle of the short pulses being preset to 1% to 5%, measuring the voltage dropped across the filter capacitor (CF) after clocking, and identifying a bridge fault condition if the dropped voltage is outside a voltage window having an upper window limit and a lower window limit. Also disclosed is an inverter having a control system designed and configured to perform the method of any one of the preceding claims and to connect the inverter to the connected grid only if a fault condition is not identified.

Description

[Technical Field]

[0001] The present invention relates to a method for testing an inverter, and further to an inverter configured to perform the testing method. [Background technology]

[0002] Inverters are used, among other things, to convert the DC power generated by solar generators into AC power and supply it to the AC grid. For this purpose, inverters have one or more bridges, each of which contains multiple semiconductor switches. By clocking the switches, the potential applied to the DC connection is alternately applied to the bridge output. The bridge output is connected to the phases of the AC voltage grid via a power supply filter. There are various bridge topologies, distinguished between single-level topologies, which simply apply a positive or negative potential to the bridge output alternately, and multilevel topologies, which apply an additional intermediate potential to the bridge output, usually generated by a divider link circuit. One embodiment of such a multilevel topology is called the ANPC (Active Neutral Point Clamp) topology, which includes six switches and allows the positive, negative, or midpoint potential of the divider link circuit at the bridge output to be applied depending on the switch configuration. The ANPC topology is a particularly efficient bridge topology.

[0003] For reasons of efficiency and cost, this topology uses semiconductor switches whose maximum allowable blocking voltage is lower than the input voltage applied to the DC connections. Therefore, this topology only works with switch configurations where the full input voltage does not drop across any switch. A known drawback is that if one of the bridge's switches fails, especially if one of the bridge switches is permanently conductive, the full input voltage will still be applied to the remaining switch, even though a permissible switch configuration exists. This can result in subsequent damage within the bridge, which can further destroy the bridge switches and other components of the inverter. Summary of the Invention

[0004] It is therefore an object of the present invention to provide a method that can determine whether there is a bridge switch failure before the inverter is started, without putting additional bridge switches or other inverter components at risk.

[0005] This object is achieved by a method having the features of claim 1 and by an inverter having the features of claim 11. Preferred embodiments of the invention are set out in the dependent claims.

[0006] The method according to the present invention is based on an inverter having a bridge, the bridge having a first switch arranged between a positive connection and a positive internal connection of a split link circuit having a center point, a second switch arranged between the positive internal connection and the bridge output, a third switch arranged between the bridge output and the negative internal connection, and a fourth switch arranged between the negative internal connection and the negative connection of the split link circuit. The bridge further has a fifth switch arranged between the center point and the positive internal connection and a sixth switch arranged between the center point and the negative internal connection, and a power supply filter having a filter inductor and a filter capacitor is connected to the bridge output. The filter capacitor can be connected by connecting to the center point of the link circuit. To test an inverter having such a bridge, the method according to the present invention includes: - applying a link circuit voltage to the split link circuit while the bridge output with the connected mains filter is isolated from the connected grid; - completely discharging the filter capacitor; - closing the first switch and the sixth switch while the fourth switch and the fifth switch are open; thereafter, clocking the second switch using a plurality of short pulses, the duty cycle of the short pulses being set to between 1% and 5%; - determining the voltage dropped across the filter capacitor after clocking; and identifying a bridge fault condition if the dropped voltage falls outside a voltage window having upper and lower window limits. When the bridge switches are fully functional, the filter capacitor is charged by multiple short pulses to a percentage of the link circuit voltage, determined by the duty cycle of the short pulses. At the same time, this type of clocking ensures that, even if a switch fails, the full link circuit voltage is not present across any of the other switches, at least for a time long enough to cause destruction of the associated switch. This allows testing to be performed without damaging the bridge. Even if the sixth switch is permanently blocked by a fault that would cause the entire link circuit voltage across the second switch to drop when the second switch is opened, the second switch is still protected because this time is so short due to the low duty cycle. If one of the bridge switches is defective and the defect causes the filter capacitor to not charge or to charge in an altered manner, this can be determined based on the voltage achieved across the filter capacitor. In this case, a fault condition is detected and the inverter responds accordingly, for example by preventing start-up or by selecting a type of bridge switch start-up that is tolerated despite the identified error and does not endanger additional components. The inverter typically already has means for determining the voltage across the filter capacitor as part of its control.

[0007] The method preferably comprises: - completely discharging the filter capacitor; - closing the fourth switch and the fifth switch while the first switch and the sixth switch are open; clocking the third switch using a plurality of short pulses, the short pulses having a duty cycle between 1% and 5%; - determining the additional voltage dropped across the filter capacitor after clocking; - identifying a fault condition of the bridge if the dropped additional voltage is outside the voltage window.

[0008] These supplemental steps correspond to repeating the steps of the method described above by clocking a negative link circuit voltage instead of a positive link circuit voltage, and allow additional potential switch faults to be detected.

[0009] In an advantageous embodiment, the second switch is clocked with a complementary clocking of the third switch, or the third switch is clocked with a complementary clocking of the second switch. Alternatively, the third switch can be left open while the second switch is clocked, or the second switch can be left open while the third switch is clocked. In this case, the second switch or the third switch can always be clocked with a set number of short pulses.

[0010] In a preferred embodiment of the test method of the present invention, before clocking the second switch there is a check to see if the potential of the negative internal connection and the center point match, or before clocking the third switch there is a check to see if the potential of the positive internal connection and the center point match, and if there is no match a fault condition of the bridge is always identified.

[0011] If the inverter has multiple bridges, the method according to the invention is preferably performed successively on each bridge to eliminate fault conditions, and proper operation of the inverter is only relieved when all bridges with their switches function without error.

[0012] Discharge of the filter capacitor connected to the center point of the link circuit can be triggered by simultaneously closing the fifth switch and the second switch, or by simultaneously closing the sixth switch and the third switch. Alternatively, discharge of the filter capacitor connected to the center point of the link circuit can also be triggered by simultaneously closing the fifth and sixth switches.

[0013] In another aspect, the present invention relates to an inverter having a bridge, the bridge having a first switch disposed between a positive connection and a positive internal connection of a split link circuit having a center point, a second switch disposed between the positive internal connection and a bridge output, a third switch disposed between the bridge output and a negative internal connection, a fourth switch disposed between the negative internal connection and a negative connection of the split link circuit, a fifth switch disposed between the center point and the positive internal connection, and a sixth switch disposed between the center point and the negative internal connection, and a mains filter connected to the bridge output, the mains filter having a filter inductor and a filter capacitor, the inverter having a controller designed and configured to perform the above method and connect the inverter to a utility grid only when no fault condition is detected.

[0014] The inverter may have multiple bridges, in which case the controller is designed and configured to perform the above method for each of the multiple bridges in succession and connect the inverter to the grid only if no fault condition is detected. [Brief explanation of the drawings]

[0015] The present invention will be described below with reference to the drawings. [Figure 1] FIG. 1 shows the first switch configuration of the bridge for discharging the filter capacitor. [Figure 2] Figure 2 shows a second switch configuration of the bridge for charging the filter capacitors in a complementary clocked manner. [Figure 3] Figure 3 shows a timing scheme for charging the filter capacitors in a complementary clocked manner. [Figure 4] Figure 4 shows a third switch configuration of the bridge for charging the filter capacitor in a single-clock manner. [Figure 5] FIG. 5 shows a fourth switch configuration of the bridge for charging the filter capacitors in a complementary clocked manner. [Figure 6] FIG. 6 shows a flow chart of the method according to the invention. DETAILED DESCRIPTION OF THE INVENTION

[0016] Figure 1 shows the switch configuration of an ANPC bridge used to discharge a filter capacitor CF at the bridge output. The input side of the ANPC bridge is connected to a splitter link circuit, which includes a first link circuit capacitor C1 connected to the positive connection DC+ and a second link circuit capacitor C2 connected to the negative connection DC-, connected in series with each other through a center point M. Between the positive connection DC+ and the negative connection DC-, a series circuit is arranged: a first switch T1 with an anti-parallel freewheeling diode D1, a second switch T2 with an anti-parallel freewheeling diode D2, a third switch T3 with an anti-parallel freewheeling diode D3, and a fourth switch T4 with an anti-parallel freewheeling diode D4. The first switch T1 and the fourth switch T4 are designed as IGBT transistors, while the second switch T2 and the third switch T3 are designed as MOSFET transistors. The center point M is connected to the positive internal connection PI between the first switch T1 and the second switch T2 via a fifth switch T5. Furthermore, the center point M is connected to the negative internal connection NI between the third switch T3 and the fourth switch T4 via a sixth switch T6. The fifth switch T5 and the sixth switch T6 are also designed as IGBT transistors. An output filter having a filter inductor LF and a filter capacitor CF is connected to the bridge output BR between the second switch T2 and the third switch T3 to provide a filtered output voltage AC.

[0017] To discharge the filter capacitor CF, the third and sixth transistors T3 and T6 are switched on, and all other transistors in the bridge are switched off. As a result, the filter capacitor CF is shorted through the filter inductor LF. Instead of the third and sixth switches T3 and T6, it is also possible to discharge the filter capacitor CF through the second and fifth switches T2 and T5, or through the fifth and sixth switches T5 and T6. A complete discharge, i.e., a discharge to zero voltage, also includes a discharge to any negligible residual voltage that may exist.

[0018] Figure 2 shows the second switch configuration of the bridge for charging the filter capacitor CF to the test voltage in a complementary clocking scheme. In this case, the first switch T1 and the sixth switch T6 are switched on, while the fifth switch T5 and the fourth switch T4 are switched off. The second switch T2 is then clocked at a higher frequency with short pulses having a duty cycle of 1% to 5%. The third switch T3 is clocked complementary to the second switch T2. During the conduction phase of the second switch T2, the filter capacitor CF is charged via the first link circuit capacitor C1 and the filter inductor LF, and then partially discharged again during the conduction phase of the third switch T3. This clocking results in a time-averaged DC voltage across the filter capacitor CF, which corresponds to the product of the voltage across the first DC link capacitor C1 and the duty cycle. After the clocking of the second switch T2 and the third switch T3 is finished, a check is made to see if the voltage across the filter capacitor CF is within the voltage window defined by the above relationship. If not, it is concluded that one of the bridge switches is faulty, and a bridge fault condition is identified.

[0019] The timing scheme for the complementary clocking of the bridge described above is shown in more detail in Figure 3. At the top of the figure, the switching state of the first switch T1 is shown as a function of time t on the x-axis, along with the switching states of the second switch T2, the third switch T3, and the sixth switch T6. The y-axis values ​​are 0 for a blocking switch state and 1 for a conducting switch state.

[0020] The bottom part of the diagram in Figure 3 plots the voltage U across the filter capacitor CF as a function of time. After the discharge phase EP, during which the voltage across the filter capacitor CF is zero, a charge phase LP follows, triggered by short pulses on the second switch T2 and complementary on the third switch T3. During this phase, the voltage U asymptotically approaches its final value, which is then compared with an acceptable voltage window with upper and lower limits in the subsequent test phase PP to verify the switch's error-free function.

[0021] The alternative switch configuration shown in Figure 4 differs from the switch configuration shown in Figure 2 for charging the filter capacitor CF in that the third switch T3 is switched off rather than clocked complementary. This prevents the filter capacitor CF from discharging during the short pulses of the second switch T2, reducing the current flowing through the filter inductor LF only through the freewheeling path formed by the third switch T3, the sixth switch T6, and the filter capacitor CF during this time. As a result, the voltage across the filter capacitor increases incrementally with each short pulse. Therefore, in the test method for the bridge switch in this switch configuration, the charging phase of the filter capacitor CF ends after a set number of short pulses or a set charging time, after which the voltage across the filter capacitor CF is measured to confirm the bridge switch state.

[0022] The alternative switch configuration shown in FIG. 5 differs from the switch configuration shown in FIG. 2 for charging the filter capacitor CF in that the filter capacitor CF is charged with the opposite polarity via the second link circuit capacitor C2. Alternatively, or preferably, this switch configuration can be used within the framework of a test method, since other switches in the bridge can be checked for their functionality in addition to the switch configuration shown in FIG. 2. In this case, the fourth switch T4 and the fifth switch T5 are switched to a conducting state, while the sixth switch T6 and the first switch T1 are switched to a blocking state. The third switch T3 is then clocked at a high frequency with short pulses having a duty cycle of 1% to 5%. The second switch T2 is clocked in a complementary manner to the third switch T3. Naturally, it is conceivable to modify such a switch configuration so that the second switch T2 is switched to a blocking state rather than being clocked in a complementary manner.

[0023] Finally, FIG. 6 shows a flowchart of a method according to the present invention for testing an inverter with a bridge. In a first step S1, a link circuit voltage is applied to the inverter's splitter link circuit, for example by connecting a DC power supply to the inverter's DC voltage connections DC+ and DC-. In this case, the bridge output, to which the mains filter is connected, remains disconnected from the AC voltage grid. In a second step S2, the filter capacitor of the mains filter is completely discharged. This discharge is caused by operating the bridge in a switch configuration that forms a conductive path from the center point of the splitter link circuit to the bridge output BR. Note that the first step S1 and the second step S2 can be performed in any order.

[0024] In the next third step S3, the first switch T1 and the sixth switch T6 are closed, and the fourth switch T4 and the fifth switch T5 are opened. As a result, the positive internal connection PI of the bridge is applied with the positive link circuit potential, and the negative internal connection NI is applied with the midpoint potential. In the fourth step S4, the second switch T2 is subsequently clocked using a plurality of short pulses, where the duty cycle of the short pulses is set to 1% to 5%.

[0025] In the fifth and final step S5, the voltage dropped across the filter capacitor is determined after clocking, and if the voltage dropped is outside a voltage window having an upper window limit and a lower window limit, a bridge fault condition is identified.

[0026] If the inverter has multiple bridges, e.g., one or more bridges for each phase of the connected AC voltage grid connected to the phases of the AC voltage grid via separate or common power filters, the method can be performed sequentially for each bridge. The method can be supplemented by additional test routines for additional fault patterns in the bridges or other components of the inverter. The method can also be performed multiple times to verify identified fault conditions.

[0027] If a fault condition of a bridge is identified by the method, it can be responded to in various ways. For example, the connection of the inverter to the AC voltage grid can be prevented, the inverter can be operated with a disabled open bridge, or a control can be selected that allows limited operation of the associated bridge. Furthermore, the fault condition can be communicated to a higher-level control entity. [Explanation of symbols]

[0028] DC+, DC- connection C1, C2 Link circuit capacitor M center point T1-T6 switches D1-D6 diodes BR Bridge Output PI, NI internal connection LF Filter Inductor CF filter capacitor AC AC voltage output S1 Step LP charging phase EP Discharge Phase PP Test Phase

Claims

1. 1. A method for testing an inverter having a bridge, comprising: The bridge is a first switch (T1) arranged between the positive connection (DC+) and the positive internal connection (PI) of a split link circuit having a center point (M); a second switch (T2) placed between the positive internal connection (PI) and the bridge output (BR); a third switch (T3) placed between the bridge output (BR) and the negative internal connection (NI); a fourth switch (T4) arranged between the negative internal connection (NI) and the negative connection (DC-) of the dividing link circuit; a fifth switch (T5) placed between the center point (M) and the positive internal connection (PI); a sixth switch (T6) arranged between the center point (M) and the negative internal connection (NI), a power supply filter having a filter inductor (LF) and a filter capacitor (CF) connected to the bridge output (BR); The method comprises: - applying a link circuit voltage to the split link circuit while the bridge output (BR) connected to the mains filter is isolated from the grid to which it is connected; - completely discharging the filter capacitor (CF); - closing the first switch (T1) and the sixth switch (T6) and opening the fourth switch (T4) and the fifth switch (T5); - subsequently clocking the second switch (T2) using a number of short pulses, the duty cycle of which is set between 1% and 5%; - after clocking, measuring the voltage dropped across the filter capacitor (CF); - identifying a fault condition of the bridge if the dropped voltage is outside a voltage window having an upper window limit and a lower window limit.

2. 10. The method of claim 1, - completely discharging the filter capacitor (CF); - closing the fourth switch (T4) and the fifth switch (T5) while the first switch (T1) and the sixth switch (T6) are open; - clocking a third switch (T3) using a number of short pulses, the duty cycle of the short pulses being between 1% and 5%; - after clocking, measuring the additional voltage dropped on the filter capacitor (CF); - identifying a fault condition in the bridge if the dropped additional voltage is outside the voltage window.

3. 3. The method according to claim 1 or 2, During the clocking of the second switch (T2), the third switch (T3) remains open, and the second switch (T2) is clocked with a set number of short pulses.

4. 4. The method according to claim 2 or 3, During the clocking of the third switch (T3), the second switch (T2) remains open, and the third switch (T3) is clocked with a set number of short pulses.

5. The method according to any one of claims 1 to 4, Before clocking the second switch (T2), there is a check to see if the potentials of the negative internal connection (NI) and the center point (M) match, and if they do not match, a fault condition of the bridge is identified.

6. The method according to any one of claims 2 to 5, Before clocking the third switch (T3), there is a check to see if the potentials of the positive internal connection (PI) and the center point (M) match, and if they do not match, a fault condition of the bridge is identified.

7. The method according to any one of claims 1, 2, 4 to 6, A method characterized in that the clocking of the second switch (T2) is performed with a complementary clocking of the third switch (T3).

8. The method according to any one of claims 2, 3, 5 to 7, A method characterized in that the clocking of the third switch (T3) is performed together with the complementary clocking of the second switch (T2).

9. The method according to any one of claims 1 to 8, 10. A method according to claim 9, wherein the inverter comprises a plurality of bridges and the method is performed sequentially on each of said bridges.

10. The method according to any one of claims 1 to 9, The method is characterized in that the filter capacitor (CF) is discharged by simultaneously closing the fifth switch (T5) and the second switch (T2), or by closing the sixth switch (T6) and the third switch (T3), or by closing the fifth switch (T5) and the sixth switch (T6).

11. The method according to any one of claims 1 to 10, The method further comprising connecting the inverter to the grid only if no fault condition is detected.

12. The method according to claim 1, further comprising: The inverter has multiple bridges, for each of a plurality of bridges, the method of any one of claims 1 to 10 is carried out, The method further comprising connecting the inverter to the grid only if no fault condition is detected.

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