Power supply terminal open detection circuit

Abstract

To provide a power terminal open detection circuit which has a saving area and is a low power consumption current as conventional one.SOLUTION: A power terminal open detection circuit comprises a parasitic diode on-detection circuit 31_1 that includes a n-1 NMOS transistor 311_1 containing a first end, a second end, a gate, and a back gate, which are connected through a parasitic element contained in a semiconductor region different from a semiconductor region in which a NMOS transistor 11_1 and a parasitic diode 12_1 are formed, and a NMOS transistor 311_0 containing the first end of the NMOS transistor 311_1 and the first end connected to the back gate and a second end connected to a second power terminal 9. In the parasitic diode on-detection circuit 31_1, an anode is connected to a path, and a cathode is connected to a first power terminal 8, and contains an output end 31o that is connected to the second end of the NMOS transistor 311_1 changed by the parasitic element when the parasitic diode 12_1 is turned on.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a power supply terminal open detection circuit. [Background technology]

[0002] In a battery device incorporating an assembled battery in which multiple battery cells are connected in series, safety and performance are maintained by monitoring the battery cells included in the assembled battery. Specifically, the battery voltage of each battery cell is monitored and controlled to stay within a specified range. To maintain the desired safety and performance, it is important that the battery voltage of each battery cell is monitored properly. For example, if the wiring between each battery cell and a voltage measurement device is broken, the voltage measurement device will not be able to measure the battery cell's voltage, and the desired protection function will not be achieved.

[0003] As an example of a technique for detecting such a disconnection, a technique has been proposed in which a change in voltage between two points before and after the disconnection is detected by a comparator (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-1446 Summary of the Invention [Problem to be solved by the invention]

[0005] This section explains an example of a battery device in which a battery pack is connected to a semiconductor integrated circuit (IC) including a charge / discharge control circuit in which a P-type semiconductor well is formed in an N-type semiconductor substrate. In the illustrated battery device, when the positive electrode of the battery cell (hereinafter referred to as the "first battery cell") located closest to the positive electrode in the battery pack is disconnected from the VDD terminal of the IC, a parasitic element is turned on between the P-type semiconductor well and the N-type semiconductor substrate. When this parasitic element is turned on, the voltage relationship between the VDD terminal and the intermediate terminal to which the negative electrode of the first battery cell is connected is reversed. Therefore, by detecting the change in voltage between the VDD terminal and the intermediate terminal with a comparator, it is possible to detect a disconnection between the VDD terminal and the positive electrode of the first battery cell.

[0006] However, when the above-described technique of detecting a change in voltage between the VDD terminal and the intermediate terminal using a comparator is applied, the area and current consumption are relatively large compared to a circuit that does not include a comparator. In other words, the above-described technique of detecting a change in voltage between the VDD terminal and the intermediate terminal using a comparator has room for improvement in terms of area and current consumption.

[0007] The present invention has been made in view of the above circumstances, and has as its object to provide a power supply terminal open detection circuit that is further reduced in area and current consumption. [Means for solving the problem]

[0008] A power supply terminal open detection circuit according to one aspect of the present invention is a circuit for detecting whether or not a positive electrode of a secondary battery including a battery pack in which a plurality of n battery cells are connected in series is disconnected from a semiconductor integrated circuit in which n-1 first transistors and n-1 parasitic diodes are formed in a semiconductor region including a P-type region and an N-type region, and the n-1 second transistors are formed in a semiconductor region different from the semiconductor region in which the first transistors and the parasitic diodes are formed, and each second transistor has a first end, a second end, a gate, and a back gate connected to the first transistor and the parasitic diode via a parasitic element included in the semiconductor region. and n-1 parasitic diode on detection circuits each having a resistor including a first terminal connected to the source and back gate of the second transistor and a second terminal connected to a second power supply terminal, wherein the parasitic diodes are connected to n-1 paths each connected to n-1 cell connection terminals, each connected to a connection point of two consecutive battery cells of the secondary battery, at their anodes, and each connected to the first power supply terminal, and the parasitic diode on detection circuit includes an output terminal connected to the second terminal of the second transistor, which changes due to the parasitic element when the parasitic diode is on. [Effects of the Invention]

[0009] According to the present invention, the power supply terminal open detection circuit can be made smaller in area and consume less current than conventional power supply terminal open detection circuits. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing a circuit configuration of a semiconductor device including a power supply terminal open detection circuit according to an embodiment of the present invention; [Figure 2] 1 is a schematic diagram showing an example of the configuration of a charge / discharge control circuit including a power supply terminal open detection circuit according to an embodiment of the present invention; [Figure 3] 1 is a circuit diagram showing a schematic circuit configuration of one parasitic diode on detection circuit in a first example of a power supply terminal open detection circuit according to the present embodiment. FIG. [Figure 4] 1 is a device cross-sectional view of one parasitic diode on detection circuit in a first example of a power supply terminal open detection circuit according to the present embodiment. FIG. [Figure 5] FIG. 10 is a schematic diagram showing a partial configuration of a parasitic diode on detection circuit in a second example of the power supply terminal open detection circuit according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A power supply terminal open detection circuit according to an embodiment of the present invention will now be described with reference to the drawings.

[0012] FIG. 1 is a block diagram showing the circuit configuration of a battery device 1, which is an example of a semiconductor device including a power terminal open detection circuit according to this embodiment. The battery device 1 includes a semiconductor integrated circuit formed on a semiconductor substrate 50 (see FIG. 4 described later) by a semiconductor process, specifically an IC chip including a charge / discharge control circuit 10 that controls the charging and discharging of the secondary battery 2.

[0013] The battery device 1 includes a secondary battery 2 including a so-called multi-cell battery pack, an external positive terminal P+, an external negative terminal P-, a discharge control FET (Field Effect Transistor) 3, a charge control FET 4, and a charge / discharge control circuit 10 for controlling the charging and discharging of the secondary battery 2. For ease of explanation, the external positive terminal P+ and the external negative terminal P- may be collectively referred to as "external terminals" in the following description.

[0014] The secondary battery 2 is a so-called multi-cell battery including an assembled battery in which n battery cells (hereinafter simply referred to as "cells") 2_1 to 2_n are connected in series, where "n" is the number of cells connected in series. In the case of a multi-cell battery, n is an integer equal to or greater than 2, i.e., a plural number. The n cells 2_1, ..., 2_n in the secondary battery 2 are connected in series in this order from the positive electrode 2a of the secondary battery 2 to the negative electrode 2b of the secondary battery 2.

[0015] The charge / discharge control device 20 includes an external positive terminal P+, an external negative terminal P-, a discharge control FET 3, a charge control FET 4, and a charge / discharge control circuit 10. In other words, the charge / discharge control device 20 is an example of a semiconductor device, and is a device obtained by omitting the secondary battery 2 from the battery device 1.

[0016] The external positive terminal P+ and the external negative terminal P- are terminals for connection to external devices (not shown), such as a charger and a load. In the battery device 1, a path connecting the external positive terminal P+ and the external negative terminal P- (hereinafter referred to as an "external terminal path") is connected to, for example, the secondary battery 2, the overcurrent detection resistor 5, the discharge control FET 3, and the charge control FET 4 in this order from the external positive terminal P+ side.

[0017] The battery device 1 and the charge / discharge control device 20 are provided with, for example, a discharge control FET 3 and a charge control FET 4 on the external negative terminal P- side, i.e., on the low side. The discharge control FET 3 and the charge control FET 4 are both NMOS transistors, and their drains are connected to each other.

[0018] The discharge control FET3 includes a gate connected to the discharge control signal output terminal DO, a drain as one end connected to the drain of the charge control FET4, and a source as the other end connected to one end of the overcurrent detection resistor 5.

[0019] The charge control FET4 includes a gate connected to the charge control signal output terminal CO, a source as one end connected to the external negative terminal P−, and a drain as the other end connected to the drain of the discharge control FET3.

[0020] The charge / discharge control circuit 10 has a positive power supply input terminal VDD, a negative power supply input terminal VSS, cell connection terminals VC1,...,VC(n-1), a charge control signal output terminal CO, a discharge control signal output terminal DO, an external negative voltage input terminal VM, and an overcurrent detection terminal VINI.

[0021] The positive power supply input terminal VDD is connected to the positive electrode 2a via a resistor R1, and is supplied with voltage from the positive electrode 2a of the secondary battery 2. The negative power supply input terminal VSS is connected to the negative electrode 2b, and is supplied with voltage from the negative electrode 2b.

[0022] The cell connection terminal VC1 is connected to the junction of the first cell 2_1 and the second cell 2_2, i.e., the negative terminal of the first cell 2_1 and the positive terminal of the second cell 2_2, via a resistor R2. Similarly to the cell connection terminal VC1, the cell connection terminals VC2, . . . , VC(n-1) are connected to the negative terminal of the second cell 2_2 and the positive terminal of the third cell 2_3, . . . , the negative terminal of the (n-1)th cell 2_(n-1), and the positive terminal of the nth cell 2_n, via resistors R3, . . . , Rn, respectively.

[0023] Here, the end of the resistors R1,...,Rn connected to the first cell 2_1 to the nth cell 2_n (the left end in Figure 1) is referred to as the first end, and the end connected to the positive power supply input terminal VDD, the cell connection terminals VC1,...,VC(n-1) and the negative power supply input terminal VSS, i.e., the end in the opposite direction to the first end, is referred to as the second end (the right end in Figure 1).

[0024] A capacitor C1 for suppressing voltage fluctuations is connected between the junction between the second end of resistor R1 and the positive power supply input terminal VDD and the junction between the negative electrode 2b and the negative power supply input terminal VSS. Similarly to capacitor C1, capacitors C2,...,Cn are connected between the junction between the second ends of resistors R2,...,Rn and the cell connection terminals VC1,...,VC(n-1), and the junction between the negative electrode 2b and the negative power supply input terminal VSS.

[0025] The charge control signal output terminal CO is a terminal that outputs a charge control signal that is generated within the charge / discharge control circuit 10 and controls the stopping and permission of charging of the secondary battery 2 to the outside of the charge / discharge control circuit 10. The charge control signal output terminal CO is connected to the gate of the charge control FET4.

[0026] The discharge control signal output terminal DO is a terminal that outputs a discharge control signal that is generated within the charge / discharge control circuit 10 and controls the stopping and permission of discharging of the secondary battery 2 to the outside of the charge / discharge control circuit 10. The discharge control signal output terminal DO is connected to the gate of the discharge control FET3.

[0027] The external negative voltage input terminal VM is connected to the external negative terminal P− and the source of the charge control FET 4 via a resistor 6 .

[0028] The overcurrent detection terminal VINI is connected to one end of the overcurrent detection resistor 5 and the source of the discharge control FET3.

[0029] 2 is a schematic diagram showing an example of the configuration of a charge / discharge control circuit 10 including a power supply terminal open detection circuit 30, which is an example of the power supply terminal open detection circuit according to this embodiment. Note that components not directly related to the power supply terminal open detection circuit 30 are omitted from the charge / discharge control circuit 10 shown in FIG.

[0030] The charge / discharge control circuit 10 includes a power supply terminal open detection circuit 30 and a control circuit 15. The power supply terminal open detection circuit 30 is a circuit that has the function of detecting an electrical disconnection between the positive power supply input terminal VDD of the IC chip including the charge / discharge control circuit 10 and the positive electrode of the cell 2_1, i.e., the positive electrode 2a of the secondary battery 2 (hereinafter referred to as "VDD open").

[0031] The power supply terminal open detection circuit 30 includes a parasitic diode on detection circuit group 31 and an OR circuit 36. The parasitic diode on detection circuit group 31 includes (n-1) parasitic diode on detection circuits 31_1,...,31_(n-1), which is the same number as the number of cell connection terminals VC1,...,VC(n-1). The OR circuit 36 ​​includes (n-1) input terminals, which is the same number as the number of cell connection terminals VC1,...,VC(n-1), and one output terminal.

[0032] The charge / discharge control circuit 10 further includes NMOS transistors 11_1,...,11_(n-1) which are off-transistors, and parasitic diodes 12_1,...,12_(n-1). The NMOS transistor 11_1 and the parasitic diode 12_1 are both connected to a path 13_1 which connects a cell connection terminal VC1 connected to a connection point of two consecutive cells 2_1, 2_2 to the parasitic diode on-detection circuit 31_1. The NMOS transistor 11_1 has a source, a gate, and a back gate connected to the path 13_1. The parasitic diode 12_1 includes an anode connected to the path 13_1 and a cathode connected to the first power supply terminal 8.

[0033] Similarly to the NMOS transistor 11_1 and the parasitic diode 12_1, the NMOS transistors 11_2,...,11_(n-1) and the parasitic diodes 12_2,...,12_(n-1) are connected to paths 13_2,...,13_(n-1) that connect the cell connection terminals VC2,...,VC(n-1) and the parasitic diode on detection circuits 31_2,...,31_(n-1). The NMOS transistors 11_2,...,11_(n-1) each include a source, a gate, and a back gate connected to the paths 13_2,...,13_(n-1). The parasitic diodes 12_2,...,12_(n-1) each include an anode connected to the paths 13_2,...,13_(n-1) and a cathode connected to the first power supply terminal 8.

[0034] The control circuit 15 is configured to be able to output a control signal that switches the transistor on and off to at least one of the charge control signal output terminal CO and the discharge control signal output terminal DO in response to signals input from other circuits, including circuits other than the power supply terminal open detection circuit 30, such as a voltage detection circuit and a voltage monitoring circuit, which are not shown in the figure.

[0035] 3 is a schematic diagram showing an example of the configuration of a parasitic diode on detection circuit 31_1 as a representative example of the parasitic diode on detection circuits 31_1 to 31_(n-1) in a power supply terminal open detection circuit 30, which is a first example of the power supply terminal open detection circuit according to this embodiment. The configuration of the parasitic diode on detection circuits 31_2 to 31_(n-1) is substantially the same as the configuration of the parasitic diode on detection circuit 31_1.

[0036] The parasitic diode on-detection circuit 31_1 has NMOS transistors 311_0 and 311_1, a parasitic PNP bipolar transistor 321, a parasitic NPN bipolar transistor 322, and a parasitic resistor 331. The NMOS transistor 311_0 as a resistor functions as an on-resistance that connects the source and back gate of the NMOS transistor 311_1 as a second transistor to a second power supply terminal 9. The second power supply terminal 9 is a terminal that can supply a second power supply voltage, such as a ground voltage, that is different from the first power supply voltage.

[0037] The NMOS transistor 11_1 as the first transistor includes a gate, a source, and a back gate connected to the path 13_1. The gate, source, and back gate of the NMOS transistor 11_1 are further connected to the emitter of the parasitic PNP bipolar transistor 321. The base of the parasitic PNP bipolar transistor 321 is connected to the first power supply terminal 8. The collector of the parasitic PNP bipolar transistor 321 is connected to the base of the parasitic NPN bipolar transistor 322 and a first end of the parasitic resistor 331.

[0038] The collector of the parasitic NPN bipolar transistor 322 is connected to the first power supply terminal 8. The emitter of the parasitic NPN bipolar transistor 322 is connected to the drain of the NMOS transistor 311_0, the source serving as a first terminal of the NMOS transistor 311_1, and the second terminal of the parasitic resistor 331.

[0039] The gate of the NMOS transistor 311_0 is connected to the gate of the NMOS transistor 311_1 and the first power supply terminal 8. The drain of the NMOS transistor 311_1, serving as a second terminal, is connected to the input terminal of the OR circuit 36. The connection point between the drain of the NMOS transistor 311_1 and the input terminal of the OR circuit 36 ​​forms the output terminal 31o of the parasitic diode on detection circuit 31_1.

[0040] FIG. 4 is a device cross-sectional view of the parasitic diode on detection circuit 31_1 shown in FIG.

[0041] A semiconductor region including, for example, three P-wells 51, 52, and 53, which are P-type regions of a second conductivity type, and one N-type region 54, is formed inside a semiconductor substrate 50 of an N-type, which is a first conductivity type. Here, the N-type region 54 is an N-type region whose ion concentration is relatively high compared to the ion concentration of the region surrounding it. This region is represented as "N+" in FIG. 4. The NMOS transistors 311_0 and 311_1, the parasitic PNP bipolar transistor 321, the parasitic NPN bipolar transistor 322, and the parasitic resistor 331, which constitute the parasitic diode on detection circuit 31_1, and the NMOS transistor 11_1 are formed on the semiconductor substrate 50.

[0042] Two N-type regions N+D and N+S, each having a relatively high ion concentration compared to the ion concentration of the P-wells 51, 52, and 53, and one P-type region P+ are formed inside each P-well 51, 52, and 53. A gate G is formed on the surface of the semiconductor substrate 50 of each P-well 51, 52, and 53 via a gate insulating film (oxide film) 55. Here, the letters "D" and "S" at the end of the N-type regions N+D and N+S correspond to "drain" and "source," respectively.

[0043] In the P-well 51, an NMOS transistor 11_1 is formed by two N-type regions N+D and N+S, a gate G, a P-type region P+, and the P-well 51. The P-type region P+ serves as the back gate of the NMOS transistor 11_1. A parasitic diode 12_1 is formed between the P-type region P+ and the N-type region N+D. The N-type region N+D is connected to a first power supply terminal 8. The N-type region N+S, the gate G, and the P-type region P+ are connected to each other and also to a cell connection terminal VC1.

[0044] In the P well 52, an NMOS transistor 311_1 is formed by two N-type regions N+D and N+S, a gate G, a P-type region P+, and the P well 52. The P-type region P+ serves as a back gate of the NMOS transistor 311_1. A parasitic diode 12_1 is formed between the P-type region P+ and the N-type region N+D. The gate G is connected to a first power supply terminal 8. The first power supply terminal 8 is a terminal capable of supplying a first power supply voltage. The P-type region P+ and the N-type region N+S are connected to each other.

[0045] The P-type region P+ of the P-well 52, the N-type region 54, and the P-type region P+ of the P-well 51 form a parasitic PNP bipolar transistor 321 and a parasitic resistor 331. The P-type region P+ of the P-well 52, the N-type region 54, and the P-type region P+ of the P-well 51 respectively form the collector, base, and emitter of the parasitic PNP bipolar transistor 321. In addition, a parasitic resistor 331 is formed between the connection point between the P-type region P+ of the P-well 51 and the N-type region 54 and the P-type region P+ of the P-well 52.

[0046] The N-type region 54, the P-type region P+ of the P-well 52, and the N-type region N+S of the P-well 52 form a parasitic NPN bipolar transistor 322. The N-type region 54, the P-type region P+ of the P-well 52, and the N-type region N+S of the P-well 52 form the collector, base, and emitter of the parasitic NPN bipolar transistor 322, respectively.

[0047] In the P well 53, an NMOS transistor 311_0 is formed by two N-type regions N+D and N+S, a gate G, a P-type region P+, and the P well 53. An on-resistor 53r is formed between the two N-type regions N+D and N+S. The N-type region N+D, which serves as a first end of the resistor, is connected to the P-type region P+ and the N-type region N+S of the P well 52. The P-type region P+ and the N-type region N+S, which serve as second ends of the resistor, are connected to the second power supply terminal 9. In this way, of the elements that constitute the parasitic diode on-detection circuit 31_1, the parasitic PNP bipolar transistor 321, the parasitic NPN bipolar transistor 322, and the parasitic resistor 331 can be configured as parasitic elements formed on the semiconductor substrate 50.

[0048] Next, the operation of the power supply terminal open detection circuit 30 of the charge / discharge control circuit 10 will be described. A voltage from the secondary battery 2 is applied to each cell connection terminal VC1,...,VC(n-1). In a normal state where VDD is not open, the parasitic diodes 12_1,...,12(n-1) are off. Therefore, no current flows between the P well 51, P well 52, and P well 53, i.e., through the parasitic resistor 331, and no voltage difference occurs across the parasitic resistor 331.

[0049] On the other hand, in the VDD open state, the parasitic diodes 12_1, . . . , 12(n-1) are turned on and conduct current in the forward direction. When the parasitic diodes 12_1, . . . , 12(n-1) are turned on, the parasitic PNP bipolar transistor 321 and the parasitic NPN bipolar transistor 322 are turned on. Therefore, a current flows between the P well 51, the P well 52, and the P well 53, i.e., through the parasitic resistor 331. When a current flows through the parasitic resistor 331 and a voltage difference occurs across the parasitic resistor 331, the voltage at the drains of the NMOS transistors 311_1, . . . , 311(n-1) rises.

[0050] The parasitic diode on detection circuit 31_1 detects a VDD open by detecting a rise in the drain voltage of the NMOS transistor 311_1. The parasitic diode on detection circuits 31_2, ..., 311(n-1) detect a VDD open by detecting a rise in the drain voltage of the NMOS transistors 311_2, ..., 311(n-1) in the same way as the parasitic diode on detection circuit 31_1. The parasitic diode on detection circuits 31_1, ..., 311(n-1) output signals including different signal levels corresponding to whether or not a VDD open has been detected from the output terminal 31o. If a VDD open has been detected, a high-level signal is output from the output terminal 31o, and if a VDD open has not been detected (no), a low-level signal is output from the output terminal 31o.

[0051] The signals output from the parasitic diode on detection circuits 31_1, . . . , 311(n-1) are supplied to the input terminal of the OR circuit 36. If any of the signals supplied to the input terminal of the OR circuit 36 ​​is a high-level signal, the OR circuit 36 ​​outputs a high-level signal to the control circuit 15. On the other hand, if all of the signals supplied from the parasitic diode on detection circuits 31_1, . . . , 311(n-1) are low-level signals, the OR circuit 36 ​​outputs a low-level signal to the control circuit 15. The control circuit 15 receives the signal output from the OR circuit 36 ​​as an output signal of the power supply terminal open detection circuit 30. The control circuit 15 generates a control signal according to the signal level of the signal received from the power supply terminal open detection circuit 30, and supplies the control signal to at least one of the charge control signal output terminal CO and the discharge control signal output terminal DO.

[0052] As described above, according to this embodiment, by utilizing the parasitic elements formed on the semiconductor substrate 50 (FIG. 4) on which the IC chip is formed, the power supply terminal open detection circuit 30 capable of detecting a VDD open can be formed with two elements per cell (NMOS transistors 311_0 and 311_1 in the parasitic diode on detection circuit 31_1 shown in FIG. 3). Therefore, it is possible to form the power supply terminal open detection circuit 30 or the like with a simpler circuit configuration than the conventional circuit equipped with a comparator.

[0053] According to this embodiment, the current consumption can be reduced to 0 (zero) under normal conditions, making it possible to form a power supply terminal open detection circuit 30 or the like that consumes less current than conventional circuits. Also, according to this embodiment, VDD open is detected using NMOS transistors 11-1, . . . , 11(n-1) connected to each cell connection terminal VC1, . . . , VC(n-1). Therefore, it is possible to form a power supply terminal open detection circuit 30 or the like that can detect VDD open without affecting component circuits in the internal area.

[0054] It should be noted that the present invention is not limited to the above-described embodiments, and can be implemented in various forms other than the above-described examples, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. For example, in the above-described embodiments, power supply terminal open detection circuit 30 may be power supply terminal open detection circuit 30A.

[0055] 5 is a schematic diagram showing a partial configuration of a parasitic diode-on detection circuit 31A in a power supply terminal open detection circuit 30A, which is a second example of the power supply terminal open detection circuit according to this embodiment. In order to ensure clarity and simplicity of the drawing, FIG. 5 shows the parasitic diode-on detection circuit 31A from which the parasitic elements and NMOS transistors 11_1 to 11_(n-1) formed in the semiconductor substrate 50 are not shown.

[0056] The power supply terminal open detection circuit 30A is a modified example of the power supply terminal open detection circuit 30 that is useful when n is an integer greater than or equal to 3. The power supply terminal open detection circuit 30A differs from the power supply terminal open detection circuit 30 in that it includes a parasitic diode on detection circuit 31A instead of the parasitic diode on detection circuit group 31 and the OR circuit 36.

[0057] The parasitic diode on detection circuit 31A is configured to have n-2 NMOS transistors 311_2 to 311_(n-1) connected in parallel to the NMOS transistor 311_1 for the parasitic diode on detection circuit 31_1, for example. Note that when n=2, the configuration is the same as that illustrated in FIG.

[0058] The power supply terminal open detection circuit 30A is configured by omitting the OR circuit 36 ​​from the power supply terminal open detection circuit 30, thereby further simplifying the circuit configuration. In other words, the power supply terminal open detection circuit 30A can be configured to have an even smaller area than the power supply terminal open detection circuit 30.

[0059] The resistor included in the power supply terminal open detection circuit 30, 30A is not limited to the NMOS transistor 311_0. Instead of the NMOS transistor 311_0, a resistive element connecting the source and back gate of the NMOS transistor 311_1 to the second power supply terminal 9, or a current source sinking a current from the source and back gate of the NMOS transistor 311_1 to the second power supply terminal 9 may be used.

[0060] These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0061] 1 Battery device (semiconductor device) 2 Secondary battery 2_1~2_n cells (battery cells) 11_1~11_(n-1) NMOS transistor (first transistor) 12_1~12_(n-1) Parasitic diode 13_1~13_(n-1) Route 20 Charge / discharge control device (semiconductor device) 30,30A power terminal open detection circuit 31 Parasitic diode on detection circuits 31_1~31_(n-1) Parasitic diode on detection circuit 36 OR circuit 311_0 NMOS transistor (third transistor) 311_1~311_(n-1) NMOS transistor (second transistor) 53r On-resistance CO Charge control signal output pin DO Discharge control signal output terminal

Claims

1. A circuit for detecting whether a positive electrode of a secondary battery including a battery pack in which a plurality of n battery cells are connected in series is connected to a semiconductor integrated circuit in which n-1 first transistors and n-1 parasitic diodes are formed in a semiconductor region including a P-type region and an N-type region, n-1 parasitic diode on-detection circuits are provided, each of which has n-1 second transistors formed in a semiconductor region different from the semiconductor region in which the first transistor and the parasitic diode are formed, the second transistors including a first end connected to the first transistor and the parasitic diode via a parasitic element included in the semiconductor region, a second end, a gate, and a back gate, and a resistor including a first end connected to the source and the back gate of the second transistor and a second end connected to a second power supply terminal; the parasitic diodes are connected to n-1 paths, each path being connected to n-1 cell connection terminals, each of which is connected to a connection point between two consecutive battery cells of the secondary battery, and each cathode is connected to a first power supply terminal; The parasitic diode on detection circuit includes an output terminal connected to the second terminal of the second transistor, which changes depending on the parasitic element when the parasitic diode is on. A power supply terminal open detection circuit.

2. 2. The power supply terminal open detection circuit according to claim 1, further comprising: a logical OR circuit including n-1 input terminals to which the output terminals of the n-1 parasitic diode on detection circuits are connected, and an output terminal that outputs a result of calculating the logical OR of signals input to the n-1 input terminals.

3. 2. The power supply terminal open detection circuit according to claim 1, wherein the second transistors included in the parasitic diode on detection circuits are connected in parallel with each other.

4. 4. The power supply terminal open detection circuit according to claim 1, wherein the resistor is an on-resistance of a third transistor formed in the semiconductor region.

5. 4. The power supply terminal open detection circuit according to claim 1, wherein the resistor is either a resistive element or a current source.

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