Communication device and communication system

Abstract

[Problem] To enable data communication to be efficiently performed. [Solution] This communication device comprises a LINK for protocol-converting a signal from a Master and outputting the converted signal to a Slave SerDes, as well as protocol-converting a signal from the Slave SerDes and outputting the converted signal to the Master. The LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master to the Slave SerDes. In the first mode, the LINK converts one byte of signal transmitted from the Master, as a unit, into a signal in a first communication standard, and transmits the converted signal to the Slave SerDes, after which the LINK receives a signal in the first communication standard that includes an ACK signal representing a positive acknowledgement or a NACK signal representing a negative acknowledgement, converts the received signal into a signal in a second communication standard, and transmits said signal to the Master.

Description

[Technical Field]

[0001] The present disclosure relates to a communication device and a communication system. [Background technology]

[0002] When data communication is performed between a master device and a slave device, a technique has been proposed for performing serial communication between a SerDes device for the master device and a SerDes device for the slave device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-239011 Summary of the Invention [Problem to be solved by the invention]

[0004] When a slave device receives data transmitted from a master device, it is common for the slave device to transmit an ACK signal to the master device to indicate that it has received the data. However, if two SerDes devices are located between the master and slave devices, the ACK signal must pass through these SerDes devices, and it takes a considerable amount of time from when the slave device transmits the ACK signal until the master device receives it.

[0005] If the master device is configured such that it cannot send a new signal to a slave device until it receives an ACK signal from the slave device, there is a risk that the processing of the master device will be delayed because it takes time to receive the ACK signal.

[0006] Therefore, the present disclosure provides a communication device and a communication system that are capable of efficiently performing data communication. [Means for solving the problem]

[0007] In order to solve the above problems, according to the present disclosure, there is provided a LINK that converts the protocol of a signal from a Master and outputs it to a Slave SerDes, and converts the protocol of a signal from the Slave SerDes and outputs it to the Master, the LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master to the Slave SerDes; In the first mode, the LINK converting a 1-byte signal transmitted from the Master into a signal conforming to a first communication standard in units of 1 byte, transmitting the converted signal to the Slave SerDes, receiving a signal conforming to the first communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal conforming to a second communication standard, and transmitting the signal to the Master; In the second mode, the LINK Each time the device receives one byte of the multiple-byte signal transmitted from the Master, it transmits a signal including the ACK signal or the NACK signal to the Master; After completing the conversion of the multiple-byte signal received from the Master, transmit the converted signals together to the Slave SerDes; Then, receiving and holding a signal of the first communication standard including the ACK signal or the NACK signal from the Slave SerDes; Then, in response to a read request from the Master, converting the signal conforming to the first communication standard into a signal conforming to the second communication standard and transmitting the converted signal to the Master; A communication device is provided in which a signal transmitted to the Slave SerDes includes command information indicating the content transmitted from the Master, and a signal transmitted to the Master includes command information indicating the content transmitted from the Slave SerDes.

[0008] The number of bytes of the signal transmitted to the Slave SerDes in the first mode may be 2 bytes or 3 bytes excluding clock frequency information and error correction code.

[0009] In the first mode, the LINK When a signal including a Start Condition is received from the Master, the device transitions to a first state; When transitioning to the first state, converting the Start Condition into a signal conforming to the first communication standard and transmitting the signal to the Slave SerDes; Thereafter, when the device receives a signal including one byte of address information of the final destination device from the Master while in the first state, the device transitions to a second state and holds the clock from the Master at a low level; In the second state, converting a signal including the address information into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; Thereafter, when a signal including the ACK signal or the NACK signal is received from the Slave SerDes while in the second state, if a specific bit of the signal including the address information has a first bit value, it is recognized as a write and transitions to a third state; In the third state, a signal including the ACK signal or the NACK signal received from the Slave SerDes may be converted into a signal of the second communication standard and transmitted to the Master, and then the low level hold of the clock from the Master may be released.

[0010] In the first mode, the LINK When in the third state, if a signal including one byte of write data is received from the Master, the state transitions to a fourth state; In the fourth state, converting the received signal into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; Thereafter, when in the fourth state, if a signal including the ACK signal or the NACK signal is received from the Slave SerDes, the received signal may be converted into a signal of the second communication standard and transmitted to the Master.

[0011] In the first mode, the LINK When in the second state or the fourth state, if a signal including the ACK signal or the NACK signal is not received from the Slave SerDes within a predetermined period of time, transition to a fifth state; Error handling may be performed in the fifth state.

[0012] In the first mode, the LINK When receiving a signal including a Start Condition or a ReStart Condition from the Master, the device transitions to a first state; When transitioning to the first state, the received signal including the Start Condition or ReStart Condition is converted into a signal conforming to the first communication standard and transmitted to the Slave SerDes. Thereafter, when the device receives a signal including one byte of address information of the final destination device from the Master while in the first state, the device transitions to a second state and holds the clock from the Master at a low level; In the second state, converting a signal including the address information into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; Thereafter, when a signal including the ACK signal or the NACK signal is received from the Slave SerDes while in the second state, if a specific bit of the signal including the address information has a second bit value, it is recognized as a read and transitions to a sixth state; In the sixth state, a signal including the ACK signal or the NACK signal received from the Slave SerDes may be converted into a signal of the second communication standard and transmitted to the Master, and then the low level hold of the clock from the Master may be released.

[0013] In the first mode, the LINK When in the sixth state, if a signal including one byte of read data is received from the Slave SerDes, the state transitions to a seventh state; In the seventh state, the received signal is converted into a signal conforming to the second communication standard and transmitted to the Master; Thereafter, when in the seventh state, if a signal including the ACK signal or the NACK signal is received from the Master, the state may transition to the sixth state, and the received signal may be converted into a signal of the first communication standard and transmitted to the Slave SerDes.

[0014] In the first mode, the LINK When the read data is not received from the Slave SerDes within a predetermined period of time while in the sixth state, the state transitions to an eighth state; When the ACK signal or the NACK signal is not received from the Master within a predetermined period while in the seventh state, the ACK signal or the NACK signal is transitioned to the eighth state; By performing error processing in the eighth state, a deadlock of the entire system including the communication device, the Master, and the Slave SerDes may be avoided.

[0015] In the second mode, the LINK holding a received signal from the Master from the time when the signal including a Start Condition is received until the signal including a Stop Condition is received, and transmitting a signal including the ACK signal or the NACK signal to the Master for each byte of the received signal; converting the received signal into a signal conforming to the first communication standard, and transmitting the converted signal to the Slave SerDes; A signal including the ACK signal or the NACK signal may be received from the Slave SerDes and held, and then, in response to a read request from the Master, the signal from the Slave SerDes may be converted into a signal of the second communication standard and transmitted to the Master.

[0016] The command information is First information for selecting the first mode or the second mode; When the first mode is selected, second information for alternatively selecting whether the Slave SerDes or the communication device generates a clock signal for data transmission and reception at its own discretion, or whether the Slave SerDes or the communication device explicitly specifies the clock signal to be used; If the first mode is selected, third information indicating whether data for writing or reading is included; and If the first mode is selected, fourth information indicating whether the NACK signal is received; and If the first mode is selected, fifth information indicating whether the ACK signal has been received; sixth information indicating whether a Stop Condition instructing the stop of information transmission is included when the first mode is selected; When the first mode is selected, the information may include at least one of a Start Condition that instructs the start of information transmission, or seventh information that indicates whether or not it includes a Repeated Start Condition that instructs the resumption of information transmission.

[0017] In the first mode, the LINK may transmit a signal including the seventh information to the Slave SerDes, and then transmit a signal including address information of a final destination device to the Slave SerDes.

[0018] In the first mode, the LINK may transmit a signal that combines the seventh information and address information of a final destination device to the Slave SerDes.

[0019] Each of the signal to the Slave SerDes and the signal to the Master may include, in addition to the command information, at least one of an error correction code, data, clock frequency information, and information indicating the type of command being transmitted or received.

[0020] The signal to the Slave SerDes is final destination address information identifying the final destination device of the signal transmitted from the Master; subaddress information of the final destination device; The data may include at least one piece of data length information indicating the length of the data transmitted from the Master.

[0021] the command information includes command format information defined in the first communication standard when the second mode is selected; The command format information may include an error command format.

[0022] When the second mode is selected, the command information may include data end determination condition information that specifies a condition for determining the end of a signal transmitted from the Master.

[0023] The signal to the Slave SerDes and the signal from the Slave SerDes may include a command obtained by converting an I2C (Inter-Integrated Circuit) communication command into a command conforming to the first communication standard.

[0024] The protocol conversion by the LINK may be a TDD (Time Division Duplex) protocol conversion.

[0025] According to the present disclosure, a LINK is provided which performs protocol conversion of a signal from a Master SerDes and outputs the signal to a Slave, and also performs protocol conversion of a signal from the Slave and outputs the signal to the Master SerDes, the LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master SerDes to the Slave; In the first mode, the LINK When receiving a signal of a first communication standard transmitted from the Master SerDes, converting the received signal into a signal of a second communication standard in units of signals, transmitting the converted signals to the Slave, receiving a signal of the second communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal of the first communication standard, and transmitting the converted signals to the Master SerDes, repeating the process; In the second mode, the LINK When receiving a multi-byte signal of the first communication standard transmitted from the Master SerDes, converting the received signal into a signal of the second communication standard and transmitting the converted signal to the Slave byte by byte; receiving and holding a signal of the second communication standard including the ACK signal or the NACK signal from the Slave every time the converted signal is transmitted byte by byte to the Slave; After completing the transmission of the signal from the Master SerDes to the Slave, transmitting a signal of the first communication standard corresponding to the held signal to the Master SerDes; A communication device is provided in which the signal from the Master SerDes includes command information indicating the content transmitted from the Master SerDes, and the signal from the Slave includes command information indicating the content transmitted from the Slave.

[0026] According to the present disclosure, a Master SerDes having a first LINK; a Slave SerDes having a second LINK; the first LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master to the Slave SerDes; In the first mode, the first LINK converting a 1-byte signal transmitted from the Master into a signal conforming to a first communication standard in units of 1 byte, transmitting the converted signal to the Slave SerDes, receiving a signal conforming to the first communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal conforming to a second communication standard, and transmitting the signal to the Master; In the second mode, the first LINK Each time the device receives one byte of the multiple-byte signal transmitted from the Master, it transmits a signal including the ACK signal or the NACK signal to the Master; After completing the conversion of the multiple-byte signal received from the Master, transmit the converted signals together to the Slave SerDes; Then, receiving and holding a signal of the first communication standard including the ACK signal or the NACK signal from the Slave SerDes; Then, in response to a read request from the Master, converting the signal conforming to the first communication standard into a signal conforming to the second communication standard and transmitting the converted signal to the Master; The signal transmitted to the Slave SerDes includes command information indicating the content transmitted from the Master, and the signal transmitted to the Master includes command information indicating the content transmitted from the Slave SerDes; the second LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master SerDes to the Slave; In the first mode, the second LINK, when receiving a signal of a first communication standard transmitted from the Master SerDes, converts the received signal into a signal of a second communication standard in units of the received signal, transmits the converted signal to the Slave, receives a signal of the second communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response transmitted from the Slave, converts the received signal into a signal of the first communication standard, and transmits the converted signal to the Master SerDes, repeating the process; In the second mode, the second LINK When receiving a multi-byte signal of the first communication standard transmitted from the Master SerDes, converting the received signal into a signal of the second communication standard and transmitting the converted signal to the Slave byte by byte; receiving and holding a signal of the second communication standard including the ACK signal or the NACK signal from the Slave every time the converted signal is transmitted byte by byte to the Slave; After completing the transmission of the signal from the Master SerDes to the Slave, transmitting a signal of the first communication standard corresponding to the held signal to the Master SerDes; A communication system is provided in which the signal from the Master SerDes includes command information indicating the content transmitted from the Master SerDes, and the signal from the Slave includes command information indicating the content transmitted from the Slave. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a block diagram showing a schematic configuration of a communication system including a communication device according to an embodiment; [Figure 2] FIG. 2 is a block diagram of a communication system that is a more specific embodiment of FIG. [Figure 3] This diagram shows the packet write format when writing data via I2C communication between Master and Slave via a general SerDes device. [Figure 4],Equivalent block diagram when Master SerDes performs I2C communication between Master and Slave SerDes. [Figure 5] Equivalent block diagram when Slave SerDes performs I2C communication between Slave and Master SerDes. [Figure 6] FIG. 2 is a diagram showing an example of a frame structure of a signal of the communication standard X protocol. [Figure 7] A diagram showing the I2C communication protocol during Random Write. [Figure 8] Timing diagram for I2C communication using the FDD method between Master and Slave. [Figure 9A] Timing diagram for Bulk I2C mode in TDD mode. [Figure 9B] Timing diagram for Byte I2C mode in TDD method. [Figure 10A] An example of cmd_mode in Bulk I2C mode. [Figure 10B] An example of cmd_mode in Byte I2C mode. [Figure 11A] A diagram showing a first example of a command format sent and received via I2C communication when Bulk I2C mode is selected. [Figure 11B] A diagram showing a second example of the command format sent and received via I2C communication when Bulk I2C mode is selected. [Figure 11C] A diagram showing a third example of the command format sent and received via I2C communication when Bulk I2C mode is selected. [Figure 11D] FIG. 11D is a diagram for explaining a method for calculating the position of the End of Data in the third example of FIG. 11C. [Figure 11E] A diagram showing a first example of a command format when Byte I2C mode is selected. [Figure 11F] A diagram showing a second example of the command format when Byte I2C mode is selected. [Figure 12] A diagram showing the types of commands and bit sequences transmitted over the communication standard X protocol. [Figure 13A] This figure shows an example of cmd-mode settings when sending condition information and instructions for the Slave SerDes to automatically generate the clock CLK number in Byte I2C mode. [Figure 13B] This figure shows an example of cmd_mode settings when sending data and an instruction for the Slave SerDes to automatically generate the clock CLK number in Byte I2C mode. [Figure 14A] This figure shows example 1 of cmd-mode settings when sending condition information, data, and the number of clocks CLK generated by the Slave SerDes in Byte I2C mode. [Figure 14B] This figure shows example 2 of cmd-mode settings when sending condition information, data, and the number of clocks CLK generated by the Slave SerDes in Byte I2C mode. [Figure 15A] An example of sending ACK and data in Byte I2C mode. [Figure 15B] An example of sending NACK and STOP commands in Byte I2C mode. [Figure 16] A diagram showing an example of cmd_mode settings when an error occurs. [Figure 17] State transition diagram of the Master SerDes (node1) and the Slave SerDes (node2). [Figure 18] Timing diagram of the basic Write model in Byte I2C mode, where the Slave SerDes automatically generates the clock CLK number. [Figure 19] FIG. 19 is a timing diagram of Write Operation 2, which is a modification of Write Operation 1 in FIG. [Figure 20] Timing diagram for basic write operation 3 with specified clock CLK number in Byte I2C mode. [Figure 21] FIG. 21 is a timing diagram of Write Operation 4, which is a modification of Write Operation 3 in FIG. 20. [Figure 22]Timing diagram of the basic read model in Byte I2C mode, where the Slave SerDes automatically generates the clock CLK number. [Figure 23] FIG. 23 is a timing diagram of a read operation 2 which is a modification of the read operation 1 of FIG. 22. [Figure 24] Timing diagram for Read operation 3 when there is no Sub Address. [Figure 25] Timing diagram for Err operation 1 in Byte I2C mode. [Figure 26] Timing diagram for Err operation 2 in Byte I2C mode. [Figure 27] A diagram showing the signals sent and received between the Master and Master SerDes in Bulk I2C mode. [Figure 28] A diagram showing an example of data stored in table1 in mem1 in Bulk I2C mode. [Figure 29] This diagram shows the process of sending a Random Write Command from the Master SerDes to the Slave SerDes using communication standard X in Bulk I2C mode. [Figure 30] A diagram showing an example of table3 in mem2 during Random Write operation in Bulk I2C mode. [Figure 31] A diagram showing the process of sending and receiving data between the Slave SerDes and Slave via I2C communication in Bulk I2C mode. [Figure 32] This diagram shows the process of replying to a Random Write Command from the Slave SerDes to the Master SerDes using communication protocol X in Bulk I2C mode. [Figure 33] A diagram showing the memory area status of mem2 before releasing the memory area for the Random Write Command in Bulk I2C mode. [Figure 34] Diagram showing Master SerDes operation in Bulk I2C mode. [Figure 35]A diagram showing the status table1 in mem1 after receiving reply data from the Slave SerDes in response to the Random Write Command in Bulk I2C mode. [Figure 36] This diagram shows the process when the Master polls the Master SerDes for a Random Write Command in Bulk I2C mode and reads out the execution result. [Figure 37] This diagram shows the transmission of a signal from the Master to the Master SerDes in Bulk I2C mode to release the memory area of ​​mem1 as a process to end a Random Write operation. [Figure 38] A diagram showing the data stored in mem1 before the storage area is released for the Random Write Command in Bulk I2C mode. [Figure 39] A diagram showing bulk command transmission with Cmd_mode[7]=1 in Bulk I2C mode. [Figure 40] Figure continues from Figure 39. [Figure 41] A diagram showing details of the data stored in table1 in mem1 when transmitting a batch command with Cmd_mode[7]=1 in Bulk I2C mode. [Figure 42] A diagram showing the Random Read operation in Bulk I2C mode. [Figure 43] A diagram showing the data stored in table1 in mem1 during a Random Read operation in Bulk I2C mode. [Figure 44] This diagram shows the process of sending a Random Read command from the Master SerDes to the Slave SerDes using communication protocol X in Bulk I2C mode. [Figure 45] A diagram showing the data stored in table3 in mem2 during a Random Read operation in Bulk I2C mode. [Figure 46A] A diagram showing the process of sending and receiving a random read command from the Slave SerDes to the Slave in Bulk I2C mode. [Figure 46B] A diagram showing the I2C communication protocol during Random Read operation. [Figure 47] A diagram showing the data stored in table3 in mem2 after a Random Read operation in Bulk I2C mode. [Figure 48] This diagram shows the response process for a Read command from the Slave SerDes to the Master SerDes in Bulk I2C mode using communication standard X. [Figure 49] This diagram shows the processing of the Master SerDes when it receives a reply from the Slave SerDes to the Random Read Command in Bulk I2C mode. [Figure 50] A diagram showing an example of data in mem1 after receiving response data from the Slave SerDes in response to a Random Read Command in Bulk I2C mode. [Figure 51] This diagram shows the process when the Master polls the Master SerDes for a Random Read Command in Bulk I2C mode and reads out the execution result. [Figure 52] A diagram showing an example of data stored in table1 in mem1 before the memory area for the Random Read Command is released in Bulk I2C mode. [Figure 53A] This diagram shows the processing on the Slave SerDes side when performing a Current read in Bulk I2C mode. [Figure 53B] A diagram showing the I2C communication protocol when performing a current read. [Figure 54] A diagram showing an example of data stored in table3 in mem2 when a Random Read Command is performed in Bulk I2C mode. [Figure 55] Timing diagram for a normal read operation in Bulk I2C mode. [Figure 56]This figure shows an example in which the ACK / NACK signal is not received from the Slave within the time limit in Bulk I2C mode. [Figure 57] A diagram showing the data stored in table3 in mem2 when the Slave SerDes sends an error command format in Bulk I2C mode. [Figure 58] A diagram showing the data stored in table1 in mem1 when the Master SerDes receives an error command format in Bulk I2C mode. [Figure 59] Timing diagram for when an error occurs during a read in Bulk I2C mode (hereafter referred to as Read Error Case 2). [Figure 60] FIG. 10 is a diagram showing data stored in table 1 in mem 1 owned by node 1 in read error case 2. [Figure 61] FIG. 10 is a diagram showing data stored in table1 in mem1 owned by node1 in the case of a write error. [Figure 62] FIG. 2 is an equivalent block diagram of a communication system according to the present embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, an embodiment of a communication device and a communication system 3 will be described with reference to the drawings. The following description will focus on the main components of the communication device and the communication system 3, but the communication device and the communication system 3 may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] Fig. 1 is a block diagram showing a schematic configuration of a communication system including a communication device according to an embodiment, and Fig. 2 is a block diagram showing a more specific communication system than Fig. 1. The communication system in Fig. 1 and Fig. 2 is, for example, a camera image recognition system that is part of an ADAS (Advanced Driver Assistance System).

[0030] The communication device of FIGS. 1 and 2 includes an ECU 4 and an SoC 5 that can operate as a Master 21, an image sensor 12 and a temperature sensor 14 that can operate as a Slave 22, a Master SerDes 7, and a Slave SerDes 13.

[0031] The Master SerDes 7 and the Slave SerDes 13 are connected to each other so that they can communicate with each other according to a predetermined communication standard (hereinafter referred to as "communication standard X"). Examples of the predetermined communication standard X include, but are not limited to, FPD-Link III, A-phy, and ASA. Each of the Master SerDes 7 and the Slave SerDes 13 corresponds to a communication device according to this embodiment. In this specification, the Master SerDes 7 may be referred to as SerDes1, and the Slave SerDes 13 may be referred to as SerDes2.

[0032] The Master 21 and the Master SerDes 7 are connected to each other so that they can communicate with each other, for example, via I2C (Inter-Integrated Circuit) communication. Note that the communication between the Master 21 and the Master SerDes 7 is not limited to I2C communication, and may be communication using, for example, GPIO (General Purpose Input / Output).

[0033] Similarly, the Slave 22 and the Slave SerDes 13 are connected to each other so that they can communicate with each other, for example, by I2C communication. Note that the communication between the Slave 22 and the Slave SerDes 13 is not limited to I2C communication, and may be communication using, for example, GPIO.

[0034] In Figures 1 and 2, the signal path on the transmission path 6 that serially transmits information from the Slaver SerDes 13 to the Master SerDes 7 is called a downlink or forward channel, and the signal path on the transmission path 6 that serially transmits information from the Master SerDes 7 to the Slave SerDes 13 is called an uplink or reverse channel.

[0035] The ECU 4 controls the entire communication system 3 and has an I2C 4a. The ECU 4 receives an image signal from the Master SerDes 7 and performs I2C communication with the Master SerDes 7 via the I2C 4a.

[0036] The SoC 5 performs, for example, image recognition and video processing, and has an I2C 5a. The SoC 5 receives image signals from the Master SerDes 7 and performs I2C communication with the Master SerDes 7 via the I2C 5a.

[0037] The image sensor 12 captures an image and has an I2C 12a and a mem 19. The image sensor 12 outputs image data of the captured image to the Slave SerDes 13 and performs I2C communication with the Slave SerDes 13 via the I2C 12a. In this specification, the image sensor 12 may be referred to as a CIS (CMOS image sensor). The mem 19 can store pixel data captured by the image sensor 12 and data transmitted from the Master 21. In this specification, the mem 19 may be referred to as mem3.

[0038] The temperature sensor 14 measures the temperature of an arbitrary object (for example, the image sensor 12) and has an I2C 14a. The temperature sensor 14 communicates with the Slave SerDes 13 via the I2C 14a and transmits temperature data relating to the measured temperature to the Slave SerDes 13.

[0039] The Master SerDes 7 converts the format of an I2C protocol signal received from the Master 21 into a communication standard X protocol signal and transmits it to the Slave SerDes 13, and also converts the format of a communication standard X protocol signal received from the Slave SerDes 13 as appropriate to generate image data and an I2C protocol signal and output them to the Master 21. The Master SerDes 7 has a LINK 11, a forward receiver (Fw.Rx) 9, a reverse transmitter (Rv.Tx) 10, and an I2C 7a.

[0040] The LINK 11 converts the format of an I2C protocol signal received from the Master 21 via the I2C 7a into a signal conforming to the communication standard X protocol and transmits it to the Slave SerDes 13 via the Rv.Tx 10. The LINK 11 also generates image data from the communication standard X protocol signal received from the Slave SerDes 13 via the Fw.Rx 9 and transmits it to the Master 21, or generates an I2C protocol signal containing information other than image data and outputs it to the Master 21 via the I2C 7a.

[0041] The Slave SerDes 13 converts the format of I2C protocol signals and image signals received from the Slave 22 into signals conforming to the communication standard X protocol and transmits them to the Master SerDes 7, and also converts the format of communication standard X protocol signals received from the Master SerDes 7 as appropriate into signals conforming to the I2C protocol and outputs them to the Slave 22. The Slave SerDes 13 has an I2C 13a, a LINK 17, a forward transmitter (Fw.Tx) 16, a reverse receiver (Rv.Rx) 15, and an I2C 13a.

[0042] The LINK 17 converts the format of I2C protocol signals and image data received from the Slave 22 via the I2C 13a into signals conforming to the communication standard X protocol, and transmits them to the Master SerDes 7 via the Fw.Tx 16. The LINK 17 also converts communication standard X protocol signals received from the Master SerDes 7 via the Rv.Rx 15 into signals conforming to the I2C standard, and transmits them to the Slave 22 via the I2C 13a. At this time, the following problems 1) and 2) may occur.

[0043] 1) When the ECU 4 or SoC 5 constituting the Master 21 uses I2C communication to control the image sensor 12 or temperature sensor 14 constituting the Slave 22, the Master 21 must receive an ACK or NACK signal from the Slave 22 every time it transmits an information unit, such as one byte. In this case, the propagation delay of the I2C communication via the Master SerDes 7 and the Slave SerDes 13 may be larger than the period of one clock cycle (the frequency of one clock is, for example, 400 kHz or 1 MHz) of I2C communication. In this case, the Master SerDes 7 receives the ACK or NACK signal from the Slave 22 via the Slave SerDes 13, and holds the clock (SCL) of the I2C protocol signal at a low level until the Master SerDes 7 is ready to output the ACK or NACK signal to the Master 21 via the I2C 7a after completing the I2C protocol conversion. After the Master SerDes 7 is ready to output the ACK or NACK signal sent by the Slave 22 to the Master 21, it releases the low level of the clock (SCL) of the I2C protocol signal that it had been holding. As a result, the Master 21 is able to resume I2C communication and receive the ACK or NACK signal. While the Master SerDes 7 is holding the SCL at a low level, the Master 21 cannot perform I2C communication, which can cause problems such as command transfer taking a long time or being unable to communicate with other Slaves 22 connected to the I2C bus (for example, the temperature sensor 14 when waiting for an ACK or NACK signal from the image sensor 12).

[0044] 3 shows I2C communication when a HOST I2C (e.g., Master 21) writes data to a REMOTE I2C (e.g., Slave 22) via Master SerDes 7 and Slave SerDes 13. Here, the SCL low period of the HOST I2C indicates that the Master SerDes 7 holds the SCL at a low level until it is ready to output an ACK or NACK signal from Slave 22, and during this period, the HOST I2C is unable to perform I2C communication.

[0045] 2) It is also preferable that various devices other than the image sensor 12 and temperature sensor 14 can be connected to the Slave SerDes 13 as Slaves 22. These various Slaves 22 may have different I2C operating clocks. For this reason, it is expected that the Slave SerDes 13 will perform I2C communication with various Slaves 22, and the I2C operating clock of the Slave 22 (the operating clock for I2C communication between the Slave 22 and the Slave SerDes 13) may be set lower than necessary.

[0046] In Figure 3, as mentioned above, if the I2C operating clock frequency of Slave 22 is set lower than necessary, it means that the I2C operating interval of REMOTE I2C (the interval other than SCL low on the REMOTE I2C side in Figure 3) will be longer, which, along with the issue of the SCLLow interval on the HOST I2C side being longer, will further extend the time required to complete I2C communication.

[0047] 1 and 2, in order to solve the above-mentioned problem 1), a storage device (mem 11a in FIG. 1) is provided in the Master SerDes 7, and when the Master SerDes 7 receives one byte from the Master 21, the Master SerDes 7 stores the one byte in the storage device and returns an ACK signal or NACK signal to the Master 21 instead of the Slave 22. This makes it possible to shorten the SCL low period extended by the Master 21.

[0048] 1, to solve the above-mentioned problem 2), the Master 21 sets the CLK_value(Data[0]) described below, and the Slave SerDes 13 performs I2C communication with the Slave 22 at the frequency specified by the CLK_value(Data[0]). As a result, the Slave 22 and the Slave SerDes 13 can realize I2C communication at the specified frequency.

[0049] The LINK 11 in FIG. 2 has an I2C Cmd Unit 8 and a mem 11a. The I2C Cmd Unit 8 stores table 2 in a ROM (not shown), and the mem 11a stores table 1. The mem 11a is a volatile memory. In this specification, the mem 11a may be referred to as mem1. Every time the LINK 11 receives one byte from the Master 21 via the I2C 7a, the LINK 11 writes the one byte to table 1 in the mem 11a and returns an ACK signal or NACK signal to the Master 21 on behalf of the Slave 22. When a predetermined condition is met (for example, data has been written up to the end of data), the LINK 11 reads table 1 and transmits it to the Slave SerDes 13 via the Rv.Tx 10. In addition, LINK 11 writes the signal received from Slave SerDes 13 via Fw.Rx to table 1 of mem 11a, and when a predetermined condition is met (for example, writing up to the end of data), it reads table 1 and performs I2C communication with Master 21 via I2C 7a, and at the same time transmits image data captured by Image Sensor 12 received from Slave SerDes 13 via Fw.Rx 9 to Master 21.

[0050] 2 includes an I2C command unit 18 and a mem 17a. The I2C command unit 18 stores table 2 in a ROM (not shown), and the mem 17a stores table 3. In this specification, the mem 17a may be referred to as mem2. The LINK 17 writes a signal received from the Master SerDes 7 via the Rv.Rx 15 to table 3 of the mem 17a, and when a predetermined condition is met (for example, writing has been completed up to the end of data), it reads table 3 and transmits it to the Slave 22 via the I2C 13a. In addition, when the LINK 17 receives signals by performing I2C communication with the Slave 22 via the I2C 13a, or receives temperature data converted into the I2C protocol from the temperature sensor 14 via the I2C 13a, it writes the data into table 3 of the mem 17a, and when a predetermined condition is met (for example, when the data has been written up to the end of data), it reads table 3 and transmits it to the Master SerDes 7 via the Fw.Tx 16.

[0051] Fig. 4 is an equivalent block diagram of the communication system 3 of Fig. 1 and Fig. 2 when the Master SerDes 7 performs I2C communication between the Master 21 and the Slave SerDes 13. In Fig. 4, the Master SerDes 7 is the communication device, the Master 21 is the first external device, and the Slave SerDes 13 is the second external device.

[0052] 4 generates a first output signal based on a first external signal from a first external device (Master 21) and outputs it to a second external device (Slave SerDes 13). Also, the communication device (Master SerDes 7) generates a second output signal based on a second external signal from the second external device (Slave SerDes 13) and outputs it to the first external device (Master 21).

[0053] 5 is an equivalent block diagram of the communication system 3 of FIGS. 1 and 2 when the Slave SerDes 13 performs I2C communication between the Slave 22 and the Master SerDes 7. In FIG. 5, the Slave SerDes 13 is a communication device, the Slave 22 is a first external device, and the Master SerDes 7 is a second external device.

[0054] 5 generates a first output signal based on a first external signal from a first external device (Slave 22) and outputs it to a second external device (Master SerDes 7). Also, the communication device (Slave SerDes 13) generates a second output signal based on a second external signal from the second external device (Master SerDes 7) and outputs it to the first external device (Slave 22).

[0055] Each of the first output signal and the second external signal in Figures 4 and 5 includes command information Cmd_mode indicating the content of the command transmitted from the first external device, final destination device identification information Slave_Adr identifying the final destination device of the data transmitted from the first external device, internal address information Sub_Adr of the final destination device, data length information Length of the data transmitted from the first external device, and data end position information End of Data transmitted from the first external device.

[0056] Slave_Adr may be placed next to Cmd_mode, Sub_Adr may be placed next to Slave_Adr, and Length may be placed next to Sub_Adr.

[0057] Cmd_mode may include command format information Cmd_mode[2:0] that defines a command format on communication standard X, including a function for distinguishing between a write command and a read command. That is, Cmd_mode may include Cmd_mode[2:0] that defines a command format on a predetermined communication standard between the communication device and the second external device.

[0058] Cmd_mode includes at least Cmd_mode[0]-Cmd_mode[7], and the data end determination condition information Cmd_mode[7] may specify a condition for determining the end of data transmitted from the first external device.

[0059] Each of the first output signal and the second external signal may further include communication frequency information CLK_value specifying a communication frequency between the second external device and the final destination device.

[0060] The first output signal and the second external signal may include a command obtained by protocol-converting an I2C (Inter-Integrated Circuit) communication command into a predetermined communication standard between the communication device and the second external device.

[0061] LINK 11, 17 may transmit an ACK signal indicating a positive response or a NACK signal indicating a negative response to the first external device each time it receives each information unit constituting the first external signal from the first external device.

[0062] LINK11, 17 has a memory unit that stores a signal corresponding to a first external signal and a signal corresponding to a second external signal,

[0063] When LINK 11, 17 finishes receiving the first external signal from the first external device, it may collectively convert the protocol of the first external signal that has been received and stored in the memory unit, and then generate a first output signal.

[0064] The protocol conversion by the LINKs 11 and 17 may be a protocol conversion compatible with TDD (Time Division Duplex).

[0065] LINK 11, 17 may transmit a first output signal to a second external device, and upon receiving information from the second external device indicating that processing of the first output signal has been completed, may store a signal indicating the completion of processing in a memory unit.

[0066] The LINK 11, 17 may release the storage area of ​​the storage unit based on a command from the first external device.

[0067] LINK 11, 17 may output processing completion information for a second external signal transmitted from a second external device to the first external device in response to a request signal from the first external device, or may output an interrupt request flag to the first external device for performing interrupt processing on the first external device.

[0068] LINK 11, 17 may receive a first external signal from a first external device, the first external signal including output instruction information cmd_done instructing the output of a first output signal and transmission end information P (STOP condition) indicating the end of transmission of the first external signal.

[0069] When a first value is received as data end determination condition information specifying the conditions for determining the end of data transmitted from the first external device, LINK 11, 17 may recognize that the first external signal transmitted from the first external device has ended when transmission end information P (STOP condition) indicating the end of transmission of the first external signal is received.

[0070] When a second value is received as data end determination condition information specifying the conditions for determining the end of data transmitted from the first external device, LINK11, 17 may recognize that the first external signal transmitted from the first external device has ended when output instruction information instructing the output of the first output signal and transmission end information indicating the end of transmission of the first external signal are received, regardless of the value of data end determination condition information received thereafter.

[0071] The LINK 11, 17 may release the storage area of ​​the storage unit after transmitting the first output signal to the second external device.

[0072] LINK11, 17 may perform at least one of the following operations within a predetermined number of times or time: outputting a signal based on a second external signal stored in a memory unit after performing protocol conversion for a second output signal to a first external device for each information unit; and receiving each information unit constituting the first external signal output from the first external device.

[0073] FIG. 6 is a diagram showing an example of a frame structure of a signal of the communication standard X protocol transmitted and received between the Master SerDes 7 and the Slave SerDes 13. In FIG.

[0074] The frame structure in Fig. 6 includes multiple containers between a Sync pattern and a Parity pattern. The Sync pattern is a signal pattern for synchronizing the physical layers of the Master SerDes 7 and the Slave SerDes 13. The multiple containers include, for example, 2 to 100 containers. The number of containers included in the frame structure varies depending on the signal transmission state. Parity is a bit or bit string for error detection or error correction processing.

[0075] The container structure includes a header, payload, and parity. The header includes address information indicating the destination of the payload. The payload is the main part of the signal being sent and received. In addition to the video signal, the payload also includes OAM (Operations, Administration, Maintenance) for SerDes control. Parity is a bit or bit string used for error detection or error correction processing of the payload.

[0076] Payload contains the following information: CLK value, Cmd_mode, Slave Adr, length, data, and End of data. CLK value is the operating clock of Slave 22, i.e., the SCL frequency used by Slave SerDes 13 for I2C communication with Slave 22. Cmd_mode indicates the content of the command sent from Master 21. Slave Adr is address information that identifies Slave 22. Length is the length of the data sent from Master 21. End of data is the end position of the data sent from Master 21.

[0077] If Cmd_mode is extended to two bytes, the most significant byte of Cmd_mode may be assigned to Cmd_ID. Cmd_ID is identification information for distinguishing and identifying commands transmitted from the Master 21.

[0078] When data communication is performed between the Master 21 and the Slave 22 using the TDD method, the signal ratio of the signal Rv from the Master 21 to the Slave 22 and the signal ratio of the signal Fw from the Slave 22 to the Master 21 within one TDD cycle can be changed by changing the number of containers included in each frame structure. Note that the container sizes of the signal Rv and the signal Fw may be the same or different.

[0079] In the communication system according to this embodiment, I2C communication is performed between the Master 21 and the Master SerDes 7, and also between the Slave SerDes 13 and the Slaver 22. In the I2C communication, it is possible to select either a first mode (also called a Byte I2C mode) in which an ACK signal / NAK signal is received every time a predetermined number of bytes of information (for example, 1 or 2 bytes when no error correction code is transmitted, or 2 or 3 bytes when an error correction code is transmitted) is transmitted, or a second mode (Bulk I2C mode) in which an ACK signal / NAK signal is received every time bulk information, which is a group of multiple bytes of information, is transmitted.

[0080] On the other hand, when I2C communication is performed between the Master SerDes 7 and the Slave SerDes 13 using the FDD (Frequency Division Duplexing) method, as shown in the timing diagram of Figure 8, to send information from the Master 21 to the Slave 22 as the final destination, an ACK / NACK signal is received repeatedly every time one byte of data is sent. Unlike the TDD method, the FDD method does not require switching between uplink and downlink, and information can be sent from the Master 21 to the Slave 22 or from the Slave 22 to the Master 21 at any timing.

[0081] 9A is a timing diagram of the Bulk I2C mode in the TDD system, and FIG. 9B is a timing diagram of the Byte I2C mode in the TDD system. In the Bulk I2C mode, the Master SerDes 7 transmits a signal including an ACK signal or a NACK signal to the Master 21 each time it receives a multi-byte signal transmitted from the Master 21, as shown in FIG. 9A. Next, after the Master SerDes 7 completes conversion of the multi-byte signal received from the Master 21, it transmits the converted signals together to the Slave SerDes 13. Specific conversion methods include converting from the I2C protocol to communication protocol X each time the Master SerDes 7 receives one byte of data from the Master 21, and converting from the I2C protocol to communication protocol X all at once after receiving all the multi-byte data from the Master 21. Thereafter, the Master SerDes 7 receives and holds a signal of communication protocol X (first communication standard) including an ACK signal or a NACK signal from the Slave SerDes 13. Thereafter, in response to a read request from the Master 21, the Master SerDes 7 converts the signal of communication protocol X into a signal of the I2C protocol (second communication standard) and transmits it to the Master 21. The signal transmitted to the Slave SerDes 13 includes command information indicating the content transmitted from the Master 21 , and the signal transmitted to the Master 21 includes information transmitted from the Slave SerDes 13 . 9A, in the Bulk I2C mode, when the Slave SerDes 13 receives a multi-byte signal of communication protocol X transmitted from the Master SerDes 7, it converts the received signal into an I2C protocol signal and transmits the converted signal byte by byte to the Slave 22. Every time it transmits the converted signal byte by byte to the Slave 22, it receives and holds an I2C protocol signal including an ACK signal or NACK signal from the Slave 22. After transmitting the signal from the Master SerDes 7 to the Slave 22, it transmits a communication protocol X signal corresponding to the held signal to the Master SerDes 7.

[0082] On the other hand, in the Byte I2C mode, as shown in FIG. 9B, the Master SerDes 7 converts a 1-byte signal transmitted from the Master 21 into a signal conforming to the first communication standard, transmits the converted signal to the Slave SerDes 13, and then receives a signal conforming to the first communication standard including an ACK signal indicating a positive response or a NACK signal indicating a negative response transmitted from the Slave SerDes 13, converts the received signal into a signal conforming to the second communication standard, and transmits it to the Master 21.

[0083] In addition, in the Byte I2C mode, as shown in FIG. 9B, when the Slave SerDes 13 receives a signal of the first communication standard transmitted from the Master SerDes 7, it converts the received signal into a signal of the second communication standard in units of one signal, transmits the converted signal to the Slave 22, and then receives a signal of the second communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response transmitted from the Slave 22, converts the received signal into a signal of the first communication standard, and transmits it to the Master SerDes 7.

[0084] The information in Cmd_mode in the frame structure shown in Figure 6 differs between Bulk I2C mode and Byte I2C mode. In this specification, Cmd_mode may be referred to as command information. Cmd_mode is, for example, 1 byte of information, and the information in each bit differs between Bulk I2C mode and Byte I2C mode.

[0085] Figure 10A shows an example of cmd_mode in Bulk I2C mode. Bit [7] of cmd_mode in Figure 10A selects the mode described above: 1 indicates Byte I2C mode, 0 indicates Bulk I2C mode. Bit [6] specifies whether to retry when a NACK signal is received in I2C communication on the slave side; 1 indicates retry, 0 indicates no retry. Bit [5] indicates the behavior of SlaveSerDes 13 when it receives a NACK signal while accessing Slave 22; 1 indicates ignoring the NACK and continuing to output raw data in the case of a write; 0 indicates normal processing. Bit [4] specifies the bulk I2C command transmission mode; 1 indicates transmission when End of Data and cmd_doen are displayed. 0 indicates transmission is terminated at the End of Data. Bit [3] selects the I2C address mode on the slave side, where 1 indicates the address of the current location without an offset address and 0 indicates the address of the current location with an offset address. Bits [2:0] indicate the I2C format type of communication standard X, where 111 indicates the error command format, 110 indicates the special command format, 10X indicates reserved, 011 indicates the read response format, 010 indicates the AC / NACK format, 001 indicates the read command format, and 000 indicates the write command format.

[0086] Figure 10B shows an example of cmd_mode in Byte I2C mode. Bit [7] of cmd_mode in Figure 10B is the same as bit [7] in Figure 10A and is sometimes referred to as "first information" in this specification. Bits [6:5] select the clock mode and are sometimes referred to as "second information" in this specification. The clock mode includes a mode in which node 2 (Master SerDes 7) automatically generates a clock signal for node 2 (Slave SerDes 13), and a mode in which node 1 calculates and notifies node 2 of the number of clock periods (9 / 8 / 1) used by node 2 on behalf of node 2. "11" indicates that node 2 generates nine clock signals including ACK / NACK signals and data. "10" indicates that node 2 generates eight clock signals including data. "01" indicates that node 2 generates one clock signal including an ACK / NACK signal. "00" indicates that node 2 automatically generates 9 / 8 / 1 clock signals.

[0087] Bits [4:0] are the I2C packet type, which defines the packetized I2C data. Bit [4] indicates whether the data is for Write or Read, or other data, and is sometimes referred to herein as the third bit. A 1 in bit [4] indicates that a Write / Read data packet follows. A 0 in bit [4] indicates that no Write / Read data packet follows. Bit [3] indicates whether a NACK signal was received, and is sometimes referred to herein as the fourth bit. A 1 in bit [3] indicates that a NACK signal was received from Slave 22 or Master 21, and a 0 indicates that a NACK signal was not received. Bit [2] indicates whether an ACK signal was received, and is sometimes referred to herein as the fifth bit. A 1 in bit [2] indicates that an ACK signal was received from Slave 22 or Master 21, and a 0 indicates that an ACK signal was not received. Bit [1] indicates whether a STOP command is included, and is sometimes referred to herein as the sixth bit. A 1 in bit [1] indicates that a STOP command was detected, and a 0 indicates that a STOP command was not detected. Bit [0] is information indicating whether a START / ReSTART command is included, and is sometimes referred to as the seventh information in this specification. A 1 in bit [0] indicates that a START / ReSTART command was detected, and a 0 indicates that a START / ReSTART command was not detected.

[0088] 10A and 10B are merely examples, and any information can be assigned to each bit of cmd_mode. Furthermore, cmd_mode may have a length of two bytes or more.

[0089] FIG. 11A shows a first example of a command format sent and received via I2C communication when Bulk I2C mode is selected. As shown in FIG. 11A, when Bulk I2C mode is selected, there are a Write command format, a Read command format, an ACK / NACK command format, a Read response format, and a Special Command Format. The Write command format includes clk_value, cmd_mode, Sl_adr, Sub_adrH, Sub_adrL, lengthH, lengthL, WDATA, and End of data. The Read command format is the same as the Write command format except that it does not include WDATA. The ACK / NACK command format includes clk_value, cmd_mode, Master_adr, Sub_adrH, Sub_adrL, lengthH, lengthL, Sl_adr, ACK / NACK, and End of data. The Read response format is the ACK / NACK command format with RDATA added. The Special Command Format includes clk_value, cmd_mode, Cmd_done, and End of data.

[0090] FIG. 11B shows a second example of a command format sent and received via I2C communication when Bulk I2C mode is selected. In the second example shown in FIG. 11B, an error correction code (CRC) is added after the End of Data at the end of each command format shown in FIG. 11A. The second example in FIG. 11B also includes a new error command format that was not present in the first example in FIG. 11A. The error command format includes clk_value, cmd_mode, End of data, and CRC. The error command format will be described later.

[0091] 11A and 11B include an End of Data (EoD) near the end of each command format, but the EoD can be omitted. Fig. 11C shows a third example of a command format sent and received via I2C communication when Bulk I2C mode is selected, with the EoD omitted from each format in Fig. 11A. Even if EoD information is used internally between the Master SerDes 7 and Slave SerDes 13, the communication format between the Master SerDes 7 and Slave SerDes 22 does not require EoD; the receiving side can calculate the data end position from information in cmd_mode, lengthH, and lengthL.

[0092] FIG. 11D is a diagram illustrating a method for calculating the end-of-data position in the third example of FIG. 11C. The Read command format, ACK / NACK format, special command format, and error command format each have a fixed byte length. More specifically, the Read command format is 7 bytes, the ACK / NACK format is 9 bytes, the special command format is 3 bytes, and the error command format is 2 bytes. This makes it possible to identify the end position of each format even without EnD. Note that the ACK / NACK format is not necessarily fixed at 9 bytes. All ACKs / NACKs received during I2C communication may be added.

[0093] On the other hand, the Write command format and Read response format contain variable-length data WDATA or RDATA, but the length of WDATA or RDATA is the sum of lengthH and lengthL. Therefore, the End of Data position can be identified from the values ​​of lengthH and lengthL. For example, if the Write command format has a 7-byte header + 64 bytes of WDATA = 71 bytes, and the Read response format has a 7-byte header + 64 bytes of RDATA = 71 bytes, the sum of lengthH and lengthL is 64, so the end position of each format can be identified even without EoD.

[0094] Fig. 11E is a diagram showing a first example of a command format when the Byte I2C mode is selected. As shown in Fig. 11E, when the Byte I2C mode is selected, the I2C condition format or the I2C data format is selected.

[0095] The I2C condition format includes cmd_mode and CRC. The I2C commands sent in the I2C condition format are S(START), Sr(ReSTART), P(STOP), and ACK / NACK. The I2C data format includes cmd_mode, Data, and CRC. The I2C commands sent in the I2C data format are S(START), Sr(ReSTART), P(STOP), and ACK / NACK+data.

[0096] A clk_value or cmd_id may be added to the command format of FIG. 11E. FIG. 11F is a diagram showing a second example of a command format when Byte I2C mode is selected. The second example of FIG. 11F shows an example in which clk_value and cmd_id are added immediately before cmd_mode in the first example of FIG. 11E. It is optional whether or not to add a CRC to the end of each format in the second example of FIG. 11F. The same applies to the first example of FIG. 11E.

[0097] Figure 12 shows the types and bit sequences of I2C commands transmitted over the communication standard X protocol in Bulk I2C mode. In Figure 12, ACK is a positive response indicating that processing has been completed successfully. NACK is a negative response indicating that processing has not been completed successfully.

[0098] Repeated_start is a start flag indicating that the I2C protocol signal is continuing. Specifically, it corresponds to Sr in the I2C combined format shown in Figure 7. Sr is a flag that is issued before starting the next I2C communication when, after starting I2C communication from the Master 21 to the Master SerDes 7 (after issuing an S (START condition)), the next I2C communication is started without terminating the previous I2C communication (without issuing a P (STOP condition)).

[0099] The end of data in an I2C command transmitted over the communication standard X protocol indicates P (STOP condition). When Cmd_mode[4]=0 in Bulk I2C mode, it indicates that the I2C protocol signals from S (START condition) to P (STOP condition) are sent to the Slave SerDes 13.

[0100] In the I2C command transmitted over the communication standard X protocol, cmd_done is a special command used when the next data is 0xFF when Cmd_mode[4]=1 in Bulk I2C mode. cmd_done is information that instructs the Slave SerDes 13 to send one or more sets of I2C protocol signals from S (START condition) to P (STOP condition), counting them as one set.

[0101] The Rsv_command in the I2C command transmitted on the communication standard X protocol is reserved and is not specified at present. The data in the I2C command indicates data to be written to the slave 22 or data read from the slave 22.

[0102] 12 shows an example in which an I2C command transmitted over the communication standard X protocol is expressed in 8 bits, but this is not limiting and it may be expressed in 9 bits or more. For example, when expressed in 9 bits, if the I2C protocol signal is "data", the 1st bit on the MSB side is set to "0", and if the I2C protocol signal is not "data", the 1st bit on the MSB side is set to "1", making it easy to determine whether the I2C protocol signal is "data" or something else. (Details of Byte I2C mode operation)

[0103] 13A and 13B are diagrams showing examples of cmd_mode settings when the Slave SerDes 13, which is node 2, automatically generates the clock CLK. FIG. 13A shows an example of cmd_mode settings when transmitting condition information and an instruction for the Slave SerDes 13 to automatically generate the number of clocks CLK in Byte I2C mode. The cmd_mode for 1 byte of data is set to 8'b1000_0001. Each bit of cmd_mode is set according to FIG. 10B. Of these, bit [7] = 1 indicates Byte I2C mode. Bits [6:5] = 00 indicate that node 2 automatically generates the clock CLK. Bit [4] = 0 indicates that no data is included. Bit [3] = 0 indicates that a NACK signal is not received. Bit [2] = 0 indicates that an ACK signal is not received. Bit [1] = 0 indicates that a STOP command is not included. Bit [0] = 1 indicates that a START command is included.

[0104] FIG. 13B shows an example of cmd_mode settings when transmitting data and an instruction for the Slave SerDes 13 to automatically generate the clock CLK number in Byte I2C mode. cmd_mode is set to 8'b1001_0000. Of these, bit [7] = 1 indicates Byte I2C mode. Bit [6:5] = 00 indicates that node2 automatically generates the clock CLK. Bit [4] = 1 indicates that data is included. Bit [3] = 0 indicates that a NACK signal was not received. Bit [2] = 0 indicates that an ACK signal was not received. Bit [1] = 0 indicates that a STOP command was not included. Bit [0] = 0 indicates that a START command was not included.

[0105] As shown in FIGS. 13A and 13B, the number of bytes of the signal transmitted from the Master SerDes 7 to the Slave SerDes 13 in the Byte I2C mode is 2 or 3 bytes excluding the clock frequency information clk_value and the error correction code CRC.

[0106] 14A and 14B are diagrams illustrating an example in which the Slave SerDes 13 (node ​​2) manually generates the clock CLK based on the number of cycles instructed by the Master SerDes 7 (node ​​1). FIG. 14A illustrates a first example of cmd-mode settings when transmitting condition information, data, and a designation of the number of clocks CLK generated by the Slave SerDes in Byte I2C mode. FIG. 14B illustrates a second example of cmd-mode settings when transmitting condition information, data, and a designation of the number of clocks CLK generated by the Slave SerDes in Byte I2C mode. The cmd_mode in FIG. 14A is set to 8'b1000_0001. Bits [6:5] of cmd_mode = 01 indicate that node 2 instructs the generation of a one-cycle clock CLK. Bit [4] = 1 indicates that data is included. The other bits are the same as in FIG. 13A.

[0107] The cmd_mode in Fig. 14B is set to 8'b1111_0001. Bits [6:5] of cmd_mode = 11 indicate that node2 instructs the generation of a clock CLK with 9 cycles. The other bits are the same as in Fig. 14A.

[0108] Similarly, FIG. 15A shows an example of transmitting ACK and data in Byte I2C mode.

[0109] FIG. 15B shows an example of sending a NACK and STOP command in Byte I2C mode.

[0110] Figure 16 shows an example of how cmd_mode is set when an error occurs. In Figure 16, cmd_mode is set to 8'b1xx0_1111. Bits [6:5] of cmd_mode = xx indicate don't care. Bits [3:0] are set to 1111. In this way, when the lowest four bits of cmd_mode are all 1, it indicates that an error has occurred during Byte I2C mode execution.

[0111] FIG. 17 is a state transition diagram of the Master SerDes 7, which is node 1, and the Slave SerDes 13, which is node 2. Both node 1 and node 2 transition states based on the state transition diagram shown in FIG. 17. The state transition diagram in FIG. 17 shows state transitions in the Byte I2C mode of FIG. 9B. Note that in the Bulk I2C mode of FIG. 9A, data is transmitted and received collectively from S (START condition) to P (STOP condition), so there is no need to consider state transitions. Below, the state transitions of node 1 and node 2 in the Byte I2C mode are explained based on FIG. 17.

[0112] When powered on, node 1 and node 2 transition to the initial state init (state S1). When node 1 receives an I2C protocol S / Sr (START / ReSTART) command from Master 21 while in the initial state init, it transitions to START state ST (state S2). When node 1 is in START state ST, it converts the I2C protocol S / Sr (START / ReSTART) command received in state S1 into a packet conforming to communication standard X in Figure 13A and sends it to node 2. When node 2 receives the S / Sr (START / ReSTART) command from node 1, it transitions to Start state ST and sends the S / Sr (START / ReSTART) command converted to I2C protocol to Slave 22.

[0113] When node 1 receives data D from Master 21 while in Start state ST, it determines whether the data is a slave address (state S3). If it is not a slave address, it returns to state S1. If it is a slave address, it transitions to slave address state S1_Addr (state S4). In slave address state S1_Addr, node 1 instructs Master 21 to perform clock stretching. Clock stretching means holding the clock from Master 21 at a low level. During the clock stretch period, Master 21 cannot send new information to node 1. Also, in slave address state S1_Addr, node 1 converts the slave address of the I2C protocol into a packet of communication standard X and sends it to node 2. When node 2 receives the slave address from node 1, it transitions to slave address state S1_Addr and transmits the slave address converted to the I2C protocol to Slave 22. When node 2 receives an ACK / NACK signal from Slave 22 while in the Slave address state S1_Addr, it transitions to Write state W, converts the ACK / NACK signal into the protocol of communication standard X, and transmits it to node 1.

[0114] When node 1 receives an ACK / NACK signal from node 2 while in the Slave address state Sl_Addr, it transitions to Write state W (state S5). In Write state W, it instructs Master 21 to release clock stretching, converts the ACK / NACK signal from node 2 to the I2C protocol, and sends it to Master 21. When node 1 receives data D from Master 21 while in Write state W, it transitions to Write data state WD (state S6). In this state, if it returns an ACK / NACK signal to Master 21, it returns to Write state W. When node 1 receives a P(STOP) command from Master 21 while in Write state W, it transitions to End state End (state S7). In End state End, it converts the P(STOP) command of the I2C protocol into a packet of communication protocol X and sends it to node 2, and then returns to the initial state init.

[0115] When node 2 receives a slave address including a read bit and transitions to the slave address state Sl_Addr of state S4, if it receives an ACK or NACK from slave 22, it transitions to read state R (state S8). After that, node 2 converts the ACK or NACK of the I2C protocol into a packet of communication protocol X and sends it to node 1. When node 2 receives data D from the slave in read state R, it transitions to read data state RD (state S9). Node 2 converts the read data into an I2C protocol packet of communication protocol X and sends it to node 1. When node 1 receives an ACK / NACK packet from node 2, it transitions to read state R and sends an ACK or NACK to master 21. After that, when it receives a read data packet, it transitions to read data state RD and sends the read data to master 21. In the read data state RD, if an ACK / NACK signal is not received within the time limit, a timeout occurs and the state transitions to a data error state (state S10). Similarly, in the read state R, if data D is not received from the slave within the time limit, a timeout occurs and the state transitions to the data error state of state S10. In the data error state, if a dummy data signal is returned to the master 21, the state returns to the read state R of state S8.

[0116] On the other hand, when in the Write data state WD of state S6, if an ACK / NACK signal is not received from the Slave within the time limit, a timeout occurs and the state transitions to the ACK error state a_err (state S11). Also, when in the Slave address state Sl_Addr of state S4, if an ACK / NACK signal is not received from the Slave within the time limit, the state transitions to the ACK error state a_err of state S11. If a predetermined error processing is performed in the ACK error state a_err, the state returns to state S1.

[0117] The state transitions when the Master SerDes 7 performs a Byte I2C mode write can be summarized as follows: When the LINK 11 in the Master SerDes 7 receives a signal including a Start Condition from the Master 21, it transitions to the Start state ST (first state). When the LINK 11 transitions to the Start state ST, it converts the Start Condition into a signal of communication protocol X (first communication standard) and sends it to the Slave SerDes 13. When the LINK 11 subsequently receives a signal including one byte of address information (slave address) of the final destination device from the Master 21 while in the Start state ST, it transitions to the Slave address state S1_Addr (second state) and holds the clock from the Master 21 at a low level. In the Slave address state S1_Addr, the LINK 11 converts the signal including the address information into a signal of communication protocol X and sends it to the Slave SerDes 13. Thereafter, when LINK 11 receives a signal including an ACK signal or a NACK signal from Slave SerDes 13 while in Slave address state S1_Addr, if a specific bit of the signal including address information is the first bit value, it recognizes it as a write and transitions to Write state W (third state). In Write state W, LINK 11 converts the signal including the ACK signal or NACK signal received from Slave SerDes 13 into a signal of the I2C protocol (second communication standard) and transmits it to Master 21, and then releases the low level hold of the clock from Master 21.

[0118] Furthermore, when the LINK 11 receives a signal including one byte of write data from the Master 21 while in the Write state W, it transitions to the Write data state WD (fourth state). In the Write data state WD, the LINK 11 converts the received signal into a signal of the communication protocol X and transmits it to the Slave SerDes 13. Thereafter, when the LINK 11 receives a signal including an ACK signal or a NACK signal from the Slave SerDes 13 while in the Write data state WD, it transitions to the Write state W and converts the received ACK / NACK signal into a signal of the I2C protocol and transmits it to the Master 21.

[0119] In addition, when LINK 11 is in the Slave address state S1_Addr or the Write data state WD, if it does not receive a signal including an ACK signal or a NACK signal from Slave 22 within a predetermined period of time, it transitions to the ACK error state a_err (fifth state) and performs error processing in the ACK error state a_err.

[0120] On the other hand, the state transitions when the Master SerDes 7 performs a Byte I2C mode read can be summarized as follows: When LINK 11 in the Master SerDes 7 receives a signal including a Start Condition or ReStart Condition from the Master 21, it transitions to the Start state ST. When LINK 11 transitions to the Start state ST, it converts the received signal including the Start Condition or ReStart Condition into a signal of communication protocol X and sends it to the Slave SerDes 13. When LINK 11 subsequently receives a signal including one byte of address information of the final destination device from the Master 21 while in the Start state ST, it transitions to the Slave address state S1_Addr and holds the clock from the Master 21 at a low level. In the Slave address state S1_Addr, LINK 11 converts the signal including the address information into a signal of communication protocol X and sends it to the Slave SerDes 13. Thereafter, when LINK 11 receives a signal including an ACK signal or a NACK signal from Slave SerDes 13 while in Slave address state S1_Addr, if a specific bit of the signal including address information is the second bit value, it recognizes it as a read and transitions to Read state R (sixth state). In Read state R, LINK 11 converts the signal including the ACK signal or NACK signal received from Slave SerDes 13 into an I2C protocol signal and transmits it to Master 21, and then releases the low level hold of the clock from Master 21.

[0121] Furthermore, when the LINK 11 receives a signal including one byte of read data from the Slave SerDes 13 while in the Read state R, it transitions to the Read data state RD (seventh state). In the Read data state RD, the LINK 11 converts the received signal into an I2C protocol signal and transmits it to the Master 21. Thereafter, when the LINK 11 receives a signal including an ACK signal or a NACK signal from the Master 21 while in the Read data state RD, it transitions to the Read state R, converts the received signal into a communication protocol X signal and transmits it to the Slave SerDes 13.

[0122] Furthermore, when the LINK 11 is in the Read state R and does not receive read data from the Slave SerDes 13 within a predetermined period of time, it transitions to a data error state d_err (eighth state). When the LINK 11 is in the Read data state RD and does not receive an ACK signal or NACK signal from the Master 21 within a predetermined period of time, it transitions to the data error state d_err. By performing error processing in the data error state d_err, the LINK 11 avoids deadlock of the entire system including the communication device, the Master 21, and the Slave SerDes 13.

[0123] Meanwhile, the state transitions of the Master SerDes 7 in the Bulk I2C mode can be summarized as follows: From the time that LINK 11 in the Master SerDes 7 receives a signal including a Start Condition from the Master 21 until it receives a signal including a Stop Condition, it holds the received signal and transmits a signal including an ACK signal or a NACK signal for each byte of the received signal to the Master 21. LINK 11 converts the received signal into a signal of communication protocol X and transmits the converted signal to the Slave SerDes 13. LINK 11 receives and holds a signal including an ACK signal or a NACK signal from the Slave 22 from the Slave SerDes 13, and then, in response to a read request from the Master 21, converts the signal from the Slave SerDes 13 into a signal of the I2C protocol and transmits it to the Master 21.

[0124] Figure 18 is a timing diagram of a basic write model (hereinafter referred to as Write Operation 1) in which the Slave SerDes automatically generates the clock CLK in Byte I2C mode. In Write Operation 1, node 2 receives a signal from node 1, recognizes cmd_mode[6:5]=2'b00 in the received signal, and automatically generates the clock CLK. Using this clock CLK, node 2 can send write data to Slave 22 and receive an ACK signal from Slave 22.

[0125] As shown in Fig. 18, when the Master 21 transmits the Slave address to the Slave 22, the Slave 22 returns an ACK signal to the Master 21. Next, when the Master 21 transmits the offset address to the Slave 22, the Slave 22 returns an ACK signal to the Master 21. Next, when the Master 21 transmits the WDATA to the Slave 22, the Slave 22 returns an ACK signal to the Master 21. After that, the transmission of the WDATA and the return of the ACK signal are repeated in byte units until the STOP command is transmitted.

[0126] Figure 19 is a timing diagram of Write operation 2, which is a modification of Write operation 1 in Figure 18. In Write operation 1 in Figure 18, when node 1 is in START state St, the START command is sent to node 2, but in Write operation 2, when node 1 is in Slave address state Sl_Addr, the START command and data D are sent together to node 2. This makes it possible to reduce the number of transactions of communication protocol X compared to Write operation 1 in Figure 18.

[0127] Figure 20 is a timing diagram of basic write operation 3, which specifies the number of clock CLK cycles in Byte I2C mode. Unlike write operations 1 and 2, in write operation 3 of Figure 19, node 1 specifies the number of clock CLK cycles used by node 2 using cmd_mode. In this case, one cycle is specified. Node 2 interprets the signal cmd_mode[6:5]=2'b01 received from node 1 and generates one cycle of clock CLK for ACK at the appropriate timing for Slave 22. Node 2 uses this clock CLK to receive the ACK signal from Slave 22. Figure 20 is used, for example, when the processing performance of node 2 is low. Node 1 calculates the required number of clock CLK cycles on behalf of node 2.

[0128] Figure 21 is a timing diagram of Write operation 4, which is a modification of Write operation 3 in Figure 20. In Write operation 3 in Figure 20, the START command was sent to node 2 when node 1 was in START state St, but in Write operation 4, the START command and data D are sent together to node 2 when node 1 is in Slave address state Sl_Addr. This makes it possible to reduce the number of transactions of a specific protocol X compared to Write operation 3.

[0129] Figure 22 is a timing diagram of a basic read model (hereinafter referred to as Read Operation 1) in which the Slave SerDes automatically generates the clock CLK number in Byte I2C mode. In Read Operation 1, node2 receives a signal from node1, recognizes cmd_mode[6:5]=2'b00 in the received signal, and automatically generates the clock CLK. As a result, node2 uses the clock CLK it generates itself to receive an ACK signal from Slave 22 and receive RDATA and send it to node1.

[0130] As shown in FIG. 22, in Read operation 1, first, a Write command is sent to the Slave 22 with a Slave address and an offset address, and then the same Slave address and Read command as the previous time are sent.

[0131] FIG. 23 is a timing diagram of Read operation 2, which is a variation of Read operation 1 in FIG. 22. In Read operation 2, node 1 specifies information about the number of cycles of the clock CLK to be used by node 2 in cmd_mode. In cmd_mode indicated as C1 in FIG. 23, node 2 interprets the signal cmd_mode[6:5]=2'b01 received from node 1 and generates one cycle of the clock CLK for ACK at an appropriate timing for Slave 22. Node 2 uses this clock CLK to receive the ACK signal from Slave 22. In cmd_mode indicated as C9, node 2 interprets the signal cmd_mode[6:5]=2'b11 received from node 1 and generates nine cycles of the clock CLK for ACK and RDATA signals at an appropriate timing for Slave 22. Node 2 uses this clock CLK to receive the ACK and RDATA signals from Slave 22. Thus, in FIG. 23, because node 2 has low processing performance, node 1 calculates and notifies node 2 of the number of cycles of the clock CLK to be used.

[0132] Figure 24 is a timing diagram of Read Operation 3 when there is no Sub Address. Unlike Read Operations 1 and 2, Read Operation 3 shows an example in which there is no offset address after the Slave address. While the Write command in Figures 22 and 23 first transmits the Slave address, Read Operation 3 transmits the Slave address in the Read command from the beginning. When node 2 transmits the Slave address to Slave 22, node 2 receives the ACK signal and RDATA transmitted from Slave 22 and transmits them to node 1. Node 1 transmits the ACK signal and RDATA from node 2 to Master 21. In the cmd_mode indicated as C8 in Figure 24, node 2 recognizes the signal cmd_mode[6:5]=2'b10 received from node 1 and generates eight cycles of the clock CLK for the RDATA signal at the appropriate timing for Slave 22. This clock CLK is used by node 2 to receive the RDATA from Slave 22.

[0133] Figure 25 is a timing diagram of Err operation 1 in Byte I2C mode. Err operation 1 is performed when the ACK / NACK signal from Slave 22 does not arrive within the time limit. If the ACK / NACK signal does not arrive from Slave 22 to node2, node1 and node2 will time out, transition to ACK_err state a_err, perform error processing, and then return to the initial state init. When node1 transitions to ACK_err state a_err, it returns a NACK signal to Master 21 and transfers an err packet to node2. At this time, node1 may register in the err register that it is in ACK_err state a_err.

[0134] Figure 26 is a timing diagram of Err operation 2 in Byte I2C mode. Err operation 2 is performed when RDATA does not arrive from Slave 22, or when part of the RDATA is missing. If RDATA does not arrive from Slave 22 to node2 within the time limit, or when part of the RDATA is missing, node1 and node2 experience a timeout and transition to the data_err state d_err. When node1 transitions to the data_err state d_err, it returns dummy RDATA to Master 21 and transfers an err packet to node2. At this time, node1 may register the data_err state d_err in the err register.

[0135] Master 21 can determine that RDATA has arrived after the timeout, and can determine whether the RDATA after the timeout is dummy data or normal data by reading the err register of node 1 as necessary.

[0136] The above is the detailed operation of the Byte I2C mode. Next, we will explain the detailed operation of the Bulk I2C mode.

[0137] (Details of Bulk I2C mode operation)

[0138] The following describes the case where the Master 21 performs a random write to the Slave 22. When the Master 21 performs a random write to the Slave 22, it first sends a command set via I2C communication to the Master SerDes 7. The I2C communication protocol for random write is as shown in FIG. 7 above, and the Master 21 sends a command set to the Master SerDes 7 in accordance with this protocol.

[0139] 27 is a diagram showing signals transmitted and received between the Master 21 and the Master SerDes 7 when performing a Random Write from the Master 21 to the Slave 22 in Bulk I2C mode. In this specification, the I2C protocol signals from the Master 21 to the Master SerDes 7 are referred to as the M I2C protocol. As shown in FIG. 27, the M I2C protocol includes S (START condition), SerDes1 St_adr, W, mem1 Sub_adr, mem1 Sub_adr, I2C setting CLK, Cmd_mode, last target Slave adr, last target Sub adrH, last target Sub adrL, Data lengthH, Data lengthL, Data×2, and P (STOP condition). Details of this information will be described later.

[0140] Data in the I2C protocol transmitted from the Master 21 is stored in table 1 in mem1 of the Master SerDes 7. Figure 28 shows an example of data stored in table 1 in mem1 in Bulk I2C mode. Each piece of data is stored in the CLK_value, which is the setting value of the I2C setting clock CLK, at the address of mem1 indicated by Sub_Adr transmitted by the M I2C protocol. Thereafter, data transmitted by the M I2C protocol is stored in incrementing address addresses of mem1. As mentioned above, CLK_value is one byte of information indicating the SCL frequency, and the Slave 22 performs I2C communication with the Slave SerDes 13 at the operating frequency specified by CLK_value.

[0141] Cmd_mode in Sub_Adr[1] is one byte of information that indicates the content of the command that the Master SerDes 7 received from the Master 21 .

[0142] The Slave Adr of Sub_Adr[2] in table 1 of FIG. 28 is one-byte information indicating the address of the Slave 22 to be written to or read from (for example, 0x02 for the image sensor 12).

[0143] Sub_adrH of Sub_Adr[3] is the upper byte information of the address that indicates which Sub_adr in mem 19 (mem 3) in the image sensor 12 is to be accessed, or which Sub_adr in mem 20 in the temperature sensor 14 is to be accessed.

[0144] Sub_adrL of Sub_Adr[4] is the lowest byte of address information that indicates which Sub_adr in mem 19 (mem 3) in the image sensor 12 is to be accessed, or which Sub_adr in mem 20 in the temperature sensor 14 is to be accessed.

[0145] LengthH of Sub_Adr[5] is the upper byte of the data length of WDATA (Data[N-2:7]). LengthL of Sub_Adr[6] is the lower byte of the data length of WDATA (Data[N-2:7]).

[0146] WDATA of Sub_Adr[N-2:7] is data to be written to the Slave 22. One byte of data is stored for each bit of Sub_Adr.

[0147] The End of Data of Sub_Adr[N-1] is written with 0x9F when P (STOP condition) is received from Master 21. By default, an initial value such as 0x00 is written.

[0148] 29 is a continuation of FIG. 27 and shows the process of transmitting a Random Write Command from the Master SerDes 7 to the Slave SerDes 13 in Bulk I2C mode using communication standard X. The I2C protocol and mem1 (Save I2C command Packet) (steps S1 and S2) in FIG. 29 are the same as those described in FIG. 27.

[0149] The Master SerDes 7 reads the data in table 1 in FIG. 28, converts the data into a signal conforming to the communication standard X protocol, and transmits the signal to the Slave SerDes 13 via a Packetized I2C on PHY (depending on the respective PHY specifications) forward channel (step S3).

[0150] When Cmd_mode=0x00, Cmd_mode[7]=0 and "end determination for each End of Data" is performed. Therefore, when LINK 11 of Master SerDes 7 receives "End of Data (0x9F)", it writes "End of Data (0x9F)" to table 1 in Fig. 28 and also reads table 1 in Fig. 28 and transmits it to Slave SerDes 13 via Rv.Tx 10.

[0151] In the case of Cmd_mode=0x80, when End of data and cmd_done are written, the data in mem1 (table1 in FIG. 28) is collectively converted into an I2C command and sent to the Slave SerDes 13 via Rv.Tx10.

[0152] The Slave SerDes 13 extracts the I2C command packet from the received communication standard X protocol signal and writes it to table 3 in mem2. In FIG. 29, this is called mem2 (Save I2C command Packet) (step S4). FIG. 30 is a diagram showing an example of table 3 in mem2 during a Random Write operation in Bulk I2C mode. The same information as in table 1 in FIG. 28 is written to table 3.

[0153] The Slave SerDes 13 converts the protocol of the data received on the reverse link and restores the data originally stored in mem1 within mem2. The Slave SerDes 13 determines the end of restoration of the I2C command packet by restoring the end of data.

[0154] 31 and 32 are continuations of Fig. 29 and show the process of transmitting data from the Slave SerDes 13 to the Slave 22 via I2C communication. mem2 (Save I2C command Packet) (step S4) in Figs. 31 and 32 is the same as that explained in Fig. 29. Fig. 31 shows the process of transmitting and receiving data between the Slave SerDes 13 and the Slave 22 via I2C communication in Bulk I2C mode.

[0155] After writing End of data to table 3 in mem2 shown in FIG. 30, the Slave SerDes 13 reads table 3, converts the format into an I2C protocol signal, and transmits it to the Slave 22 via the I2C 13a using the M I2C protocol (step S5).

[0156] (data) Cmd_mode(0x00) issues an S (START condition) and generates a W (Write) command or an R (Read) command according to the value of Cmd_mode[0] after the next Sl_adr is issued.

[0157] (data)Sl_adr(0x02) indicates that "0x02" is specified as the Sl_adr mentioned above. Since it is "0x02", image sensor 12 is selected. (data)Sub_adrH(0x00) indicates that "0x00" is specified as the upper bits of the address of mem3 (the final target to be accessed) within image sensor 12. (data)Sub_adrL(0x00) indicates that "0x00" is specified as the lower bits of the address of mem3 (the final target to be accessed) within image sensor 12. (data)WDATA×2 indicates 16 bytes of data.

[0158] The slave 22 sequentially returns an ACK signal indicating that the signal has been received normally to the slave SerDes 13 using the SI2C protocol (step S5).

[0159] While data is being transmitted and received from the Slave SerDes 13 to the Slave 22 via I2C communication, the same information as that shown in FIG. 30 is stored in table 3 in mem2.

[0160] When the Slave SerDes 13 has Cmd_mode[6]=0 and all signals returned from the Slave 22 are ACK signals, it writes ACK to Sub_Adr=N in table 3, and when there are one or more NACK signals, it writes NACK.

[0161] When the Slave SerDes 13 has Cmd_mode[6]=1, if all signals returned from the Slave 22 are ACK signals, it writes ACK to Sub_Adr=N in table 3, and if there is one or more NACK signals, it performs the write again. If there is also a NACK signal the second time, it writes NACK to Sub_Adr=N in table 3. Figure 33 shows the state of the memory area of ​​mem2 before the memory area is released for a Random Write Command in Bulk I2C mode, when I2C communication between the Slave SerDes 13 and the Slave 22 is completed and ACK or NACK is written to Sub_Adr=N.

[0162] As a method for generating the ACK or NACK to be written to Sub_Adr=N in table 3 in mem2, for example, the logical product of the ACK signal and NACK signal returned from Slave 22 may be calculated.

[0163] 32 is a continuation of FIG. 31 and shows the process of sending a reply to a Random Write Command from the Slave SerDes 13 to the Master SerDes 7 using communication protocol X in Bulk I2C mode. The S I2C protocol (step S5) in FIG. 32 is the same as that described in FIG. 31.

[0164] The Slave SerDes 13 converts the I2C communication result with the Slave 22 into a signal conforming to the communication standard X protocol and transmits it to the Master SerDes 7 via the Packetized I2C on PHY (depending on the respective PHY specifications) forward channel (step S6). After writing ACK or NACK to Sub_Adr=N in table 3 in mem2, the Slave SerDes 13 reads table 3 (Sub_Adr 0 to N) and transmits necessary information (in this embodiment, this means Data[7:0] when Sub_Adr is 2 or N, and also includes Cmd_ID when Cmd_mode is extended to 2 bytes) to the Master SerDes 7. When transmission is complete, the Slave SerDes 13 releases the storage area of ​​mem2 shown in FIG. 33.

[0165] Here, since mem1 and mem2 occupy the same memory area (Sub_Adr = 0 to N-1), Slave SerDes 13 knows the Sub_Adr of mem1 to write to next (the Sub_Adr that is free in mem2 and to which ACK / NACK has been written). Slave SerDes 13 also understands that when it writes to Slave 22, it must return two bytes (the Slave Adr that performed the I2C communication and the I2C communication result) to Master SerDes 7.

[0166] Figure 34 is a continuation of Figure 32 and shows the operation of the Master SerDes 7 in Bulk I2C mode. The Packetized I2C on PHY (depends on the respective PHY specifications) forward channel (step S6) in Figure 34 is the same as that explained in Figure 32. The Master SerDes 7 extracts the I2C command packet from the communication standard X protocol signal received from the Slave SerDes 13 and writes it to Sub_Adr N to N+9 of table1 in mem1.

[0167] Figure 35 shows table 1 in mem1 after receiving reply data from the Slave SerDes in response to a Random Write Command in Bulk I2C mode. Sub_Adr N to N+6 and N+9 in table 1 store the I2C command packets generated by the I2C Cmd Unit in Slave SerDes 13 in Figure 32. Sub_Adr N+7 and N+8 in table 1 in Figure 35 store the Slave Adr of sub_Adr(2) in mem2 and the ACK or NACK of sub_Adr(N) read and transferred.

[0168] 36 is a diagram showing the process when the Master 21 polls the Master SerDes 7 for a Random Write Command in Bulk I2C mode and reads out the execution result. The Master 21 polls the Master SerDes 7 for the result of the request command using the MI2C protocol (step S7). The Master 21 polls Sub_Adr=N+9 in table 1, and if it is 0x9F, reads Sub_Adr=N+8 and determines whether it is ACK or NACK.

[0169] For example, if the "write of 16 bytes to Slave 22" requested of Master SerDes 7 is completed, the End of Data (0x9F) and the resulting ACK (0x81) can be read. In this example, a 1-byte read is performed, the End of Data result is checked to determine whether polling is necessary, and another 1-byte read is performed to read an ACK or NACK, but it is also possible to read 2 bytes at a time and determine the polling result and the I2C communication result to Slave 22. If a NACK is returned, Master 21 can check whether the corresponding Slave 22 sent the NACK by reading the Slave adr of Sub_adr (N+7).

[0170] 35 is a diagram showing an example of data stored in mem1. Because Master 21 itself issues a write command to Master SerDes 7, it knows the access point of mem1 for Master SerDes 7. Similarly, because Master SerDes 7 itself stores data in mem1, it knows the access point of mem1. For example, when writing to Slave 22, if the response is 2B, the Header will be 7 Bytes + 2B Bytes + EoD (1 Byte) = 10 Bytes, and the next Sub_Adr will be N + 10 = 34.

[0171] FIG. 37 is a diagram showing transmission of a signal in Bulk I2C mode in which the Master 21 releases the storage area of ​​mem1 to the Master SerDes 7 as a random write operation termination process. FIG. 38 is a diagram showing data stored in mem1 before the storage area for the random write command is released. The Master 21 performs M I2C protocol processing, S I2C protocol processing, and mem1 (Save I2C command packet) processing, reads Sub_Adr=N+8 of table1, and if ACK is received, writes Clear to Sub_Adr=N+10 of table1 in mem1, as shown in FIG. 38 (step S8). When this Clear is written, the Master SerDes 7 releases the memory area of ​​table1 in mem1.

[0172] When 0xFF is written to Sub_adr (N+10) in mem1, the Master SerDes 7 releases the memory area of ​​mem1 that it has been using as the end process of the request command. Alternatively, the Master 21 may release the memory area of ​​mem1 in accordance with a write command that initializes the memory area used by the Master 21.

[0173] 39 to 41 are diagrams showing the operation of sending a batch of I2C commands. FIGS. 39 and 40 are diagrams showing bulk command transmission with Cmd_mode[7]=1 in Bulk I2C mode. FIG. 41 is a diagram showing details of data stored in table 1 in mem1 when sending a batch of commands with Cmd_mode[7]=1 in Bulk I2C mode. The operation of sending a batch of I2C commands is a write operation when Cmd_mode [2:0]=000 and Cmd_mode [7]=1. Specifically, this shows the case where Master 21 writes 8 bytes of data to the image sensor 12 (Sl_adr=0x02) and the temperature sensor 14 (Sl_adr=0x03) in a batch.

[0174] Block b1 in Figure 39 shows a write operation of 8 bytes of data to the image sensor 12 (Sl_adr=0x02), and Block b2 shows a write operation of 8 bytes of data to the temperature sensor 14 (Sl_adr=0x03). Block b3 shows the end of the batch operation with cmd_done and P (STOP condition).

[0175] More specifically, as shown in Figures 39 and 40, the operation of b1 begins with the Master 21 issuing a command to the Master SerDes 7 using the MI2C protocol to request I2C communication with the Slave 22 (step S11). When the Master SerDes 7 receives data from the Master 21, it returns an ACK at its own timing using the MI2C protocol (step S11). This request command indicates an I2C command batch operation with Cmd_mode [2:0] = 000 and Cmd_mode [7] = 1, so even if End of Data is saved in mem1, transfer to the Slave SerDes 13 does not begin. The operation of the following b2 is the same as b1, except that Slave_adr is the temperature sensor 14 (Sl_adr = 0x03). The final b3 indicates a special code with Cmd_code [2] = 1, and the following Data indicates the special code. In this example, by successively receiving a special cmd_done (0xFF) indicating the end of the command and a STOP condition (step S12), the Master SerDes 7 transmits the received data (Figure 41) stored in mem1 to the Slave SerDes 13 in a batch as an I2C command batch transmission.

[0176] In this embodiment, when the Master 21 sets Cmd_mode[7]=1, it must not set Cmd_mode[7]=0 until 0xFF is written to cmd_done.

[0177] 42 to 52 show the Random Read operation (the Read operation when Cmd_mode [3:0]=0001 and [7]=0). The Random Read operation differs significantly from the Random Write operation in the following ways.

[0178] In a read operation, as shown in FIGS. 42 to 45, first, the Master 21 writes a read request to the Master SerDes 7 (FIGS. 42 to 43), and the Master SerDes 7 writes this read request to the Slave SerDes 13 (FIGS. 44 to 45).

[0179] Then, as shown in the processing of the M I2C protocol in step S25 of Figures 46A and 47, "S", "SL_adr", "W", and "Sub_adr" are used to write that the processing target is mem3 of image sensor 12, and then "Sr", "SL_adr", and "R" are used to read from the processing target.

[0180] The processing procedure for Random Read will be explained below in order with reference to Figs. 42 to 52. Fig. 42 shows the procedure for transmitting an I2C command packet from the Master 21 to the Master SerDes 7 in Bulk I2C mode. First, as shown in step S21 of Fig. 42, the M I2C protocol processing is performed. Here, the Master 21 issues a command to the Master SerDes 7 requesting I2C communication with the Slave 22. The command set transmitted from the Master 21 includes SerDes1 St_adr, mem1 Sub_adr, mem1 Sub_adr, I2C setting CLK, Cmd_mode, last target Slave adr, last target Sub_adrH, last target Sub_adr, Data lengthH, Data lengthL, and P (STOP condition).

[0181] The Master SerDes 7 returns an ACK signal to the Master 21 using the SI2C protocol every time it receives an information unit from the Master 21 (step S21). The Master SerDes 7 also stores the received I2C command packet in mem1 (step S22). Figure 43 is a diagram showing data stored in table 1 in mem1 during a Random Read operation in Bulk I2C mode. As shown in Figure 43, mem1 stores (data) CLK_value, (data) Cmd_mode, (data) Sl_adr, (data) Sub_adrH, (data) Sub_adrL, (data) length, (data) lengthL, and End of data.

[0182] 44 is a diagram showing a process performed following FIG. 42, in which the Master SerDes 7 transmits a Random Read command in communication protocol X from the Master SerDes 7 to the Slave SerDes 13 in Bulk I2C mode. The Master SerDes 7 converts the protocol of the data in mem1 and transmits it to the Slave SerDes 13 using the Packetized I2C on PHY (depending on the respective PHY specifications) forward channel (step S23). More specifically, when End of data is stored in mem1 with Cmd_mode=0x00, the data in mem1 is collected, converted into an I2C command, and transmitted to the Slave SerDes 13 via the reserved link. On the other hand, when End of data is stored in mem1 with Cmd_mode=0x10 and cmd_done is written, the data in mem1 is collected, converted into an I2C command, and transmitted to the Slave SerDes 13 via the reserved link. The Slave SerDes 13 converts the protocol of the received data on the reserved link and stores the data originally stored in mem1 in mem2 (step S24). The Slave SerDes 13 determines that the restoration of the I2C command packet is complete when the End of Data is restored. Figure 45 shows an example of the data stored in mem2 during a Random Read operation in Bulk I2C mode.

[0183] FIG. 46A is a diagram showing the process following FIG. 44, in which the Slave SerDes 13 transmits a random read command to the Slave 22 in Bulk I2C mode. The Slave SerDes 13 transmits an I2C command packet to the Slave 22 using the M I2C protocol (step S25). The Slave 22 returns an ACK signal to the Slave SerDes 13 using the S I2C protocol for each received information unit, and transmits RDATA sequentially from the addresses specified by Sub_adrH and Sub_adrL to the Slave SerDes 13. FIG. 47 is a diagram showing the data stored in table 3 in mem2 after a Random Read operation in Bulk I2C mode. As shown in FIG. 47, the Slave SerDes 13 transmits an ACK signal to the Slave 22 for each byte indicating that it has received the RDATA, and stores the RDATA from the Slave 22 in mem2.

[0184] It can be seen that the Slave SerDes 13 and Slave 22 in FIG. 46A are communicating using a protocol that complies with the I2C communication protocol during the Random Read operation shown in FIG. 46B.

[0185] Figure 48, which follows Figure 46, shows processing in which the Slave SerDes 13 sends a reply to a Read command to the Master SerDes 7 using communication standard X in Bulk I2C mode. The Slave SerDes 13 transmits RDATA via the packetized I2C on PHY (depending on the respective PHY specification) forward channel (step S26). More specifically, the Slave SerDes 13 converts the I2C communication result with the Slave 22 (RDATA, ACK) + End of data and transmits it to the Master SerDes 7 via the forward link. Figure 47 shows the data stored in table 3 in mem2 after the Random Read operation.

[0186] Fig. 49 is a diagram following Fig. 48, showing the processing of the Master SerDes 7 when a reply to a Random Read Command is received from the Slave SerDes 13 in Bulk I2C mode. The Master SerDes 7 performs protocol conversion on the data received on the forward link and stores the received data, including the I2C communication result (ACK / NACK) with the Slave 22, in mem1. Fig. 50 is a diagram showing an example of data in mem1 after receiving reply data from the Slave SerDes 13 in response to a Random Read Command in Bulk I2C mode.

[0187] 51 is a diagram showing the process in which the Master 21 polls the Master SerDes 7 for a Random Read Command in Bulk I2C mode and reads out the execution result. The Master 21 polls the Master SerDes 7 for the request command result using the MI2C protocol (step S27). The Master 21 polls at its own timing without waiting for an ACK from the Slave 22, and the Master SerDes 7 returns an ACK or RDATA, which is the polling result, to the Master 21 (step S27).

[0188] When the result of the "16-byte read to Slave 22" requested by Master 21 to Master SerDes 7 has finished, it can read End of data (0x9F) and the resulting ACK (0x81). If the End of data read result is anything other than 0x9F, it continues polling. In this example, it checks the End of data result with a 1-byte read to determine whether polling is necessary, and then reads RDATA (16 bytes) + ACK / NACK again with a 17-byte read. However, it is also possible to read 18 bytes at once and determine the polling result and the I2C communication result to Slave 22. If the result is a NACK, Master 21 can confirm whether the NACK is from the corresponding Slave 22 by reading the Slave adr of Sub_Adr (15).

[0189] FIG. 52 is a diagram showing an example of data stored in table1 in mem1 before the storage area for the Random Read Command is released in Bulk I2C mode.

[0190] In Figure 46A, the process in which Slave SerDes 13 performs a random read on Slave 22 was explained. However, as shown in Figure 53A, a random read must be performed when accessing mem3 in Slave 22 for the first time, but a current read can be used from the second time onwards.

[0191] When End of data or End of data and cmd_done are written to mem2, the Slave SerDes 13 converts the data written to mem2 into I2C protocol and performs I2C communication with the Slave 22. When performing a current read (when Cmd_mode[3:0]=1001), Sub_adrH and Sub_adrL in mem2 shown in Figure 54 are not used. As a result, the I2C command protocol sent from the Slave SerDes 13 to the Slave 22 is reduced by 2 bytes.

[0192] It can be seen that the Slave SerDes 13 and Slave 22 in FIG. 53A communicate with each other using a protocol that conforms to the I2C communication protocol shown in FIG. 53B.

[0193] (Error command format) As shown in Figure 11B above, if an error command format is provided in the command format, data will be transmitted in the error command format if an error occurs when Bulk I2C mode is selected. Figure 55 is a timing diagram of a read operation in normal Bulk I2C mode, and Figure 56 is a timing diagram of what happens when an error occurs during a read in Bulk I2C mode (hereinafter referred to as Read Error Case 1).

[0194] As shown in Figure 55, under normal conditions, node 2 transmits the slave address and offset address to Slave 22, then receives RDATA from Slave 22 and transmits it to node 1. Figure 56 shows an example in which node 2 transmits the offset address to Slave 22, but does not receive an ACK / NACK signal from Slave 22 within the limited time period. In this case, when the time expires, node 2 forcibly terminates communication with Slave 22, transmits an error command format to node 1, and performs initialization processing. By reading the error command format received by node 1, Master 21 determines that an error has occurred during the I2C communication.

[0195] Figure 57 shows the data stored in table 3 in mem2 when Slave SerDes 13, which is node 2 in Bulk I2C mode, transmits an error command format. Compared to table 3 in Figure 45, the value of the Read command format in SubAdr[0:7] is the same. SubAdr[8:N-1] in table 3 in Figure 45 is the Read response format, while SubAdr[8:N-1] in Figure 57 is the error command format. RDATA is written to SubAdr[10:N-2] in Figure 45, while SubAdr[10:N-2] in Figure 57 is a don't care. Furthermore, End of Data in the error command format is written to SubAdr[N-1] in Figure 57.

[0196] Figure 58 shows the data stored in table 1 in mem1 when Master SerDes 7, which is node 1 in Bulk I2C mode, sends an error command format. Compared to table 1 in Figure 50, the value of the Read command format in SubAdr[0:7] is the same. SubAdr[8:N-1] in table 1 in Figure 50 is the Read response format, while SubAdr[8:N-1] in Figure 58 is the error command format. RDATA is written to SubAdr[N-3:N-2] in Figure 45, while SubAdr[N-3:N-2] in Figure 58 is a don't care. Because the End of Data in the error command format is written to SubAdr[N-] in Figure 58, Master 21 can perform the same polling process in both normal and error situations.

[0197] Figure 59 is a timing diagram of what happens when an error occurs during a read in Bulk I2C mode (hereinafter referred to as Read Error Case 2). Figure 59 shows the case where a Read command format cannot be sent from node 1 to node 2. Because node 1 is unable to send the Read command format to node 2 within the time limit, it sends an error command format to node 2 to notify that an error has occurred. Master 21 determines that an error has occurred during I2C communication by reading the error command format from node 1. When node 2 receives the error command format, it performs initialization processing as necessary.

[0198] FIG. 60 is a diagram showing data stored in table 1 in mem1 of node 1 (Master SerDes 7) in read error case 2. The read command format of SubAdr[0:7] is the same as the read command format of SubAdr[0:7] of table 1 in FIG. 50. SubAdr[8:N-1] in FIG. 50 is a read response format, while SubAdr[8:N-1] in FIG. 60 is an error command format. SubAdr[10:N-2] in the error command format is a don't care, and the End of Data of the error command format is written to SubAdr[N-1]. This allows Master 21 to perform similar polling processing in both normal and error situations.

[0199] FIG. 61 is a diagram showing data stored in table 1 in mem1 of node 1 in the case of a write error. The write command format of SubAdr[0:N-1] is the same as the write command format of SubAdr[0:N-1] in table 1 of FIG. 35. SubAdr[N:N+9] in FIG. 35 is an ACK / NACK format, while SubAdr[N:N+9] in FIG. 61 is an error command format. SubAdr[N+2:N+8] in the error command format are don't care, and the End of Data of the error command format is written to SubAdr[N+9]. This allows Master 21 to perform similar polling processing in both normal and error situations.

[0200] FIG. 62 is an equivalent block diagram of a communication system 3 according to this embodiment. In the communication system 3 of FIG. 62, when data communication is performed between a first external device corresponding to Master 21 and a second external device corresponding to Slave 22, a Master SerDes 7 and a Slave SerDes 13 are provided between Master 21 and Slave 22 to relay data communication between Master 21 and Slave 22. The Master SerDes 7 has a first LINK (LINK 11). The Slave SerDes 13 has a second LINK (LINK 17). The first LINK generates a first output signal based on a first external signal from Master 21 and outputs it to Slave SerDes 13, and also generates a third output signal based on a second output signal from Slave SerDes 13 and outputs it to Master 21. The second LINK generates a second output signal based on a second external signal from Slave 22 and outputs it to Master SerDes 7, and generates a fourth output signal based on the first output signal from Master SerDes 7 and outputs it to the Slave.

[0201] The first LINK is capable of alternatively selecting between a first mode in which an ACK signal representing a positive acknowledgment or a NACK signal representing a negative acknowledgment is received every time a predetermined number of bytes (e.g., 1 byte or 2 bytes) of information is transmitted, and a second mode in which an ACK signal or a NACK signal is received every time bulk information, which is a block of information consisting of multiple bytes, is transmitted. A communication system, wherein each of the first output signal and the second external signal includes command information representing the content of a command transmitted from the first external device.

[0202] By configuring the communication system 3 as shown in FIG. 62, high-speed data communication can be performed between the Master 21 and the Slave 22.

[0203] Between the Master SerDes 7 and the Slave SerDes 13, high-speed data communication can be performed, for example, by the TDD method or the FDD (Frequency Division Duplexing) method.

[0204] As described above, in this embodiment, the Master SerDes 7 and the Slave SerDes 13 are disposed between the Master 21 and the Slave 22, and various types of information can be serially transmitted at high speed between the Master SerDes 7 and the Slave SerDes 13 using the communication standard X. The communication standard X may be the FDD method or the TDD method. Between the Master SerDes 7 and the Slave SerDes 13, it is possible to select either the Byte I2C mode (first mode), in which an ACK / NACK signal is received every time one or two bytes of information is transmitted, or the Bulk I2C mode (second mode), in which an ACK / NAK signal is received every time bulk information, which is a group of multiple bytes of information, is transmitted. When the Byte I2C mode is selected, I2C communication using the TDD method can be performed in a format similar to I2C communication using the FDD method. Furthermore, when the Bulk I2C mode is selected, when the Master SerDes 7 receives a command sent by the Master 21 to the Slave 22, the Master SerDes 7 can return an ACK to the Master 21 at its own discretion without waiting for an ACK from the Slave 22. This allows the Master 21 to quickly receive the ACK and quickly perform processing after receiving the ACK. In other words, the Master 21 can shorten the period in which the clock is stretched until it receives an ACK, improving the processing efficiency of the Master 21.

[0205] The present technology can be configured as follows: (1) A LINK is provided which converts the protocol of a signal from a Master and outputs it to a Slave SerDes, and converts the protocol of a signal from the Slave SerDes and outputs it to the Master; the LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master to the Slave SerDes; In the first mode, the LINK converting a 1-byte signal transmitted from the Master into a signal conforming to a first communication standard in units of 1 byte, transmitting the converted signal to the Slave SerDes, receiving a signal conforming to the first communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal conforming to a second communication standard, and transmitting the signal to the Master; In the second mode, the LINK Each time the device receives one byte of the multiple-byte signal transmitted from the Master, it transmits a signal including the ACK signal or the NACK signal to the Master; After completing the conversion of the multiple-byte signal received from the Master, transmit the converted signals together to the Slave SerDes; Then, receiving and holding a signal of the first communication standard including the ACK signal or the NACK signal from the Slave SerDes; Then, in response to a read request from the Master, converting the signal conforming to the first communication standard into a signal conforming to the second communication standard and transmitting the converted signal to the Master; A communication device in which a signal transmitted to the Slave SerDes includes command information indicating the content transmitted from the Master, and a signal transmitted to the Master includes command information indicating the content transmitted from the Slave SerDes. (2) The communication device according to (1), wherein the number of bytes of the signal transmitted to the Slave SerDes in the first mode is 2 bytes or 3 bytes, excluding clock frequency information and error correction code. (3) In the first mode, the LINK When a signal including a Start Condition is received from the Master, the device transitions to a first state; When transitioning to the first state, converting the Start Condition into a signal conforming to the first communication standard and transmitting the signal to the Slave SerDes; Thereafter, when the device receives a signal including one byte of address information of the final destination device from the Master while in the first state, the device transitions to a second state and holds the clock from the Master at a low level; In the second state, converting a signal including the address information into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; Thereafter, when a signal including the ACK signal or the NACK signal is received from the Slave SerDes while in the second state, if a specific bit of the signal including the address information has a first bit value, it is recognized as a write and transitions to a third state; In the third state, the communication device according to (1) or (2) converts a signal including the ACK signal or the NACK signal received from the Slave SerDes into a signal of the second communication standard and transmits it to the Master, and then releases the low-level hold of the clock from the Master. (4) In the first mode, the LINK When in the third state, if a signal including one byte of write data is received from the Master, the state transitions to a fourth state; In the fourth state, converting the received signal into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; The communication device described in (3), wherein, when the communication device receives a signal including the ACK signal or the NACK signal from the Slave SerDes while in the fourth state, the communication device converts the received signal into a signal of the second communication standard and transmits it to the Master. (5) In the first mode, the LINK When in the second state or the fourth state, if a signal including the ACK signal or the NACK signal is not received from the Slave SerDes within a predetermined period of time, transition to a fifth state; The communication device according to (4), wherein error processing is performed in the fifth state. (6) In the first mode, the LINK When receiving a signal including a Start Condition or a ReStart Condition from the Master, the device transitions to a first state; When transitioning to the first state, the received signal including the Start Condition or ReStart Condition is converted into a signal conforming to the first communication standard and transmitted to the Slave SerDes. Thereafter, when the device receives a signal including one byte of address information of the final destination device from the Master while in the first state, the device transitions to a second state and holds the clock from the Master at a low level; In the second state, converting a signal including the address information into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; Thereafter, when a signal including the ACK signal or the NACK signal is received from the Slave SerDes while in the second state, if a specific bit of the signal including the address information has a second bit value, it is recognized as a read and transitions to a sixth state; In the sixth state, the communication device according to (1) or (2) converts a signal including the ACK signal or the NACK signal received from the Slave SerDes into a signal of the second communication standard and transmits it to the Master, and then releases the low-level hold of the clock from the Master. (7) In the first mode, the LINK When in the sixth state, if a signal including one byte of read data is received from the Slave SerDes, the state transitions to a seventh state; In the seventh state, the received signal is converted into a signal conforming to the second communication standard and transmitted to the Master; The communication device described in (6), wherein, when in the seventh state, if a signal including the ACK signal or the NACK signal is received from the Master, the device transitions to the sixth state, converts the received signal into a signal of the first communication standard, and transmits it to the Slave SerDes. (8) In the first mode, the LINK When the read data is not received from the Slave SerDes within a predetermined period of time while in the sixth state, the state transitions to an eighth state; When the ACK signal or the NACK signal is not received from the Master within a predetermined period while in the seventh state, the ACK signal or the NACK signal is transitioned to the eighth state; The communication device according to (7), wherein the communication device performs error processing in the eighth state to avoid deadlock of the entire system including the communication device, the Master, and the Slave SerDes. (9) In the second mode, the LINK holding a received signal from the Master from the time when the signal including a Start Condition is received until the signal including a Stop Condition is received, and transmitting a signal including the ACK signal or the NACK signal to the Master for each byte of the received signal; converting the received signal into a signal conforming to the first communication standard, and transmitting the converted signal to the Slave SerDes; A communication device described in any one of (1) to (8), which receives and stores a signal including the ACK signal or the NACK signal from the Slave SerDes, and then, in response to a read request from the Master, converts the signal from the Slave SerDes into a signal of the second communication standard and transmits it to the Master. (10) The command information is First information for selecting the first mode or the second mode; When the first mode is selected, second information for alternatively selecting whether the Slave SerDes or the communication device generates a clock signal for data transmission and reception at its own discretion, or whether the Slave SerDes or the communication device explicitly specifies the clock signal to be used; If the first mode is selected, third information indicating whether data for writing or reading is included; and If the first mode is selected, fourth information indicating whether the NACK signal is received; and If the first mode is selected, fifth information indicating whether the ACK signal has been received; sixth information indicating whether a Stop Condition instructing the stop of information transmission is included when the first mode is selected; A communication device described in any one of (1) to (9), which, when the first mode is selected, includes at least one of a Start Condition that instructs the start of information transmission, or seventh information that indicates whether or not it includes a Repeated Start Condition that instructs the resumption of information transmission. (11) In the communication device described in (10), in the first mode, the LINK transmits a signal including the seventh information to the Slave SerDes, and then transmits a signal including address information of a final destination device to the Slave SerDes. (12) The communication device according to (10), wherein in the first mode, the LINK transmits a signal to the Slave SerDes that combines the seventh information and address information of the final destination device. (13) A communication device described in any one of (1) to (12), wherein each of the signals to the Slave SerDes and the Master includes, in addition to the command information, at least one of an error correction code, data, clock frequency information, and information indicating the type of command being sent or received. (14) The signal to the Slave SerDes is final destination address information identifying the final destination device of the signal transmitted from the Master; subaddress information of the final destination device; The communication device according to any one of (1) to (13), further comprising at least one piece of data length information indicating the length of data transmitted from the Master. (15) When the second mode is selected, the command information includes command format information defined by the first communication standard; The communication device according to any one of (1) to (14), wherein the command format information includes an error command format. (16) A communication device described in any one of (1) to (15), wherein the command information includes data end determination condition information that specifies the conditions for determining the end of a signal transmitted from the Master when the second mode is selected. (17) A communication device described in any one of (1) to (16), wherein the signals to the Slave SerDes and the signals from the Slave SerDes include commands that have been protocol-converted from I2C (Inter-Integrated Circuit) communication commands to the first communication standard. (18) The communication device according to (17), wherein the protocol conversion by the LINK is a TDD (Time Division Duplex) protocol conversion. (19) A LINK is provided which converts the protocol of a signal from a Master SerDes and outputs the signal to a Slave, and converts the protocol of a signal from the Slave and outputs the signal to the Master SerDes, the LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master SerDes to the Slave; In the first mode, the LINK When receiving a signal of a first communication standard transmitted from the Master SerDes, converting the received signal into a signal of a second communication standard in units of signals, transmitting the converted signals to the Slave, receiving a signal of the second communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal of the first communication standard, and transmitting the converted signals to the Master SerDes, repeating the process; In the second mode, the LINK When receiving a multi-byte signal of the first communication standard transmitted from the Master SerDes, converting the received signal into a signal of the second communication standard and transmitting the converted signal to the Slave byte by byte; receiving and holding a signal of the second communication standard including the ACK signal or the NACK signal from the Slave every time the converted signal is transmitted byte by byte to the Slave; After completing the transmission of the signal from the Master SerDes to the Slave, transmitting a signal of the first communication standard corresponding to the held signal to the Master SerDes; A communication device, wherein the signal from the Master SerDes includes command information indicating the content transmitted from the Master SerDes, and the signal from the Slave includes command information indicating the content transmitted from the Slave. (20) a Master SerDes having a first LINK; a Slave SerDes having a second LINK; the first LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master to the Slave SerDes; In the first mode, the first LINK converting a 1-byte signal transmitted from the Master into a signal conforming to a first communication standard in units of 1 byte, transmitting the converted signal to the Slave SerDes, receiving a signal conforming to the first communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal conforming to a second communication standard, and transmitting the signal to the Master; In the second mode, the first LINK Each time the device receives one byte of the multiple-byte signal transmitted from the Master, it transmits a signal including the ACK signal or the NACK signal to the Master; After completing the conversion of the multiple-byte signal received from the Master, transmit the converted signals together to the Slave SerDes; Then, receiving and holding a signal of the first communication standard including the ACK signal or the NACK signal from the Slave SerDes; Then, in response to a read request from the Master, converting the signal conforming to the first communication standard into a signal conforming to the second communication standard and transmitting the converted signal to the Master; The signal transmitted to the Slave SerDes includes command information indicating the content transmitted from the Master, and the signal transmitted to the Master includes command information indicating the content transmitted from the Slave SerDes; the second LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master SerDes to the Slave; In the first mode, the second LINK, when receiving a signal of a first communication standard transmitted from the Master SerDes, converts the received signal into a signal of a second communication standard in units of the received signal, transmits the converted signal to the Slave, receives a signal of the second communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response transmitted from the Slave, converts the received signal into a signal of the first communication standard, and transmits the converted signal to the Master SerDes, repeating the process; In the second mode, the second LINK When receiving a multi-byte signal of the first communication standard transmitted from the Master SerDes, converting the received signal into a signal of the second communication standard and transmitting the converted signal to the Slave byte by byte; receiving and holding a signal of the second communication standard including the ACK signal or the NACK signal from the Slave every time the converted signal is transmitted byte by byte to the Slave; After completing the transmission of the signal from the Master SerDes to the Slave, transmitting a signal of the first communication standard corresponding to the held signal to the Master SerDes; A communication system, wherein the signal from the Master SerDes includes command information indicating the content transmitted from the Master SerDes, and the signal from the Slave includes command information indicating the content transmitted from the Slave.

[0206] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0207] 1 Communication equipment, 3 Communication system, 4 ECU, 4a I2C, 5 SoC, 5a I2C, 7 Master SerDes, 8 I2C Cmd Unit, 9 Fw. Rx, 10 Rv. Master, 22 Slaves

Claims

1. a LINK that converts the protocol of a signal from a Master and outputs it to a Slave SerDes, and also converts the protocol of a signal from the Slave SerDes and outputs it to the Master; the LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master to the Slave SerDes; In the first mode, the LINK converting a 1-byte signal transmitted from the Master into a signal conforming to a first communication standard in units of 1 byte, transmitting the converted signal to the Slave SerDes, receiving a signal conforming to the first communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal conforming to a second communication standard, and transmitting the signal to the Master; In the second mode, the LINK Each time the device receives one byte of the multiple-byte signal transmitted from the Master, it transmits a signal including the ACK signal or the NACK signal to the Master; After completing the protocol conversion of the multiple-byte signals received from the Master, the protocol-converted signals are sent together to the Slave SerDes; Then, receiving and holding a signal of the first communication standard including the ACK signal or the NACK signal from the Slave SerDes; Thereafter, in response to a read request from the Master, converting the signal conforming to the first communication standard into a signal conforming to the second communication standard and transmitting the converted signal to the Master; A communication device in which a signal transmitted to the Slave SerDes includes command information indicating the content transmitted from the Master, and a signal transmitted to the Master includes command information indicating the content transmitted from the Slave SerDes.

2. The communication device according to claim 1 , wherein the number of bytes of the signal transmitted to the Slave SerDes in the first mode is 2 bytes or 3 bytes excluding clock frequency information and an error correction code.

3. In the first mode, the LINK When a signal including a Start Condition is received from the Master, the device transitions to a first state, When transitioning to the first state, converting the Start Condition into a signal conforming to the first communication standard and transmitting the signal to the Slave SerDes; Thereafter, when the device receives a signal including one byte of address information of the final destination device from the Master while in the first state, the device transitions to a second state and holds the clock from the Master at a low level; In the second state, converting a signal including the address information into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; Thereafter, when a signal including the ACK signal or the NACK signal is received from the Slave SerDes while in the second state, if a specific bit of the signal including the address information has a first bit value, it is recognized as a write and transitions to a third state; 2. The communication device according to claim 1, wherein in the third state, a signal including the ACK signal or the NACK signal received from the Slave SerDes is converted into a signal of the second communication standard and transmitted to the Master, and then the low level hold of the clock from the Master is released.

4. In the first mode, the LINK When the device is in the third state and receives a signal including one byte of write data from the Master, the device transitions to a fourth state. In the fourth state, converting the received signal into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; 4. The communication device according to claim 3, wherein when a signal including the ACK signal or the NACK signal is received from the Slave SerDes while in the fourth state, the communication device converts the received signal into a signal conforming to the second communication standard and transmits it to the Master.

5. In the first mode, the LINK When in the second state or the fourth state, if a signal including the ACK signal or the NACK signal is not received from the Slave SerDes within a predetermined period of time, transition to a fifth state; The communication device according to claim 4 , wherein error processing is performed in the fifth state.

6. In the first mode, the LINK When a signal including a Start Condition or a ReStart Condition is received from the Master, the device transitions to a first state; When transitioning to the first state, the received signal including the Start Condition or ReStart Condition is converted into a signal conforming to the first communication standard and transmitted to the Slave SerDes. Thereafter, when the device receives a signal including one byte of address information of the final destination device from the Master while in the first state, the device transitions to the second state and holds the clock from the Master at a low level; In the second state, converting a signal including the address information into a signal conforming to the first communication standard and transmitting the converted signal to the Slave SerDes; Thereafter, when a signal including the ACK signal or the NACK signal is received from the Slave SerDes while in the second state, if a specific bit of the signal including the address information has a second bit value, it is recognized as a read and transitions to a sixth state; 4. The communication device according to claim 3, wherein in the sixth state, a signal including the ACK signal or the NACK signal received from the Slave SerDes is converted into a signal of the second communication standard and transmitted to the Master, and then the low level hold of the clock from the Master is released.

7. In the first mode, the LINK When in the sixth state, if a signal including one byte of read data is received from the Slave SerDes, the state transitions to a seventh state; In the seventh state, the received signal is converted into a signal conforming to the second communication standard and transmitted to the Master; 7. The communication device according to claim 6, wherein when a signal including the ACK signal or the NACK signal is received from the Master while in the seventh state, the communication device transitions to the sixth state, converts the received signal into a signal of the first communication standard, and transmits the converted signal to the Slave SerDes.

8. In the first mode, the LINK When the read data is not received from the Slave SerDes within a predetermined period of time while in the sixth state, the state transitions to an eighth state; When the ACK signal or the NACK signal is not received from the Master within a predetermined period while in the seventh state, the ACK signal or the NACK signal is transitioned to the eighth state; The communication device according to claim 7 , wherein the communication device performs error processing in the eighth state to avoid deadlock of the entire system including the communication device, the Master, and the Slave SerDes.

9. In the second mode, the LINK holding a received signal from the Master from the time when the signal including a Start Condition is received until the signal including a Stop Condition is received, and transmitting a signal including the ACK signal or the NACK signal to the Master for each byte of the received signal; converting the received signal into a signal conforming to the first communication standard, and transmitting the converted signal to the Slave SerDes; 2. The communication device according to claim 1, wherein the communication device receives and stores a signal including the ACK signal or the NACK signal from the Slave SerDes, and then, in response to a read request from the Master, converts the signal from the Slave SerDes into a signal of the second communication standard and transmits it to the Master.

10. The command information is first information for selecting the first mode or the second mode; When the first mode is selected, second information for alternatively selecting whether the Slave SerDes or the communication device generates a clock signal for data transmission and reception at its own discretion, or whether the Slave SerDes or the communication device explicitly specifies the clock signal to be used; If the first mode is selected, third information indicating whether data for writing or reading is included; and If the first mode is selected, fourth information indicating whether the NACK signal is received; and If the first mode is selected, fifth information indicating whether the ACK signal has been received; sixth information indicating whether a Stop Condition instructing the stop of information transmission is included when the first mode is selected; and seventh information indicating whether or not the first mode includes at least one of a Start Condition instructing the start of information transmission or a Repeated Start Condition instructing the restart of information transmission when the first mode is selected.

11. 11. The communication device of claim 10, wherein in the first mode, the LINK transmits a signal including the seventh information to the Slave SerDes, and then transmits a signal including address information of a final destination device to the Slave SerDes.

12. The communication device according to claim 10 , wherein, in the first mode, the LINK transmits a signal that combines the seventh information and address information of a final destination device to the Slave SerDes.

13. 2. The communication device according to claim 1, wherein each of the signals to the Slave SerDes and the Master includes, in addition to the command information, at least one of an error correction code, data, clock frequency information, and information indicating the type of command being transmitted or received.

14. The signal to the Slave SerDes is final destination address information identifying the final destination device of the signal transmitted from the Master; subaddress information of the final destination device; The communication device according to claim 1 , further comprising at least one piece of data length information indicating the length of data transmitted from said Master.

15. the command information includes command format information defined by the first communication standard when the second mode is selected; The communication device of claim 1 , wherein the command format information includes an error command format.

16. 2. The communication device according to claim 1, wherein the command information includes data end determination condition information that specifies a condition for determining the end of a signal transmitted from the master when the second mode is selected.

17. 2. The communication device according to claim 1, wherein the signal to the slave SerDes and the signal from the slave SerDes include a command obtained by protocol-converting an I2C (Inter-Integrated Circuit) communication command into the first communication standard.

18. The communication device according to claim 17, wherein the protocol conversion by the LINK is a TDD (Time Division Duplex) protocol conversion.

19. a LINK that performs protocol conversion of a signal from a Master SerDes and outputs the signal to a Slave, and also performs protocol conversion of a signal from the Slave and outputs the signal to the Master SerDes; the LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master SerDes to the Slave; In the first mode, the LINK When receiving a signal of a first communication standard transmitted from the Master SerDes, converting the received signal into a signal of a second communication standard in units of one signal, transmitting the converted signal to the Slave, receiving a signal of the second communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal of the first communication standard, and transmitting the converted signal to the Master SerDes, repeating the process; In the second mode, the LINK When receiving a multi-byte signal of the first communication standard transmitted from the Master SerDes, converting the received signal into a signal of the second communication standard and transmitting the converted signal to the Slave byte by byte; receiving and holding a signal of the second communication standard including the ACK signal or the NACK signal from the Slave every time the converted signal is transmitted byte by byte to the Slave; After completing the transmission of the signal from the Master SerDes to the Slave, transmitting a signal of the first communication standard corresponding to the held signal to the Master SerDes; A communication device, wherein the signal from the Master SerDes includes command information indicating the content transmitted from the Master SerDes, and the signal from the Slave includes command information indicating the content transmitted from the Slave.

20. a Master SerDes with a first LINK; a Slave SerDes having a second LINK; the first LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master to the Slave SerDes; In the first mode, the first LINK converting a 1-byte signal transmitted from the Master into a signal conforming to a first communication standard in units of 1 byte, transmitting the converted signal to the Slave SerDes, receiving a signal conforming to the first communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converting the received signal into a signal conforming to a second communication standard, and transmitting the signal to the Master; In the second mode, the first LINK Each time the device receives one byte of the multiple-byte signal transmitted from the Master, it transmits a signal including the ACK signal or the NACK signal to the Master; After completing the protocol conversion of the multiple-byte signals received from the Master, the protocol-converted signals are sent together to the Slave SerDes; Then, receiving and holding a signal of the first communication standard including the ACK signal or the NACK signal from the Slave SerDes; Thereafter, in response to a read request from the Master, converting the signal conforming to the first communication standard into a signal conforming to the second communication standard and transmitting the converted signal to the Master; The signal transmitted to the Slave SerDes includes command information indicating the content transmitted from the Master, and the signal transmitted to the Master includes command information indicating the content transmitted from the Slave SerDes; the second LINK is capable of alternatively selecting a first mode or a second mode when transmitting a signal from the Master SerDes to the Slave; In the first mode, the second LINK, when receiving a signal of a first communication standard transmitted from the Master SerDes, converts the received signal into a signal of a second communication standard in units of the received signal, transmits the converted signal to the Slave, receives a signal of the second communication standard including an ACK signal representing a positive response or a NACK signal representing a negative response, converts the received signal into a signal of the first communication standard, and transmits the converted signal to the Master SerDes, repeating the process; In the second mode, the second LINK When receiving a multi-byte signal of the first communication standard transmitted from the Master SerDes, converting the received signal into a signal of the second communication standard and transmitting the converted signal to the Slave byte by byte; receiving and holding a signal of the second communication standard including the ACK signal or the NACK signal from the Slave every time the converted signal is transmitted byte by byte to the Slave; After completing the transmission of the signal from the Master SerDes to the Slave, transmitting a signal of the first communication standard corresponding to the held signal to the Master SerDes; A communication system, wherein the signal from the Master SerDes includes command information indicating the content transmitted from the Master SerDes, and the signal from the Slave includes command information indicating the content transmitted from the Slave.

Images