Plasma processing equipment

Abstract

To improve process performance using three power pulse signals.SOLUTION: A plasma processing apparatus has: a source RF generating part for generating source RF pulse signals of at least three power levels; first and second bias RF generating parts for generating first and second bias RF pulse signals of at least two power levels having frequencies lower than frequencies of the source RF pulse signals; a synchronization signal generating part for generating a synchronization signal for making the source RF generating part and the first and second bias RF generating parts synchronized with each other; a first matching circuit which is connected to the source RF generating part and the antenna and can supply the source RF pulse signals to the antenna through the first matching circuit from the source RF generating part; and a second matching circuit which is connected to the first and second bias RF generating part and a substrate support part, and can supply the first and second bias RF pulse signals to the substrate support part through the second matching circuit from the first and second bias RF generating parts.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a plasma processing device. Place Regarding. [Background technology]

[0002] For example, Patent Document 1 proposes an ICP (Inductively Coupled Plasma) apparatus that has two high-frequency power supplies and supplies dual-frequency power to an antenna in the upper part of the chamber and a lower electrode (susceptor). One of the two high-frequency power supplies supplies bias high-frequency power of, for example, 13 MHz to the lower electrode. An antenna is provided above the chamber, and the other high-frequency power supply supplies plasma excitation high-frequency power of, for example, 27 MHz to the midpoint or near the center of the line that constitutes the outer coil of the antenna. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-67503 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides techniques that can improve process performance using three radio frequency (RF) power pulses. [Means for solving the problem]

[0005] According to one aspect of the present disclosure, there is provided a semiconductor device including a chamber, a substrate support provided within the chamber, an antenna provided on an upper portion of the chamber, a source RF generator configured to generate a source RF pulse signal, the source RF pulse signal having at least three power levels, each power level being equal to or greater than zero, a first bias RF generator configured to generate a first bias RF pulse signal, the first bias RF pulse signal having a frequency lower than a frequency of the source RF pulse signal, the first bias RF pulse signal having at least two power levels, each power level being equal to or greater than zero, and a second bias RF generator configured to generate a second bias RF pulse signal, the second bias RF pulse signal having at least two power levels, each power level being equal to or greater than zero. a synchronization signal generator configured to generate a synchronization signal for synchronizing the source RF generation unit, the first bias RF generation unit, and the second bias RF generation unit with each other; a first matching circuit connected to the source RF generation unit and the antenna, the first matching circuit enabling the source RF pulse signal to be supplied from the source RF generation unit to the antenna via the first matching circuit; and a second matching circuit connected to the first bias RF generation unit, the second bias RF generation unit, and the substrate support, the second matching circuit enabling the first bias RF pulse signal to be supplied from the first bias RF generation unit to the substrate support via the second matching circuit and enabling the second bias RF pulse signal to be supplied from the second bias RF generation unit to the substrate support via the second matching circuit. [Effects of the Invention]

[0006] In one aspect, three high frequency power pulse signals can be used to improve process performance. [Brief explanation of the drawings]

[0007] [Figure 1]1 is a schematic cross-sectional view showing an example of a plasma processing system according to an embodiment; [Figure 2] FIG. 1 is a diagram showing an example of a plasma processing apparatus according to an embodiment. [Figure 3] FIG. 2 is a diagram showing an example of a matching circuit for two bias RF pulse signals according to the embodiment. [Figure 4] FIG. 10 is a diagram showing an example of radicals, ions, electron temperatures, ion energies, and by-products. [Figure 5] FIG. 3 is a diagram showing pulse patterns of dual-frequency high-frequency power pulses according to the embodiment. [Figure 6] FIG. 3 is a diagram showing pulse patterns of high-frequency power pulses of three frequencies according to the embodiment. [Figure 7] FIG. 3 is a diagram showing pulse patterns of high-frequency power pulses of three frequencies according to the embodiment. [Figure 8] FIG. 3 is a diagram showing pulse patterns of high-frequency power pulses of three frequencies according to the embodiment. [Figure 9] FIG. 10 is a diagram showing an example of a plasma processing apparatus according to a modified example of the embodiment. [Figure 10] FIG. 10 is a diagram showing pulse patterns of a DC pulse and a high-frequency power pulse according to Modification 1. [Figure 11] FIG. 10 is a diagram showing pulse patterns of a DC pulse and a high-frequency power pulse according to Modification 2. [Figure 12] FIG. 10 is a diagram showing pulse patterns of a DC pulse and a high-frequency power pulse according to Modification 3. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0009] [Plasma processing system] First, a plasma processing system according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view showing an example of a plasma processing system according to an embodiment. Figure 2 is a view showing an example of a plasma processing apparatus 1 according to an embodiment.

[0010] In the embodiment, the plasma processing system includes a plasma processing apparatus 1 and a controller 2. The plasma processing apparatus 1 is configured to generate plasma from a processing gas in the chamber 10 by supplying three high-frequency power pulses (three RF pulse signals) into the chamber 10. The plasma processing apparatus 1 then processes a substrate by exposing the substrate to the generated plasma.

[0011] The plasma processing apparatus 1 includes a chamber (plasma processing chamber) 10, a substrate support 11, and a plasma generation unit. The chamber 10 defines a plasma processing space 10s. The chamber 10 also has a gas inlet 10a for supplying at least one processing gas to the plasma processing space 10s and a gas outlet 10b for exhausting gas from the plasma processing space. The gas inlet 10a is connected to at least one gas supply unit 20.

[0012] The gas outlet 10b is, for example, an exhaust port provided at the bottom of the chamber 10 and is connected to an exhaust system 40. The exhaust system 40 may be connected to the gas outlet. The exhaust system 40 may include a pressure valve and a vacuum pump. The vacuum pump may include a turbomolecular pump, a roughing pump, or a combination thereof.

[0013] The substrate support 11 is disposed in the plasma processing space 10s and supports the substrate W. The plasma generation unit is configured to generate plasma from at least one processing gas supplied into the plasma processing space 10s.

[0014] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In an embodiment, as shown in FIG. 1 , part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include, for example, a computer 21. The computer 21 may include, for example, a processing unit (CPU: Central Processing Unit) 21a, a storage unit 21b, and a communication interface 21c. The processing unit 21a may be configured to perform various control operations based on programs stored in the storage unit 21b. The storage unit 21b may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 21c may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0015] 2 as an example, a configuration example of the plasma processing apparatus 1 will be further described below. The plasma processing apparatus 1 includes a chamber 10. The chamber 10 includes a dielectric window 10c and a sidewall 10d. The dielectric window 10c and the sidewall 10d define a plasma processing space 10s within the chamber 10. The plasma processing apparatus 1 also includes a substrate support 11, a gas inlet 13, a gas supply unit 20, a power supply unit, and an antenna 14.

[0016] The substrate support 11 is disposed in a plasma processing space 10s within the chamber 10. The antenna 14 is disposed at or above the upper portion of the chamber 10 (dielectric window 10c).

[0017] The substrate support 11 includes a main body and an annular member (edge ​​ring) 12. The main body has a central region (substrate support surface) 11a for supporting a substrate (wafer) W and an annular region (edge ​​ring support surface) 11b for supporting the annular member 12. The annular region 11b of the main body surrounds the central region 11a of the main body. The substrate W is disposed on the central region 11a of the main body, and the annular member 12 is disposed on the annular region 11b of the main body so as to surround the substrate W on the central region 11a of the main body. In the embodiment, the main body includes an electrostatic chuck 111 and a conductive member 112. The electrostatic chuck 111 is disposed on the conductive member 112. The conductive member 112 functions as an RF electrode, and the upper surface of the electrostatic chuck 111 functions as a substrate support surface (central region 11a). Although not shown, in the embodiment, the substrate support 11 may include a temperature control module configured to adjust at least one of the electrostatic chuck 111 and the substrate W to a target temperature. The temperature control module may include a heater, a flow path, or a combination thereof. A temperature control fluid such as a refrigerant or a heat transfer gas flows through the flow path. The chamber 10, the substrate support 11, and the annular member 12 are arranged so that the axis Z is aligned with each other as a central axis.

[0018] The gas inlet 13 is configured to supply at least one process gas from the gas supply 20 to the plasma processing space 10s. In an embodiment, the gas inlet 13 is disposed above the substrate support 11 and attached to a central opening formed in the dielectric window 10c.

[0019] The gas supply unit 20 may include at least one gas source 23 and at least one flow controller 22. In an embodiment, the gas supply unit 20 is configured to supply one or more process gases from respective gas sources 23 to the gas inlet 13 via respective flow controllers 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include one or more flow modulation devices to modulate or pulse the flow rate of one or more process gases.

[0020] The power supply unit includes an RF power supply unit 31 coupled to the chamber 10. The RF power supply unit 31 is configured to supply three RF signals (RF power) to the conductive member 112 of the substrate support 11 or the antenna 14. This generates plasma from at least one processing gas supplied to the plasma processing space 10s. The plasma generation unit may include a gas supply unit 20 that supplies at least one processing gas into the plasma processing space 10s and the RF power supply unit 31, and may be configured to generate plasma from the processing gas.

[0021] The antenna 14 includes one or more coils. In an embodiment, the antenna 14 may include an outer coil and an inner coil arranged coaxially. In this case, the RF power supply 31 may be connected to both the outer coil and the inner coil, or to either the outer coil or the inner coil. In the former case, the same RF generator may be connected to both the outer coil and the inner coil, or separate RF generators may be connected to the outer coil and the inner coil separately.

[0022] In the embodiment, the RF power supply unit 31 includes a source RF generation unit 31a, a first bias RF generation unit 31b, and a second bias RF generation unit 31c. The source RF generation unit 31a is coupled to the antenna 14, and the first bias RF generation unit 31b and the second bias RF generation unit 31c are coupled to the conductive member 112. The source RF generation unit 31a is connected to the antenna 14 via a first matching circuit 33 and is configured to generate a source RF pulse signal (hereinafter also referred to as HF power) for plasma generation. In the embodiment, the source RF pulse signal has a frequency in the range of 10 MHz to 100 MHz. In the embodiment, the source RF pulse signal has a frequency in the range of 20 MHz to 60 MHz. In the embodiment, the source RF pulse signal has a frequency of 100 MHz or more. The generated source RF pulse signal is supplied to the antenna 14. The source RF pulse signal has at least three power levels, each of which is equal to or greater than 0. Therefore, the source RF pulse signal may have high / middle / low power levels, which are greater than 0. The source RF pulse signal may also have high / low power levels and a zero power level (Off).

[0023] The first bias RF generation unit 31b is connected to the conductive member 112 of the substrate support unit 11 via the second matching circuit 34 and the power supply line 37, and is configured to generate a first bias RF pulse signal (hereinafter also referred to as LF1 power). The generated first bias RF pulse signal is supplied to the conductive member 112 of the substrate support unit 11. In an embodiment, the first bias RF pulse signal has a frequency different from that of the source RF pulse signal. In an embodiment, the first bias RF pulse signal has a frequency lower than that of the source RF pulse signal. In an embodiment, the first bias RF pulse signal has the same frequency as that of the source RF pulse signal. In an embodiment, the first bias RF pulse signal has a frequency in the range of 1 MHz to 40 MHz. In an embodiment, the first bias RF pulse signal has a frequency in the range of 1.2 MHz to 15 MHz. The first bias RF pulse signal has at least two power levels, each of which is equal to or greater than 0. Therefore, the first bias RF pulse signal may have high and low power levels, which are greater than 0. The first bias RF pulse signal may also have a power level greater than 0 and a zero power level, ie, an on / off signal.

[0024] The second bias RF generation unit 31c is connected to the conductive member 112 of the substrate support unit 11 via the second matching circuit 34 and the power supply line 37, and is configured to generate a second bias RF pulse signal (hereinafter also referred to as LF2 power). The generated second bias RF pulse signal is supplied to the conductive member 112 of the substrate support unit 11. In an embodiment, the second bias RF pulse signal has a lower frequency than the frequency of the first bias RF pulse signal. In an embodiment, the second bias RF pulse signal has a frequency within a range of 100 kHz to 5 MHz. In an embodiment, the second bias RF pulse signal has a frequency within a range of 200 kHz to 4 MHz. In an embodiment, the second bias RF pulse signal has a frequency within a range of 400 kHz to 2 MHz. The first bias RF pulse signal has at least two power levels, each of which is equal to or greater than 0. Therefore, the second bias RF pulse signal may have high and low power levels, which are greater than 0. The second bias RF pulse signal may also have a power level greater than 0 and a zero power level, ie an on / off signal.

[0025] In this manner, the source RF pulse signal, the first bias RF pulse signal, and the second bias RF pulse signal are pulsed. The first bias RF pulse signal and the second bias RF pulse signal are pulsed between an on state and an off state, or between two or more different on states (High / Low). The source RF pulse signal is pulsed between two or more different on states (High / Low) and an off state, or between three or more different on states (High / Middle / Low).

[0026] The first matching circuit 33 is connected to the source RF generating unit 31a and the antenna 14. The first matching circuit 33 enables a source RF pulse signal to be supplied from the source RF generating unit 31a to the antenna 14 via the first matching circuit 33.

[0027] The second matching circuit 34 is connected to the first bias RF generation unit 31b, the second bias RF generation unit 31c, and the substrate support unit 11 (the conductive member 112). The second matching circuit 34 enables the first bias RF pulse signal to be supplied from the first bias RF generation unit 31b to the substrate support unit 11 via the second matching circuit 34. The second matching circuit 34 also enables the second bias RF pulse signal to be supplied from the second bias RF generation unit 31c to the substrate support unit 11 via the second matching circuit 34.

[0028] The RF power supply unit 31 further includes a synchronization signal generator 31d. The synchronization signal generator 31d is configured to generate a synchronization signal 31s for synchronizing the source RF generator 31a, the first bias RF generator 31b, the second bias RF generator 31c, the first matching circuit 33, and the second matching circuit 34 with one another. The synchronization signal generator 31d is disposed in one of the source RF generator 31a, the first bias RF generator 31b, and the second bias RF generator 31c. The synchronization signal generator 31d is configured to supply the synchronization signal 31s to the remaining two RF generators, the first matching circuit 33, and the second matching circuit 34. In one embodiment, the synchronization signal generator 31d is disposed in the source RF generator 31a and configured to generate the synchronization signal 31s for the first bias RF generator 31b, the second bias RF generator 31c, the first matching circuit 33, and the second matching circuit 34. In addition, the synchronization signal generating unit 31d may be arranged separately, in which case the synchronization signal 31s is supplied to the source RF generating unit 31a, the first bias RF generating unit 31b, the second bias RF generating unit 31c, the first matching circuit 33, and the second matching circuit 34.

[0029] The control unit 2 outputs control signals to each of the source RF generation unit 31a, the first bias RF generation unit 31b, and the second bias RF generation unit 31c to instruct them to supply each pulse signal. As a result, the source RF pulse signal, the first bias RF pulse signal, and the second bias RF pulse signal are supplied at predetermined timing, and plasma is generated from the processing gas in the chamber 10. The substrate is then exposed to the generated plasma for substrate processing. This improves process efficiency and enables high-precision substrate processing. The control timing of the control unit 2 for controlling the on / off state or power levels of 0 or more of the source RF pulse signal, the first bias RF pulse signal, and the second bias RF pulse signal will be described later.

[0030] [An example of the internal configuration of the second matching circuit] Next, an example of the configuration of the second matching circuit 34 will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of the internal configuration of the second matching circuit 34 according to the embodiment.

[0031] The first bias RF generation unit 31b and the second bias RF generation unit 31c are connected to the substrate support unit 11 (conductive member 112) via a second matching circuit 34 and a power feed line 37. The first bias RF pulse signal supplied from the first bias RF generation unit 31b will also be referred to as LF1 power in the following description. Also, the second bias RF pulse signal supplied from the second bias RF generation unit 31c will also be referred to as LF2 power in the following description.

[0032] When the first bias RF pulse signal (LF1 power) supplied from the first bias RF generation unit 31b is coupled to the opposite side (the second bias RF generation unit 31c side) via the power feed line 36 in the second matching circuit 34, the supply efficiency of the LF1 power supplied to the chamber 10 decreases. Similarly, when the second bias RF pulse signal (LF2 power) supplied from the second bias RF generation unit 31c is coupled to the opposite side (the first bias RF generation unit 31b side) via the power feed line 36, the supply efficiency of the LF2 power supplied to the chamber 10 decreases. This reduces the supply of bias power to the chamber 10, making it difficult to control ion energy, and degrading process performance.

[0033] Therefore, the second matching circuit 34 according to this embodiment includes a first adjustment circuit 34b1, a first isolation circuit 34b2, a second adjustment circuit 34c1, and a second isolation circuit 34c2. The first adjustment circuit 34b1 and the first isolation circuit 34b2 are connected between the first bias RF generation unit 31b and the power feed line 37. The second adjustment circuit 34c1 and the second isolation circuit 34c2 are connected between the second bias RF generation unit 31c and the power feed line 37. With this configuration, the first bias RF pulse signal (LF1 power) generated in the first bias RF generation unit 31b is supplied to the substrate support unit 11 (conductive member 112) while suppressing coupling to the second bias RF generation unit 31c. Furthermore, the second bias RF pulse signal (LF2 power) generated in the second bias RF generation unit 31c is supplied to the substrate support unit 11 (conductive member 112) while suppressing coupling to the first bias RF generation unit 31b.

[0034] The first adjustment circuit 34b1 has a variable element and is configured to match the impedance on the load side (substrate support 11 side) of the first bias RF generation unit 31b to the output impedance of the first bias RF generation unit 31b. In one embodiment, the variable element of the first adjustment circuit 34b1 is a variable capacitor.

[0035] The second isolation circuit 34c2 is connected between the second bias RF generation unit 31c and the substrate support unit 11, and prevents coupling of the first bias RF pulse signal, which is the LF1 power from the first bias RF generation unit 31b.

[0036] The second adjustment circuit 34c1 has a variable element and is configured to match the impedance on the load side (substrate support 11 side) of the second bias RF generation unit 31c to the output impedance of the second bias RF generation unit 31c. In one embodiment, the variable element of the second adjustment circuit 34c1 is a variable inductor.

[0037] The first isolation circuit 34b2 is connected between the first bias RF generation unit 31b and the substrate support unit 11, and prevents coupling of the second bias RF pulse signal, which is the LF2 power from the second bias RF generation unit 31c.

[0038] The second isolation circuit 34c2 is an RF choke circuit including an inductor L2. The first isolation circuit 34b2 is a resonant circuit including a capacitor C1 and an inductor L1. The first isolation circuit 34b2 is composed of the capacitor C1 and the inductor L1. The second isolation circuit 34c2 is composed of the inductor L2.

[0039] The first separation circuit 34b2 sets the circuit constants C1 and L1 so that the impedance seen from the first bias RF pulse signal is 0 or close to 0, the impedance seen from the second bias RF pulse signal is high, and the first bias RF generation unit 31b side appears to be a wall. As a result, the impedance seen from the second bias RF pulse signal in the first separation circuit 34b2 is set to Z LF2 and the plasma load impedance is Z chamber When written as Z LF2 >>Z chamber holds true.

[0040] The second separation circuit 34c2 sets the circuit constant L2 so that the impedance seen from the second bias RF pulse signal is 0 or close to 0, and the impedance seen from the first bias RF pulse signal is high, and the second bias RF generation unit 31c side appears to be a wall. As a result, the impedance seen from the first bias RF pulse signal in the second separation circuit 34c2 is set to Z LF1 Then, Z LF1 >>Z chamber holds true.

[0041] In this way, by setting the circuit constant of the first separation circuit 34b2 as described above, the first separation circuit 34b2 has an impedance Z LF2 is the plasma load impedance Z chamber This makes the first isolation circuit 34b2 prevent coupling of the second bias RF pulse signal from the second bias RF generation unit 31c ("LF2 Power → ×" in FIG. 3). As a result, the LF2 power is supplied into the chamber 10 via the power supply line 37, thereby suppressing a decrease in the supply efficiency of the LF2 power.

[0042] Similarly, by setting the circuit constant of the second separation circuit 34c2 as described above, the second separation circuit 34c2 has an impedance Z LF1 is the plasma load impedance Z chamber This makes the second isolation circuit 34c2 prevent coupling of the first bias RF pulse signal from the first bias RF generation unit 31b ("LF1 Power → ×" in FIG. 3). As a result, the LF1 power is supplied into the chamber 10 via the power supply line 37, thereby suppressing a decrease in the supply efficiency of the LF1 power.

[0043] With this configuration, pulse signals of two bias powers (LF1 power and LF2 power) having different frequencies can be efficiently supplied to the substrate support part 11.

[0044] [Pulse signal] For example, in a process for etching deep holes with high aspect ratios, pulsed signals of HF power, LF1 power, and LF2 power can be used to make the ion incident angle perpendicular and increase the mask selectivity.

[0045] FIG. 4 is a diagram showing an example of radicals, ions, electron temperature, ion energy, and by-products. The horizontal axis of FIG. 4 indicates the elapsed time (one cycle) after the supply of RF power is stopped (turned off). The vertical axis of FIG. 4 indicates the radicals (Radical), ions (Ions), electron temperature (Te), and ion energy (ε l ), and by-products at each time.

[0046] According to this, radicals change slowly after RF power is turned off, whereas ions and plasma temperature (Te) change more quickly than radicals after RF power is turned off. The pulse signals of the HF power and LF power (e.g., LF1 power and LF2 power) are controlled taking into consideration the decay and energy changes of radicals and ions in the plasma. One example of a pulse signal of the LF power to be supplied after the HF power is turned off is to turn the LF power off during the initial period when the plasma temperature (Te) is high, and then turn the LF power on after the plasma temperature (Te) has dropped. This allows ions to be efficiently attracted to the substrate by using the LF power during the period when the plasma temperature (Te) is low, even though ions still remain.

[0047] Another example of the pulse signal of the LF power to be supplied after the HF power is turned off is ε l By using this, the LF2 power is controlled at a time when the plasma electron temperature Te is almost unchanged. l By controlling the angle of incidence of ions, it is possible to control the angle of incidence of ions more perpendicularly.

[0048] In this way, the timing of turning on and off the HF power and the LF power is precisely controlled according to the behavior of plasma parameters such as radicals, ions, plasma electron temperature, ion energy, and by-products. This improves the process performance. The supply timing of the high frequency power pulse signal will be explained below with reference to FIGS. 5 to 8. The supply timing of the high frequency power pulse signal is controlled by the control unit 2.

[0049] (2-frequency pulse signal) Fig. 5 is a diagram showing a pulse pattern of dual-frequency high-frequency power pulses according to an embodiment. First, the supply timing of the pulse signals of HF power (Source Power) and LF1 power (Bias Power), which are dual-frequency high-frequency powers shown in Fig. 5, will be described. The horizontal axis of Fig. 5 indicates the time of one cycle, and the vertical axis indicates the on / off state of the HF power and LF1 power. Periods (1) to (4) constitute one cycle, and control of the pulse signals of the HF power and LF1 power is repeated.

[0050] In the control of the dual-frequency radio frequency power pulse, the on state of the HF power and the on state of the LF1 power do not overlap in time, and the LF1 power is turned off while the HF power is turned on, and the LF1 power is turned on while the HF power is turned off. The source RF generator 31a is configured to generate a source RF pulse signal (HF power), and in this embodiment, the source RF pulse signal has two power levels (On / Off). For example, the source RF pulse signal may have a frequency of 27 MHz.

[0051] The first bias RF generating unit 31b is configured to generate a first bias RF pulse signal (LF1 power). In this embodiment, the first bias RF pulse signal has two power levels (On / Off). The frequency of the first bias RF pulse signal is lower than the frequency of the source RF pulse signal. For example, the first bias RF pulse signal has a frequency of 13 MHz.

[0052] 5, the HF power is turned on and the LF1 power is turned off. That is, during the time T s In this method, plasma containing radicals and ions is generated by supplying HF power.

[0053] Time T s When the HF power is controlled to be off at time t1 after the time has elapsed, the radicals, ions, and plasma temperature decay with their respective time constants, as shown in an example in Figure 4. Depending on the decay state of these plasma parameters, the timing of turning on the LF1 power is controlled during periods (2) and (3) when the HF power is controlled to be off. During period (2), the behavior of ions is mainly controlled by controlling the supply timing of the LF1 power. During period (3), the exhaust of by-products is controlled.

[0054] For example, if the LF1 power is turned on when the plasma temperature is high, a large amount of by-products are generated, which may hinder etching. Therefore, it may be preferable to turn on the LF1 power when the plasma temperature is not high. In other words, the LF1 power is turned on after a predetermined delay time T from the time t1 when the HF power is turned off. delay By controlling the LF1 power to be in the ON state at time t2, which is shifted by only 1, the amount of by-products generated during etching can be suppressed, and etching can be accelerated.

[0055] Delay time T delay In this case, both the HF power and the LF1 power are temporarily turned off. This temporarily stops the generation of radicals and ions before the time t2 when the LF1 power is supplied. As a result, the time T b In this method, the ion flux (amount of ions) that reaches the bottom of the recess to be etched can be controlled, and etching can be accelerated.

[0056] In addition, the delay time T delay By providing this, the LF1 power can be controlled to be turned on after the plasma temperature has dropped. lThe peak-to-peak voltage (Vpp) of the LF1 power can be increased, and the ion incident angle into the etched recess can be controlled more vertically. However, the delay time T delay If the delay time T is too long, ions will disappear due to the ion decay shown in Figure 4. delay is preset to an appropriate value.

[0057] At time t3, the LF1 power is controlled to be in the OFF state. In period (3), the exhaust period T off During the exhaust period T, both the HF power and the LF1 power are controlled to be in the OFF state, and the by-products are exhausted. off is preset as a time during which by-products do not adhere to the substrate W.

[0058] Exhaust period T off At time t4 after the time T has elapsed, the HF power is controlled to be in the on state again, and the period (4) returns to the period (1). In this way, the on / off states of the HF power and the LF1 power are controlled so that their on states do not overlap in time, and the time T s , time T b , delay time T delay , time T off In particular, the first bias RF generation unit 31b is configured to shift the timing of the change in the power level of the first bias RF pulse signal relative to the timing of the change in the power level of the source RF pulse signal. This causes a delay time T delay As a result, the supply of the HF power and the LF1 power is stopped for a period T b However, the timing of supplying the HF power and the LF1 power is not limited to this. For example, when the delay time T delay may not be provided.

[0059] (3-frequency pulse signal) 6 to 8 are diagrams showing pulse patterns of triple-frequency high-frequency power pulses according to an embodiment. First, the supply timing of the pulse signals of HF power (Source Power), LF1 power (Bias1 Power), and LF2 power (Bias2 Power), which are triple-frequency high-frequency power pulses shown in FIGS. 6 to 8, will be described. The horizontal axis in FIGS. 6 to 8 indicates the time of one cycle, and the vertical axis indicates the on / off states of the HF power, LF1 power, and LF2 power. Periods (1) to (4) constitute one cycle, and control of the pulse signals of the HF power, LF1 power, and LF2 power is repeated.

[0060] In the control of the triple-frequency high-frequency power pulse, the on states of LF1 power and LF2 power do not overlap in time, and while LF1 power is on, LF2 power is off, and while LF1 power is off, LF2 power is on. The on states of HF power and LF1 power, and the on states of HF power and LF2 power may or may not overlap in time.

[0061] The source RF generator 31a is configured to generate a source RF pulse signal (HF power). In this embodiment, the source RF pulse signal has four power levels (High / Middle / Low / Off). These power levels can be arbitrarily set and changed depending on the target process. For example, the source RF pulse signal has a frequency of 27 MHz.

[0062] The first bias RF generating unit 31b is configured to generate a first bias RF pulse signal (LF1 power), and in this embodiment, the first bias RF pulse signal has two power levels (On / Off). That is, the first bias RF pulse signal has two or more power levels including a zero power level. The frequency of the first bias RF pulse signal is lower than the frequency of the source RF pulse signal. For example, the first bias RF pulse signal has a frequency of 13 MHz.

[0063] The second bias RF generating unit 31c is configured to generate a second bias RF pulse signal (LF2 power), and in this embodiment, the second bias RF pulse signal has two power levels (On / Off). That is, the second bias RF pulse signal has two or more power levels including a zero power level. The frequency of the second bias RF pulse signal is lower than the frequency of the first bias RF pulse signal. For example, the second bias RF pulse signal has a frequency of 1.2 MHz.

[0064] 6 to 8, Source Power (HF power) indicates the state of the source RF pulse signal, Bias Power1 (LF1 power) indicates the state of the first bias RF pulse signal, and Bias Power2 (LF2 power) indicates the state of the second bias RF pulse signal.

[0065] 6, the HF power has a high power level, and the LF1 power and the LF2 power are in an off state. 11 Time until T s In this case, plasma containing radicals and ions is generated by supplying HF power, and as a result, the etching target film 100 is etched through the mask 101, and mainly radicals R adhere to the inner walls of holes HL formed in the etching target film 100, as shown in FIG.

[0066] Time T s Time t after elapse 11 When the HF power transitions to the OFF state, the radicals, ions, and plasma temperature decay with their respective time constants, as shown in an example in Figure 4. Depending on the decay state of these plasma parameters, the power level of the HF power is reduced or the timing of turning on the LF1 power and the LF2 power is controlled during the periods (2) and (3) when the HF power is controlled to the OFF state and during the period (4) when by-products are exhausted.

[0067] In this embodiment, the HF power is reduced from the high power level to the middle power level (or the off state) at time t 11 to delay time T delay1Time t shifted by 12 The LF1 power is switched on at this time. This allows the ion flux that reaches the bottom of the etched recess to be controlled, as shown in Figure 6(b). It also reduces the amount of by-products produced during etching.

[0068] In addition, the delay time T delay1 By setting the LF1 power on after the plasma temperature has dropped, the ion energy ε l However, as shown in Figure 4, the delay time T delay1 If the delay time T is too long, ions will disappear. delay1 is preset to an appropriate value.

[0069] In period (2), the HF power is at the Middle power level, the LF1 power is on, and the LF2 power is maintained in the off state. 13 At time t, the HF power transitions to a low power level (or OFF state) and the LF1 power transitions to an OFF state. 13 to delay time T delay2 The time t shifted (delayed) by 14 At time t 13 In period (3), the HF power is at the low power level (or in the off state), and the LF2 power is in the on state, and the LF1 power is in the off state.

[0070] In this embodiment, LF2 power having a frequency lower than that of the LF1 power supplied in period (2) is supplied in period (3). The Vpp of the LF2 power is larger than the Vpp of the LF1 power. This allows the bias voltage Vpp to be larger in period (3) than in period (2), and the ion energy ε l This allows the ion incident angle to be controlled more vertically. b2In this way, the ion flux that reaches the bottom of the etched recess can be controlled. As a result, as shown in FIG. 6(c), by-products B remaining at the corners of the bottom of the hole HL are etched, and etching can be accelerated. However, as shown in FIG. 4, the delay time T delay2 If the delay time T is too long, ions will disappear. delay2 is preset to an appropriate value.

[0071] In this way, in the process of etching deep holes with a high aspect ratio, the mask selectivity can be increased and the ion incident angle can be made vertical by using the pulse signals of the HF power, LF1 power, and LF2 power. This makes it possible to make the etching profile vertical and promote etching. However, the process of etching deep holes with a high aspect ratio is one example of substrate processing, and the type of process is not limited to this.

[0072] In period (4), exhaust of by-products is controlled. That is, in period (4), the HF power, LF1 power, and LF2 power are controlled to be in the off state. As a result, as shown in FIG. 6(d), by-products B adhering to the inside of the hole HL are exhausted. This can promote etching in the next cycle. Period (4) is preset to a time during which by-products B do not re-adhere to the substrate W.

[0073] 6, the power level of the HF power is controlled to four levels, and the power levels of the LF1 power and the LF2 power are controlled to two levels, an on / off state, but this is not limiting. For example, the power level of the HF power may be controlled to three or more levels.

[0074] 7 shows another example of the pulse pattern of triple-frequency high-frequency power pulses. In this example, periods (1) to (4) form one cycle, and control of the pulse signals of the HF power, LF1 power, and LF2 power is repeated.

[0075] In period (1), the time T from time t0 to time t1 s1The HF power has a high power level, which generates a plasma containing radicals and ions.

[0076] The time T when the HF power is at a high power level s1 Time T b1 At this time, the LF1 power is switched to the ON state, which attracts the generated ions into the substrate W and promotes etching.

[0077] At time t1, the LF1 power transitions to the off state, and then the HF power transitions to the middle power level. s2 In the period (3), the supply of reduced HF power reduces the generation of radicals and ions. The HF power transitions to the off state. In the period (3), the HF power may have a power level lower than the power level in period (2). In this case, the HF power has a middle power level in period (2) and a low power level in period (3). As shown in an example in Figure 4, radicals, ions, and plasma temperature decay with their respective time constants. The timing of turning on and off the LF1 power and LF2 power is controlled according to the decay state of these plasma parameters and the power level of the HF power.

[0078] For example, if the LF1 power or the LF2 power is turned on when the plasma temperature is high, a large amount of by-products are generated, which may hinder etching. Therefore, it is considered to turn on the LF2 power when the plasma temperature is not high. In other words, when the LF2 power is turned on after a predetermined delay time T delay At time t2 after the time has elapsed, the plasma temperature has dropped. At this timing, the LF2 power is switched on. That is, after the delay time T delayThe LF2 power transitions to the ON state after a shift (delay) of 1000 Hz. This reduces the amount of by-products produced during etching, accelerating etching. In this embodiment, the power level of the HF power during period (2) is lower than the power level of the HF power during period (1). However, the HF power may be OFF during period (2).

[0079] In this embodiment, the delay time T delay At this time, the LF1 power is turned off and the power level of the HF power is reduced. This causes a delay time T delay As a result, the generation of radicals and ions can be reduced during the time T b2 In this case, the ion flux that reaches the bottom of the recess formed in the film to be etched can be controlled.

[0080] In addition, during period (1), the LF2 power is turned off, and after the plasma temperature drops, the LF2 power is turned on, allowing the ion incident angle to be controlled more vertically. However, as shown in Figure 4, the delay time T delay If the delay time T is too long, ions will disappear. delay is preset to an appropriate value.

[0081] By this control, the on / off state of the LF1 power and the on / off state of the LF2 power are transitioned to the on state at different time periods, thereby mainly controlling the behavior of ions. b1 and the LF2 power has a power level greater than 0 at time T b1 The LF2 power has a zero power level at time T b2 and the LF1 power has a power level greater than 0 at time T b2 That is, the LF1 power and the LF2 power do not overlap at times when they have a power level greater than 0.

[0082] LF2 power has a higher mask selectivity than LF1 power, enabling vertical etching. During period (1) when the power level of the HF power is higher than during period (2), a large amount of radicals and ions are generated, and supplying LF2 power during period (1) makes it difficult to achieve the above-mentioned effects. On the other hand, during period (2) when the power level of the HF power is lower than during period (1), the generation of radicals and ions decreases, and supplying LF2 power during period (2) makes it easier to achieve the above-mentioned effects. Therefore, by supplying LF2 power during period (2), the ion energy can be increased and the ion incident angle can be made vertical. As a result, during period (2), the mask selectivity is higher than during period (1), enabling vertical etching.

[0083] The LF1 power and the LF2 power can generate pulse signals having two power levels, an on state and an off state. However, pulse signals having two or more power levels may be generated, such as an on state, an off state, and an intermediate power level for the LF1 power and the LF2 power. The LF1 power and the LF2 power may have two different on states.

[0084] At time t3, the HF power is switched off. In period (3), the exhaust of by-products is controlled. That is, during the exhaust period T from time t3 to time t4, off During the exhaust period T, the HF power, the LF1 power, and the LF2 power are turned off, thereby exhausting the by-products. off is preset as a time during which by-products do not adhere to the substrate W.

[0085] Exhaust period T off At time t4 after the lapse of time, the HF power transitions to the High power level, and at time t5, the period (4) returns to period (1). In this way, the power levels of the HF power, LF1 power, and LF2 power are controlled separately.

[0086] 6 and 7, the timing of the change in the power level of the second bias RF pulse signal is shifted relative to the timing of the change in the power level of the source RF pulse signal and / or the power level of the first bias RF pulse signal. However, this is not limiting, and a delay time does not have to be provided.

[0087] 8 shows another example of the pulse pattern of triple-frequency high-frequency power pulses. In this example, too, periods (1) to (4) form one cycle, and control of the pulse signals of the HF power, LF1 power, and LF2 power is repeated.

[0088] The difference between this example and the pulse signal pattern in Figure 7 will be described. In the example in Figure 7, the power level of the HF power had three levels including a 0 power level (off state). In contrast, as in this example, the power level of the HF power may have four levels. Furthermore, the power level of the HF power may or may not include the 0 power level. For example, as in this example, during period (3) in which by-products are exhausted, the HF power may not be turned off, but the power level of the HF power may be reduced and maintained in the on state.

[0089] In addition, in FIG. 7, the LF1 power has two levels, on and off. In contrast, in this example, the LF1 power is turned on and off for a time T b1-1 , time T b1-2 Alternatively, the LF1 power may have two levels of ON state, and three levels including a power level of 0. In this example as well, the ON state (High power level) where the power level of the LF1 power is the highest and the ON state of the LF2 power do not overlap in time.

[0090] [Modification of Plasma Processing Apparatus] A modified example of the plasma processing apparatus 1 will be described with reference to Fig. 9. Fig. 9 is a diagram showing an example of the plasma processing apparatus 1 according to the modified example. The plasma processing apparatus 1 according to the modified example differs from the configuration of the plasma processing apparatus 1 shown in Fig. 2 only in that the power supply unit includes a DC power supply unit 32.

[0091] The DC power supply unit 32 includes a DC pulse generation unit 32a coupled to the substrate support unit 11. The DC pulse generation unit 32a is connected to the conductive member 112 of the substrate support unit 11 via a second matching circuit 34 and is configured to generate a bias DC pulse signal (voltage). The generated bias DC pulse signal is applied to the conductive member 112 of the substrate support unit 11. The DC pulse generation unit 32a may be provided in addition to the RF power supply unit 31, or may be provided instead of the second bias RF generation unit 31c. The other configurations of the plasma processing apparatus 1 according to the modified example are the same as those of the plasma processing apparatus 1 shown in FIG. 2, and therefore description thereof will be omitted.

[0092] Next, examples of pulse patterns of DC pulses and high frequency power pulses according to Modifications 1 to 3 will be described with reference to Fig. 10 to Fig. 12. Fig. 10 to Fig. 12 are diagrams showing pulse patterns of DC pulses and high frequency power pulses according to Modifications 1 to 3.

[0093] 10 shows pulse patterns of the HF power, the LF1 power, and the DC pulse voltage (DC pulse signal) when the DC pulse generating unit 32a is provided instead of the second bias RF generating unit 31c. In the first modification, the control of the pulse signals of the HF power, the LF1 power, and the DC pulse voltage is repeated, with periods (1) to (3) and an exhaust period (not shown) after period (3) being one cycle.

[0094] From time t0 to time t 21 In the period (1) until time t, the HF power has a high power level, the LF1 power has a high power level, and the DC pulse voltage is in the off state. 21 At time t, the HF power transitions to a low power level, the LF1 power transitions to a low power level, and the DC pulse voltage remains off. 21 From time t 22 In the period (2) until time t, the HF power has a low power level, the LF1 power has a low power level, and the DC pulse voltage is in an off state. 22At time t, the HF power transitions to the OFF state, the LF1 power transitions to the OFF state, and the DC pulse voltage remains OFF. 22 to delay time T delay After the time t, the DC pulse voltage transitions to the ON state. 22 to delay time T delay After elapsed, time t 23 During the period (3) up to , the HF power and the LF1 power are in the OFF state, and the DC pulse voltage is in the ON state. The DC pulse generating unit 32a generates a pulse sequence while the DC pulse voltage is in the ON state.

[0095] As described above, in Modification 1, the LF1 power has a zero power level during the on time of the DC pulse voltage in Period (3). The DC pulse generating unit 32a is configured to generate a DC pulse signal during the DC on time and to stop generating the DC pulse during the DC off time that is different from the DC on time.

[0096] 11 shows pulse patterns of the HF power, LF1 power, LF2 power, and DC pulse voltage when the DC pulse generating unit 32a is provided in addition to the second bias RF generating unit 31c. In the second modification, periods (1) to (4) and an exhaust period (not shown) after period (4) constitute one cycle, and control of the pulse signals of the HF power, LF1 power, LF2 power, and DC pulse voltage is repeated.

[0097] From time t0 to time t 24 In the period (1) until time t, the HF power and the LF1 power are in the ON state, and the LF2 power and the DC pulse voltage are in the OFF state. 24 At time t, the HF power remains on, the LF1 power transitions to the off state, the LF2 power remains off, and the DC pulse voltage transitions to the on state. 24 From time t 25 During the period (2) up to time t, the HF power is in the ON state, the LF1 power and the LF2 power are in the OFF state, and the DC pulse voltage is in the ON state. The DC pulse generating unit 32a generates a pulse sequence while the DC pulse voltage is in the ON state.25 At time t, the HF power remains on, the LF1 power remains off, the LF2 power transitions to the on state, and the DC pulse voltage transitions to the off state. 25 From time t 26 In the period (3) until time t, the HF power is in the ON state, the LF1 power is in the OFF state, the LF2 power is in the ON state, and the DC pulse voltage is in the OFF state. 26 At time t, the HF power transitions to the OFF state, the LF1 power remains OFF, the LF2 power remains ON, and the DC pulse voltage remains OFF. 26 From time t 27 In the period (4) up to, the HF power is in the OFF state, the LF1 power is in the OFF state, the LF2 power is in the ON state, and the DC pulse voltage is in the OFF state.

[0098] As described above, in Modification 2, the LF2 power has a zero power level during the on time of the DC pulse voltage in Period (2). The DC pulse generating unit 32a is configured to generate a DC pulse signal during the DC on time and to stop generating the DC pulse during the DC off time that is different from the DC on time.

[0099] 12 shows another example of the pulse patterns of the HF power, LF1 power, LF2 power, and DC pulse voltage when the DC pulse generating unit 32a is provided in addition to the second bias RF generating unit 31c. In the third modification, the control of the pulse signals of the HF power, LF1 power, LF2 power, and DC pulse voltage is repeated, with periods (1) to (3) and an exhaust period (not shown) after period (3) being one cycle.

[0100] From time t0 to time t 28During a period (1) up to time t, the HF power has a high power level, the LF1 power has a high power level, the LF2 power is in an off state, and the DC pulse voltage is in an on state. The DC pulse voltage transitions to the on state with a delay relative to the transition of the HF power to the high power level and the transition of the LF1 power to the high power level. The DC pulse generating unit 32a generates a pulse sequence when the DC pulse voltage is in the on state. At time t 28 At time t, the HF power transitions to a low power level, the LF1 power transitions to a low power level, the LF2 power remains off, and the DC pulse voltage remains on. 28 From time t 29 In a period (2) until time t, the HF power has a low power level, the LF1 power has a low power level, the LF2 power is in an off state, and the DC pulse voltage is in an on state. 29 At time t, the HF power transitions to the OFF state, the LF1 power transitions to the OFF state, the LF2 power remains OFF, and the DC pulse voltage transitions to the OFF state. 29 to delay time T delay After time t, the LF2 power transitions to the ON state. 29 to delay time T delay After elapsed, time t 30 In the period (3) up to the time point, the HF power and the LF1 power are in the OFF state, the LF2 power is in the ON state, and the DC pulse voltage is in the OFF state.

[0101] As described above, in Modification 3, the LF2 power has a zero power level during the on times of the DC pulse voltage in Periods (1) and (2). The DC pulse generating unit 32a is configured to generate a DC pulse signal during the DC on times and to stop generating DC pulses during DC off times that are different from the DC on times.

[0102] As described above, the ON state of the DC pulse voltage and the ON state of the LF2 power do not overlap in time. Note that the ON state of the DC pulse voltage and the ON state of the LF1 power may or may not overlap in time.

[0103] As described above, according to the plasma processing apparatus and plasma processing method of this embodiment, the process performance can be improved by using three high frequency power pulse signals.

[0104] The plasma processing apparatus and plasma processing method according to the presently disclosed embodiments should be considered to be illustrative in all respects and not restrictive. The embodiments can be modified and improved in various ways without departing from the spirit and scope of the appended claims. The features described in the above embodiments can be configured in other ways as long as they are not inconsistent, and can be combined as long as they are not inconsistent.

[0105] For example, although the above embodiment has been described using an inductively coupled plasma device as an example, the present invention is not limited thereto and may be applied to other plasma devices. For example, a capacitively coupled plasma (CCP) device may be used instead of the inductively coupled plasma device. In this case, the capacitively coupled plasma device includes an upper electrode and a lower electrode. The lower electrode is disposed within the substrate support, and the upper electrode is disposed above the substrate support. The first matching circuit 33 is coupled to the upper electrode, and the second matching circuit 34 is coupled to the lower electrode. Therefore, the first matching circuit 33 is coupled to the antenna 14 of the inductively coupled plasma device or the upper electrode of the capacitively coupled plasma device. That is, the first matching circuit 33 is coupled to the chamber 10. [Explanation of symbols]

[0106] 1. Plasma processing equipment 2. Control section 10 Chambers 10s Plasma treatment space 11 Substrate support 12 Annular member 13 Gas inlet 14 Antenna 20 Gas supply unit 21 Computer 21a Processing section 21b Storage section 21c communication interface 31 RF power supply section 31a Source RF generation section 31b First bias RF generation unit 31c Second bias RF generator 31d Synchronization signal generation section 32a DC pulse generator 34b1 1st adjustment circuit 34b2 1st separation circuit 34c1 2nd adjustment circuit 34c2 2nd separation circuit 33 1st matching circuit 34 Second matching circuit 37 Power Supply Line

Claims

1. a plasma processing chamber; a substrate support disposed within the plasma processing chamber; a first matching circuit; a second matching circuit; a source RF generator coupled to the plasma processing chamber through the first matching circuit and configured to generate a source RF pulse signal; a first bias RF generator configured to provide a first bias RF pulse signal to the substrate support through the second matching circuit; a second bias RF generator configured to provide a second bias RF pulse signal to the substrate support through the second matching circuit; Equipped with The second matching circuit a first isolation circuit connected between the first bias RF generator and the substrate support, configured to suppress coupling of the second bias RF pulse signal from the second bias RF generator to the first bias RF generator and to supply the first bias RF pulse signal from the first bias RF generator to the substrate support; a second isolation circuit connected between the second bias RF generator and the substrate support, configured to suppress coupling of the first bias RF pulse signal from the first bias RF generator to the second bias RF generator and to supply the second bias RF pulse signal from the second bias RF generator to the substrate support; Equipped with Plasma processing equipment.

2. a synchronization signal generator configured to generate a synchronization signal for synchronizing the source RF generator, the first bias RF generator, and the second bias RF generator with each other; The plasma processing apparatus according to claim 1 .

3. the source RF pulse signal has at least three power levels; the first bias RF pulse signal has at least two power levels; the second bias RF pulse signal has at least two power levels; The plasma processing apparatus according to claim 1 .

4. the frequency of the second bias RF pulse signal is different from the frequency of the first bias RF pulse signal; The plasma processing apparatus according to claim 1 .

5. the frequency of the second bias RF pulse signal is lower than the frequency of the first bias RF pulse signal; The plasma processing apparatus according to claim 1 .

6. the synchronization signal generator is disposed in any one of the source RF generator, the first bias RF generator, and the second bias RF generator; The plasma processing apparatus according to claim 2 .

7. the first bias RF generation unit is configured to shift a timing of a change in a power level of the first bias RF pulse signal relative to a timing of a change in a power level of the source RF pulse signal. The plasma processing apparatus according to claim 1 .

8. the second bias RF generation unit is configured to shift a timing of a change in a power level of the second bias RF pulse signal relative to a timing of a change in a power level of the source RF pulse signal and / or a timing of a change in a power level of the first bias RF pulse signal. The plasma processing apparatus according to claim 1 .

9. the second bias RF pulse signal has two power levels including a zero power level; The plasma processing apparatus according to claim 3 .

10. the first bias RF pulse signal has a power level greater than 0 at a first time; the second bias RF pulse signal has a zero power level at the first time. The plasma processing apparatus according to claim 3 .

11. the first isolation circuit includes a capacitor and a first inductor; the second isolation circuit includes a second inductor; The plasma processing apparatus according to any one of claims 1 to 10.

12. a plasma processing chamber; a substrate support disposed within the plasma processing chamber; an RF generator connected to the substrate support and configured to generate a bias RF pulse signal; a voltage pulse generator connected to the substrate support and configured to generate a voltage pulse signal; a matching circuit connected to the RF generating unit, the voltage pulse generating unit, and the substrate support unit; Equipped with The matching circuit includes: a first isolation circuit connected between the RF generator and the substrate support, the first isolation circuit configured to suppress coupling of the voltage pulse signal from the voltage pulse generator to the RF generator and to provide the bias RF pulse signal from the RF generator to the substrate support; a second isolation circuit connected between the voltage pulse generator and the substrate support, the second isolation circuit configured to suppress coupling of the bias RF pulse signal from the RF generator to the voltage pulse generator and to provide the voltage pulse signal from the voltage pulse generator to the substrate support; Equipped with the first isolation circuit includes a capacitor and a first inductor; the second isolation circuit includes a second inductor; Plasma processing equipment.

13. Further comprising a synchronization signal generator configured to generate a synchronization signal for synchronizing the RF generator and the voltage pulse generator with each other. The plasma processing apparatus according to claim 12 .

14. a plasma processing chamber; a substrate support disposed within the plasma processing chamber; an antenna disposed on or above the plasma processing chamber; a source RF generator connected to the antenna and configured to generate a source RF pulse signal; a voltage pulse generator connected to the substrate support and configured to generate a bias voltage pulse signal; a bias RF generator connected to the substrate support and configured to generate a bias RF pulse signal; a first matching circuit connected to the source RF generator and the antenna, the first matching circuit enabling the source RF pulse signal to be supplied from the source RF generator to the antenna through the first matching circuit; a second matching circuit connected to the voltage pulse generator and the substrate support, the second matching circuit enabling the bias voltage pulse signal to be supplied from the voltage pulse generator to the substrate support via the second matching circuit; Equipped with The second matching circuit a first isolation circuit connected between the bias RF generator and the substrate support, configured to suppress coupling of the bias voltage pulse signal from the voltage pulse generator to the bias RF generator and to provide the bias RF pulse signal from the bias RF generator to the substrate support; a second isolation circuit connected between the voltage pulse generator and the substrate support, configured to suppress coupling of the bias RF pulse signal from the bias RF generator to the voltage pulse generator and to provide the bias voltage pulse signal from the voltage pulse generator to the substrate support; Equipped with the first isolation circuit includes a capacitor and a first inductor; the second isolation circuit includes a second inductor; Plasma processing equipment.

15. a synchronization signal generator configured to generate a synchronization signal for synchronizing the source RF generator, the bias RF generator, and the voltage pulse generator with each other; The plasma processing apparatus according to claim 14 .

16. a synchronization signal generator configured to generate a synchronization signal for synchronizing the source RF generator and the voltage pulse generator with each other; The plasma processing apparatus according to claim 14 .

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