Power Factor Correction Circuit

Abstract

To provide a power factor improvement circuit that enables zero voltage switching regardless of an instantaneous value of an input voltage and a value of an output voltage.SOLUTION: A power factor improvement circuit includes a rectifier circuit 2 that rectifies an input voltage of an AC power supply, a series circuit in which a reactor L and a control switch Q1 are connected in series at both ends of the rectifier circuit, a series circuit in which a synchronous rectifier switch Q2 and an output capacitor C1 are connected in series at both ends of two main terminals of the control switch, and a control circuit 10 that alternately turns on and off the control switch and the synchronous rectifier switch such that the output voltage of the output capacitor becomes a predetermined value, and controls an on-period of the control switch such that a peak value of a current flowing through the control switch is proportional to the input voltage, and the control circuit turns the control switch and the synchronous rectifier switch on and off so as to adjust the amount of reverse excitation that reverse-excites a reactor by causing the current flowing through the reactor to flow back from the output voltage side to the input voltage side according to an instantaneous value of the input voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power factor correction circuit. [Background technology]

[0002] In conventional critical current power factor correction (PFC) circuits that perform synchronous rectification, zero voltage switching (ZVS) is not possible unless the ratio of the instantaneous value of the input voltage Vin to the output voltage Vo is above a certain value (2Vin≦Vo).In addition, high efficiency cannot be achieved because the frequency changes depending on the input voltage.

[0003] Therefore, in Patent Document 1, for a synchronous rectification boost chopper circuit, the choke coil current is set to a predetermined value so that it flows in both the positive and negative directions within one switching cycle when the output current is equal to or less than the rated value.As a result, by turning off the rectifier element when the current in the output choke coil is flowing in the negative direction, the parasitic capacitance of the main switching element can be removed.

[0004] That is, when the main switching element is turned off, the output choke coil is inversely excited from the output via the rectifier element, so that the voltage of the main switching element drops, making zero voltage switching possible. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-220342 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in Patent Document 1, power factor correction operation that corrects the power factor by inputting AC is not taken into consideration, and the amount of back excitation is not adjusted during control. Furthermore, with the conventional technology, zero voltage switching is not possible unless the relationship between the instantaneous value of the input voltage and the output voltage satisfies (2Vin≦Vo).

[0007] An object of the present invention is to provide a power factor correction circuit capable of zero voltage switching regardless of the instantaneous value of the input voltage and the value of the output voltage. [Means for solving the problem]

[0008] In order to solve the above problems, a power factor correction circuit according to the present invention includes a rectifier circuit that rectifies the input voltage of an AC power supply; a first series circuit in which a reactor and a control switch are connected in series across the rectifier circuit; a second series circuit in which a synchronous rectifier switch and an output capacitor are connected in series across two main terminals of the control switch; and a control circuit that alternately turns on and off the control switch and the synchronous rectifier switch so that the output voltage of the output capacitor becomes a predetermined value, and controls the on period of the control switch so that the peak value of the current flowing through the control switch is proportional to the input voltage, and the control circuit turns on and off the control switch and the synchronous rectifier switch according to the instantaneous value of the input voltage so as to reverse the current flowing through the reactor from the output voltage side to the input voltage side, thereby adjusting the amount of back excitation that back excites the reactor. [Effects of the Invention]

[0009] According to the present invention, the control switch and the synchronous rectifier switch are turned on and off to adjust the amount of back excitation that back excites the reactor by causing the current flowing through the reactor to flow back from the output voltage side to the input voltage side in accordance with the instantaneous value of the input voltage, so that zero voltage switching of the control switch can be performed regardless of the instantaneous value of the input voltage or the value of the output voltage.As a result, the frequency also decreases, enabling high efficiency. [Brief explanation of the drawings]

[0010] [Figure 1]1 is a circuit configuration diagram of a power factor correction circuit according to a first embodiment. [Figure 2] 2 is a circuit diagram illustrating the parasitic capacitances of the control switches and synchronous rectification switches of the power factor correction circuit shown in FIG. 1 and an external capacitor. [Figure 3] 2 is a diagram showing a circuit network when a synchronous rectification switch of the power factor correction circuit shown in FIG. 1 is turned off. [Figure 4] 2 is a diagram showing the minimum backflow current versus the input voltage of the power factor correction circuit shown in FIG. 1. FIG. [Figure 5] 2 is a diagram showing an asymptote representing the slope of a backflow current when the input voltage of the power factor correction circuit shown in FIG. 1 is the same as the output voltage. [Figure 6] 2 is a diagram showing an AC input current of the power factor correction circuit shown in FIG. 1 and a peak value envelope IR of a reverse current that enables ZVS. [Figure 7] 2 is a diagram showing a current waveform when a control switch of the power factor correction circuit shown in FIG. 1 is turned on and a current waveform when a synchronous rectification switch is turned on. [Figure 8] 1 is a diagram showing a conventional switching peak current envelope by a dotted line and a switching peak current envelope of the present invention when a reverse current flows by a solid line. [Figure 9] FIG. 10 is a circuit configuration diagram of a power factor correction circuit according to a second embodiment. [Figure 10] 10 is a circuit diagram illustrating the control switch of the power factor correction circuit shown in FIG. 9, the parasitic capacitance of the synchronous rectification switch, and an external capacitor. [Figure 11] 10 is a diagram illustrating a control switch, a synchronous rectification switch, and a polarity changeover switch when the AC input voltage is a positive voltage in the power factor correction circuit shown in FIG. [Figure 12] 10 is a diagram illustrating a control switch, a synchronous rectification switch, and a polarity changeover switch when the AC input voltage is a negative voltage in the power factor correction circuit shown in FIG. 9. FIG. [Figure 13] FIG. 10 is a circuit configuration diagram of a power factor correction circuit according to a third embodiment. [Figure 14] FIG. 10 is a circuit configuration diagram of a power factor correction circuit according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Power factor correction circuits according to embodiments of the present invention will be described in detail below with reference to the drawings.

[0012] The power factor correction circuit according to the embodiment adjusts the back excitation amount of the reactor according to the instantaneous value of the AC input voltage, thereby enabling zero voltage switching when the control switch is off for all phases of the AC voltage, and enabling power factor correction with little distortion. Furthermore, the power factor correction circuit keeps the on width of the control switch constant even when the load fluctuates by adjusting the back excitation amount, enabling power factor correction with little distortion.

[0013] (Zero voltage switching solution) First, we will explain the solution that enables zero voltage switching. In Figure 1, consider the condition under which the drain-source Vds of the control switch Q1 becomes zero regardless of the input voltage. In other words, if the drain-source Vds of the control switch Q1 does not become zero even after the reactor L has finished releasing energy through the synchronous rectifier switch Q2, the synchronous rectifier switch Q2 will continue to be on, and the reactor L will be back-excited by the output voltage Vo.

[0014] Then, after allowing a certain amount of current to flow backward from the output side to the input side, the synchronous rectifier switch Q2 is turned off. The required amount of back excitation can be obtained by analyzing the behavior immediately after the synchronous rectifier switch Q2 is turned off.

[0015] Figure 3 shows the circuit network when the synchronous rectifier switch Q2 is turned off. Since the switches Q1 and Q2 are off, they are not added to the circuit network. The current i(t) and the voltage v(t) of the capacitor C are set as shown by the arrows in Figure 3. If the back-excitation current at time t=0 is Ir, then

[0016]

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[0017] The network equation is

[0018]

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[0019] From equations 1 and 2, we obtain the following equation 3.

[0020]

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[0021] From equation 3, we can find the condition for the back-excitation current Ir relative to the input voltage Vin. Since the voltage v(t) must be at least zero V or less,

[0022]

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[0023] Therefore,

[0024]

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[0025] To obtain the minimum backflow current Ir for the first equation of Equation 5 to hold, the first equation of Equation 5 must be satisfied when the cosine function is at its minimum, in other words, when it is -1, and so Equation 6 is obtained.

[0026]

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[0027] The reverse current Ir should satisfy Equation 7.

[0028]

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[0029]

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[0030] For example, if we use Equation 7 to plot the minimum reverse current Ir for the input voltage under the conditions of Equation 8, we get the result shown in Figure 4. When Vo / 2 ≥ Vin = 200V, there is no need for reverse current, so the reverse current Ir is zero when Vin is between 0V and 200V.

[0031] The reverse current Ir may be controlled by performing the complex calculation of equation (7), but it may also be controlled by the asymptote IR of the reverse current Ir when 0≦Vin≦Vo, as in equation 9. In this case, control is simpler.

[0032]

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[0033] Figure 5 shows the asymptote IR according to Equation 9 and the reverse current Ir according to Equation 7.

[0034] Since Vin is the instantaneous value of the AC input voltage, providing the reverse current Ir in equation 9 means that if the reverse current Ir is always at least the fixed value shown in equation 10 with respect to the instantaneous value of the AC input voltage, zero voltage switching will be possible even if Vin is at any voltage lower than Vo.

[0035]

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[0036] That is, when the reverse current Ir is equal to or greater than the fixed value shown in Equation 10, zero voltage switching is possible.

[0037] Figure 6 shows the AC input current at this time and the reverse current peak value envelope IR at which ZVS is possible. Figure 7 shows the current waveform when the control switch Q1 is on and the current waveform when the synchronous rectifier switch Q2 is on.

[0038] In Figure 8, the dotted line shows the conventional switching peak current envelope under the condition of Equation 8, and the solid line shows the switching peak current envelope of the present invention when a reverse current flows based on Equation 10. In this case, the input voltage is 200V AC.

[0039] (First embodiment) Next, a power factor correction circuit according to a first embodiment that enables zero voltage switching will be described.

[0040] Fig. 1 is a circuit diagram of a power factor correction circuit according to a first embodiment. Fig. 2 is a circuit diagram illustrating the parasitic capacitances (capacitors indicated by dotted lines) of the control switches and synchronous rectifier switches of the power factor correction circuit shown in Fig. 1, and external capacitors. The power factor correction circuit shown in Fig. 2 includes an AC power source 1, a full-wave rectifier circuit 2 that full-wave rectifies the input voltage of the AC power source 1, and an input capacitor C2 connected across the full-wave rectifier circuit 2.

[0041] In Fig. 1, the input voltage Vin is a rectified voltage collectively output from the AC power supply 1, full-wave rectifier circuit 2, and input capacitor C2 shown in Fig. 2. A reactor L and a control switch Q1 made of a MOSFET are connected in series across the full-wave rectifier circuit 2.

[0042] A synchronous rectifier switch Q2 and an output capacitor C1 are connected in series across the drain and source terminals of the control switch Q1. A series circuit of resistors R1 and R2 is connected across the output capacitor C1. An output voltage Vo is output from both ends of the output capacitor C1.

[0043] The control circuit 10 includes an error amplifier 11, comparators 12 and 17, RS flip-flop circuits 14 and 18, and an amplifier 15. The error amplifier 11 amplifies the error voltage between the output voltage Vo from the resistor R2 and a reference voltage Vref, and outputs the error voltage to the inverting input terminal of the comparator 12. The current sensor 13 detects the drain current flowing through the control switch Q1.

[0044] When the error voltage from error amplifier 11 is equal to or greater than the voltage based on the current detected by current sensor 13, comparator 12 outputs a low level to reset terminal R of RS flip-flop circuit 14. At this time, a high level is output from output terminal Q of RS flip-flop circuit 14, turning on control switch Q1. A low level is output from the inverting output terminal of RS flip-flop circuit 14 to set terminal S of RS flip-flop circuit 18, turning off synchronous rectifier switch Q2.

[0045] When the error voltage from the error amplifier 11 is less than a voltage based on the current detected by the current sensor 13, the comparator 12 outputs a high level to the reset terminal R of the RS flip-flop circuit 14. At this time, a low level is output from the output terminal Q of the RS flip-flop circuit 14, so the control switch Q1 is turned off. A high level is output from the inverting output terminal of the RS flip-flop circuit 14 to the set terminal S of the RS flip-flop circuit 18, so the synchronous rectifier switch Q2 is turned on. Therefore, by alternately turning on and off the control switch Q1 and the synchronous rectifier switch Q2, the output voltage Vo of the output capacitor C1 can be controlled to a predetermined value.

[0046] Furthermore, the control circuit 10 controls the ON period of the control switch Q1 so that the peak value of the current flowing through the control switch Q1 is proportional to the input voltage Vin. To this end, the amplifier 15 amplifies the input voltage Vin by a factor of A, and outputs the amplified input voltage from the inverting output terminal of the RS flip-flop circuit 18 to the set terminal S of the RS flip-flop circuit 14 via the comparator 17, thereby turning on the control switch Q1.

[0047] In addition, the control circuit 10 turns on and off the control switch Q1 and the synchronous rectifier switch Q2 in accordance with the instantaneous value of the input voltage Vin so as to adjust the amount of reverse excitation that reversely excites the reactor L by causing the current flowing through the reactor L to flow from the output voltage Vo side to the input voltage Vin side.

[0048] That is, immediately after the synchronous rectifier switch Q2 is turned on to release the excitation energy of the reactor L, the synchronous rectifier switch Q2 continues to be turned on, causing current to flow back from the output capacitor C1 to the input voltage Vin side.

[0049] The amount of current to be reversed is determined by at least the coefficient of the inductance value L of the reactor L used and the parasitic capacitance value C of the boost control switch Q1, and the instantaneous value of the AC input voltage Vin.

[0050] As a result, enough energy to absorb the charge stored in the parasitic capacitance C of the boost control switch Q1 is stored in the reactor L. The charge stored in the parasitic capacitance C of the control switch Q1 is proportional to the input voltage Vin and the parasitic capacitance value, and if the inductance of the reactor L is large, the amount of back excitation can be small.

[0051] To adjust the amount of back excitation, the power factor correction circuit shown in Fig. 1 includes an amplifier 15, a current sensor 16, and a comparator 17. The amplifier 15 amplifies the input voltage Vin by a factor of A, and outputs the amplified input voltage to the inverting input terminal of the comparator 17. The fixed value A is the value shown in Equation 10. The amplifier 15 multiplies the input voltage Vin by A to find the asymptote IR shown in Equation 9.

[0052] The current sensor 16 corresponds to a back-excitation current detection unit, and detects the back-excitation current that flows when the reactor L is back-excited. The comparator 17 corresponds to a zero-voltage switching determination unit, and when the value of the back-excitation current detected by the current sensor 16 is equal to or greater than the output from the amplifier 15, determines that zero-voltage switching of the control switch Q1 is possible, and outputs a high level to the reset terminal R of the RS flip-flop circuit 18.

[0053] As a result, the output terminal Q of the RS flip-flop circuit 18 outputs a low level signal to the synchronous rectifier switch Q2, turning off the synchronous rectifier switch Q2 and stopping the reverse current flow.

[0054] That is, the current in the reactor L is reversed up to a value obtained by multiplying the instantaneous value of the input voltage Vin by the fixed value shown in Equation 10. By controlling the on / off of the control switch Q1 and the synchronous rectifier switch Q2 in this way, perfect zero-voltage switching of the control switch Q1 is possible over the entire phase range of the input voltage, which changes as a sine wave, without changing the circuit.

[0055] Q1 and Q2 are controlled to be turned on and off complementarily with a dead time provided.

[0056] (Second embodiment) Next, a power factor correction circuit according to a second embodiment that enables zero voltage switching will be described with reference to Fig. 9. The power factor correction circuit shown in Fig. 9 is a totem-pole bridgeless power factor correction circuit, and includes an AC power supply 1, a full-wave rectifier circuit 2, a reactor L, current sensors 13a and 16a, switches Q1-Q4, an output capacitor Co, and a control circuit 10a.

[0057] The current sensor 13a is connected in series to the reactor L and detects the current flowing through the reactor L.

[0058] Switches Q1 and Q2 are connected in series, and one end of reactor L is connected to the connection end of switches Q1 and Q2. A series circuit of switches Q3 and Q4 is connected to both ends of the series circuit of switches Q1 and Q2. Both ends of the series circuit of switches Q3 and Q4 are connected to both ends of output capacitor Co, and output voltage Vo is obtained from output capacitor Co.

[0059] The switches Q1 and Q2 are turned on and off in a complementary manner with a dead time provided, and the switches Q3 and Q4 are switched between polarities in a complementary manner with a dead time provided.

[0060] The control circuit 10a includes a full-wave rectifier circuit 2, an error amplifier 11, comparators 12 and 17, RS flip-flop circuits 14a and 18a, an amplifier 15, a polarity determination unit 19, and polarity switching units 20-22.

[0061] The functions of the full-wave rectifier circuit 2, error amplifier 11, comparators 12 and 17, and amplifier 15 shown in FIG. 9 are the same as those shown in FIG. 1, and therefore a description thereof will be omitted here.

[0062] The output terminal Q of the RS flip-flop circuit 14a is connected to one input terminal of the polarity switching unit 21, and the output terminal Q of the RS flip-flop circuit 18a is connected to the other input terminal of the polarity switching unit 21.

[0063] The polarity determination unit 19 determines whether the input voltage Vin is positive or negative, and outputs the positive or negative polarity to the polarity switching units 20-22. If the polarity determined by the polarity determination unit 19 is positive, the polarity switching unit 21 switches Q1 to a control switch and Q2 to a synchronous rectification switch. The control switch Q1 is turned on and off by the output from the output terminal Q of the RS flip-flop circuit 14a. The synchronous rectification switch Q2 is turned on and off by the output from the output terminal Q of the RS flip-flop circuit 18a.

[0064] When the polarity determined by the polarity determination unit 19 is negative, the polarity switching unit 21 switches Q1 to a synchronous rectification switch and Q2 to a control switch. The synchronous rectification switch Q1 is turned on and off by the output from the output terminal Q of the RS flip-flop circuit 14a. The control switch Q2 is turned on and off by the output from the output terminal Q of the RS flip-flop circuit 18a.

[0065] When the polarity determined by the polarity determining unit 19 is positive, the polarity switching unit 22 switches the polarity switching switch Q3 on and switches the polarity switching switch Q4 off. When the polarity determined by the polarity determining unit 19 is negative, the polarity switching unit 22 switches the polarity switching switch Q3 off and switches the polarity switching switch Q4 on.

[0066] FIG. 10 illustrates the parasitic capacitances (capacitors indicated by dotted lines) of the switches Q1 to Q4 and the external capacitors C1 to C4 of the power factor correction circuit shown in FIG.

[0067] Next, we will explain the operation of the power factor correction circuit shown in Fig. 9 when the AC input voltage Vin is a positive voltage. At this time, due to the operation of the polarity determination unit 19 and the polarity switching unit 21, Q1 operates as a control switch, Q2 operates as a synchronous rectification switch, and the polarity switching switch Q3 turns on and the polarity switching switch Q4 turns off, as shown in Fig. 11.

[0068] To simplify the closed circuit at this time, the capacitance of the control switch Q1 is C = C1 + C2, and the capacitance of the polarity changeover switch Q4 is C4 in Figure 11. When the polarity changeover switch Q3 is on, C and C4 are connected in parallel, so the reverse current IR is expressed by equation (11).

[0069]

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[0070] During reverse current, the charge in capacitor C4 is extracted via the first path: C4 → Q2 → L → Vin → C4. The charge in capacitor C is extracted via the second path: C → L → Vin → Q3 → C. Furthermore, the charge in capacitor C is extracted via the third path: Co → Q2 → L → Vin → Q3 → Co, which compensates for the insufficient reverse excitation provided by capacitors C and C4.

[0071] Next, we will explain the operation when the AC input voltage Vin is negative. In this case, due to the operation of the polarity determination unit 19 and the polarity switching unit 21, Q1 operates as a synchronous rectification switch, Q2 operates as a control switch, and the polarity switching switch Q3 is turned off and the polarity switching switch Q4 is turned on, as shown in Figure 12.

[0072] To simplify the closed circuit at this time, the capacitance of the control switch Q2 is C = C1 + C2, and the capacitance of the polarity changeover switch Q3 is C3 in Figure 12. When the polarity changeover switch Q4 is turned on, C and C3 are connected in parallel, so the reverse current IR is expressed by equation (12).

[0073]

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[0074] During reverse current, the charge in capacitor C3 is extracted via the first path: C3 → vIN → L → Q1 → C3. The charge in capacitor C is extracted via the second path: C → Q4 → Vin → L → C. Furthermore, the charge that is not yet fully excited by capacitors C and C3 is reverse excited via the third path: Co → Q4 → Vin → L → Q1 → Co.

[0075] As described above, the power factor correction circuit according to the second embodiment can achieve high efficiency through zero voltage switching at a high power factor with the same control as the power factor correction circuit according to the first embodiment.

[0076] (Third embodiment) Next, a power factor correction circuit according to a third embodiment that enables zero voltage switching will be described with reference to Fig. 13. In the power factor correction circuits according to the first and second embodiments, a current sensor 16 is provided to detect the back excitation current that flows when the reactor L is back excited.

[0077] In contrast, the power factor correction circuit according to the third embodiment shown in FIG. 13 is characterized in that it eliminates the current sensor 16 shown in FIG. 1 and realizes all-range ZVS by calculating the on-time of the control switch Q1 by digitally adding a fixed value determined by the reactor L and the parasitic capacitance value C of the control switch Q1 to the on-time of a conventional critical current type PFC.

[0078] In the power factor correction circuit shown in Fig. 13, a reactor L, a current sensor 13a, and a control switch Q1 made of a MOSFET are connected in series across an input voltage Vin. A synchronous rectifier switch Q2 and an output capacitor C0 are connected in series to the drain and source terminals of the control switch Q1. A series circuit of resistors R1 and R2 is connected across the output capacitor C0. An output voltage Vo is output from both ends of the output capacitor C0.

[0079] The control circuit 10 b includes a tonQ1 calculator 31 , a tonQ2 calculator 32 , a multiplier 33 , an adder 34 , a sawtooth wave generating circuit 35 , a comparator 36 , and an inverter 37 .

[0080] The current sensor 13a is connected in series to the reactor L and detects the input current Iin flowing through the reactor L.

[0081] 7 is the input current Iin, the on-time tonQ1 of the control switch Q1 is expressed by equation (13): A tonQ1 calculator 31 calculates the on-time tonQ1 of the control switch Q1 using equation (13).

[0082]

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[0083] The first on-time of the control switch Q1 of the conventional critical current PFC corresponds to the first term in equation (13). The second term in equation (13) is the second on-time, which is a fixed value determined by the reactor L and the parasitic capacitance C of the control switch Q1, and represents the amount of back excitation shown in equation (9).

[0084] That is, the on-time tonQ1 of the switch Q1 of the present invention is the sum of the first on-time of the control switch Q1 of the conventional critical current type PFC and the second on-time, which is a fixed value determined by the inductance value of the reactor L and the parasitic capacitance value C of the control switch Q1.

[0085] For this reason, the tonQ1 calculator 31 calculates a first on-time of the control switch Q1 based on the input current Iin and input voltage Vin detected by the current sensor 13a and the reactance value of the reactor L, and adds a second on-time determined by the inductance value of the reactor L and the parasitic capacitance value C of the control switch Q1 to the first on-time to obtain the on-time tonQ1 of the control switch Q1.

[0086] That is, by adding a fixed value determined by the reactance value of reactor L and the parasitic capacitance value C of control switch Q1 to the time calculated based on input current Iin, input voltage Vin, and the reactance value of reactor L, the on time tonQ1 of control switch Q1 that takes the amount of back excitation into account can be obtained.

[0087] Therefore, even if the backflow current (amount of back excitation) as shown in equation (9) is not detected by the current sensor 16, ZVS of the control switch Q1 can be achieved by obtaining the on time tonQ1 of the control switch Q1 taking the amount of back excitation into consideration.

[0088] The tonQ2 calculator 32 calculates the differential voltage (Vo-Vp) between the input voltage Vin (Vp) and the output voltage Vo, and obtains a division value by dividing the input voltage Vp by the differential voltage (Vo-Vp).

[0089] Furthermore, to obtain the on-time tonQ2 of the switch Q2, a multiplier 33 multiplies the on-time tonQ1 of the control switch Q1 by the divided value obtained by the tonQ2 calculator 32, based on the relationship of the voltage-time product of the reactor L. That is, the multiplier 33 calculates the on-time tonQ2 of the switch Q2 using equation (14).

[0090]

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[0091] The adder 34 adds the on-time tonQ1 of the control switch Q1 to the on-time tonQ2 of the switch Q2 output from the multiplier 33 to obtain the time T. The switching period T is determined by the time T.

[0092] The sawtooth wave generating circuit 35 generates a sawtooth wave signal having a peak value T based on the time T from the adder 34. The comparator 36 receives the sawtooth wave signal from the sawtooth wave generating circuit 35 at its inverting input terminal, and receives the on-time tonQ1 of the control switch Q1 from the tonQ1 calculator 31 at its non-inverting input terminal.

[0093] If the on-time tonQ1 of the control switch Q1 from the tonQ1 calculator 31 is equal to or greater than the value of the sawtooth wave signal from the sawtooth wave generating circuit 35, the comparator 36 applies a high-level signal to the gate of the control switch Q1 to turn on the control switch Q1.

[0094] Furthermore, when the on-time tonQ1 of the control switch Q1 from the tonQ1 calculator 31 is equal to or greater than the value of the sawtooth wave signal from the sawtooth wave generating circuit 35, the comparator 36 inverts the high-level signal using an inverter 37 and applies a low-level signal to the gate of the switch Q2 to turn off the switch Q2.

[0095] If the on-time tonQ1 of the control switch Q1 from the tonQ1 calculator 31 is less than the value of the sawtooth wave signal from the sawtooth wave generating circuit 35, the comparator 36 applies a low-level signal to the gate of the control switch Q1 to turn off the control switch Q1.

[0096] Furthermore, when the on-time tonQ1 of the control switch Q1 from the tonQ1 calculator 31 is less than the value of the sawtooth wave signal from the sawtooth wave generating circuit 35, the comparator 36 inverts the low-level signal using an inverter 37 and applies a high-level signal to the gate of the switch Q2 to turn on the switch Q2. Also, the switches Q1 and Q2 are provided with a dead time, and are controlled to turn on and off complementarily by the operations of the sawtooth wave generating circuit 35 and the comparator 36.

[0097] As a result, the same switching current waveform as that shown in FIG. 7 can be obtained.

[0098] As described above, according to the power factor correction circuit of the third embodiment, the current sensor 16 is eliminated, and the on-time of the switch Q1 is calculated by digitally adding a fixed value determined by the reactor L and the parasitic capacitance value C to the on-time of a conventional critical current type PFC, thereby realizing all-range ZVS.

[0099] (Fourth embodiment) Next, a power factor correction circuit according to a fourth embodiment that enables zero voltage switching will be described with reference to Fig. 14. The power factor correction circuit according to the fourth embodiment shown in Fig. 14 is characterized in that it eliminates the current sensor 16a shown in Fig. 9 and realizes all-range ZVS by calculating the on-time of the control switch Q1 by digitally adding a fixed value determined by the reactor L and the parasitic capacitance value C of the control switch Q1 to the on-time of a conventional critical current type PFC.

[0100] The control circuit 10c includes a full-wave rectifier circuit 2, a polarity discriminator 19, polarity switching units 20-22, a tonQ1 calculator 31a, a tonQ2 calculator 32, a multiplier 33, an adder 34, a sawtooth wave generating circuit 35, a comparator 36a, and an inverter 37a. The full-wave rectifier circuit 2, the polarity discriminator 19, and the polarity switching units 20-22 have been described in FIG. 9, so their description will be omitted here.

[0101] The tonQ1 calculator 31a calculates a first on-time of the control switch Q1 based on the input current Iin detected by the current sensor 13a, the input voltage Vin from the full-wave rectifier circuit 2, and the reactance value of the reactor L, and obtains the on-time tonQ1 of the control switch Q1 by adding a second on-time determined by the inductance value of the reactor L and the parasitic capacitance value C of the control switch Q1 to the first on-time. The comparator 36a outputs a comparator output to the polarity switching unit 21. The inverter 37a outputs an inverter output to the polarity switching unit 21.

[0102] The power factor correction circuit of the fourth embodiment configured as described above includes a tonQ1 calculator 31a, a tonQ2 calculator 32, a multiplier 33, an adder 34, a sawtooth wave generating circuit 35, a comparator 36a, and an inverter 37a, and therefore provides effects similar to those of the power factor correction circuit of the third embodiment. [Explanation of symbols]

[0103] 1 AC power supply 2 Full wave rectifier circuit 10, 10a, 10b, 10c control circuit 11 Error amplifier 12,17 Comparator 13, 13a, 16, 30 Current sensor 14, 14a, 18, 18a RS flip-flop circuit 15 amps 19 Polarity determination section 20, 21, 22 Polarity switching section 31,31a tonQ1 calculator 32 tonQ2 calculator 33 Multiplier 34 Adder 35 Sawtooth wave generator circuit 36,36a Comparator 37,37a Inverter Vin Input voltage C1 Output capacitor C2 input capacitor L reactor Q1 control switch Q2 synchronous rectifier switch D1, D2 internal diodes C10, C11 external capacitors R1,R2 resistance

Claims

1. a rectifier circuit that rectifies an input voltage of an AC power supply; a first series circuit in which a reactor and a control switch are connected in series to both ends of the rectifier circuit; a second series circuit in which a synchronous rectifier switch and an output capacitor are connected in series to the two main terminals of the control switch; a control circuit that alternately turns on and off the control switch and the synchronous rectification switch so that the output voltage of the output capacitor becomes a predetermined value, and controls the on period of the control switch so that the peak value of the current flowing through the control switch is proportional to the input voltage, the control circuit turns on and off the control switch and the synchronous rectification switch so as to adjust the amount of back excitation that back excites the reactor; The amount of back excitation is determined by a coefficient based on the inductance value L of the reactor and the parasitic capacitance C of the control switch, and the instantaneous value of the input voltage. Power factor correction circuit.

2. A rectifier circuit that rectifies the input voltage of an AC power supply; a first series circuit in which a reactor and a control switch are connected in series to both ends of the rectifier circuit; a second series circuit in which a synchronous rectifier switch and an output capacitor are connected in series to the two main terminals of the control switch; a control circuit that alternately turns on and off the control switch and the synchronous rectification switch so that the output voltage of the output capacitor becomes a predetermined value, and controls the on period of the control switch so that the peak value of the current flowing through the control switch is proportional to the input voltage, the control circuit turns on and off the control switch and the synchronous rectification switch so as to adjust the amount of back excitation that back excites the reactor; The control circuit includes a first calculator that calculates a first on-time of the control switch based on an input current flowing through the reactor, the input voltage, and a reactance value of the reactor, and obtains the on-time of the control switch by adding a second on-time, which is a fixed value determined by the reactance value of the reactor and a parasitic capacitance value of the control switch, to the first on-time. Power factor correction circuit.

3. a reverse excitation current detection unit that detects a reverse excitation current that flows when the reactor is reverse excited, 2. The power factor correction circuit according to claim 1, wherein the control circuit comprises a zero voltage switching determination unit that determines that zero voltage switching of the control switch is possible when the value of the inverse excitation current detected by the inverse excitation current detection unit is equal to or greater than the value obtained by multiplying the instantaneous value of the input voltage by the coefficient.

4. the control circuit includes a second calculator that calculates an on-time of the synchronous rectifier switch based on the input voltage, the output voltage, and the on-time of the control switch calculated by the first calculator; 3. The power factor correction circuit according to claim 2, further comprising a function of alternately turning on and off the control switch and the synchronous rectification switch using a period obtained by adding together the on-time of the control switch calculated by the first calculator and the on-time of the synchronous rectification switch calculated by the second calculator.

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