Power System

Abstract

The power system provides power from a power source to a load via a power distribution bus and includes a DC-DC converter coupled in parallel with a network of switching elements coupled between an output terminal of the power source and the power distribution bus. A controller is configured to selectively activate or deactivate each of the DC-DC converter and the switching elements to enable the power source to power the load via the power distribution bus. The switching elements may be transistors and the diodes may be parasitic body diodes of the transistors. The power source may be a battery, such as a rechargeable battery. An output voltage level from the battery may be regulated by the controller depending on the operation of the DC-DC converter and the number of activated or deactivated transistors.

Description

[Technical Field]

[0001] This application is a continuation-in-part of U.S. Patent Application No. 16 / 760,762, filed April 30, 2020, which is a national stage application of International Application No. PCT / US2017 / 068301, filed December 22, 2017, both of which are incorporated herein by reference.

[0002] The present disclosure relates generally to power supply technology, and more particularly to a system for monitoring and controlling the discharge of battery cells when connected to a power distribution bus. [Background technology]

[0003] This section is intended to introduce various aspects of the art that may be related to example embodiments of the present disclosure. This description is believed to help provide a framework to facilitate a better understanding of certain aspects of the present disclosure. Accordingly, it should be understood that this section should be read in this light, and not necessarily as admissions of prior art.

[0004] Modern information technology and telecommunications systems include power distribution buses that operate at a variety of power distribution bus voltages. For example, computer servers typically distribute 12 volts (“V”) to internal subsystems such as memory, processors, storage, cooling fans, and I / O (such internal subsystems to which a power distribution bus provides supply voltage are referred to herein as “load circuits,” or simply “loads”). Wired telecommunications systems typically use a 48V power distribution bus voltage level, while wireless telecommunications and cell site systems often use 24V as their internal power distribution bus voltage level. Despite the different power distribution bus voltage levels, all of the above systems share some common characteristics in that these power distribution buses can carry tens or hundreds of amperes (“A”) of current under normal operation and generally have a requirement that the voltage on these buses be regulated to ensure that the maximum voltage excursion on the bus is limited to a fixed value above or below a desired nominal value. A regulated power distribution bus is subject to a specified voltage tolerance around its nominal value. For example, a 12V power distribution bus with a tolerance of + / -10% has an operating envelope ranging from a maximum level of 13.2V to a minimum level of 10.8V.

[0005] Within the past decade, battery systems optimized for delivering very high currents for short periods of time have been developed. Battery systems typically include one or more battery cells (the terms "battery" and "cell" may be used interchangeably herein). Their compact size makes them attractive for some equipment types to replace traditional uninterruptible power supplies ("UPS"), which serve as short-term electrical backup for equipment in the event of an AC mains power outage. These high-power battery systems are unique in their ability to deliver very high discharge currents, but suffer from the drawback of only being able to accept charge currents slowly. This ratio of discharge current to charge current can be as high as 30:1 or even 40:1 with currently commercially available technology.

[0006] High-power battery systems used today for short-term backup applications typically use output regulators in the form of DC-DC converters capable of handling high energy (e.g., output DC-DC converters) to match the battery system's output voltage to the power distribution bus voltage and prevent reverse current flow from the power distribution bus to the battery, which results in unsafe charging currents and represents a safety hazard. In many of today's systems, the charging current is provided via a path separate from the discharge current and may be provided by a separate low-power charging DC-DC converter. Therefore, an opportunity exists for cost reduction and electrical efficiency improvement if such high-power output DC-DC converters can be eliminated or replaced with a different approach having higher electrical efficiency and lower cost, allowing the battery system to be directly connected to the power distribution bus via this improved approach.

[0007] Conventional technology exists today for directly connecting battery systems to electric buses, and nearly all of it uses high-side or low-side metal-oxide-semiconductor field-effect transistor ("MOSFET") pairs that function as switching elements (also referred to herein simply as "switches") for on / off control of charge and discharge currents. MOSFETs are commonly used in these applications because, by the nature of their manufacturing process, they contain a diode (i.e., a parasitic body diode) that allows current to flow in one direction through the MOSFET even when the MOSFET is switched off. While this body diode is a problem in many applications, it is actually utilized as an advantage in embodiments of the present disclosure.

[0008] Many of today's battery systems utilize two switches arranged back-to-back, each containing either a parasitic body diode in parallel with the switch or an external diode beyond the switch. The switch with the forward-facing diode (pointing from the battery to the load) is considered the "charge" switch (when in the off state, it blocks any charging current), and the other switch is the "discharge" switch (when in the off state, it blocks any discharging current). This scheme works for low-power distribution buses where the following conditions are met: (1) the total current capacity of the bus (either available on the bus or consumed by loads coupled to the bus) does not exceed the safe charging or discharging current of the battery, (2) the distribution bus voltage is controllable so that it can be made high enough when necessary so that the battery receives a full charge after being discharged, and (3) the allowable operating voltage of the load circuit is between or includes the minimum battery terminal voltage when the battery is fully discharged (i.e., 0% state of charge) and the maximum battery terminal voltage when the battery is fully charged (i.e., 100% state of charge). However, it is impractical to use this approach when the voltage tolerances required by the load circuits coupled to the power distribution bus require tight regulation such that the voltage supplied to the power distribution bus must remain below the fully charged voltage of the battery, nor can it be used when the current normally available from the bus exceeds the safe charging current level of the battery.

[0009] Low-power systems, such as those implemented for notebook and tablet computers and mobile phones, have industry standards for direct connection of single-cell or multi-cell battery systems to a power distribution bus. These devices use the aforementioned single-transistor switch “back-to-back” configuration for charge and discharge control. Figure 2 shows a “high-side” switch configuration, in which switches Q1 and Q2 (e.g., MOSFETs) are positioned to connect to the high-voltage side (+) of the battery. Switches Q1 and Q2 are connected so that the battery can be charged and discharged depending on which of the two switches is switched on. A controller is coupled to each of the switches and controls which switch is switched on under which conditions and for which duration. In this manner, charge and discharge control by the controller is achieved. The controller may permit or disallow charging or discharging based on the battery’s state of health, charge level, instantaneous capacity, voltage, current, temperature, or any other parameter the designer can select. The combination of the switches, their parasitic body diodes, and the controller allows for controlled charging (prohibiting the flow of charge from the power distribution bus to the battery), controlled discharging (prohibiting the flow of charge from the battery to the power distribution bus), or complete electrical isolation of the battery terminals from the power distribution bus (prohibiting the flow of charge in either direction).

[0010] This dual-switch control scheme works for many battery applications where the allowable charge current, discharge current, and available bus current are close in magnitude, or where the allowable charge current is significantly higher than the available bus current. Laptop computer batteries have a typical design point where the charge rate is approximately equal to the discharge rate, e.g., approximately 1 C (i.e., 1 x the nominal battery capacity C). Cell phone batteries may be designed to have higher charge rates (e.g., up to 4 C), but typically have a very low discharge rate. This allows the phone to charge quickly while simultaneously having a long operating life on a single charge. At these low charge and discharge rates, the parasitic body diode of the switch has sufficient thermal and power capabilities to pass the required charge and discharge currents with minimal temperature rise and power loss.

[0011] However, there are increasing examples of real-world systems with battery charge-discharge asymmetries where the allowable discharge rate far exceeds the allowable charge rate. For example, batteries performing electrical backup duty are typically designed for a 60-90 minute charge time and a fast discharge time that can completely deplete the battery in 60-90 seconds. This very large imbalance between the normal charge current and the normal discharge current (i.e., large charge-discharge current asymmetry) makes the dual-switch control scheme of Figure 2 impractical. Specifically, the body diode found in the charge control switch Q1 is completely inadequate to carry the discharge current seen when such a scheme is used, as its voltage drop and power loss would adversely affect system operation. Additionally, in the example of a tightly regulated +12V distribution bus with lithium-ion batteries as the energy storage device, the batteries selected for such an application should be as close as possible to +12V (e.g., three or four series-connected cells charged to 4.0V per cell). As those skilled in the art will appreciate, it is not possible to fully charge this battery from a +12V supply through an isolation diode with low forward voltage characteristics (as typically found in the parasitic body diode of a conventional MOSFET).

[0012] In addition to the isolation switch mentioned above, regulated systems are designed to convert battery voltage from one voltage level to another to control electrical output when safely connecting to a power bus. For example, a linear regulator can be used to provide a uniform voltage output at a specific value or set point. Referring to FIG. 3, a feedback circuit including an operational amplifier ("OPAMP") driving a series pass element (e.g., a transistor with a diode in parallel) is shown. In such a regulated system, the circuit of FIG. 3 essentially replaces the discharge control switch Q2 of FIG. 2 and provides a regulated voltage output at the load up to a crossover point where a minimum voltage drop across the series pass element creates a voltage drop between the input to the linear regulator and its output (i.e., between the battery terminals and the load terminals) sufficient to reduce the voltage at the load terminals to within the load circuit's specified operating voltage threshold (e.g., minimum allowable operating voltage level).

[0013] Such linear regulators may work satisfactorily when implemented for low-power devices. However, there are many deficiencies that arise as power levels increase. First, the series pass element is operated in its linear mode, and the voltage difference between the input and output voltages is imposed on the series pass element, generating very high power dissipation and V*I-based heat at high currents. This generated heat must be transferred to the environment or otherwise removed from the device; otherwise, it concentrates within the series pass element package, causing even high-power transistors to quickly overheat and fail. Packages capable of handling the heat generated from this power dissipation require a direct-attached heat sink and a very large physical package with significant airflow to cool the device. Most high-power battery systems have physical space limitations and manufacturing constraints that prevent the use of this type of transistor packaging. Furthermore, it is difficult to find practical surface-mount transistors ("SMT") that can dissipate sufficient heat through their printed circuit board ("PCB") contacts.

[0014] Switching regulators are also used to convert battery voltages to fixed bus voltages, and they can be much more electrically efficient due to their operating mode. Generally, step-down or "buck" converters require a higher input voltage than their output voltage to operate and cannot generate an output voltage above that input voltage. A typical input-output voltage relationship for a buck converter is shown in Figure 4. This requires a series-connected battery stack with a higher series cell count to raise the input voltage to the converter to the required level necessary to achieve high efficiency and a manageable switching duty cycle. However, such a high cell count can increase cost, circuit complexity, total circuit packaging, and battery management system ("BMS") component count and complexity. Figure 5 shows an alternative implementation of a DC-DC converter as a "buck-boost" converter, which can generate a constant output voltage regardless of whether the input voltage is lower than, equal to, or higher than the constant output voltage, recognizing that if the input voltage drops too low, converter operating parameters such as input current may become too large to continue safe operation. For this reason, most buck-boost converters include an input undervoltage protection limit, or "UV shutdown," to prevent damage to the converter. While a buck-boost converter can accommodate fewer series cells than is achievable with a buck converter, the integrated circuit that forms the heart of a buck-boost converter's control circuitry is more difficult to find and generally more expensive than a buck converter's control integrated circuit ("IC"). A typical input / output voltage relationship for a buck-boost converter is shown in Figure 5. Regardless of which DC-DC topology—linear, switching buck, or switching buck-boost—is used in today's modern configurations, it's important to note that the DC-DC converter must be designed, both electrically and thermally, to handle the maximum output power of the battery system. For example, a battery system rated for 1500 watts of output power requires a DC-DC converter designed to handle the full 1500 watts the battery can deliver.Therefore, a large and expensive DC-DC converter must be connected between the battery and the load circuit. This is shown in Figure 6, which shows the battery (+) terminal and the output voltage terminal V. o The DC-DC converter is connected between the battery and the output voltage terminal V o All power delivered to the must be processed through a DC-DC converter, so the DC-DC converter must be sized to safely handle the maximum power expected to be delivered. [Prior art documents] [Patent documents]

[0015] [Patent Document 1] U.S. Patent Application No. 2020 / 0350779 [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a circuit block diagram configured in accordance with an embodiment of the present disclosure. [Figure 2] 1 is a system representing a prior art example of a charge / discharge control system for a battery coupled to a power source and a load. [Figure 3] FIG. 1 illustrates a prior art implementation of a linear regulator DC-DC converter for regulating the output of a battery connected to a load. [Figure 4] FIG. 2 illustrates input voltage versus output voltage characteristics of a step-down (buck) converter suitable for use in embodiments of the present disclosure. [Figure 5] FIG. 2 illustrates input voltage versus output voltage characteristics of a step-up / step-down (buck-boost) converter suitable for use in embodiments of the present disclosure. [Figure 6] FIG. 1 illustrates a prior art system for using a DC-DC converter in combination with a battery and a controller for providing a regulated output voltage to a load. [Figure 7] FIG. 1 is a circuit block diagram of a system disclosed in U.S. Patent Application No. 2020 / 0350779. [Figure 8] 1 is a plot of a family of voltage curves versus state of charge (“SOC”) at different possible load currents for an exemplary lithium-ion rechargeable battery in which four cells are connected in series, the cells being constructed of lithium manganese cobalt chemistry. [Figure 9] FIG. 1 illustrates a non-limiting representation of control steps using a binary sequencing scheme that can be utilized in the system disclosed in U.S. Published Patent Application No. 2020 / 0350779. [Figure 10] 1 is a plot of a family of voltage curves versus state of charge ("SOC") at different possible load currents for an exemplary lithium-ion rechargeable battery in which four cells are connected in series, the cells being constructed of lithium iron phosphate ("LFP") chemistry. [Figure 11] FIG. 1 illustrates the output current limit characteristics of a DC-DC converter suitable for use in embodiments of the present disclosure. [Figure 12] FIG. 10 illustrates a specified load voltage tolerance range and various control thresholds and set points for control of a system according to an embodiment of the present disclosure. [Figure 13] FIG. 2 is a simplified block diagram of the system shown in FIG. 1 configured in accordance with an embodiment of the present disclosure. [Figure 14] FIG. 2 is a block diagram of a non-limiting example of a control element used in embodiments of the present disclosure that implements a system state determination function, inputs signals to the control element, and outputs signals for the control element. [Figure 15] FIG. 2 is a schematic diagram of a non-limiting example of an electronic circuit that implements a state determination function, according to an embodiment of the present disclosure. [Figure 16] 1 is a truth table implemented in a non-limiting example of a state determination element used in an embodiment of the present disclosure showing output signal levels from a control element based on different states of input signals and defining which combinations of output signal levels will trigger a control action. [Figure 17]2 is a table demonstrating several non-limiting on / off control sequences that result in a gradual increase or decrease in the overall impedance of the FET / resistor pair network shown in FIG. 1. [Figure 18] FIG. 1 is a flowchart diagram of a process configured in accordance with an embodiment of the present disclosure. [Figure 19] 2 is a diagram illustrating a time domain analysis showing the instantaneous level of the voltage at the output node Vo of the system shown in FIG. 1, the slope (rising or falling) of the voltage at the output node Vo, and the resulting instantaneous state of the control signal for various exemplary situations that the system may encounter during operation. [Figure 20] 2 is a diagram illustrating a time domain analysis showing the instantaneous level of the voltage at the output node Vo of the system shown in FIG. 1, the slope (rising or falling) of the voltage at the output node Vo, and the resulting instantaneous state of the control signal for various exemplary situations that the system may encounter during operation. DETAILED DESCRIPTION OF THE INVENTION

[0017] It will be understood that the specific embodiments described herein are shown by way of illustration and not as limitations of the embodiments of the present disclosure, and that the principal features of the present disclosure can be employed in various embodiments without departing from the scope of the present disclosure.

[0018] By convention, current in circuit diagrams and equations is referred to by the symbol i and is expressed in units of amperes, or ("A").

[0019] As an alternative to linear or switching regulators, the system disclosed in U.S. Published Patent Application No. 2020 / 0350779 provides a set of individually controlled switches that connect a power source (e.g., a battery terminal voltage) to an output (e.g., a power distribution bus) to which a load circuit (e.g., see FIG. 7) can be connected. When MOSFETs are utilized as switches, the MOSFETs can operate in a predetermined (e.g., programmed) manner to regulate the output voltage and current supply from the battery by utilizing the inherent forward voltage drop of the MOSFET's body diode and / or an external resistor (e.g., a resistive element) coupled in series with each MOSFET. Such a circuit can be configured to replace a battery discharge DC-DC converter and operate more efficiently in many operating modes compared to linear or switching regulators that withstand high discharge currents and / or operate at high power.

[0020] To understand how the parallel connection of discharge control switches can control the application of battery discharge voltage and provide equivalent output voltage regulation, the characteristic behavior of an exemplary battery will now be described.

[0021] Rechargeable batteries, such as lithium-ion ("Li-ion")-based rechargeable batteries, may be constructed with different internal materials and specific chemical compositions that define each battery cell's operating voltage range, maximum discharge current, internal impedance, and specific capacity. Each of these parameters defines a family of discharge voltage versus discharge current curves (also called "VI curves") that are unique to each type of cell.

[0022] A battery may be configured with a fixed chemical energy capacity determined by the finite weight or volume of active chemicals contained within each cell of the battery. Capacity is measured by discharge at a given current and time until a certain minimum voltage is achieved. Capacity is typically reported in milliampere-hours (“mAh”) or ampere-hours (“Ah”). This capacity is represented herein by the letter “C,” which corresponds to the continuous current available from a battery over one hour as the battery discharges from 100% state of charge (“SOC”) (i.e., fully charged to the maximum allowable voltage) to 0% SOC (i.e., fully discharged to the minimum allowable voltage). For any given discharge current, the battery's terminal voltage drops according to its SOC. As the battery's chemical capacity is depleted, the SOC decreases from 100% to 0%.

[0023] FIG. 8 shows a family of plots (i.e., VI curves) of voltage curves versus SOC at different possible load currents for an exemplary battery of four series-connected lithium-ion rechargeable cells using nickel manganese cobalt (“NMC”) chemistry. These curves define an exemplary operating envelope within which the battery voltage may operate for various conditions of battery current and SOC. More specifically, the plots in FIG. 8 represent voltage curves versus SOC at different load currents where the battery has a capacity of 1 Ah during current demands of 10 A, 12 A, 15 A, and 20 A.

[0024] As can be seen, the terminal voltage of a battery at any given SOC shifts lower as current demand increases. The distance between the curves on the voltage scale increases as current demand increases is due to the internal resistance or impedance of the battery cell. The higher the internal impedance, the lower the battery terminal voltage for a given applied discharge current present at the battery output terminals. Therefore, the battery terminal voltage at a given SOC depends not only on the SOC but also on the discharge current demand, and lies within the operating envelope defined by the characteristic curve.

[0025] As can be seen from the diagram of FIG. 8 , the output (discharge) voltage of a typical battery is not constant but rather variable with the discharge current present at the battery output terminals and SOC; therefore, a typical battery itself does not have an inherent ability to regulate or maintain its discharge voltage within a particular voltage range over the time it takes for stored energy to be depleted from the battery or as the load current changes. However, as previously described herein, it is very common in power systems for any source supplying power to a power distribution bus to regulate the voltage supplied to the power distribution bus to ensure that maximum and minimum voltage excursions on the power distribution bus are limited to a desired nominal value, i.e., a specified value above or below a voltage tolerance range that can be tolerated by a load coupled to the power distribution bus (referred to herein as a “specified load voltage tolerance”) to ensure specified (e.g., error-free) operation. This is one reason why voltage regulators or DC-DC converters, such as those described above, are implemented to maintain the output voltage supplied to the power distribution bus (e.g., by a battery or other power source) within such specified load voltage tolerance range.

[0026] Referring again to FIG. 8 , for purposes of illustrating embodiments of the present disclosure, the operating envelope for a discharging battery to a particular load may be divided into several regions, in this example, Regions 1, 2, 3, and 4. The Region 1 area defines operating points on the battery terminal voltage for an SOC curve that is below the load's specified load voltage tolerance. The Region 2 area defines operating points on the battery terminal voltage for an SOC curve that is within the specified load voltage tolerance. The Region 3 area defines several operating points on the battery terminal voltage for an SOC curve that is above the specified load voltage tolerance. As described further herein, while operating within this Region 3 area, embodiments of the present disclosure are configured to utilize an N-FET / resistor pair network (e.g., see FIG. 9 ) to provide finer control of the output voltage provided to the load. According to an exemplary embodiment of the present disclosure, the upper boundary of the Region 3 area is less than about 5% above the upper boundary of the Region 2 area by the nominal value of the load voltage (e.g., 0.6 V for a 12 V nominal load voltage, 1.2 V for a 24 V nominal load voltage, etc.). The Region 4 area defines operating points on the battery terminal voltage for the SOC curve that are above the Region 3 area. The operating envelope of the exemplary battery described with respect to FIG. 10 is also divided into similar regions.

[0027] 7 is a circuit block diagram of a system 700 disclosed in U.S. Patent Application Publication No. 2020 / 0350779. System 700 employs a battery system 706 configured to selectively couple the output terminals of a battery 708 to a power distribution bus 704 via a defined switching arrangement including a network of N (where N≧2) parallel-connected discharge switches 710a-710d (e.g., MOSFETs), each coupled in series with a resistor 750a-750d to form a network of N FET / resistor pairs.

[0028] System 700 may be utilized with batteries having battery terminal voltages that extend beyond a specified load voltage tolerance (e.g., required by load 705; see, e.g., the Region 2 area shown in the example of FIG. 8 ). As described herein, typical batteries have terminal voltages at some operating points outside such narrowly specified load voltage tolerances required by many loads. Thus, system 700 may be used to regulate the supply voltage to power distribution bus 704 substantially within this specified load voltage tolerance of 12 V + / −5%, as shown in the Region 2 area of ​​FIG. 8 , even though the voltage present at the terminals of battery 708 exceeds this Region 2 range. The voltage present at the terminals of battery 708 may be configured to be above the specified load voltage tolerance of power distribution bus 704 (e.g., see the Region 3 and Region 4 areas shown in the example of FIG. 8 ) under some SOC and battery current conditions, while the voltage supplied to load 705 is regulated to substantially match the specified load voltage tolerance of power distribution bus 704 under other SOC or battery current conditions, such as the Region 2 area.

[0029] Each of resistors 750a-750d may be configured with a different resistance value, and each resistor in series 750a-750d may be configured so that its resistance value is lower than the previous resistor in the series (e.g., resistor 750b has a lower resistance value than resistor 750a, resistor 750c has a lower resistance value than resistor 750b, etc.). The FET / resistor pairs may be connected in parallel between the battery terminals and the power distribution bus 704 via another switching element (e.g., MOSFET) 711 that prevents charging of the battery directly from the power distribution bus 704, and each of the N FETs 710a-710d and their paired resistors, as well as FET 711, are independently controlled by controller 702 via control lines 721a-721e. However, embodiments may be implemented with one or more of resistors 750a-750d having substantially equivalent resistance values.

[0030] The number N of parallel-connected discharge control FET / resistor pairs can range from two to any number that can be practically controlled by the controller 702. The number N of discharge control FET / resistor pairs can generally be determined by several factors, such as the minimum and maximum voltage available from the battery 708, the expected range of minimum and maximum output current, and the required minimum and maximum output voltage range (e.g., as determined by a specified load voltage tolerance (e.g., see Region 2 area shown in the example of FIG. 8 )).

[0031] The battery 708 may be coupled to the power distribution bus 704 by the controller 702 activating (e.g., switching on) one or more of the N FETs 710a-710d in a predetermined manner (e.g., sequentially, in a binary count sequence, or in any other sequence), such as starting with the FET 710a, which may be paired with the highest resistance value resistor 750a. When the FET 710a is switched on, current begins to flow through the load 705, and the terminal voltage of the battery 708 begins to drop according to a battery impedance characteristic curve (see, e.g., FIGS. 8 and 10 ). If the current supplied to the load 705 through the series combination of the FET / resistor pair 710a / 750a is sufficiently high, the voltage drop across the series combination of the FET / resistor pair 710a / 750a increases until the voltage supplied to the load 705 drops to a predetermined threshold, which may be set (e.g., within the controller 702) according to the minimum regulation point specification of the load 705 (e.g., the lower limit of a specified load voltage tolerance range). When this threshold is reached and sensed by controller 702 via output voltage sensor 741, controller 702 may be configured to switch off FET / resistor pair 710a / 750a and switch on the FET paired with resistor 750b, which may have the next highest resistance in the series of resistors 750a-750d. Resistor 750b in series with FET 710b may be configured to have a significantly smaller resistance than that of resistor 750a, such that the voltage drop across the series combination of FET 710b and resistor 750b is lower than that across the series combination of FET 710a and resistor 750a. The effect of this is to raise the output voltage delivered to load 705 above the aforementioned threshold associated with the minimum regulation point specification of load 705 (e.g., the lower limit of a specified load voltage tolerance range), thus keeping the output voltage delivered to load 705 above this minimum predetermined threshold.In this manner, the output voltage supplied to the load 705 can be maintained by the controller 702 within an application regulatory window (e.g., a specified load voltage tolerance range (e.g., see the region 2 area shown in the example of FIG. 8 )) under varying battery terminal voltages and load currents sensed by the controller 702 via the battery voltage sensor 742, the output voltage sensor 741, and the current sensor 707 by the controller 702 selectively activating the N FETs 710a-710d (e.g., in an upward binary count sequence or other suitable sequence) to increase the voltage supplied to the load 705 or selectively deactivating the N FETs 710a-710d (e.g., in a downward binary count sequence) to decrease the voltage supplied to the load 705, where FET 710a is associated with the least significant bit of the binary sequential counter and FET 710d (or more) is associated with the most significant bit.

[0032] A non-limiting example of a regulation scheme that may be implemented within controller 702 is shown in Figure 9, which illustrates the total voltage drop across parallel-connected FET / resistor pairs in response to a binary count sequence for selective activation by controller 702 of N FETs 710a-710d. As can be seen, the voltage drop across the FET / resistor pair network is 2 The voltage can be controlled in discrete steps (e.g., 16 when N=4) from essentially 0 V to some desired maximum voltage (approximately 3.0 V in this example). oDue to its placement in battery system 706 between , load 705 sees its input voltage as the terminal voltage of battery 708 minus the voltage drop across the FET / resistor pair network. By this technique, regulation of the voltage supplied to load 705 (e.g., substantially within a specified load voltage tolerance) can be achieved and maintained by controller 702 switching N FETs 710a-710d on / off to regulate the impedance (i.e., the voltage drop) across the FET / resistor pair network.

[0033] Such a network of N parallel discharging switching elements (i.e., N FET / resistor pairs) may be configured (e.g., in response to instructions received from controller 702) to operate as a high-current digital-to-analog converter where the power supply voltage (i.e., from battery 708) is not constant over time (see, e.g., FIG. 8) but varies with the load current and SOC. In this configuration, information from voltage sensors 741, 742 and current sensor 707 may be utilized by controller 702 to compensate for variations in both the input and output voltages (i.e., battery 708 and load 705).

[0034] The resulting system 700 is thus configured as a network of N fixed impedance elements (i.e., N FETs 710a-710d and associated resistors 750a-750d), which can be switched in and out of the network by the controller 702 to compensate for changes in voltage on the input (i.e., battery 708) and output (i.e., load 705). By varying the resistance of the resistors 750a-750d, individual element impedances are defined. Each FET / resistor pair can be configured with a specific voltage drop at a given applied current. As a result, the system 700 can be configured to control a network of elements that defines a variable, controllable impedance between the battery 708 and the load 705. As the voltage on the load 705 increases, the network is adjusted by the controller 702 so that the total impedance increases and the voltage delivered to the load 705 decreases. As the voltage of the battery 708 drops, the network is reconfigured by the controller 702 so that the total impedance drops and therefore the voltage across the network also drops, thereby serving to maintain the voltage delivered to the load 705 within a desired range (e.g., substantially within a specified load voltage tolerance). The compensating voltage drop across the network, which is subtracted from the battery voltage, can then be controlled by the controller 702 using any number of different control techniques such that the resulting voltage delivered to the load 705 is controlled by the sequencing of the various N FET / resistor pairs in the system 700 to provide high-resolution voltage matching whenever the battery operating point lies within (e.g., drifts for whatever reason) Region 1, 2, or 3 operating ranges (e.g., as shown in FIG. 8 ).

[0035] Because system 700 can only reduce the supplied battery voltage to some lower voltage required by load 705, there are some areas of the battery characteristic curves that are unusable, corresponding to the Region 1 area, for example, as shown in Figure 8. Any energy contained in the Region 1 area cannot be used by system 700 and is essentially stuck. While the Region 1 area contains only a small portion of the total battery energy represented by this family of VI curves, other battery chemistry types and configurations may have significantly more energy stuck in the unusable Region 1 area (see, for example, Figure 10).

[0036] 1 shows a circuit block diagram of a system 100 configured in accordance with an embodiment of the present disclosure. System 100 may be configured to supply power to a load from a secondary power source via a power distribution bus when there is a failure of the primary power source. The primary power source may be a power supply unit coupled to an AC power source, and the secondary power source may be a battery, although embodiments of the present disclosure are not limited to such a configuration.

[0037] In the non-limiting exemplary embodiment shown with respect to FIG. 1 , the system 100 uses a battery system 106 configured to selectively couple the output terminals of a battery 108 to a power distribution bus 104 via a DC-DC converter 170 under the control of a controller 102, and a switching arrangement including a network of N (where N≧1) parallel-connected discharge switches 110b-110d (e.g., MOSFETs), each coupled in series with a resistor 150b-150d to form a network of N FET / resistor pairs (also referred to herein as an “N-FET / resistor pair network”).

[0038] Each of resistors 150b-150d may be configured with a different resistance value, and may be configured such that the resistance value of each resistor in series 150b-150d is lower than the previous resistor in the series (e.g., resistor 150c has a lower resistance value than resistor 150b, resistor 150d has a lower resistance value than resistor 150c, etc.). However, embodiments may be implemented with one or more of resistors 150b-150d having substantially equivalent resistance values.

[0039] The N FET / resistor pairs may be connected in parallel between the positive terminal of the battery 108 and the power distribution bus 104 via another switching element (e.g., a MOSFET) 111, which may be implemented to prevent charging of the battery 108 directly from the power distribution bus 104, and may similarly be interposed, with each of the N FETs 110b-110d, as well as FET 111, being selectively and independently controlled by the controller 102 via control lines 121b-121e.

[0040] The number N of parallel-connected discharge control FET / resistor pairs can range from 1 to any number that can be practically controlled by controller 102, and generally can be determined by one or more factors, such as the minimum and maximum voltage available from battery 108, the expected range of minimum and maximum output current, and the required minimum and maximum output voltage range (e.g., as determined by a specified load voltage tolerance (e.g., see Region 2 area shown in the example of FIG. 8 )). Changes in the terminal voltage and load current of battery 108 can be sensed by controller 102 via battery voltage sensor 142 and current sensor 107.

[0041] System 100 may be utilized with batteries having battery terminal voltages at useful operating points that extend beyond a specified load voltage tolerance range (e.g., as required by load 105, as compared to the full range of battery operating points, including those outside of Region 2 area, e.g., those included in Regions 1, 3, and 4, see Region 2 area shown in the example of FIG. 8 ). As described herein, a typical battery or series-connected batteries will, in almost all cases, have terminal voltages at some operating points that are outside the narrower, more tightly restricted specified load voltage tolerance range required by most loads. Therefore, system 100 may be used to regulate the supplied battery voltage substantially within this specified load voltage tolerance range. The voltage of battery 108 may be configured to be above the specified load voltage tolerance range of power distribution bus 104 (e.g., see Region 3 and Region 4 areas shown in the example of FIG. 8 ) under some SOC and battery current conditions and to substantially match the specified load voltage tolerance range of power distribution bus 104 (see Region 2 area shown in the example of FIG. 8 ) under other SOC or battery current conditions.

[0042] The operation of the system 100 depends on the type of VDC converter 170 implemented within the system 100. IN Against V OUT and output current limiting characteristics (see, e.g., FIG. 11 ), and may be configured to be able to handle supplying current to load 105 when load 105 is requesting low current (i.e., less than about 25% of the maximum current that may be required by load 105) and battery 108 is operating at a high state of charge (e.g., an SOC value greater than about 70%), e.g., corresponding to operation of system 100 in Region 4 area as shown in FIG. 8 or FIG. 10 .

[0043] DC-DC converter 170 may be any of the types described herein (e.g., linear regulator, switching buck, switching buck-boost, etc.), including but not limited to those described in connection with Figures 4, 5, and 11. DC-DC converter 170 need not be configured (e.g., sized) to handle the battery's maximum output power as in prior art implementations, but rather, in system 100, it may be configured to be able to handle approximately 25% to 30% of the battery's maximum output power, since the balance of the output power is supplied by an N-FET / resistor pair network, as described further herein. This provides an advantage of system 100 over such prior art implementations that use DC-DC converters, since the relative cost and size of a DC-DC converter are substantially higher than the relative cost and size of a FET / resistor pair network of similar power supply capability.

[0044] FIG. 4 illustrates the input vs. output voltage (V) of a non-limiting example of a switching buck converter suitable for implementation as DC-DC converter 170 in system 100. IN Against V OUT ) characteristics. V IN >V OUT At the set point, the DC-DC converter operates as a normal buck converter, with an output voltage V OUT V OUT However, the input voltage V IN V OUT When it crosses the set point, the output voltage V OUT will increase the input voltage VOUT until it falls below the VOUT set point and reaches some threshold, shown in this example as 11V. IN This is called a "low dropout" characteristic, and is commonly found in linear regulator designs. OUTThe set point, also referred to herein as the battery DC-DC converter set point (see, e.g., FIG. 12 ), may be predetermined to be a voltage level at which the DC-DC converter 170 is configured to begin supplying current to the load 105 after a failure of the PSU 101, as further described herein with respect to FIGS. 12 and 19 .

[0045] FIG. 5 shows the input vs. output voltage (V IN Against V OUT ) characteristic, which is also suitable for implementation as DC-DC converter 170 in system 100, where the "low dropout" characteristic described above is not required and the DC-DC converter can be IN <V OUT When the set point is reached, the buck mode (V IN >V OUT The input voltage V IN Regardless of the output voltage V OUT V OUT Maintain it equal to the set point.

[0046] 11 shows the current limit characteristic of the DC-DC converter implemented in system 100, with the x-axis representing time. All DC-DC converter output currents I below an output current value referred to as the current limit transition point (where the DC-DC converter output voltage changes from a constant voltage to a constant current) are o On the other hand, the DC-DC converter outputs voltage V OUT The DC-DC converter is configured to maintain a constant output current I o (represented by the dashed line in Figure 11) is the current limit transition point (I limit(A) ), the output voltage V OUT will drop slightly, or is said to "droop." This marks the DC-DC converter's transition from "constant voltage" mode to "droop current limit" mode, and the output voltage V OUT I limit(A) and I limit(A)For a narrow range of output current values ​​between + a few percent, V OUT It is allowed to fall below the set point. In other words, it is limit(A) For any current value up to OUT V OUT Maintained at set point. limit(A) When this is reached, the output voltage V OUT begins to droop, and this droop continues to accentuate as the output current continues to rise (I limit(A) Although the current slope at appears flat, it is actually slightly positive.

[0047] During an event such as a hardware failure in the PSU 101 or an AC outage (generally referred to herein as a PSU 101 failure) that operates the system 100 such that the battery 108 discharges onto the power distribution bus 104, the voltage of the battery 108 drops as the discharge current increases (e.g., as shown in FIGS. 8 and 10 ), and at lower voltages, there is a gradual increase in current, as traced by different characteristic curves. This drop in the voltage of the battery 108 as the battery discharge current increases may be caused by the internal resistance or impedance of each battery cell. The amount of voltage drop of the battery 108 depends on the magnitude of the current supplied by the battery 108 to the load 105 and the internal impedance of each cell within the battery 108. The chemical composition of the cells of the battery 108 may be selected for their voltage, current capability, and impedance characteristics such that they can support the full power requirements of the power distribution bus 104 to which they are coupled, while maintaining a voltage drop small enough to keep the power distribution bus 104 within its voltage limits (e.g., substantially within a specified load voltage tolerance) during a discharge event.

[0048] According to an embodiment of the present disclosure, the system 100 detects the current limit transition point (I shown in FIG. 11) of the DC-DC converter 170. limit(A)108) and at a high state of charge of the battery 108, the current may be configured to be supplied to the load 105 by the DC-DC converter 170 alone or in combination with some predetermined number of FET / resistor pairs in the N-FET / resistor pair network depending on the instantaneous operating point of the family of VI curves of the battery 108.

[0049] Embodiments of the present disclosure will now be described with respect to a non-limiting example application and operation of system 100 in which controller 102 is configured to supply power to load 105 within a specified load voltage tolerance. Such specified load voltage tolerance is sometimes referred to herein as an application regulation window, which defines the voltage range that may be required by a load associated with a particular end application. Such specified load voltage tolerance may be greater than or equal to the nominal, or desired, output voltage V o and a + / - percentage range.

[0050] Figure 12 shows the desired output voltage V o12 shows a non-limiting example graphical representation of various set points and thresholds that may be implemented in system 100 based on a load voltage tolerance (e.g., 12V) and a specified load voltage tolerance (e.g., + / - 5%). For purposes of illustrating embodiments of the present disclosure only, reference is made to the non-limiting example VI curve of FIG. 8. The specified load voltage tolerance is shown extending from a lower regulatory limit (12V-5%=11.4V in this example) to an upper regulatory limit (12V+5%=12.6V in this example). According to embodiments of the present disclosure, controller 102 may be configured to maintain the voltage supplied to load 105 between the upper and lower regulatory limits that define the specified load voltage tolerance. FIG. 12 also illustrates that several other thresholds and set points may be configured within the design of system 100 within the upper and lower regulatory limits. There may be a PSU output voltage set point for PSU 101, which may be predetermined during the design of system 100 (e.g., as a function of load dynamics, PSU control loop response, etc.), and in this example is selected to be 12.35V (as shown by solid line 2 in FIG. 12 ). The value of the PSU output voltage set point for PSU 101 may be selected as the normal operating output voltage supplied by PSU 101, and is selected to be within a specified load voltage tolerance. There may be a battery DC-DC converter set point for DC-DC converter 170, which is set lower than the PSU output voltage set point, and in this example is selected to be 12.0V (as shown by dashed line 3 in FIG. 12 ). There may be two control threshold set points: an upper control threshold ("UCT") set between the PSU output voltage set point and the battery DC-DC converter set point (selected at 12.3V in this example), and a lower control threshold ("LCT") set below the battery DC-DC converter set point and above the lower regulatory limit (LCT selected at 11.9V in this example). UCT and LCT values ​​are further described with respect to Figures 14 and 15. The utilization of these thresholds and set points is further described herein.

[0051] The battery DC-DC converter set point is selected to be within a specified load voltage tolerance, lower than the PSU output voltage set point, and higher than the LCT, and may be optimized by analyzing the dynamic characteristics of the system 100. The selection of the upper and lower regulation limits (i.e., the specified load voltage tolerance) may be determined according to the specifications and requirements of the load 105. The value of UCT is determined by the output voltage V below UCT. o , the output voltage V supplied to the load 105 by the battery system 106 may be monitored to detect a possible failure of the PSU 101 or o The output voltage V below the LCT may be selected at any suitable value below the PSU output voltage setpoint to indicate to the battery system 106 that V may increase excessively and potentially outside the specified load voltage tolerance range. o The value of LCT may be selected at any suitable value below the battery DC-DC converter set point so that monitoring the drop in C indicates to the battery system 106 that more current needs to be supplied from the battery 108 through the N-FET / resistor pair network to the load 105. The system 100 designer's selection of UCT and LCT values ​​that fall within a specified load voltage tolerance range depends on the particular characteristics of the battery 108 (e.g., terminal voltage, characteristic curve, etc.), the dynamic characteristics of the load 105 (e.g., dynamic load current magnitude and rise and fall times), and C LOAD This system capacitance C LOAD 160 is the output node V in the system 100 o (e.g., any output capacitor present in PSU 101 that is included to help stabilize the feedback control loop of PSU 101, any output capacitor present at the output of DC-DC converter 170 to improve transient response or help stabilize the control loop of DC-DC converter 170, any capacitance associated with load 105, and any other capacitance added by the designer of battery system 106).

[0052] FIG. 13 shows a simplified block diagram of a system 100, which, as further described herein, provides a voltage at an output node V in accordance with an embodiment of the present disclosure. o is used by the controller 102 to adjust the amount of impedance inserted between the battery 108 and the load 105. The battery system 106 and PSU 101 are connected to the output node V o , and is coupled to the power distribution bus 104 at the output node V o In the power distribution bus 104, a load 105 and a system capacitance C LOAD 160 is also combined.

[0053] According to well-known circuit theory, the sum of any currents at any node in a system must be zero. Therefore, at node V o The total current present in is: i Batt +i PSU -i Capacitance -i Load =0 i Capacitance When solved, we get the following: (i Batt +i PSU )-i Load =i Capacitance Considering the characteristic equation of a capacitor, it is as follows: i Capacitance =C*dV Capacitance / dt In the formula, dV Capacitance / dt=dV o / dt.

[0054] From the above formula, (i Batt +i PSU ) is i Load If it is equal to i Capacitance becomes zero with respect to time, and dV Capacitance We can conclude that / dt also becomes zero. Therefore, the output node V o The voltage at (i Batt +iPSU )>i Load If i Capacitance becomes positive (i.e., the system capacitance C LOAD 160 is charging), dV Capacitance / dt also becomes positive and the voltage at the output node Vo increases with respect to time. Batt +i PSU ) Load If i Capacitance becomes negative (i.e., the system capacitance C LOAD 160 is discharging into the load 105), dV Capacitance / dt also becomes negative, and the output node V o The voltage at decreases with time. These variables, the system capacitance C LOAD Voltages over 160 (i.e., V o ) and system capacitance C LOAD Current in 160 (C*dV Capacitance / dt) represents the set of state variables of the system 100 and is utilized within the embodiments of the present disclosure described herein. Capacitance / dt can be positive or negative and has units of amperes (current), and dV Capacitance Note that dV / dt can be positive or negative and has units of volts / hour. Capacitance / dt and dV o Note also that σ is equal to σ / dt and represents the same state variable.

[0055] FIG. 14 shows the state variables of the system 100 (i.e., V o and dV o 1 shows a block diagram of a non-limiting implementation for a state determination system 141 (see FIG. 1 ) that may be configured to determine a value representing the output voltage V o It receives as input and V o is compared with the UCT and LCT limits (see FIG. 12). The truth table for the operation of threshold detector 1401 is shown in Table 16a of FIG. 16. The output voltage V o ​is at a voltage level above UCT, the Upper Control Threshold Exceeded (“UCTE”) signal is set to logic level 1 and the output voltage V o When V falls below UCT, UCT is reset to logic level 0. o is at a voltage level below LCT, the Lower Control Threshold Exceeded (“LCTE”) signal is set to logic level 1, and the output voltage V o When exceeds LCT, the LCTE signal is reset to logic level 0.

[0056] The differentiator 1402 outputs an output voltage V o as input and dV o Determine the sign of / dt and dV o dV is set to logic level 1 whenever / dt>0 o / dt Positive signal and dV o dV is set to logic level 1 whenever / dt>0 o / dt Negative signal and therefore the state variable dV o The instantaneous sign of UCTE, LCTE, dV is provided to the controller 102. The truth table for the operation of the differentiator 1402 is shown in Table 16b of FIG. o / dt Negative, and dV o / dt Positive signals (also collectively referred to herein as "state determination signals") are provided from state determination system 141 to controller 102 via signal line 180. Note that truth tables 16a and 16b contain entries that are designated as not allowed or not possible. For example, output voltage V o It is not possible for a value to be above the UCT and below the LCT at the same time, and therefore the conditions UTCE=1 and LTCE=1 cannot occur simultaneously.

[0057] Controller 102 is configured to receive state determination signals from state determination system 141 and perform operations according to the truth table set forth in Table 16c of Figure 16, as further described with respect to system and process 1800 of Figure 18. Figure 15 shows a schematic diagram of a non-limiting example of how state determination system 141 may be implemented using operational amplifiers (OP1) and voltage comparators (CMP1-CMP4) to generate the truth table shown in Table 16c of Figure 16, with comparator reference values ​​related to the example provided with respect to Figure 12.

[0058] Considering the non-limiting example of system 100 implemented with battery 108 as described with respect to Figure 8, when operating in the Region 4 area, the inclusion of DC-DC converter 170 provides higher electrical efficiency as well as more precise control over the exact input / output voltage differential over a wider range of currents, down to zero (0) battery discharge current, than was previously available with respect to system 700 of Figure 7. This is evident by inspecting Figure 9. As described herein, for any number N of FET / resistor pairs, the available N 2 Due to the decreasing resistance nature of resistors 710a-710d in system 700, the granularity of the control steps is not constant across the operating range, and it can be seen that while operating in Region 3 area (see FIG. 8), fine control is available (in FIG. 9, 70% of the available control steps are V below 0.5V). BAT -V o Note that the difference is in the range BAT -V o When operating in Region 4, where the difference is in the range of 0.5 V to 3.0 V, only very coarse and imprecise control is available due to the small number of control steps available. Region 4 is an electrically inefficient operating range due to the high V-I losses in the resistive elements in this range. Therefore, Region 4 is an area where the output voltage V can be reduced by incorporating a DC-DC converter 170. oThis is the area where coarse control of output voltage V is provided, and the DC-DC converter is specifically intended to have high efficiency in this area, thereby mitigating such efficiency issues. Thus, system 700 has poor efficiency and control in the Region 4 area, while system 100 mitigates these issues by incorporating DC-DC converter 170, which significantly improves performance in the Region 4 area, while also reducing the output voltage V o Finer control of can be provided by controlling the total impedance of the N-FET / resistor pair network, as described further herein with respect to FIG.

[0059] The choice of using a standard buck DC-DC converter or a buck-boost DC-DC converter may be determined by the requirements of the load 105 powered by the system 100, as well as the VI curve for the particular chemistry and configuration of the battery 108. As described herein with respect to FIG. 7, the system 700 can only supply current to the load 705 at voltages below the battery voltage. As a result, there is often unavailable energy in the battery 708. With reference to FIG. 8, the Region 1 area identifies battery operating points that are below the specified load voltage tolerance for the load. Whenever a battery operating point falls within the Region 1 area of ​​the family of VI curves, battery energy is unavailable. Therefore, the resulting portion of the VI curve that falls within this Region 1 area is very small and exists only at very low states of charge where the SOC is near zero. For many end-user applications, this unavailable Region 1 energy can simply be ignored. However, compare the VI curves shown in FIG. 8 with the operation of different battery configurations as shown in FIG. 10, which represents the VI curves for a four-series cell configuration of iron phosphate battery cells operating at currents between 1 A and 60 A. It can be seen that the Region 4 area of ​​operation for the iron phosphate battery system of FIG. 10 is significantly smaller in area than the nickel manganese cobalt system of FIG. 8. This may be suitable for a 12V system. Note, however, that the area of ​​the curve present in the Region 1 area for the iron phosphate battery system of FIG. 10 is significantly larger than that for the nickel manganese cobalt system of FIG. 8 (e.g., up to about 40% SOC when operating at a maximum load of 60 A). This represents a significant amount of unusable energy contained in the Region 1 area, as discussed above, which may be unacceptable for certain applications desired to be powered by such a battery system.A potential solution is to replace battery system 706 of FIG. 7 with battery system 106 of FIG. 1 that implements a DC-DC converter design (e.g., a buck-boost DC-DC converter) with appropriate maximum power and current limit settings for DC-DC converter 170, because this type of converter can boost a battery voltage that is lower than the voltage within the specified load voltage tolerance range to an output voltage that fits the specified load voltage tolerance. Note that care may be needed when using a buck-boost converter for DC-DC converter 170 to prevent power cycling from the output to the battery (input) when DC-DC converter 170 is boosting an output voltage that exceeds the voltage supplied by battery 108. To prevent this, the connection point of the output of DC-DC converter 170 may be moved to the drain side of transistor 111 (compared to FET / resistor pairs 110b-110d and 150b-150d, which are coupled to the source side of transistor 111). When operating in boost mode, transistor 111 is switched off, thus blocking any power circulation from the output of DC-DC converter 170 to battery 108. A consequence of operating DC-DC converter 170 in boost mode is that 100% of the output power supplied while battery 108 is discharging in Region 4 should be supplied through DC-DC converter 170, not through the N-FET / resistor pair network. This means that operation of system 100 in Region 4 exceeds the power limit and current limit transition points (I limit(A) ) or less. However, in applications where the system 100 is utilized as a computer server, it is not uncommon to specifically allow this "power-down" operation from the battery 108 at low SOC.

[0060] FIG. 17 shows some non-limiting examples of FET / resistor activation / deactivation sequences that may be implemented within controller 102 depending on particular battery and load characteristics and requirements. Table 17a represents a binary counting sequence similar to that described with respect to FIG. 9 that may be implemented within controller 102. FETs 110b, 110c, and 110d may be switched on in a binary count-up sequence, with FET 110b representing the least significant bit and FET 110d representing the most significant bit, with each subsequent binary digit representing a decreasing total impedance of the N-FET / resistor pair network. Thus, counting up one binary digit at a time will decrease the total impedance of the N-FET / resistor pair network, and counting down one digit at a time will increase the total impedance of the N-FET / resistor pair network. Table 17b represents a sequential sequence in which the FETs may be switched on and off, rather than in a binary counting mode, so that first FET 110b is switched on, then FET 110c is switched on (without first switching FET 110b off), and finally FET 110d is switched on to decrease the total impedance of the N-FET / resistor pair network. Similarly, to increase the impedance of the N-FET / resistor pair network, controller 102 may be configured to switch off the FET in the most significant bit position, then the FET in the next most significant bit position, and so on, until all FETs are switched off. This sequential sequence results in fewer discrete impedance steps, but when starting from any given impedance value, the minimum or maximum impedance value is reached more quickly.

[0061] According to an embodiment of the present disclosure, the binary count sequence represented in Table 17a may be implemented in the controller 102 when the battery 108 is comprised of NMC battery cells such as those represented in FIG. 8, where only about 20% of the area traced by the minimum and maximum current VI curves is within the Region 2 area, with most of the area outside the Region 2 area located in Regions 3 and 4 above the Region 2 area. According to an embodiment of the present disclosure, the sequential sequence in Table 17b may be implemented in the controller 102 when the battery 108 is comprised of iron phosphate battery cells such as those represented in FIG. 10, where the area traced by the minimum and maximum current VI curves is about 60% within the Region 2 area, with only about 30% in Regions 3 and 4 above the Region 2 area.

[0062] An alternative binary / sequential or "hybrid" counting approach is shown in Table 17c, where the binary counting sequence and the sequential sequence are combined, with FETs 110b and 110c operating in binary sequence and FET 110d being added in sequential sequence after FETs 110b and 110c reach their maximum binary values.

[0063] Embodiments of the present disclosure are further illustrated by the following examples, which are set forth to illustrate the subject matter of the present disclosure and are not to be construed as limiting.

[0064] A non-limiting example implementation of system 100 is now described. In this 12V example (V o = 12V), the upper regulation limit is 12.6V and the lower regulation limit is 11.4V, defining a specified load voltage tolerance range. The exemplary battery 108 is based on a four-series cell iron phosphate battery shown in FIG. 10, with a maximum load current of 60 amps and a minimum load current of 1 amp. The DC-DC converter 170 is configured as a suitable buck DC-DC converter (with characteristics as shown in FIG. 4) and has a current limit transition point I as shown in FIG. limit(A)is selected to be 15 amps, or 25% of the maximum current of the load 105. As shown in FIG. 12, the battery DC-DC converter set point is set to 12.0 V, the PSU output voltage set point is set to 12.35 V, the UCT is set to 12.3 V, and the LCT is set to 11.9 V. The controller 102 is configured to sequentially step up and step down the impedance of the N-FET / resistor pair network as shown in Table 17b of FIG. 17. Resistor 150b may be configured with the highest resistance value of all resistors 150b-150d. According to embodiments of the present disclosure, this resistance value of resistor 150b may be determined by the maximum value of the battery 180 voltage traced by the allowable VI curves of the minimum and maximum load current design points. In this example, this resistance value is identified by point A (13.4 V) shown in FIG. 10 and can be subtracted from the value of the battery DC-DC converter set point, which is 12.0 V, represented by point B shown in FIG. 10. The result is then used to determine the current limit transition point (I limit(A) , i.e., 15 A) to provide the desired resistance value for resistor 150b. Using these values, the result is: Resistance value of element 150b = (13.4V - 12.0V) / 15A Resistance of element 150b = 93 milliohms

[0065] Resistor 150c may be configured to have the next lowest resistance in the sequence, and may be configured to have a resistance equal to or slightly less than 1 / 10 of the resistance of resistor 150b (e.g., 9 milliohms). Resistor 150d may be configured to have a resistance equal to or slightly less than 1 / 10 of the resistance of resistor 150c (e.g., 0.9 milliohms). As a result, the total resistance of the N-FET / resistor pair network when all FETs are switched on is 0.8 milliohms. This provides a total voltage drop of 48 millivolts across the N-FET / resistor pair network at a maximum load of 60 A.

[0066] As shown in Figure 10, the iron phosphate cell characteristic VI curve has a current limit transition point I of 15A. limit(A) Since the VI curves lie largely within the Region 2 operating range of current values ​​above 100 and below the maximum defined load current of 60 A, system 100 may be configured with relatively few parallel FET / resistor pairs, a sequential FET activation sequence, and a relatively aggressive reduction in resistance value for each sequential pair, as described above. If system 100 is configured with a battery 108 composed of NMC cells such as those represented by FIG. 8, since a relatively larger portion of the VI curve lies beyond the Region 2 operating range (i.e., the specified load voltage tolerance), as shown in FIG. 8, system 100 may be configured with a larger number of parallel FET / resistor pairs, a binary count sequence, and a more gradual reduction in resistance value for each sequential pair.

[0067] 1, when operating properly (i.e., when AC input power is present and within specified values ​​and / or there are no hardware faults within PSU 101), PSU 101 is designed to have sufficient output current capacity to supply full load current to load 105. If there is a failure of the AC input to PSU 101 or if there is a hardware fault within PSU 101, PSU 101 will stop supplying current to load 105 and battery system 106 will discharge energy from battery 108 to supply current to load 105.

[0068] According to an embodiment of the present disclosure, the battery system 106 includes an output node V oThe controller 102 is configured to source current from the battery 108 between current paths provided by the DC-DC converter 170 in combination with the N-FET / resistor pair network so as to maintain the voltage at load 105 within a specified load voltage tolerance range bounded by upper and lower regulatory limits as shown in FIG. 12 . Depending on the current required to meet the demand of the load 105, the current can flow through any combination of elements of the DC-DC converter 170 and the N-FET / resistor pair network. The controller 102 may be configured to control the balancing of the output current from the discharging battery 108, as between the DC-DC converter 170 and the N-FET / resistor pair network, such that the voltage delivered to the load 105 is regulated between the upper and lower regulatory limits (i.e., within the specified load voltage tolerance range). The following description represents example transitions that may occur as part of the current balancing and voltage regulation process.

[0069] A non-limiting exemplary process for supplying current from the battery 108 to the load 105 by the battery system 106 according to embodiments of the present disclosure will now be described with reference to the system and process 1800 of FIG. 18, which may be implemented for operation within the controller 102. In this example, the DC-DC converter 170 operates according to FIG. 4, the state determination system 141 is configured to operate according to the truth tables set forth in Tables 16a and 16b of FIG. 16, and the controller 102 is configured to operate according to the truth tables set forth in Table 16c of FIG. 16 and the FET sequence set forth in Table 17b of FIG. 17. The signals generated by the state determination system 141 according to the truth tables set forth in Tables 16a and 16b are received by the controller 102 via signal line 180.

[0070] 19 and 20 show the output voltage V o 19 shows a time domain analysis illustrating an exemplary operation of the system 100 of providing an output voltage to the controller 102 and the corresponding transitions of the signals provided from the state determination system 141 to the controller 102.10 20 shows an exemplary time domain analysis during the time interval t 10 ~t 21 19 and 20 illustrate an exemplary time domain analysis between 1800 and 2000. An exemplary operation of system and process 1800 will be described with reference to the time instances in Figures 19 and 20 to describe what happens at the moment of each time instance and during the time intervals between each time instance. Note that Figures 19 and 20 are not drawn to scale, and some of the time intervals shown may be measured in microseconds, while other time intervals may be measured in seconds or minutes.

[0071] In process block 1801, the PSU 101 is operating properly and may have been on for some previous period of time. In this example, the output voltage set point of the PSU 101 is 12.35V and supplies full load current to the load 105. Also, for some previous period of time, the components of the battery system 106 are initialized (represented by the dashed lines around process blocks 1802-1805). The controller 102 may be initialized in process block 1802 (e.g., upon receiving an AC_OK signal). In process block 1803, the controller 102 switches off the DC-DC converter 170 and all FETs 110b-110d via signal lines 171 and 121b-121d, respectively. In process block 1804, the controller 102 switches off the DC-DC converter 170 and all FETs 110b-110d via signal lines 171 and 121b-121d, respectively. o that the voltage present at the output voltage V is equal to the PSU output voltage set point (e.g., by a voltage sensor implemented within the state determination system 141 in a manner similar to the battery voltage sensor 142). o is provided to the controller 102 via signal line 180), and the AC_OK signal on signal line 112 is present (e.g., a logic level 1 is received).

[0072] In process block 1805, DC-DC converter 170 is turned on via control signal 171, causing DC-DC converter 170 to regulate its output to its battery DC-DC converter set point (12.0 V in this example). However, the output node V o 19 and 20. Because the voltage at load 105 is held at 12.35V by PSU 101, no current is drawn from DC-DC converter 170 and all current to load 105 is supplied by PSU 101. At some point after DC-DC converter 170 has stabilized its output, system and process 1800 proceeds to process block 1806 and waits for an interrupt generated by a rising edge transition of either the UCTE or LCTE signal received by controller 102 from state determination system 141 via signal line 180. This wait condition represents a steady state condition and, in this example, is represented as the system state shown at time t0 in FIG. 19. As will be described further, controller 102 may be configured to generate an interrupt upon receiving a rising edge (transition from logic level 0 to logic level 1) of either the UCTE signal (e.g., see 1901 in FIG. 19) or the LCTE signal (e.g., see 1902 in FIGS. 19 and 20). This interrupt causes the system and process 1800 to transition from process block 1806 to process block 1807, where the state determination signal from state determination system 141 is evaluated to determine whether any FET control action is required to adjust the impedance of the N-FET / resistor pair network either up or down, as further described herein.

[0073] This steady state condition continues during time interval t0-t1 in process block 1806. Controller 102 keeps FETs 110b-110d switched off. All load currents are directed to the output node V at a point above the battery DC-DC converter set point of DC-DC converter 170. o The output node V is continuously supplied by the PSU 101, which regulates the voltage supplied to the oSince the voltage supplied to is higher than UCT, the UCTE signal is at logic level 1 (see Table 16a in Figure 16), and the voltage V o does not change, the state determination system 141 determines whether dV o / dt Positive and dV o The / dt Negative signal is maintained at a logic level 0 value (see Table 16b of FIG. 16). At process block 1806, no interrupt is generated because the controller 102 is still waiting for the rising edge of either the UCTE or LCTE signal.

[0074] In this example, consider that at some subsequent time period, either an AC line fault (signaled to the controller 102 via the AC_OK signal 112) or a hardware failure of the PSU 101 occurs. This is shown in FIG. 19 as time t1. Eventually, the output voltage of the PSU 101 begins to drop from 12.35V. The voltage V o As the falls, C LOAD 160 then discharges and supplies part of the current to the load 105, and the PSU 101 supplies the rest of the current. o begins to drop, this is sensed by the state determination system 141, which changes dV from logic level 0 to logic level 1. o / dt Negative signal transition (see Table 16b in FIG. 16). Following time t1, the voltage V o decreases sufficiently to fall below UCT, and the state determination system 141 transitions the UCTE signal from logic level 1 to logic level 0. Process block 1806 is still waiting for an interrupt caused by either the UCTE or LCTE signal transitioning from logic level 0 to logic level 1. As more energy is transferred to C LOAD 160 to the load 105, so that the voltage V o The decrease continues during the time interval t1 to t2.

[0075] At time t2, the voltage V oDuring time interval t2-t3, current is supplied from battery 108 through DC-DC converter 170 as the current supplied by DC-DC converter 170 transitions from zero current at time t2 to a current limit transition point I at time t3. limit(A) As the voltage V o The output voltage V during the time interval t2 to t3 is kept constant. o In response to this unchanged value of , the dV received by the controller 102 from the state determination system 141 o The / dt Negative signal returns to a logic 0 value (see Table 16b in Figure 16).

[0076] At time t3, the current limit transition point I limit(A) When C is reached, the DC-DC converter 170 enters its voltage "droop" mode (see FIG. 11) and LOAD As the load 160 begins to supply energy to the load 105 again, the output voltage V o begins to decrease, which can be seen during the time interval t3-t4 in Figure 19. dV supplied to the controller 102 from the state determination system 141 o The / dt Negative signal transitions to logic level 1 during this time interval. However, no interrupt is yet generated at process block 1806. Therefore, controller 102 keeps FETs 110b-110d switched off (corresponding to impedance sequence 0 set forth in Table 17b of FIG. 17) according to the truth table of Table 16c of FIG. 16.

[0077] At time t4, the output voltage V ofalls below LCT, causing the state determination system 141 to transition the LCTE signal from logic level 0 to logic level 1 (shown as 1902 in FIG. 19 at time t4), and an interrupt is generated by process block 1806. The system and process 1800 proceed to process block 1807, where the level of the state determination signal received from the state determination system 141 is read by the controller 102. According to the truth tables in Tables 16a and 16b of FIG. 16, the signal levels are UCTE=0, LCTE=1, dV o / dt Positive=0, and dV o 17b, where FET 110b is the impedance sequence of the N-FET / resistor pair network. In this example, at time t4, the level of the state-determining signal is determined to correspond to condition 3c in Table 16c, so the system and process 1800 proceeds to process block 1810, where the controller 102 determines that the impedance of the N-FET / resistor pair network needs to decrease. Because the N-FET / resistor pair network is currently in impedance sequence 0 (i.e., all FETs are switched off), the next step in Table 17b of FIG. 17b, which represents a decreased impedance, is identified as impedance sequence 1. In process block 1810, the controller 102 switches on FET 110b via control signal 121b to configure the N-FET / resistor pair network into the impedance sequence 1 configuration.

[0078] The time interval t4-t5 represents the potential propagation delay along control line 121b for the switch ON signal sent to FET 110b. Such propagation delay may consist of the processing time of process block 1806 in processing the interrupt at time t4, the execution time of process blocks 1807, 1808, and 1810, the signal propagation time required for the ON signal to propagate from controller 102 to FET 110b, and the switching time of FET 110b. While this propagation time may be relatively short (e.g., on the order of microseconds), there may be a measurable time delay between time t4, when the need for an impedance change is first recognized, and time t5, when the impedance state of the N-FET / resistor pair network actually changes and the system state variable responds. To prevent overcompensation of the N-FET / resistor pair network, process block 1811 may optionally be included to insert a time delay (e.g., equal to the longest possible value of the propagation delay) before the system and process 1800 return to process block 1807 and again reset the state of the state-determining signal. Time t5 represents the end of the propagation delay period, at which point the system state changes to reflect the control action taken at time t4 (i.e., voltage V o Therefore, after time t5, the system and process 1800 return to process block 1807.

[0079] At time t5, the optional propagation delay of process block 1811 is complete and FET 110b is now switched on. The current generated by battery 108, which previously flowed solely through DC-DC converter 170 to load 105, now has a second path to load 105, namely through FET 110b and resistor 150b. As a result, the current in DC-DC converter 170 is reduced as current is diverted from DC-DC converter 170 and the output voltage of DC-DC converter 170, and therefore the output voltage V o falls below the current limit transition point as it ramps back up towards its 12.0V set point.

[0080] Following time t5, in process block 1807, the controller 102 again reads the state determination signal and passes control to process block 1808. As illustrated by the example shown in FIG. 19, during the time interval t5-t6, the voltage V o is below LCT, but the voltage V o is rising, and the state determination signal received from state determination system 141 causes controller 102 to determine in process block 1808 that the N-FET / resistor pair network is operating in accordance with condition 3b (see Table 16c of FIG. 16 ), which corresponds to the “neither” path out of process block 1808. In process block 1812, signals UCTE and LCTE are each evaluated by controller 102 for a logic level 1. Because the LCTE signal remains at a logic level 1, system and process 1800 determine that the rising output voltage V o Continually loop from process block 1812 to process block 1807 to process block 1808 to process block 1812 back to process block 1812 until exceeds the LCT threshold (shown to occur at time t6), resulting in the LCTE signal transitioning from a logic level 1 to a logic level 0.

[0081] At time t6, the output current from the DC-DC converter 170 continues to increase, so that the output voltage V o continues to rise. When process block 1812 is first invoked after the LCTE signal transitions to a logic level 0, the system and process 1800 exit process block 1812 and return to process block 1806 to re-engage the wait for an interrupt triggered by the rising edge of either the UCTE or LCTE signal.

[0082] Referring again to FIG. 19, during a first portion of the time interval t6 to t7, the output voltage V ocontinues to increase towards the battery DC-DC converter set point of 12.0 V as the output current ramps up within DC-DC converter 170. Eventually, a current limit transition point is reached, shown approximately halfway between times t6 and t7. At this point, DC-DC converter 170 once again enters "droop" mode, and the output voltage V o begins to decrease (see Figure 11). o The reversal of / dt occurs midway between times t6 and t7. o / dt Positive and dV o This is shown by the change in the signal level of / dt Negative. During the time interval t6 to t7, there is no rising edge in either the UCTE or LCTE signals, so no interrupt is generated and the system and process 1800 remain in process block 1806.

[0083] At time t7, the output voltage V o falls above LCT, a rising edge is generated on the LCTE signal (shown as 1902 in FIG. 19 at time t7), and an interrupt is generated, and the system and process 1800 proceeds from process block 1806 to process block 1807, where the controller 102 reads the state determination signal received from the state determination system 141. The system and process 1800 then proceeds to process block 1808, where the controller 102 evaluates the state determination signal and determines that UCTE=0, LCTE=1, dV o / dt Positive=0, and dV o16c. This shows that the combination of / dt Negative=1 corresponds to condition 3c in Table 16c. As a result, system and process 1800 then proceed to process block 1810, where it is determined that because the N-FET / resistor pair network is configured in impedance sequence 1 according to the truth table in Table 17b, the next step in the impedance sequence corresponding to condition 3c is impedance sequence 2. To accomplish this, controller 102 keeps FET 110b switched on and switches FET 110c on via control signal 121c, then exits process block 1810 and proceeds to process block 1811. During time interval t7-t8, system and process 1800 may remain in process block 1811, waiting for FET 110c to switch on.

[0084] At time t8, when FET 110c is switched on, the current generated by battery 108 now has a conductive path through DC-DC converter 170, FET 110b / resistor 150b pair, and FET 110c / resistor 150c pair. The addition of a conductive path through FET 110c / resistor 150c pair, and the much lower impedance of this new conductive path, diverts more current away from DC-DC converter 170, reducing that current to I limit(A) and therefore the output voltage V o begins to increase again. The system and process 1800 then proceeds to process block 1807, whereby the controller 102 reads the state determination signal. In process block 1808, the controller 102 sets UCTE=0, LCTE=1, dV o / dt Positive=1, dV o16c. The system and process 1800 then proceeds to process block 1812, where the voltage V o Since is less than LCT, LCTE=1, and the system and process 1800 loops from process block 1812 to process block 1807 to process block 1808 and then to process block 1812 to increase the voltage V o It remains in this loop until increases above the LCT.

[0085] Referring to FIG. 19, at time t9, the output voltage V o indicates that rises and exceeds LCT, causing the LCTE signal to be reset to logic level 0 (see Table 16a). Following the transition of the LCTE signal to logic level 0, the system and process 1800 proceed to process block 1806 on the next pass through process block 1812. The system and process 1800 remain in process block 1806 until the next interrupt caused by the rising edge of either the UCTE signal or the LCTE signal.

[0086] As shown in Figure 19, t8 to t 10 The time interval including represents a steady-state condition where the current to the load 105 is held at a constant level and the battery 108 is slowly discharging. The controller 102 maintains the N-FET / resistor pair network in the Impedance Condition 2 configuration.

[0087] In this example, time t 10 is dV o 1 illustrates the occurrence of a discontinuity in the trajectory of the output voltage Vo, where V / dt increases abruptly from a relatively small positive value to a relatively large positive value. A condition that can cause this type of discontinuity is a sudden decrease in current to the load 105, resulting in a large decrease in C LOAD Positive current and dV to 160 o resulting in a corresponding change (increase) in / dt.

[0088] Referring to FIG. 20, the time interval t 10 ~t 11 During this time, the output voltage V o The value of has increased and the system and process 1800 is waiting for an interrupt at process block 1806.

[0089] time t 11 is the output voltage V o rises above UCT, causing a rising edge on the UCTE signal (time t 11 1901) illustrates a situation that generates an interrupt in process block 1806. The system and process 1800 then proceeds to process block 1807 where a state determination signal received from the state determination system 141 is received by the controller 102. In process block 1808, the controller 102 converts the received signal generated by the state determination system 141 (see Tables 16a and 16b of FIG. 16) into a state determination signal with UCTE=1, LCTE=0, dV o / dt Positive=1, and dV oFET 110b is switched on, FET 110c is switched on, and FET 110d is switched off), controller 102 determines that the impedance of the N-FET / resistor pair network needs to be increased. Since the N-FET / resistor pair network is currently configured in impedance sequence 2 (i.e., FET 110b is switched on, FET 110c is switched on, and FET 110d is switched off), controller 102 determines from Table 17b that increasing the impedance will result in the N-FET / resistor pair network being configured in impedance sequence 1. Therefore, controller 102 switches FET 110c off via control line 121c to configure the N-FET / resistor pair network into the impedance sequence 1 configuration. System and process 1800 then proceeds to process block 1811 and enters an optional wait state equal to the maximum propagation delay, as previously described herein.

[0090] Referring again to FIG. 20, at time t 12 is dV o Change the sign of / dt and change the sign of dV o / dt Positive signal and dV o 18 illustrates the effect of increasing impedance on inverting the logic level of the / dt Negative signal. System and process 1800 proceeds to process block 1807 where the level of the state determination signal received from state determination system 141 is received and read by controller 102. At process block 1808, controller 102 converts the received signal, which in this situation is generated by state determination system 141 (see Tables 16a and 16b of FIG. 16), into UCTE=1, LCTE=0, dV o / dt Positive=0, and dV o / dt Negative=1. According to Table 16c, the controller 102 determines that the signal combination is condition 2c. Process block 1808 completes the "neither" path and the system and process 1800 proceeds to process block 1812. Because the UCTE signal remains at logic level 1, the system and process 1800 then evaluates the output voltage V o is UCT (time t in Figure 20). 13 The process loops through process blocks 1807, 1808 and back to process block 1812 until the UCTE signal falls below logic level 1 (denoted by 1807), causing the UCTE signal to transition from logic level 1 to logic level 0 (see Table 16a). The next time process block 1812 is processed, neither the UCTE nor the LCTE signal will be at logic level 1, so the system and process 1800 exit process block 1812 and proceed to process block 1806 where it again waits for an interrupt.

[0091] time t 14 is the output voltage V o falls below LCT, resulting in the LCTE signal changing from logic level 0 to logic level 1 (time t in Figure 20). 14 16A and 16B, the controller 102 transitions to a state determination signal (shown as 1902) which illustrates a situation where an interrupt is generated at process block 1806. The system and process 1800 then proceeds to process block 1807 where the levels of the state determination signals received from the state determination system 141 are received and read by the controller 102. At process block 1808, the controller 102 reads the received signals generated by the state determination system 141 (see Tables 16a and 16b of FIG. 16A) as follows: UCTE=0, LCTE=1, dV o / dt Positive=0, and dV o / dt Negative=1. According to Table 16c, controller 102 determines that the signal combination is condition 3c. The system and process 1800 then proceed to process block 1810, where it is determined that the next step in the impedance sequence corresponding to condition 3c is impedance sequence 2 because the N-FET / resistor pair network is configured in impedance sequence 1 according to the truth table in Table 17b. To accomplish this, controller 102 keeps FET 110b switched on and switches FET 110c on via control signal 121c, then exits process block 1810 and proceeds to process block 1811. In process block 1811, an optional appropriate propagation delay time may occur.

[0092] In process block 1807, the controller 102 15 In process block 1808, the controller 102 evaluates the received signal generated by the state determination system 141 (see Tables 16a and 16b of FIG. 16) in this situation and determines whether the state determination signal is generated at time t 14 In UCTE=0, LCTE=1, dV o / dt Positive=0, and dV o16c, controller 102 determines that the signal combination remains in condition 3c. System and process 1800 then proceeds to process block 1810, where it is determined that because the N-FET / resistor pair network is configured in impedance sequence 2, the next step in the impedance sequence corresponding to condition 3c is impedance sequence 3. To accomplish this, controller 102 keeps FETs 110b and 110c switched on, and controller 102 switches FET 110d on via control signal 121d. According to this non-limiting example, the N-FET / resistor pair network is now in the lowest impedance state. System and process 1800 then exits process block 1810 and proceeds to process block 1811, where it optionally determines that the N-FET / resistor pair network is now in the lowest impedance state at time t 16 The synchronous signal may wait one or more propagation delay time intervals until the synchronous signal is received.

[0093] time t 16 After this, the system and process 1800 proceeds from process block 1811 to process block 1807 where the state determination signal generated by the state determination system 141 is received by the controller 102. In process block 1808, the controller 102 evaluates the received signal and sets the state determination signal to UCTE=0, LCTE=1, dV o / dt Positive=1, dV o / dt Negative=0. According to Table 16c, the controller 102 determines that the signal combination is condition 3b. The system and process 1800 takes no impedance action and exits process block 1808 via the path marked "neither" to process block 1812, where the LCTE signal is evaluated and determined to be at logic level 1. The system and process 1800 then determines that at time t 17 As shown in the figure, the output voltage V oThe process 1800 continuously loops through process blocks 1807, 1808, and back to process block 1812 until the LCTE signal exceeds the LCT. At this point, the LCTE and UCTE signals are both at logic level 0, and the next pass through process block 1812 will cause the system and process 1800 to exit to process block 1806 where it will wait for the next interrupt.

[0094] time t 18 is the dV that can result from events such as an increase in load current o / dt changes. Output voltage V o Since time t is within the range established by the UCT and LCT, no interrupt is generated at process block 1806 and the system and process 1800 remain at process block 1806. 19 represents another event that can occur during operation of the system 100 when the current delivered to the load 105 decreases. o is still within the range established by the UCT and LCT, so no interrupt is generated at process block 1806. The system and process 1800 remain waiting for an interrupt at process block 1806.

[0095] time t 20 is the output voltage V o rises above UCT, causing a rising edge on the UCTE signal (time t 20 1901), resulting in the generation of an interrupt at process block 1806. The system and process 1800 then proceeds to process block 1807, where the level of the state determination signal received from the state determination system 141 is received and read by the controller 102. At process block 1808, the controller 102 sets the received signal generated by the state determination system 141 (see Tables 16a and 16b of FIG. 16) to UCTE=1, LCTE=0, dV o / dt Positive=1, and dV o17b of FIG. 17 representing an increased impedance is determined to be Impedance Sequence 2. As a result, controller 102 switches off FET 110d via control line 121d to configure the N-FET / resistor pair network according to Impedance Sequence 2. System and process 1800 then proceed to process block 1811, where the controller 102 determines that the impedance of the N-FET / resistor pair network needs to be increased, and the N-FET / resistor pair network is currently configured according to Impedance Sequence 3. 20 ~t 21 Optional wait state is entered, which is equal to (denoted as

[0096] The battery system 106 continues to generate an output voltage V according to the system and process 1800 until the battery 108 is depleted of energy and the battery system 106 shuts off, or until AC power is restored and the PSU 101 returns to operation. o10 ) while continuing to discharge the battery 108. According to an embodiment of the present disclosure, in such a situation, the controller 102 may be configured to incrementally increase the impedance of the N-FET / resistor pair network (e.g., stepwise according to Table 17b of FIG. 17 ) until all FETs are switched off. At this point, the DC-DC converter 170 may be switched off. Additionally, at some point, charge may be restored to the battery 108 via the charger 103. In a situation where the battery 108 is depleted of energy (such as when the terminal voltage of the battery 108, as sensed via the voltage sensor 147, drops to a level equal to the voltage at the boundary between Region 2 and Region 1 of FIG. 10 ), the controller 102 may be configured to turn off the battery system, for example, by switching off all of the FETs in the N-FET / resistor pair network and switching off the DC-DC converter 170.

[0097] As described with respect to the exemplary operation of FIG. 18 , the N-FET / resistor pair network can be operated according to several terminal configurations. In one configuration, all FET / resistor pairs in the N-FET / resistor pair network are switched off, resulting in no current flowing through the N-FET / resistor pair network. For example, this may occur during the initial state of system 100, when no current is being supplied from battery 108 to load 105 through the N-FET / resistor pair network. In this case, current from battery 108 is supplied only through DC-DC converter 170, which prevents the current supplied to load 105 from exceeding the current limit transition point I limit(A) until it reaches the output voltage V oto be within the range between the UCT and LCT. When the output voltage of DC-DC converter 170 falls below the LCT, controller 102 reduces the impedance of the N-FET / resistor pair network, and all of the FET / resistor pairs in the N-FET / resistor pair network are switched off so that the N-FET / resistor pair network has a full range of impedance reduction actions available to controller 102 (see, e.g., Tables 17a, 17b, and 17c of FIG. 17 ). When controller 102 needs to increase the impedance of the N-FET / resistor pair network (e.g., in response to a decrease in required load current), and UCTE is triggered enough times to switch off all of the FET / resistor pairs, DC-DC converter 170 will be able to reduce the output voltage V without any additional conduction path provided for current through the N-FET / resistor pair network. o The remaining current to the load 105 can be supplied by the DC-DC converter 170 since the current to the load 105 has dropped sufficiently so that the load 105 can be regulated again.

[0098] In another terminal configuration, a situation may arise where all of the FET / resistor pairs in the N-FET / resistor pair network are switched on and the controller is unable to further reduce the impedance of the N-FET / resistor pair network (e.g., according to any one of the impedance sequences set forth in Tables 17a, 17b, and 17c of FIG. 17). For example, this may occur under conditions of high load current and / or low battery state of charge, such as when the operating point of the battery 108 on the VI curve is at the lower end of Region 2 (see, e.g., FIGS. 8 and 10). In such a situation, using a linear regulator or buck converter as DC-DC converter 170 and discharging battery 108, when its operating point approaches the boundary between the Region 2 and Region 1 areas, controller 102 may need to reduce the current supplied to load 105 or reduce the output voltage V oIt may be necessary to stop operation of the system 100 to prevent the current limit from dropping below a lower regulatory limit (see, for example, FIG. 12 ). If a buck-boost converter is used as the DC-DC converter 170, there may be an additional option if the current supplied to the load 105 is reduced to a value below the current limit transition point. If this occurs, operation of the system 100 can continue discharging the battery 108 via the DC-DC converter 170 until the operating point of the battery 108 reaches the bottom boundary of the Region 1 area, which represents the minimum allowable battery voltage. Another situation in which this may occur is a short circuit in the load 105 or other overload that exceeds the design point of the system 100, and therefore the battery operating point is at a current level outside the allowable characteristic VI curve of the battery 108. If this situation occurs, the system 100 may be configured to protect itself, for example, by terminating all current paths between the battery 108 and the load 105 (e.g., by switching off all FET / resistor pairs in the N-FET / resistor pair network). The DC-DC converter 170 may also be switched off via its control line 171, although this is not strictly necessary as the DC-DC converter 170 may be protected by its current limiting characteristics.

[0099] As a result of the foregoing, it can be readily appreciated that system 100 can be configured to maintain the output voltage provided from battery 108 to load 105 within a desired voltage range when battery 108 is discharging, including maintaining such output voltage within a required operating voltage range (e.g., substantially within a specified load voltage tolerance), such that system 100 can be implemented as a voltage regulator (e.g., for use as a battery backup unit or DC UPS).

[0100] Although embodiments of the present disclosure are disclosed herein as utilizing a battery as a power source (e.g., for battery backup), embodiments of the present disclosure may be configured to utilize any suitable type of power source. Correspondingly, system 100 is suitable for use with any type of power source (instead of a battery) that has an unregulated output voltage (e.g., the output voltage of such a power source varies outside of a specified load voltage tolerance for a particular power distribution bus and its associated load).

[0101] As will be appreciated by those skilled in the art, aspects of the present disclosure (e.g., system and process 1800) may be embodied as a system, method, and / or program product. Accordingly, aspects of the present disclosure (e.g., system and process 1800), as well as the threshold detection and differentiator blocks illustrated in FIG. 14, may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a “circuit,” “circuitry,” “module,” or “system.” Furthermore, aspects of the present disclosure may take the form of a program product embodied in one or more computer-readable storage media having computer-readable program code embodied thereon (although any combination of one or more computer-readable media may be utilized; the computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium).

[0102] It should also be noted that each block of the circuit block diagrams and / or functions illustrated in the diagrams of Figures 1 and 18, and combinations of the block diagrams and / or functions illustrated in the diagrams of Figures 14 and 15, can be implemented by a dedicated hardware-based system that performs the specified functions or acts, or a combination of dedicated hardware and computer instructions. For example, a module (e.g., controller 102) can be implemented as a hardware circuit including custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, controllers, or other discrete components. A module (e.g., controller 102) can also be implemented in a programmable hardware device such as a field programmable gate array, programmable array logic, programmable logic device, or the like.

[0103] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the presently disclosed subject matter belongs. As used in this application, including the claims, the terms "a" and "an" mean "one or more."

[0104] As used herein, the term "about" is used to provide flexibility to the endpoints of numerical ranges by providing that a given value may be "just above" or "just below" the endpoint.

[0105] As used herein, the term "substantially" refers to the complete or nearly complete extent or degree of an action, property, quality, state, structure, item, or result. For example, a "substantially" enclosed object means that the object is completely enclosed or nearly completely enclosed. The exact acceptable degree of deviation from absolute perfection may, in some cases, depend on the particular situation. Generally speaking, however, the proximity of perfection will result in an overall result similar to that which would result if absolute and complete perfection were achieved. The use of "substantially" is equally applicable when used in a negative sense to refer to the complete or nearly complete absence of an action, property, quality, state, structure, item, or result.

[0106] As used herein, the term "and / or" and the " / " character between two words, when used in the context of a list of entities, refer to the entities occurring singly or in combination. Thus, for example, the phrase "A, B, C, and / or D" includes A, B, C, and D individually, but also any and all combinations and subcombinations of A, B, C, and D.

[0107] As used herein, the terms "electrically coupled" or "coupled," when used to describe a path in an electric or electronic circuit, refer to components having a conduction path for electrical energy (i.e., current) in at least one direction between the components. Current does not have to flow along the conduction path for components to be coupled or electrically coupled. Components may be directly coupled with a conduction path that includes only low-impedance wires, etc., or may be indirectly coupled with semiconductors or higher impedance components that allow electrical energy to flow along the conduction path. [Explanation of symbols]

[0108] 100 systems 102 Controller 103 Charger 104 Power Distribution Bus 105 Load 106 Battery System 108 Battery 110b~110d FET / resistor pair 111 Transistor 141 State Determination System 147 Voltage Sensor 150b~150d resistor 160 C LOAD 170 DC-DC converter 180 signal line 700 System 702 Controller 704 Power Distribution Bus 705 Load 706 Battery System 707 Current Sensor 708 Battery 710a~710d Discharge switch 711 Switching element 721a~721e control lines 741 Voltage Sensor 742 Voltage Sensor 750a~750d resistor 1401 Threshold Detector 1402 Differentiator

Claims

1. 1. A method for regulating power supplied to a power distribution bus, comprising: monitoring an output voltage supplied to the power distribution bus, the output voltage resulting from a supply of current to the power distribution bus by a first power source; when the monitored output voltage decreases to a level equal to a voltage regulation set point of a DC-DC converter, supplying current from a second power source to the power distribution bus through the DC-DC converter, the DC-DC converter being coupled in parallel with a network of N FET / resistor pairs between the second power source and the power distribution bus, where N≧1; A method comprising:

2. 2. The method of claim 1, further comprising sourcing current from the second power supply to the power distribution bus through the network of N FET / resistor pairs when the monitored output voltage falls below a first predetermined threshold.

3. 3. The method of claim 2, wherein the N FETs in the network of N FET / resistor pairs are switched off when the current is being sourced by the DC-DC converter before the monitored output voltage decreases below the first predetermined threshold, such that no current is sourced from the second power source to the power distribution bus during a first period of time before the monitored output voltage decreases below the first predetermined threshold.

4. 3. The method of claim 2, wherein the current provided to the power distribution bus from the second power source is provided to be shared by the DC-DC converter and the network of N FET / resistor pairs for a second time period after the monitored output voltage decreases below the first predetermined threshold.

5. The method of claim 1 , wherein the second power source is a discharged battery.

6. The method of claim 5 , wherein the decrease in the monitored output voltage is due to a failure of the first power supply.

7. 5. The method of claim 4, wherein when the monitored output voltage falls below a first predetermined threshold, sourcing current from the second power source to the power distribution bus through the network of N FET / resistor pairs comprises switching on one or more of the N FETs in the network of N FET / resistor pairs.

8. 1. A method for regulating a delivery of current from a power source to a load over a power distribution bus, comprising: monitoring a voltage supply to the power distribution bus; maintaining the voltage within a specified load voltage tolerance by controlling how much current is provided from the power source to the power distribution bus through each of a first conductive path and a second conductive path coupled in parallel between the power source and the power distribution bus, the first conductive path including a DC-DC converter and the second conductive path including a network of N FET / resistor pairs coupled in parallel between the power source and the power distribution bus, each of the N FET / resistor pairs including a FET coupled in series with a resistor; A method comprising:

9. 9. The method of claim 8, wherein maintaining the voltage within the specified load voltage tolerance comprises modifying the total impedance of the network of N FET / resistor pairs by selectively switching each of the N FETs on and off according to a predetermined sequence.

10. The method of claim 9 , wherein the N resistors each have a different resistance value.

11. modifying the total impedance of the network of N FET / resistor pairs; decreasing the total impedance when the voltage is below a first predetermined threshold and the voltage is decreasing over time; increasing the total impedance when the voltage is greater than a second predetermined threshold and the voltage is increasing over time, the first predetermined threshold and the second predetermined threshold being within the specified load voltage tolerance range; 10. The method of claim 9, comprising:

12. 1. A power system for supplying power to a load over a power distribution bus, comprising: Power supply and a network of N transistors (where N>1) coupled between an output terminal of the power supply and the power distribution bus, each of the N transistors coupled in series with a resistor; a DC-DC converter coupled in parallel with the network of N transistors between the output terminal of the power supply and the power distribution bus; a controller configured to selectively and independently activate / deactivate the DC-DC converter and the network of N transistors to enable the power supply to power the load via the power distribution bus at an output voltage level adjusted in response to activation / deactivation of the DC-DC converter and the network of N transistors; Electric power system including.

13. The system of claim 12 , wherein the power source is a battery including one or more series-connected cells.

14. 13. The system of claim 12, wherein the controller is configured to regulate a voltage drop across the network by activating / deactivating a specific number of the N parallel-connected transistor / resistor pairs according to a predetermined sequence.

15. 15. The system of claim 14, wherein the output voltage level is regulated to be within a specified load voltage tolerance.

16. a differentiator configured to determine whether the output voltage level is increasing or decreasing over time; a threshold detector configured to determine when the output voltage level is greater than a first predetermined threshold and less than a second predetermined threshold, wherein the controller is configured to regulate the output voltage level within the specified load voltage tolerance range by selectively and independently activating / deactivating certain numbers of the N parallel-connected transistor / resistor pairs according to the predetermined sequence; 16. The system of claim 15, further comprising a state determination system comprising:

17. The controller: a circuit configured to reduce a total impedance of the network when the output voltage level is below the second predetermined threshold and the output voltage level is decreasing over time; a circuit configured to increase the total impedance when the output voltage level is greater than the first predetermined threshold and the output voltage level is increasing over time; and 17. The system of claim 16, comprising:

18. 13. The system of claim 12, wherein the DC-DC converter coupled in parallel with the network of N transistors is configured to handle no more than about 30% of the maximum output power of the power supply.

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