Indication device

Abstract

To provide a display device including a circuit suitable for controlling a liquid crystal element.SOLUTION: A display device includes two memories in a pixel and shares a gate line among a plurality of pixels in horizontal and vertical directions. The display device includes a liquid crystal element, and by writing a charge in a capacitor element that is different for each polarity, the power consumption at the inversion operation can be reduced. In addition, it is possible to suitably deal with a liquid crystal element with high threshold voltage and apply voltage in a wide range without deteriorating the gradation characteristic. Furthermore, the voltage more than or equal to the output voltage of a source driver can be applied to the liquid crystal element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the invention disclosed herein more specifically relates to The technical field of one aspect of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof This can be cited as an example.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. The term generally refers to a semiconductor device. A transistor and a semiconductor circuit are examples of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for constructing a transistor using a metal oxide formed on a substrate has been attracting attention. For example, a transistor using zinc oxide or In-Ga-Zn oxide is used for the display of a display device. The technology used for the basic switching elements is disclosed in Patent Document 1 and Patent Document 2. .

[0005] In addition, a memory device having a structure in which a transistor with extremely low off-state current is used as a memory cell is disclosed in a patent document. This is disclosed in reference 3.

[0006] Furthermore, various improvements and applications have been attempted for liquid crystal display devices. For example, the response speed has been improved. Optically Compensated Bend (OCB) mode was used. A liquid crystal display device is disclosed in Patent Document 4. Also, a liquid crystal display device using a field sequential operation Patent Document 5 discloses a transparent display that displays images. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119674 [Patent Document 4] Japanese Patent Application Laid-Open No. 2003-107506 [Patent Document 5] Japanese Patent Application Publication No. 2018-21974 Summary of the Invention [Problem to be solved by the invention]

[0008] Generally, LCD displays have a slow response time and lower video quality than self-luminous displays. On the other hand, by using the OCB mode with special orientation control, This can significantly improve the response speed of the liquid crystal display device.

[0009] Transparent displays using polymer dispersed liquid crystals are also being developed. Since it can be replaced with window glass, information can be displayed on train windows and shop windows. Various applications are expected, such as:

[0010] However, elements using OCB mode or polymer dispersed liquid crystal (reverse mode) Because the threshold voltage is high, it is necessary to supply a relatively high voltage to operate it. This creates issues such as power consumption and driver IC selection.

[0011] In addition, in the OCB mode, high voltage is not applied or maintained at a certain voltage or higher in order to control the orientation. Therefore, a special driving method must be used.

[0012] Therefore, one embodiment of the present invention provides a display device having a circuit suitable for controlling a liquid crystal element. One of the purposes is to provide a display device that can supply a high voltage to a liquid crystal element. One of the objects of the present invention is to provide a device that outputs a voltage equal to or higher than the output voltage of a source driver. It is an object of the present invention to provide a display device capable of supplying a liquid crystal element with a light emitting element.

[0013] Another object is to provide a display device with low power consumption. One of the purposes is to provide a new display device. Another object is to provide a method for operating the display device. Another object is to provide a novel semiconductor device or the like.

[0014] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0015] One embodiment of the present invention is a display device having a circuit suitable for controlling a liquid crystal element, and a display device for controlling the operation of the display device. Regarding the method.

[0016] One embodiment of the present invention is a semiconductor device including a first pixel, a second pixel, a first wiring, a second wiring, and a third wiring. a first pixel and a second pixel; Each of the pixels includes a first transistor, a first memory, a second memory, and a liquid crystal element. In each of the first pixel and the second pixel, the gate of the first transistor is electrically connected to the first wiring and is connected to one of the source and drain of the first transistor. is electrically connected to the sixth wiring and is connected to the other of the source and drain of the first transistor. is electrically connected to one electrode of the liquid crystal element, and the first memory is electrically connected to the second wiring. The first memory is electrically connected to one electrode of the liquid crystal element, and the second memory is The second memory is electrically connected to one electrode of the liquid crystal element. In the first pixel, the first memory is electrically connected to the fourth wiring, and the second memory is The first memory is electrically connected to the fifth wiring, and in the second pixel, the first memory is a display device electrically connected to the wiring, and a second memory electrically connected to the fourth wiring; be.

[0017] Furthermore, each of the first pixel and the second pixel has a first capacitance element, In each of the first and second pixels, one electrode of the first capacitor element is connected to one electrode of the liquid crystal element. The electrode may be electrically connected to the electrode.

[0018] The first memory includes a second transistor and a second capacitor, and the second memory includes a third transistor and a third capacitor element, and In each of the second transistors, the gate of the second transistor is electrically connected to the second wiring. One of the source and the drain of the transistor is electrically connected to one electrode of the second capacitor. the other electrode of the second capacitor is electrically connected to one electrode of the liquid crystal element; The gate of the third transistor is electrically connected to the third wiring. One of the source and the drain is electrically connected to one electrode of the third capacitor element. The other electrode of the capacitor element is electrically connected to one electrode of the liquid crystal element, and The other of the source and the drain of the second transistor is electrically connected to a fourth wiring. The other of the source and the drain of the third transistor is electrically connected to a fifth wiring. In the second pixel, the other of the source and the drain of the second transistor is connected to a fifth the other of the source and drain of the third transistor is electrically connected to the wiring of the fourth transistor. The wiring can be electrically connected to the wiring.

[0019] Furthermore, the image sensor has a third pixel and a fourth pixel, and each of the third pixel and the fourth pixel has a fourth transistor, and in each of the third pixel and the fourth pixel, The gate of the first transistor is electrically connected to the first wiring, and the source of the fourth transistor is electrically connected to the first wiring. One of the source and the drain may be electrically connected to a sixth wiring.

[0020] As the liquid crystal element, an element driven in OCB mode can be used. An element having a polymer dispersed liquid crystal may also be used.

[0021] The first transistor has a metal oxide in a channel formation region, and the metal oxide includes In and Zn and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) , preferably having

[0022] In another embodiment of the present invention, a transistor is connected to a node to which one electrode of a liquid crystal element is connected. one of the source and drain of the capacitor, one electrode of the first capacitor element and one electrode of the second capacitor element A method of operating a display device in which each of the electrodes on one side is electrically connected directly, comprising: supplying one of a high potential and a low potential to one of the electrodes via a transistor; a first capacitor having an operation of supplying the other of a high potential and a low potential to the other electrode of the first capacitor; and an operation of supplying either a high potential or a low potential to the other electrode of the first capacitor. and a second step having the first step and the second step. This is a method of operation of the display device.

[0023] In the second step, the absolute value of the potential of one electrode of the liquid crystal element is set to 15 V or more. is preferred.

[0024] Furthermore, an operation of supplying a first potential to one electrode of a liquid crystal element through a transistor, and and a third step of supplying a second potential to the other electrode of the second capacitor element. However, the operations may be performed in the order of the first step, the third step, and the second step.

[0025] In the first step, the other of the high potential and the low potential is applied to the other electrode of the second capacitor element. In the second step, a high potential or a low potential is applied to the other electrode of the second capacitor. Alternatively, an operation of supplying one of the two positions may be performed.

[0026] In addition, a node to which one electrode of the liquid crystal element is connected is connected to one electrode of the third capacitor. A method for operating a display device in which a third capacitor is electrically connected to a first capacitor, The other electrode of the element is supplied with a high potential or a low potential, and in a third step and an operation of supplying either a high potential or a low potential to the other electrode of the third capacitor element. Alternatively, the operations may be performed in the order of step (1), step (3), and step (2).

[0027] Another embodiment of the present invention is a liquid crystal display device in which a transistor is connected to a node to which one electrode of a liquid crystal element is connected. one of the source and drain of the first capacitor element, one electrode of the second capacitor element, A method for operating a display device in which the electrodes of the liquid crystal element are electrically connected directly to each other, An operation of supplying a first potential to one electrode of the first capacitor through a transistor and A first step including an operation of supplying a second potential to the other electrode of the second capacitor element; A second step of applying a third potential to one electrode of the liquid crystal element and a second step of applying a transistor to one electrode of the liquid crystal element. an operation of supplying a fourth potential to the other electrode of the first capacitor through the capacitor; a third step including an operation of supplying a sixth potential to the other electrode of the first capacitor; and a fourth step of supplying the first step, the second step, the third step. The fourth step is a method for operating a display device.

[0028] The absolute values ​​of the second and fifth potentials are up to twice the absolute value of the first or fourth potential. Alternatively, the first potential and the fourth potential may be equal to each other, and the second potential may be equal to the fourth potential. The potential may be an inverted potential of the sixth potential. [Effects of the Invention]

[0029] By using one embodiment of the present invention, a display device having a circuit suitable for controlling a liquid crystal element can be provided. Alternatively, a display device capable of supplying a high voltage to a liquid crystal element can be provided. Alternatively, a voltage higher than the output voltage of the source driver can be supplied to the liquid crystal element. It is possible to provide a display device that can do this.

[0030] Alternatively, a display device with low power consumption can be provided. Alternatively, a novel display device or the like can be provided. Furthermore, a method for operating the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided. It can be provided. [Brief explanation of the drawings]

[0031] [Figure 1] 1A and 1B are diagrams illustrating a display device. [Figure 2] (A) and (B) are diagrams illustrating the operation of a liquid crystal element. [Figure 3] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 4] 1A to 1C are diagrams illustrating a selection circuit. [Figure 5] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 6] 4A and 4B are timing charts illustrating the operation of the display device. [Figure 7] 1A to 1C are diagrams illustrating charges held in a capacitance element. [Figure 8] 4 is a timing chart illustrating the operation of the display device. [Figure 9] 4 is a timing chart illustrating the operation of the display device. [Figure 10] 4A and 4B are timing charts illustrating the operation of the display device. [Figure 11] 4 is a timing chart illustrating the operation of the display device. [Figure 12] 4 is a timing chart illustrating the operation of the display device. [Figure 13] 4 is a timing chart illustrating the operation of the display device. [Figure 14] (A) and (B) are diagrams illustrating a pixel circuit. [Figure 15] (A) A diagram illustrating the configuration of a pixel circuit used in the simulation. (B) A timing chart used in the simulation. [Figure 16] (A) and (B) Schematic illustrating the simulation results. [Figure 17] 1 is a timing chart used in a simulation. [Figure 18] FIG. 10 is a diagram illustrating the results of a simulation. [Figure 19] 1A to 1C are diagrams illustrating a display device. [Figure 20] (A) and (B) are diagrams illustrating the touch panel. [Figure 21] 1A and 1B are diagrams illustrating a display device. [Figure 22] 1A and 1B are diagrams illustrating a display device. [Figure 23] 1A and 1B are diagrams illustrating a display device. [Figure 24] 1A and 1B are diagrams illustrating a display device. [Figure 25] 1A to 1E are diagrams illustrating a display device. [Figure 26] 1A to 1C are diagrams illustrating a transistor. [Figure 27] 1A to 1C are diagrams illustrating a transistor. [Figure 28] 1A to 1C are diagrams illustrating a transistor. [Figure 29] 1A to 1C are diagrams illustrating a transistor. [Figure 30] (A) to (F) are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various forms and details without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-described embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. The same elements in the drawings are used interchangeably, and repeated explanations may be omitted. In some cases, the timing may be omitted or changed as appropriate between different drawings.

[0033] In addition, even if a circuit diagram shows a single element, there may be functional problems. If there is no need for a single element, the element may be composed of multiple elements. For example, a transistor that operates as a switch may be used. In some cases, multiple resistors may be connected in series or in parallel. In some cases, the sensor may be divided and placed in multiple positions.

[0034] In addition, when one conductor has multiple functions such as wiring, electrode, and terminal, In this specification, the same element may be referred to by multiple names. Even if the circuit diagram shows direct connections between elements, In some cases, the elements are connected via multiple conductors, and in this specification, Even configurations such as this are included in the category of direct connection.

[0035] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0036] One aspect of the present invention is to provide a memory cell having two memories in a pixel, and a plurality of pixels in the horizontal and vertical directions. The display device has a liquid crystal element and reduces power consumption during inversion operation. It also supports liquid crystal elements with high threshold voltages, and is suitable for gray scale display. A wide range of voltages can be applied as required.

[0037] FIG. 1 illustrates a display device according to one embodiment of the present invention. The display device includes a pixel 10 and a source The pixel circuit includes a switch driver 12 and a gate driver 13 .

[0038] The pixel 10 includes a memory M1, a memory M2, and a circuit block 11. The memory M2 is electrically connected to the circuit block 11. The circuit block 11 includes, for example, The pixel includes a transistor, a capacitor, and a liquid crystal element, which are electrically connected to each other.

[0039] In two pixels 10 adjacent to each other in the vertical direction (the direction in which the source lines extend), The memory M1 is electrically connected to the first wiring (gate line). The memory M2 included in each of the memory cells 10 is electrically connected to the second wiring (gate line). In addition, the transistors included in each circuit block 11 in the two pixels 10 are: It is electrically connected to the third wiring (gate line).

[0040] Furthermore, the memory M1 included in one pixel 10 and the memory M2 included in the other pixel 10 are The fourth wiring (source line) is electrically connected to the memory M The memory M1 of the pixel 10 is electrically connected to the fifth wiring (source line). In addition, the transistors included in the circuit blocks 11 of the two pixels 10 are is electrically connected to the sixth wiring (source line).

[0041] Therefore, each of the memories M1 has a different value according to the signal supplied to the first wiring. Data can be written to each of the memories M2. Depending on the signal, different data can be written.

[0042] The transistors included in the circuit blocks 11 of the two pixels 10 are the third The same data can be supplied to each liquid crystal element according to the signal supplied to the wiring. As shown in FIG. 1, the sixth wiring is adjacent to the horizontal direction (the direction in which the gate lines extend). The transistors can be electrically connected to the transistors of the circuit block 11 included in the pixel 10 .

[0043] As described above, since the wiring is shared by a plurality of pixels 10, This reduces the number of wiring to 1.5 gate lines and 2.5 source lines. Therefore, the aperture ratio can be increased compared to when the wiring is not shared. Writing can be done at high speed.

[0044] In the display device of one embodiment of the present invention, data written to one electrode of the liquid crystal element and data written to the memory M 1 or the data to be written to memory M2. It is possible to supply a voltage higher than the driver's output voltage to the liquid crystal element, and liquid crystal with a high threshold voltage Even with a general-purpose source driver, gradation control is relatively easy. This allows a lower voltage to be supplied to the liquid crystal element, reducing the cost of the display element. do.

[0045] One of the memories M1 and M2 stores a first potential for driving the liquid crystal element. The other of the memories M1 and M2 stores a second voltage for driving the liquid crystal element. Here, the first potential and the second potential are set to a value that prevents burn-in of the liquid crystal element. For example, when the first potential is a positive potential, the second potential is a In this way, the polarity of the potentials stored in memory M1 and memory M2 is constant. By not changing the voltage, the amount of charge supplied can be reduced, leading to power savings. do.

[0046] As liquid crystal elements with high threshold voltages, for example, OCB mode and polymer dispersed liquid crystal are known. In the OCB mode, liquid crystal is injected into parallel-rubbed cells, and splay alignment is achieved. Then, a relatively strong vertical electric field is applied to create a bend alignment. The liquid crystal element can perform gray scale control while maintaining the bend alignment, but the applied voltage If the field is reduced below a certain value, the alignment returns to the splay orientation.

[0047] Figure 2(A) shows the voltage-transmittance characteristics of an OCB mode liquid crystal element (transmittance in parallel Nicols mode). This is an example where the bend alignment is performed at a high voltage, and then at about 2V. The transmittance increases with decreasing voltage up to 1000 kJ / s, but then the transmittance drops sharply. This means that the alignment has returned to the splay orientation. Therefore, in OCB mode, at least Therefore, a voltage of about 2 V must be applied to the

[0048] FIG. 2(B) shows an example of the voltage-transmittance characteristics of a polymer dispersed liquid crystal element (light from a light source). The polymer dispersed liquid crystal element operates in reverse mode and This shows a state where the transmittance is high when no voltage is applied. The transmittance decreases when the voltage exceeds 2V. Initially, it becomes constant at about 8 V. Gradation control can be performed using the voltage between these levels.

[0049] As mentioned above, in the OCB mode liquid crystal element and the polymer dispersed liquid crystal element, the development of gradation control At first, it is necessary to apply at least several volts. This voltage is referred to as the offset voltage (V of There is a method to cancel out the voltage equivalent to the offset voltage with the common voltage, but Liquid crystal elements, which require a rotation drive, consume a lot of power. If the voltage and offset voltage are dependent on the supply from the source driver, This requires a driver, which may result in additional development costs.

[0050] In one aspect of the present invention, even if a liquid crystal element has a large offset voltage, a common voltage is applied when the liquid crystal element is driven. The offset voltage can be made constant, and a general-purpose source driver can be used. It is easy to maintain the voltage and generate a high voltage to bend the liquid crystal in OCB mode. Note that a display device having a pixel according to one embodiment of the present invention can be implemented using an OCB mode liquid crystal display device. The present invention is not limited to a configuration having a polymer dispersed liquid crystal element, but may also be applicable to a configuration having other liquid crystal elements. It is also possible.

[0051] FIG. 3 shows the pixel array in the mth and m+1th columns, nth and n+1th rows (m and n are 1 or more). 3 shows a specific example of the pixel 10 in the pixel area (n, m). Four pixels: pixel 10[n+1,m], pixel 10[n,m+1], pixel 10[n+1,m+1] However, for pixel 10[n,m+1] and pixel 10[n+1,m+1], , details are omitted.

[0052] The pixel 10 includes a transistor 101, a transistor 102, a transistor 103, and a capacitor. A configuration including a capacitor 104, a capacitor 105, a capacitor 106, and a liquid crystal element 107. It is possible.

[0053] One of the source and drain of the transistor 101 is connected to one electrode of the capacitor 104. The other electrode of the capacitor 104 is electrically connected to the source or One electrode of the capacitor 104 is electrically connected to one of the drains of the capacitor 105. The other electrode of the capacitor 105 is electrically connected to one electrode of the transistor 10 One electrode of the capacitor 105 is electrically connected to one of the source and drain of the capacitor 105. , is electrically connected to one electrode of the capacitor 106. It is electrically connected to one electrode of the liquid crystal element 107 .

[0054] Here, one of the source and drain of the transistor 101 and one of the potentials of the capacitor 104 one electrode of the capacitor 105, one electrode of the capacitor 106, and one electrode of the liquid crystal element 107 The wiring to which one electrode is connected is called node NM. Node NM is set to be floating. The liquid crystal element 107 operates in accordance with the potential of the node NM.

[0055] In addition, one of the source and drain of the transistor 102 and the other of the capacitor 104 The wiring to which the electrode is connected is referred to as a node ME1. The wiring to which one of the drain electrodes and the other electrode of the capacitor 105 are connected is referred to as a node ME2. do.

[0056] The memory M1 in FIG. 1 corresponds to the node ME1 and its peripheral elements. The memory M2 in FIG. 1 corresponds to the node ME2 and its peripheral elements. The elements of the circuit block 11 include a transistor 101, a capacitance element 106, and a liquid crystal element 107 is the applicable number.

[0057] The elements of pixel 10[n,m] and pixel 10[n+1,m] and the connections between various wirings are explained. First, the connection topology common to pixel 10[n,m] and pixel 10[n+1,m] is The gate of the transistor 101 is electrically connected to the wiring 123[n]. The gate of the transistor 102 is electrically connected to the wiring 121. The gate of the transistor 103 is electrically connected to the wiring 122. The other drain is electrically connected to the wiring 126[m]. The other electrode of the liquid crystal element 107 is electrically connected to a wiring 133. are electrically connected.

[0058] Next, the different connection forms for pixel 10[n,m] and pixel 10[n+1,m] will be explained. In the pixel 10[n,m], the other of the source and drain of the transistor 102 is electrically connected to the wiring 124[m]. The other end of the drain is electrically connected to the wiring 125[m]. The other of the source and drain of the transistor 102 is electrically connected to the wiring 125[m]. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 12. 4[m] and is electrically connected.

[0059] In addition, in the pixel 10[n, m+1] and the pixel 10[n+1, m+1], the transistor The other of the source and drain of the transistor 101 is electrically connected to the wiring 126[m]. The transistor 102 included in the pixel 10[n,m+1] is connected to the wiring 127[m+1 ], and the transistor 103 can be electrically connected to the wiring 128[m+1]. In addition, the transistor 10[n+1, m+1] of the pixel 10[n+1, m+1] can be connected The transistor 102 can be electrically connected to the wiring 128[m+1]. It can be electrically connected to the wiring 127[m+1].

[0060] The wirings 121, 122, and 123 function as gate lines, and are connected to a gate driver 13 (see FIG. 1 The wiring 132 and the wiring 133 are connected to a common wiring for supplying a constant potential. The wirings 124, 125, 127, and 128 function as source lines. and is electrically connected to the source driver 12 (see FIG. 1).

[0061] The wiring 126 also functions as a source line, but since it is a wiring that supplies a constant potential, It can be electrically connected to a predetermined power supply circuit 15 via the circuit 14 (see FIG. 1). The number of power supply circuits 15 is not limited to one. Also, the power supply circuit 15 may be connected to other circuits such as a source driver. The power supply circuit may be a power supply circuit included in the circuit.

[0062] The selection circuit 14 may have the configuration shown in FIGS. 4(A) and 4(B), for example. Depending on the reset voltage (RES+, RES-), the power supply voltage of the source driver (SVDD, SVSS) can be selected and supplied to the wiring 126. To achieve this, a path that can select the common potential (VCOM) is added to the configurations shown in Figures 4(A) and (B). SEL_RES-, SEL_RES+, SEL_SVDD, SEL_S VSS and SEL_COM are signals for controlling each transistor.

[0063] The nodes NM, ME1, and ME2 act as storage nodes. By turning on the transistor connected to In addition, by making the transistor non-conductive, the data is held in each node. By using a transistor with extremely low off-state current as the transistor, leakage current can be reduced. This makes it possible to suppress the current and maintain the potential of each node for a long period of time. The transistor is, for example, a transistor using a metal oxide in the channel formation region (hereinafter referred to as O S transistor) can be used.

[0064] Specifically, OS transistors can be used as the transistors 101, 102, and 103. It is also preferable to use OS transistors for the elements included in the circuit block 110. In addition, when operating within an allowable range of leakage current, Si is used in the channel formation region. Alternatively, a transistor having a silicon nitride film (hereinafter referred to as a silicon transistor) may be used. The Si transistor may be used in combination with a silicon transistor. , amorphous silicon transistors, crystalline silicon (typically low-temperature poly Examples include transistors using silicon (polysilicon, single crystal silicon).

[0065] The semiconductor material used for the OS transistor has an energy gap of 2 eV or more. Metal oxides having a specific resistance of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium, for example, a CAAC -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Because it exhibits high mobility, it is suitable for use in transistors that operate at high speed.

[0066] Because the OS transistor has a large energy gap, the The OS transistor exhibits extremely low off-state current (current per The Si transistor is free from impact ionization, avalanche breakdown, and short channel effects. It has different characteristics from transistors and can form highly reliable circuits. The variation in electrical characteristics caused by the non-uniformity of crystallinity, which is a problem in i-transistors, is also reduced by OS transistors. This is unlikely to occur with transistors.

[0067] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as tin, neodymium, or hafnium The film can be made of a material such as a silicon dioxide film.

[0068] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, The atomic ratio of the metal elements in the sputtering target used to form a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios were In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0069] The semiconductor layer is made of an oxide semiconductor with a low carrier density. Carrier density is 1×10 17 / cm 3 Less than 1 × 10 15 / cm 3 Further details are as follows: Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 Below, further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a highly pure intrinsic or This oxide semiconductor has a low density of defect states and is stable. It can be said that this oxide semiconductor has stable characteristics.

[0070] However, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (e.g., the mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer must be carefully considered. It is preferable to appropriately set the density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. stomach.

[0071] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase, causing the semiconductor layer to become n-type. The concentrations of phosphate and carbon (obtained by secondary ion mass spectrometry) were measured at 2 × 10 18 atom s / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0072] In addition, alkali metals and alkaline earth metals generate carriers when bonded with oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration obtained is 1 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 Do the following:

[0073] In addition, if nitrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, electrons, which are carriers, This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5 x 10 18 atoms / cm 3 It is preferable to do the following:

[0074] In addition, if hydrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the oxide that bonds with the metal atoms Since the oxygen reacts with oxygen to form water, oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the conductor contains oxygen vacancies, the transistor will be normally on. Furthermore, defects in which hydrogen has entered the oxygen vacancies act as donors, In addition, some of the hydrogen atoms bond with the metal atoms, resulting in the generation of carrier electrons. It may combine with hydrogen to generate electrons, which are carriers. A transistor including an oxide semiconductor having such a structure tends to be normally on.

[0075] A defect in which hydrogen is inserted into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, the acid As a parameter of the compound semiconductor, we assume a state in which no electric field is applied, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "donor concentration."

[0076] Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor be reduced as much as possible. In oxide semiconductors, secondary ion mass spectrometry (SIMS) The hydrogen concentration obtained by mass spectrometry was calculated as 1×1020 a toms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / c m 3 The oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used as the transistor chip. By using it in the channel forming region, stable electrical characteristics can be imparted.

[0077] The semiconductor layer may also have a non-single crystal structure, for example. The non-single crystal structure may have a c-axis orientation. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystalline structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0078] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain crystalline components. Alternatively, the amorphous oxide film may have a completely amorphous structure and no crystalline portion. stomach.

[0079] The semiconductor layer may have an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a CAAC structure. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminated structure. It may have a structure.

[0080] Hereinafter, we will discuss CAC (Cloud-Aligned C), which is one type of non-single-crystal semiconductor layer. This article explains the structure of the .NET composite OS.

[0081] CAC-OS is a type of oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm thick. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or in the vicinity thereof. In the following, it is assumed that one or more metal elements are contained in the oxide semiconductor. The region containing the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixed state of particles with sizes of 2 nm or less or close to that size is called a mosaic or patch state. It is also called.

[0082] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more selected from tantalum, tungsten, magnesium, etc. It may be included.

[0083] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OS) α-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0) or indium zinc oxide compound (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) . ), or gallium zinc oxide (Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into two parts, forming a mosaic pattern. Mosaic InO X1 , or In X2 Zn Y2 O Z2 is uniformly distributed in the film This is a cloud-like configuration (hereinafter also referred to as "cloud-like").

[0084] In other words, CAC-OS is X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Compared to region 2, the concentration of In is higher.

[0085] IGZO is a common name and refers to a compound of In, Ga, Zn, and O. A typical example is InGaO3(ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of such crystalline compounds include:

[0086] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0087] On the other hand, CAC-OS refers to the material structure of an oxide semiconductor. In a material composition containing Ga, Zn, and O, some nanoparticles with Ga as the main component were observed. The region where the In nanoparticles are observed is shown in part. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0088] It should be noted that the CAC-OS does not include a laminated structure of two or more films with different compositions. For example, a structure consisting of two layers, one containing In as the main component and the other containing Ga as the main component, is not included. do not have.

[0089] In addition, GaO X3 The region where In is the main component and X2 Zn Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the main component region and the main component region cannot be observed.

[0090] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected elements such as sodium are included, CAC-OS will In the region, nanoparticles containing the metal element as the main component are observed, and in a part, In is the main component. The nanoparticle-like regions are randomly dispersed in a mosaic pattern. say.

[0091] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas is The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. It is more preferable to set the content to 0% or more and 10% or less.

[0092] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, from the X-ray diffraction measurement, It can be seen that the orientation of the regions in the ab plane direction and the c axis direction is not observed.

[0093] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped area of ​​high brightness (phosphor) is formed. The electron diffraction pattern is Therefore, the crystal structure of CAC-OS does not have orientation in the planar direction and the cross-sectional direction. It can be seen that it has a nano-crystal structure.

[0094] For example, in the CAC-OS of In-Ga-Zn oxide, energy dispersive X Energy Dispersive X-ray Spectroscopy (EDX) EDX mapping obtained using scopy revealed that GaO X3 The region where is the principal component And, In X2 Zn Y2 O Z2 , or InO X1 The area where the main component is unevenly distributed and mixed It can be confirmed that the compound has a structure similar to that of the compound shown in FIG.

[0095] CAC-OS has a structure different from that of IGZO compounds, in which metal elements are uniformly distributed. CAC-OS has different properties from ZO compounds. X3 The main ingredients are In a certain area, X2 Zn Y2 O Z2 , or InO X1 The region where is the principal component and The phases are separated into two, and the regions containing each element as the main component are arranged in a mosaic pattern.

[0096] Here, In X2 Zn Y2 O Z2 , or InO X1 The region where is the main component is GaO X3 This region has higher conductivity than the region where In is the main component. X2 Zn Y 2O Z2 , or InO X1 The carriers flow through the region where the main component is oxidized. Therefore, the conductivity of In is expressed as a semiconductor. X2 Zn Y2 O Z2 , or In O X1 The region where the main component is distributed in a cloud-like shape in the oxide semiconductor allows for a high electric field. Effective mobility (μ) can be achieved.

[0097] On the other hand, GaO X3 The region where the main components are In X2 Zn Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching. Switching operation can be realized.

[0098] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, In X2 Zn Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ) This can be done.

[0099] Furthermore, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0100] The pixel 10 may have a configuration in which the capacitor element 106 is omitted, as shown in FIG. As described above, an OS transistor can be used as the transistor connected to the node NM. Since the leakage current of the OS transistor is extremely small, it can be used as a capacitance element that functions as a storage capacitor. Even if 106 is omitted, the display can be maintained for a relatively long time. In addition, in cases where the display period can be shortened by high-speed operation, such as field sequential driving, In this case, it is effective to omit the capacitor element 106. By omitting the capacitor element 106, the aperture ratio can be improved. Alternatively, the transmittance of the pixel can be improved.

[0101] Next, an operation method using the pixel 10 according to one embodiment of the present invention will be described. First, a common operation will be described. The operation for each application will be explained later.

[0102] 6A and 6B are diagrams illustrating positive and negative polarity driving of a liquid crystal element. The positive polarity drive and the negative polarity drive are usually performed alternately every frame. 5[m] is the source line for the mth column, and different data can be supplied to each of them. The wirings 121, 122, and 123 are gate lines. As shown in FIG. 3, the wiring 121[n] , 122[n], 123[n] are the pixels 10 in the nth row and the pixels 10 in the (n+1)th row. In addition, the wirings 121[n-2], 122[n-2], and 123[n-2] are The pixels 10 in the (n-2)th row and the pixels 10 in the (n-1)th row are electrically connected.

[0103] First, a signal potential (W) corresponding to the weight is applied to the wiring 124[m] and the wiring 125[m]. Then, a signal potential (D) corresponding to the data is supplied. When the voltage is positive (positive drive), the signal potential used is "+", and when the voltage is applied to the liquid crystal element, When the voltage applied is negative (negative drive), the signal potential is marked with a "-" sign. That is, "W+" and "D+" represent the weight and data used for positive polarity drive. "W-" and "D-" represent the weight and data used for negative polarity drive. "W+" is written when driven negatively, and "W-" is written when driven positively. Also, "W-" and "D+" can be positive potentials, and "W+" and "D-" can be negative potentials.

[0104] In the signal potentials supplied to the wirings 124 and 125 shown in FIGS. 6(A) and 6(B), [n], [n-1] indicates the row number. For example, W-[n-1] is the pixel in the [n-1]th row. represents the weight (W-) supplied to 10.

[0105] In the positive polarity driving shown in FIG. 6A, W-[n-3] and W-[n-2] are applied between times T1 and T2. are supplied and written to pixel 10 in the [n-3]th row and pixel 10 in the [n-2]th row, respectively. In addition, D+[n-2] and D+[n-3] are supplied between times T3 and T4, and [n-2 ]th row, and pixel 10 in the [n-3]th row.

[0106] Here, W-[n-3] and W-[n-2] written between time T1 and time T2 are the frames in question. It is not used in the positive polarity drive of the next frame, but is held until the negative polarity drive of the next frame, and is written in the next frame. The data is added to D-[n-2] and D-[n-3] written at time T3 and T4. The written D+[n-2] and D+[n-3] contain the data written and stored in the previous frame. W+[n-3] and W+[n-2] are added.

[0107] In the negative polarity driving shown in FIG. 6B, W+[n-3] and W+[n-2] are applied between times T1 and T2. are supplied and written to pixel 10 in the [n-3]th row and pixel 10 in the [n-2]th row, respectively. In addition, D-[n-2] and D-[n-3] are supplied between times T3 and T4, and [n-2 ]th row, and pixel 10 in the [n-3]th row.

[0108] Here, W+[n-3] and W+[n-2] written between times T1 and T2 are the frames It is not used in the negative polarity drive of the frame, but is maintained until the positive polarity drive of the next frame. It is added to the written D+[n-2] and D+[n-3]. The written D-[n-2] and D-[n-3] contain the data written and stored in the previous frame. W-[n-3] and W-[n-2] are added together.

[0109] The above is a common operation in one aspect of the present invention, and includes writing weights and data and adding operations. Note that W- and D+ (positive potential) always connect one memory (for example, node ME1) to the other. The memory M1 is written to, and W+ and D- (negative potential) are always written to the other memory ( For example, the memory having node ME2 is written to memory M2. Charges of the same polarity are always written to the capacitance elements of the memory or the other memory. Therefore, since the charge is not written so that the polarity of the electrode is reversed, The amount of charge supplied can be reduced, and power consumption can be reduced. The polarities of the potentials written to the memory and the second memory may be reversed.

[0110] 7A to 7C show the state of one memory or the other at a particular pixel 10. FIG. 1 is a diagram illustrating the charge written to the capacitance element of one memory. The capacitance element of the other memory is indicated by C+, and the capacitance element of the other memory is indicated by C-. corresponds to the capacitance element 104 shown in FIGS. 3 and 5. C- corresponds to the capacitance element 104 shown in FIGS. This corresponds to the capacitor element 105 shown in FIG.

[0111] In Figures 7(A) to 7(C), [N] and [N+1 ] etc. means the frame used for addition. Also, qw is the weight charge, and + and - are the charge polarity, and + and - after qw are the type of capacitance element (if it is +, the charge stored in C+ (N), (N+1), etc. refer to the frames used for addition.

[0112] For clarity, the behavior of the capacitance element C- will be mainly explained here. FIG. 10 is a diagram showing the charges stored in the capacitance elements C− and C+ in the 3rd frame (positive polarity drive). The left side shows the weight (W) write, and the right side shows the data (D) write for the same frame. In the (N-1)th frame, first, a weight “W-[N]” is supplied to one electrode of the capacitance element C-. The other electrode is supplied with a potential of 0 V, for example. At this time, +qw -(N), and the other electrode has a charge of -qw-(N).

[0113] Next, when data “D+[N-1]” is supplied to one electrode of the capacitance element C+, the capacitance The electrodes at both ends of the element C- are set to be floating, and the charge of the capacitive element C- is maintained.

[0114] Next, in the Nth frame (negative polarity drive) shown in FIG. 7B, one of the capacitance elements C+ When the weight “W+[N+1]” is applied to the electrode, one electrode of the capacitance element C- is floating. Since this is a switching operation, the charge in the capacitive element C− continues to be held.

[0115] Next, negative data “D-[N]” is supplied to one electrode of the capacitance element C-, and the capacitance element The other electrode of the electrode C- is capacitively coupled with the weight “W-[N]” held, The other electrode is floating, so the charge held in the capacitance element C- does not change. do not have.

[0116] Next, in the (N+1)th frame (positive polarity drive) shown in FIG. 7(C), one of the capacitance elements C- A weight "W-[N+2]" is applied to one electrode, and a potential of 0V is applied to the other electrode. At this time, the charge of the capacitance element C- is rewritten, and one electrode is charged with +qw-(N+ 2), and a charge of -qw-(N+2) accumulates on the other electrode.

[0117] Up to this point, the polarity of the charge stored on both electrodes of the capacitance element C- remains constant without reversal. Similarly, the polarity of the charge accumulated on both electrodes of the capacitance element C+ can be made constant. Therefore, in one embodiment of the present invention, the amount of charge supplied during the inversion operation can be reduced. This makes it possible to reduce the power consumption of the display device.

[0118] Next, examples of operation for different applications will be described. First, the operation of applying a high voltage to a liquid crystal element will be described. This operation is, for example, the case of an OCB mode liquid crystal that requires a bend alignment operation by applying a high voltage. Here, "SVDD" is used as the high potential and "S VSS” is used, but other potentials may be used. However, if the generated voltage is higher, In this case, the greater the difference between the high potential and the low potential, the more preferable.

[0119] FIG. 8 is a diagram illustrating the operation from power-on to the first frame using the pixel 10 shown in FIG. In the first frame, the operation to generate a high potential is performed, so the image data input Although no power is applied, a positive polarity operation is applied here. This includes the operation of writing the weight (W-) for negative polarity drive of the frame. In this case, the circuit shown in FIG. 4A can be used for the selection circuit 14.

[0120] In this embodiment, for the sake of clarity, the liquid crystal element 107 and the capacitance element included in the pixel 10 are It is assumed that the capacitance value of the resistor 106 is sufficiently small. Until the first frame, a high voltage is applied to the liquid crystal element in a common operation for all pixels. The same potential signal is supplied to 4[m] and 125[m]. To supply different image data to the 0, wires 124[m] and 125[m] are used. However, since the weight (W) is a specific value, In this case, the same weight (W) is supplied to the wirings 124[m] and 125[m]. Lines 132 and 133 are set to 0V.

[0121] At time T1, “SVDD” is connected to wire 126[m], and “S VSS” is supplied and the potential of the wiring 121[n] and the wiring 123[n] is set to “H”, The transistor 101 is turned on, and the potential of the node NM becomes "SVDD." The resistor 102 becomes conductive, and the potential of the node ME1 becomes "SVSS."

[0122] At time T2, when the potential of the wiring 121[n] and the wiring 123[n] is set to "L", The transistor 101 and the transistor 102 become non-conductive, and the potential of the node NM and the node The potential of ME1 is maintained.

[0123] At time T3, “RES+” is applied to the wire 126, and weights (W) are applied to the wires 124[m] and 125[m]. "W-" is supplied as a signal, and the potential of the wiring 122[n] and the wiring 123[n] is set to "H". Then, the transistor 101 becomes conductive, and the node NM changes from "SVDD" to the reset potential "RE At this time, the potential of the node ME1 is reset to SVSS due to capacitive coupling. -(SVDD-(RES+))".

[0124] Here, the reset potential (RES) is the offset voltage (V of ) or nearby The absolute value of the positive potential (RES+) in the frame for positive polarity drive, and the negative potential (RES+) in the frame for negative polarity drive. In this case, a positive potential is applied to the reset potential (RES). For example, +2V.

[0125] Furthermore, the transistor 103 is turned on, and the potential of the node ME2 becomes "W-". The weight (W) is an absolute value twice the reset voltage (RES) and is a positive polarity drive frame. If the weight is written in a frame with positive potential, it is written in a frame with negative polarity drive. By writing such a value as a weight, the node ME2 or A potential difference equivalent to the reset potential (RES) is maintained between the node ME1 and the node NM. Therefore, when data (D) is written to node ME2 or node ME1, The potential of the node NM is the reset potential (RES) + data (D). ) is applied with a positive potential, for example +4V.

[0126] At time T4, when the potential of the wiring 122[n] and the wiring 123[n] is set to "L", The transistor 101 and the transistor 103 become non-conductive, and the potential of the node NM and the node The potential of ME2 is maintained.

[0127] At time T5, positive polarity drive data “D1+” is supplied to wires 124[m] and 125[m]. When the potential of the wiring 121[n] is set to “H”, the transistor 102 is turned on, and the node M The potential of E1 becomes "D1+". Here, when "SVDD" is supplied as "D1+", Therefore, the potential of the node NM is In this case, "(RES+)+(SVDD-(SVSS-(SVDD-(RES+)))) "="2SVDD-SVSS". In other words, the absolute value of "SVDD" and "SVSS". If the voltage is the same, a voltage about three times as large as the voltage can be applied to the liquid crystal element 107.

[0128] In order to bend-align the liquid crystal in the OCB mode, it is necessary to apply about 15V. The switch driver only needs to supply about one-third of that voltage. Considering the gradation control by the output 107, the power supply voltage that the source driver 12 can output is 5V. It is preferably 6V or more, and more preferably 7V or more.

[0129] The above operation was explained when the first frame was driven with positive polarity. In the negative polarity drive, the first frame may be negative polarity drive. [m] Supply "SVSS" as "SVDD", "W+", and data "D1-". This allows the generation of a high voltage (-SVDD+2SVSS) to be applied to the liquid crystal element 107. do.

[0130] Also, the operation of writing the weight (W) may be omitted, and only the operation of generating a high voltage may be performed. For example, the operation can be performed according to the timing chart shown in FIG. The potential of the node NM was raised by capacitive coupling using one capacitance element. In operation, the potential of the node NM can be raised by two capacitance elements, generating a higher voltage. It can be achieved.

[0131] In addition, since there is no operation to write the weight (W), the operation shown by the dashed line of the wiring 132 (common wiring) The potential of the node NM may be raised by three capacitance elements using the above. In this case, the potential of the wiring 132 is preferably changed from SVSS to SVDD.

[0132] As shown in FIG. 10B, the supply of SVDD and SVSS is switched. Good too.

[0133] Next, we will explain the second frame and onwards. When using OCB mode, After the operations of the first frame are performed, the operations of the second frame and thereafter, which will be described below, are performed.

[0134] Furthermore, when a polymer dispersed liquid crystal is used, there is no need to apply a high voltage to the liquid crystal element. Therefore, in the first frame, the weight (W) is set to "W-" and the reset potential (R ES), and then writes "RES+" in the second frame as described below. The following operations are performed. Note that Figure 11 shows an example of positive polarity drive, but "W+", " When a polymer dispersed liquid crystal is used, the selection circuit 4(A) or (B) can be used for 14.

[0135] In the first frame, in addition to the high voltage generation operation described above, the weight (W) writing operation is performed. If the first frame is a positive operation, the weight "W-" for the negative operation of the next frame is If it is a negative polarity operation, the weight "W+" for the positive polarity operation of the next frame is written. The weight (W) for the next frame is written from the second frame onwards.

[0136] FIG. 12 shows the second and third frames following the first frame shown in FIG. The second frame is negative polarity drive, and the third frame is negative polarity drive. is a positive drive.

[0137] At time T1, “RES-” is assigned to wire 126 [m], and weights are assigned to wires 124 [m] and 125 [m]. When “W+” is supplied and the potential of the wiring 121[n] and the wiring 123[n] is set to “H”, The transistor 101 is turned on, and the node NM is reset to the reset potential "RES-". At this time, the potential of the node ME2 is "(W-)-(RES+)+(R ES-)"="0". Also, the transistor 102 is turned on, and the potential of the node ME1 becomes It becomes “W+”.

[0138] At time T2, when the potential of the wiring 121[n] and the wiring 123[n] is set to "L", The transistor 101 and the transistor 102 become non-conductive, and the potential of the node NM and the node The potential of ME1 is maintained.

[0139] At time T3, negative polarity drive data “D2-[n]” is sent to wiring 124[m] and 125[m]. , "D2-[n+1]" are supplied, and the potential of the wiring 122[n] is set to "H", The transistor 103 is turned on, and the potential of the node ME2 of the pixel 10[n,m] is “D2-[n ]”. The potential of the node ME2 of the pixel 10[n+1,m] is “D2-[n+1] "

[0140] Therefore, the potential of the node NM of the pixel 10[n,m] is "(RES-) +D2-[n]”. The potential of the node NM of the pixel 10[n+1,m] is This results in "(RES-)+D2-[n+1]". Also, the node ME of pixel 10[n,m] The potential of pixel 10[n+1,m] becomes "(W+)+D2-[n]" due to capacitive coupling. ], the potential of the node NM becomes "(W+)+D2-[n+1]" due to capacitive coupling.

[0141] At time T4, the potential of the wiring 122[n] is set to "L," so that the transistor 103 is turned off. The potential of the node NM is maintained, and the display is maintained until the next frame is rewritten. This explains the behavior of the second frame.

[0142] Next, we will explain the operation in the third frame, which is a positive polarity drive.

[0143] At time T6, “RES+” is applied to the wire 126, and weight “W-” is applied to the wires 124[m] and 125[m]. " is supplied, and the potential of the wiring 122[n] and the wiring 123[n] is set to "H", The resistor 101 becomes conductive, and the node NM is reset to the reset potential "RES+". When this happens, the potential of the node ME1 becomes "(W+) + (RES+) - (RES- )"="0". Also, the transistor 103 is turned on, and the potential of the node ME2 becomes "W- "

[0144] At time T7, when the potential of the wiring 122[n] and the wiring 123[n] is set to "L", The transistor 101 and the transistor 103 become non-conductive, and the potential of the node NM and the node The potential of ME2 is maintained.

[0145] At time T8, the positive polarity drive data “D3+[n]” is sent to the wiring 124[m] and 125[m]. , "D3+[n+1]" are supplied, and the potential of the wiring 121[n] is set to "H", The transistor 102 is turned on, and the potential of the node ME1 of the pixel 10[n,m] becomes “D3+[n ]”. The potential of the node ME1 of the pixel 10[n+1,m] is “D3+[n+1] "

[0146] Therefore, the potential of the node NM of the pixel 10[n,m] is "(RES+) +D3+[n]”. The potential of the node NM of the pixel 10[n+1,m] is This results in "(RES+)+D3+[n+1]". Also, the node ME of pixel 10[n,m] The potential of pixel 10[n+1,m] becomes "(W-)+D3+[n]" due to capacitive coupling. The potential of the node NM of [n+1] is "(W-)+D3+[n+1]" due to capacitive coupling.

[0147] At time T9, the potential of the wiring 121[n] is set to “L,” so that the transistor 102 is turned off. The potential of the node NM is maintained, and the display is maintained until the next frame is rewritten. This explains the behavior of the third frame.

[0148] As mentioned above, at node NM, a high voltage is generated in the first frame, and then in the second frame, In negative polarity drive, the reset potential is maintained at "RES-" or a potential lower than that. In the third frame (positive polarity drive), the reset potential "RES+" or a higher potential is maintained. Therefore, when an OCB mode liquid crystal element is used, the bend alignment is changed to the spray alignment. The phenomenon of returning to the i orientation can be suppressed.

[0149] Although the operation has been described above with respect to a liquid crystal element having a high threshold voltage, The pixel 10 and its operation method are applicable regardless of the type of liquid crystal element. If a different operating method is used, a voltage approximately twice the output voltage of the source driver can be generated. can be applied to the liquid crystal element.

[0150] FIG. 13 shows a case where a voltage approximately twice the output voltage of the source driver 12 is applied to the pixel 10 shown in FIG. 10 is a timing chart illustrating an operation in which the voltage can be applied to the liquid crystal element 107. In this operation, the polarity inversion data of the data (D) to be written in the next frame is used as the weight (W). Also, 0V (for example, common potential) is used as the reset potential (RES). Here, the absolute values ​​of the weight (W) and data (D) are the same, and the output voltage is approximately doubled. The operation is explained below. By supplying an arbitrary weight (W) within the output range of the source driver 12, , the desired voltage can be generated.

[0151] In the signal potential supplied to the wirings 124[m] and 125[m] shown in FIG. The "D" in "D_N+[n]" stands for data, "N" stands for the frame used, and "+" stands for The signal potential is for positive polarity drive, and [n] is the signal potential of the pixel 10 for the n-th row. The polarity inversion data of the signal potential is expressed as "-(D_N+[n])". The first frame is driven with positive polarity.

[0152] At time T1, the reset potential "0V" is applied to the wiring 126[m] and the weight "-( D_N+1-[n])” and wire 125[m] has weight “-(D_N+1-[n+1])”. When the potential of the wiring 122[n] and the wiring 123[n] is set to "H", The transistor 101 is turned on, and the node NM is reset to "0V." is turned on, and the potential of the node ME2 of the pixel 10[n,m] becomes "-(D_N+1-[n])". In addition, the potential of the node ME2 of the pixel 10[n+1, m] is "-(D_N+1-[n+ 1])”.

[0153] At time T2, when the potential of the wiring 122[n] and the wiring 123[n] is set to "L", The resistor 101 and the transistor 103 become non-conductive, and the potential of the node NM of each pixel 10 and the potentials of node ME2 are maintained.

[0154] At time T3, the positive polarity drive data “D_N+[n]” is sent to the wiring 124[m] and the positive polarity drive data “D_N+[n]” is sent to the wiring 125[m]. [m] is supplied with positive polarity drive data “D_N+[n+1]” and wiring 121[ When the potential of the node of the pixel 10[n, m] is set to "H", the transistor 102 is turned on, and the node of the pixel 10[n, m] is turned on. The potential of the node ME1 becomes "D_N+[n]". The potential of E1 becomes "D_N+[n+1]".

[0155] Therefore, the potential of the node NM of the pixel 10[n,m] is higher than 0V due to capacitive coupling. However, since there is no weight writing operation in the previous frame, it is not established. The blank line is not suitable for display operations.

[0156] At time T4, the potential of the wiring 121[n] is set to "L," so that the transistor 102 is turned off. The potential of the node NM is maintained. This concludes the description of the operation of the first frame.

[0157] Next, we will explain the operation in the second frame, which is negative polarity drive.

[0158] At time T5, the reset potential “0V” is applied to the wiring 126[m] and the weight “-(D_N +2-[n])” and wire 125[m] is supplied with weight “-(D_N+2-[n+1])”. When the potentials of the wiring 121[n] and the wiring 123[n] are set to “H”, the transistor 10 1 is turned on, and the node NM is reset to the reset potential "0V."

[0159] At this time, in the pixel 10[n,m], the potential of the node ME2 becomes "- (D_N+1-[n])" Also, the transistor 102 becomes conductive, and the node ME1 The potential becomes "-(D_N+2+[n])". In addition, in the pixel 10[n+1,m], The potential of the node ME2 becomes "-(D_N+1-[n+1])" due to capacitive coupling. In addition, the potential of the node ME1 becomes "-(D_N+2+[n+1])".

[0160] At time T6, when the potential of the wiring 121[n] and the wiring 123[n] is set to "L", The transistor 102 and the transistor 103 become non-conductive, and the potential of the node NM and the node The potentials of ME1 and ME2 are maintained. At this point, the potentials of all nodes are determined.

[0161] At time T7, the negative polarity drive data “D_N+1-[ n]”, “D_N+1-[n+1]”, and “D_N+1-[n+1]”, respectively, and the potential of the wiring 122[n] is set to “H ", the transistor 103 is turned on, and the potential of the node ME2 of the pixel 10[n,m] is The potential of the node ME2 of the pixel 10[n+1,m] is It becomes “D_N+1-[n+1]”.

[0162] Therefore, the potential of the node NM of the pixel 10[n,m] is 0-(-(D_ N+1-[n])-D_N+1-[n])=2(D_N+1-[n]). The potential of node NM of element 10[n+1,m] is 0-(-(D_N+1-[ n+1])-D_N+1-[n+1])=2(D_N+1-[n+1]). That is, a voltage twice as high as the signal potential supplied as data can be supplied to the liquid crystal element 107. do.

[0163] At time T8, the potential of the wiring 122[n] is set to “L,” so that the transistor 102 is turned off. The potential of the node NM is maintained, and display continues until the next frame is rewritten. This is an explanation of the operation of the second frame.

[0164] Next, we will explain the operation in the third frame, which is a positive polarity drive.

[0165] At time T9, the reset potential “0V” is applied to the wiring 126[m] and the weight “-( D_N+3-[n])” and wire 125[m] has weight “-(D_N+3-[n+1])”. When the potential of the wiring 122[n] and the wiring 123[n] is set to "H", The transistor 101 becomes conductive, and the node NM is reset to the reset potential "0V."

[0166] At this time, in the pixel 10[n,m], the potential of the node ME1 becomes "- (D_N+2+[n])”. Also, the transistor 103 becomes conductive, and the node ME2 The potential is "-(D_N+3-[n])". In addition, in pixel 10[n+1,m], The potential of the node ME1 becomes "-(D_N+2+[n+1])" due to capacitive coupling. In addition, the potential of the node ME2 becomes "-(D_N+3-[n+1])".

[0167] At time T10, when the potential of the wiring 122[n] and the wiring 123[n] is set to "L", The transistor 101 and the transistor 103 become non-conductive, and the potential of the node NM and the The potentials of the electrodes ME2 and ME3 are maintained.

[0168] At time T11, the positive polarity drive data “D_N+2+ [n]”, “D_N+2+[n+1]”, and the potential of the wiring 121[n] is set to “ When the transistor 102 is set to H”, the potential of the node ME1 of the pixel 10[n,m] becomes becomes "D_N+2+[n]". In addition, the potential of the node ME1 of the pixel 10[n+1,m] becomes "D_N+2+[n+1]".

[0169] Therefore, the potential of the node NM of the pixel 10[n,m] is 0+(D_N+ 2+[n])-(-(D_N+2+[n])=2(D_N+2+[n]). Also, The potential of the node NM of the pixel 10[n+1,m] is 0+(D_N+2+[n +1])-(-(D_N+2+[n+1])=2(D_N+2+[n+1]). That is, it is possible to supply to the liquid crystal element 107 a voltage twice the signal potential supplied as data. can.

[0170] At time T12, when the potential of the wiring 121[n] is set to “L”, the transistor 102 is turned off. The potential of the node NM is maintained, and display continues until the next frame is rewritten. This explains the behavior of the third frame.

[0171] As described above, by using the above operation method, a voltage twice the signal potential supplied as data can be obtained. In this operation method, the voltage can be supplied to the liquid crystal element 107. The weights are rewritten without inverting the charges on both electrodes, so it operates with low power consumption. It can be made to work.

[0172] As shown in FIG. 14A, the pixel 10 has back-transistors 101, 102, and 103. FIG. 14(A) shows a configuration in which a back gate is connected to a front gate. This shows an electrically connected structure, which has the effect of increasing the on-state current. The port may be electrically connected to a wiring that can supply a constant potential. The threshold voltage of the transistor can be controlled. The transistor may also be provided with a back gate.

[0173] In addition, in a display device that is premised on performing the operation of FIG. 13, the reset potential is set to 0V (common 14B, the source potential of the transistor 101 is fixed to the The other of the source and drain may be connected to the wiring 132. 26 can be reduced, and the aperture ratio can be improved.

[0174] Next, a simulation result of the pixel 10 of the display device shown in FIG. The operation was performed on four pixels, and one side of the liquid crystal element (Clc) of one of the pixels (see FIG. 15(A)) The voltage change at node N to which the electrode is connected was calculated. The transistor size is L / W=4 μm / 4 μm (the pixel 10 has The capacitance of the capacitors C+ and C- is 500 fF, and the capacitance of the capacitor Cs is The capacitance of the liquid crystal element Clc is 100fF, and the common electrodes VCOM and TCOM are The voltage applied to the gate of the transistor was set to +15V for "H" and L” was set to -5V. SPICE was used as the circuit simulation software. there was.

[0175] FIG. 15(B) is a timing chart used in the simulation. The simulation was carried out in the order of OCB mode, etc. Operation A can maintain a certain voltage or more at the target node N, and operation B can maintain a certain voltage or more at the target node N. In the former case, "RES-" is -2V, and "RES +” is +2V, W+ is -4V, D- is -5V, W- is +4V, and D+ is +5V. The latter So, "RES-" and "RES+" are 0V, W+ is -4V, D- is -5V, W- is + 4V, D+ is +5V.

[0176] FIG. 16(A) shows the simulation results of operation A. The horizontal axis is time, and the vertical axis is the number of nodes N. The upper part of the graph indicates positive polarity operation, and the lower part indicates negative polarity operation, with 0V at the center of the graph as the boundary. In the first negative polarity operation, there is no writing to W- by the previous operation, so the voltage is low. However, in other operations, a voltage higher than the input data is output by the weight. It was also confirmed that the offset voltage "R The period during which ES+ or RES- is held can be confirmed, and the node N is kept at a certain voltage or higher. From this result, it was confirmed that when an OCB mode liquid crystal element is used, It was verified that in this case, it is possible to suppress the return from the bend alignment to the splay alignment.

[0177] FIG. 16(B) shows the simulation results of operation B. As with operation A, the initial negative polarity In operation, the voltage is low because there is no writing of W- by the previous operation. In other operations, it was confirmed that a voltage higher than the input data was output. In addition, it is confirmed that the weights can be maintained even after the period when the polarity operation changes in operations A and B. I was able to confirm this.

[0178] In addition, using the timing chart shown in FIG. 17, a high voltage is applied to the pixel shown in FIG. 15(A). The operation was verified by using three capacitance elements C+, C-, and Cs. This is the operation of raising the potential of node N. Here, SVDD is +5V and SVSS is -5V. The simulation results are shown in Figure 18. By performing this operation, the S It was confirmed that a voltage nearly three times higher than VDD could be obtained. It was verified that bend alignment was possible when a liquid crystal element was used.

[0179] The above simulation results confirmed the effect of one aspect of the present invention.

[0180] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0181] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal element will be described. In this embodiment, the description of the elements, operations, and functions of the display device described in the first embodiment will be omitted. Abbreviated.

[0182] 19A to 19C show the structure of a display device to which one embodiment of the present invention can be applied. Figure.

[0183] In FIG. 19A, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display portion 215 is attached to the sealant 4005 and the second substrate 4. Sealed by 006.

[0184] The display portion 215 can be provided with the pixel 10 described in Embodiment 1. The scanning line driver circuit, which will be explained below, corresponds to the gate driver, and the signal line driver circuit corresponds to the source driver. do.

[0185] In FIG. 19A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline The common line driving circuit 241a is made of a semiconductor. , 132, 133, etc., have the function of supplying a specified potential.

[0186] The scanning line driving circuit 221a, the common line driving circuit 241a, the signal line driving circuit 231a, and the signal Various signals and potentials given to the signal line driving circuit 232a are transmitted through an FPC (Flexible Printed Circuit). Powered by BLE Printed Circuit) 4018.

[0187] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 included in the drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. It is implemented in a different area from the area where it is installed.

[0188] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0189] FIG. 19(B) shows an integrated circuit included in the signal line driver circuit 231a and the signal line driver circuit 232a. The circuit 4042 is implemented by the COG method. The display unit 215 and the display unit 216 can be integrally formed on the same substrate to form a system-on-panel. Cut.

[0190] In FIG. 19B, the scanning line driving circuit 221a and the common line driving circuit 241a are connected to the display unit 2. 15. The driving circuit is formed on the same substrate as the pixel circuit in the display unit 215. By forming the parts at the same time, the number of parts can be reduced, which increases productivity. can.

[0191] In FIG. 19B, the display portion 215 provided on the first substrate 4001 and the scanning line driver A sealant 4005 is provided to surround the common line driving circuit 221a and the common line driving circuit 241a. In addition, a display unit 215, a scanning line driving circuit 221a, and a common line driving circuit The second substrate 4006 is provided on the display unit 215, the scanning line driver 241a. The driving circuit 221a and the common line driving circuit 241a are mounted on the first substrate 4001 and the sealing material 40. The display element is sealed by the second substrate 4005 and the second substrate 4006 .

[0192] In addition, in FIG. 19B, the signal line driver circuit 231a and the signal line driver circuit 232a are separately 4001 and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as part of the signal line driver circuit or the scanning line driver circuit. A part of the driver circuit may be formed separately and mounted. The signal line driving circuit 231a and the signal line driving circuit 232a are formed on the same substrate as the display unit 215. That's fine.

[0193] The display device also includes a panel in which a display element is sealed, and a controller for the panel. This may also include a module in which an IC or the like including the above is mounted.

[0194] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment can be used as the transistor. can be done.

[0195] The structure of the transistors in the peripheral driver circuits and the pixel circuits in the display area is The transistors in the peripheral driver circuit may be the same or different. The transistors may have the same structure, or may have two or more types of transistor structures. Similarly, the transistors in the pixel circuit may all have the same structure. Alternatively, the semiconductor device may have two or more transistor structures.

[0196] In addition, an input device 4200 can be provided over the second substrate 4006. The display device shown in any one of (a) to (c) provided with an input device 4200 functions as a touch panel. It can be done.

[0197] There is no limitation on the detection elements (also referred to as sensor elements) included in the touch panel of one embodiment of the present invention. We offer a variety of sensors that can detect the proximity or contact of a finger, stylus, or other object. , can be applied as a sensing element.

[0198] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods can be used, such as a pressure-sensitive method, an optical method, or the like.

[0199] In this embodiment, a touch panel having a capacitance type detection element will be described as an example. .

[0200] The capacitance type includes a surface capacitance type, a projected capacitance type, etc. The capacitance type includes the self-capacitance type and the mutual capacitance type. This is preferable because it enables simultaneous multi-point detection.

[0201] The touch panel of one embodiment of the present invention is formed by bonding a display device and a sensing element that are separately manufactured. A detector element is formed on one or both of a substrate supporting a display element and an opposing substrate. Various configurations can be applied, such as a configuration in which electrodes or the like are provided.

[0202] 20(A) and (B) show examples of touch panels. FIG. 20(A) shows a touch panel 4 20(B) is a perspective view of the input device 4200. For clarity, only representative components are shown.

[0203] The touch panel 4210 is made by bonding a display device and a sensing element that are separately manufactured. be.

[0204] The touch panel 4210 has an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0205] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 4237. , a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wires 4239. and electrically connects to each of the plurality of wirings 4238. 3b can be provided.

[0206] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In this case, in addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also available. may be applied.

[0207] FIG. 21 is a cross-sectional view of the portion indicated by the chain line N1-N2 in FIG. 19(B). The display device has electrodes 4015, and the electrodes 4015 are connected to terminals of the FPC 4018. The electrodes 40 are electrically connected via an anisotropic conductive layer 4019. In addition, in FIG. 15 is formed in the openings formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110. The wiring 4014 is electrically connected to the wiring 4014 .

[0208] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The same conductive layer is used.

[0209] The display portion 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are In FIG. 21, the display unit 215 includes a transistor 401. 0 and a transistor 4011 included in the scanning line driver circuit 221a. In FIG. 21, the transistors 4010 and 4011 are bottom gate Although a top-gate transistor is shown as an example, a top-gate transistor may also be used.

[0210] In FIG. 21, an insulating layer 4112 is provided on the transistor 4010 and the transistor 4011. It is being used.

[0211] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The electrode 4017 is formed on the semiconductor substrate 401. The electrode 4017 functions as a back gate electrode. It is possible.

[0212] The display device shown in FIG. 21 further includes a capacitor 4020. The electrode 4021 formed in the same process as the gate electrode of the transistor 4010, and the source electrode and The gate electrode and the drain electrode are formed in the same process. Overlapping via 103.

[0213] Generally, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set to be able to hold charge for a predetermined period, taking into consideration factors such as leakage current of the capacitor. The capacitance of the capacitor may be set in consideration of the off-state current of the transistor.

[0214] The transistor 4010 provided in the display portion 215 is electrically connected to a display element. is an example of a liquid crystal display device using a liquid crystal element as a display element. The liquid crystal element 4013 includes a first electrode layer 4030, a second electrode layer 4031, and a The liquid crystal layer 4008 is sandwiched between insulating layers that function as alignment layers. The second electrode layer 4031 is formed on the second substrate 4 The first electrode layer 4030 and the second electrode layer 4031 are provided on the liquid crystal layer 4008 side. The signals are superimposed via the

[0215] As the liquid crystal element 4013, liquid crystal elements to which various modes are applied can be used. For example, VA (Vertical Alignment) mode, TN (Twisted Nematic (IPS) mode, In-Plane-Switching (IPS) mode, A SM(Axially Symmetrically aligned Micro-cell) Mode, OCB (Optically Compensated Bend) Mode, F LC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, EC B(Electrically Controlled Birefringence) Use of LCD elements that use mode, VA-IPS mode, guest host mode, etc. can be done.

[0216] In addition, the liquid crystal display device shown in this embodiment may be a normally black liquid crystal display device, for example. A transmissive liquid crystal display device employing a vertical alignment (VA) mode may also be used. The code is MVA (Multi-Domain Vertical Alignment) nt) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc. can.

[0217] The liquid crystal element is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. The optical modulation effect of liquid crystals is due to the electric field (horizontal electric field, vertical electric field or The liquid crystal used in the liquid crystal element is thermoelectric. ropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC) Dispersed Liquid Crystal, Ferroelectric Liquid Crystal, Antiferroelectric Liquid Crystal These liquid crystal materials can exhibit a cholesteric phase, a smectic phase, etc. depending on the conditions. These phases include nematic, cubic, chiral nematic, and isotropic phases.

[0218] Although an example of a display device having a vertical electric field type liquid crystal element is shown in FIG. 21, In the case of the display device, a display device having a liquid crystal element of the horizontal electric field type can be applied. In this case, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of cholesteric liquid crystal is increased, the phase transition occurs from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is difficult to narrow the temperature range. In order to improve the liquid crystal layer 4008, a liquid crystal composition containing 5% by weight or more of a chiral agent is used. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time and is optically The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is subjected to an alignment treatment. Since no alignment film is required, the viewing angle dependency is small. This eliminates the need for rubbing, preventing electrostatic damage caused by rubbing. This can reduce defects or damage to the liquid crystal display device during the manufacturing process.

[0219] The spacers 4035 are columnar spacers obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0220] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, an anti-reflection member, etc. may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. A backlight, a sidelight, or the like may be used. Micro LEDs or the like may be used as the light.

[0221] In the display device shown in FIG. 21, a light-shielding layer 413 is provided between the substrate 4006 and the second electrode layer 4031. 2, a colored layer 4131 and an insulating layer 4133 are provided.

[0222] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, Examples of the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film made of an inorganic material such as a metal. For example, a laminated film of a film containing a material of a colored layer may be used as the light-shielding layer. A film containing a material used for a color layer that transmits light of a certain color and a material used for a color layer that transmits light of another color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0223] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, and dyes. The light-shielding layer and the colored layer may be formed by, for example, an ink-jet method. It can be formed using:

[0224] 21 also includes an insulating layer 4111 and an insulating layer 4104. The insulating layer 411 and the insulating layer 4104 are formed using an insulating layer that is not easily permeated by impurity elements. The semiconductor layer of the transistor is sandwiched between the insulating layer 4104 and the insulating layer 4105, which prevents impurities from entering from the outside. It can be prevented.

[0225] In addition, since transistors are easily damaged by static electricity, a protection circuit for protecting the drive circuit is required. It is preferable that the protection circuit is configured using a non-linear element.

[0226] As shown in FIG. 22, the transistors and the capacitors are arranged so as to have an overlapping region in the height direction. For example, the transistor 4011 and the transistor 4020 which form the driver circuit may be By overlapping the transistor 4021 and the transistor 4022, a display device with a narrow frame can be obtained. The pixel circuit is made up of a transistor 4010, a transistor 4023, a capacitor element 402, and a If the pixels are arranged so that they overlap even partially, the aperture ratio and resolution can be improved. can be done.

[0227] In addition, in the pixel circuit, a transparent conductive film with high transparency to visible light is used for the electrodes and wiring. By doing so, it is possible to increase the light transmittance within the pixel, and it is possible to substantially improve the aperture ratio. In addition, when an OS transistor is used, the semiconductor layer also has a light-transmitting property. This allows for an increased aperture ratio. This is especially useful when transistors are not stacked. It is also effective in

[0228] Furthermore, a display device may be configured by combining a liquid crystal display device and a light emitting device.

[0229] The light emitting device is disposed on the opposite side of the display surface or at the edge of the display surface. The light-emitting device can also be called a backlight.

[0230] Here, the light emitting device is a plate-shaped or sheet-shaped light guide part (also called a light guide plate) and a light source that emits light of different colors. The light emitting element may be disposed near a side surface of the light guide portion. Then, light can be emitted from the side of the light guide to the inside. The light guide has a mechanism to change the light path ( This allows the light-emitting device to emit light to the pixel area of ​​the display panel. Alternatively, a light-emitting device can be placed directly under the pixel without providing a light guide section. It may also be configured to place

[0231] The light emitting device preferably has light emitting elements of three colors: red (R), green (G), and blue (B). Furthermore, it may have a white (W) light emitting element. It is preferable to use an LED (Light Emitting Diode). .

[0232] Furthermore, the light emitting element has a full width at half maximum (FWHM) of its emission spectrum. at Half Maximum) is 50 nm or less, preferably 40 nm or less, more preferably Preferably, the diameter is 30 nm or less, more preferably 20 nm or less, and the color purity is extremely high. It is preferable that the full width at half maximum of the emission spectrum is as small as possible. However, it can be set to, for example, 1 nm or more. It is possible to produce a vivid display with high color reproducibility.

[0233] In addition, the red light emitting element has a peak wavelength of 625 nm or more and 650 nm or less in the emission spectrum. It is preferable to use an element located within the range below. Use an element whose spectral peak wavelength is in the range of 515 nm to 540 nm. It is preferable that the blue light emitting element has an emission spectrum with a peak wavelength of 445 nm or more. It is preferable to use elements that lie within the 70 nm range or less.

[0234] The display device sequentially blinks the three color light emitting elements and drives the pixels in synchronization with this. The color display can be performed based on the sequential additive color mixing method. This can also be called sequential driving.

[0235] Field sequential driving allows for the display of vivid color images. By using the above driving method, it is possible to display smooth moving images. It is not necessary to configure a pixel with multiple sub-pixels of different colors, and the effective reflective area of ​​one pixel (effective surface area) The display area (also called the aperture ratio) can be increased, allowing for brighter displays. Since there is no need to provide a color filter to the pixel, the transmittance of the pixel can also be improved. Furthermore, the manufacturing process can be simplified and the manufacturing cost can be reduced. can be reduced.

[0236] 23(A) and 23(B) are schematic cross-sectional views of a display device capable of field sequential driving. The display device has a backlight on the substrate 4001 side that can emit light in each of the RGB colors. In field sequential driving, the time division of each RGB color is Since colors are expressed by split light, color filters are not required.

[0237] The backlight unit 4340a shown in FIG. 23(A) has a diffusion plate 4352 directly below the pixels. The light emitting element 4342 is provided in a plurality of layers. 42 to the substrate 4001 side, and the function of diffusing the light emitted from the substrate 4001 side to make the brightness uniform within the display surface. A polarizing plate may be provided between the light emitting element 4342 and the diffusion plate 4352 as needed. In addition, the diffusion plate 4352 may not be provided if it is not necessary. It may be omitted.

[0238] The backlight unit 4340a can be equipped with many light-emitting elements 4342. In addition, a light guide plate is not required, and the light efficiency of the light emitting element 4342 is If necessary, the light emitting element 4342 may be provided with a lens 43 for diffusing light. 44 may be provided.

[0239] The backlight unit 4340b shown in FIG. 23(B) has a diffusion plate 4352 directly below the pixels. The light guide plate 4341 is provided at the end of the light guide plate 4341. The light guide plate 4341 has an uneven shape on the side opposite to the diffusion plate 4352. The guided light can be scattered by the uneven surface and emitted in the direction of the diffusion plate 4352.

[0240] The light emitting element 4342 can be fixed to a printed circuit board 4347. ), the light emitting elements 4342 of each color of RGB are shown overlapping, but The light emitting elements 4342 of each color B can be arranged side by side. A reflective layer 4348 that reflects visible light is provided on the side opposite to the light emitting element 4342. It is okay to do so.

[0241] The backlight unit 4340b can reduce the number of light-emitting elements 4342. It can be made low cost and thin.

[0242] The liquid crystal element may be a light-scattering type liquid crystal element. It is preferable to use an element having a composite material of a liquid crystal and a polymer. For example, a polymer dispersed liquid crystal Alternatively, a polymer network liquid crystal (PNLC) A liquid crystal (LC) element may also be used.

[0243] The light-scattering liquid crystal element is a liquid crystal layer in a three-dimensional network structure of a resin part sandwiched between a pair of electrodes. The liquid crystal part is made of a material such as nematic liquid crystal. The resin portion can be made of a photo-curable resin. For example, monofunctional monomers such as acrylates and methacrylates, diacrylates, triacrylates, Multifunctional monomers such as acrylates, dimethacrylates, trimethacrylates, or A polymerizable compound in which these are mixed can be used.

[0244] Light-scattering liquid crystal elements utilize the anisotropy of the refractive index of the liquid crystal material to transmit or scatter light. The resin portion may also have anisotropy in refractive index. When the liquid crystal molecules are aligned in a certain direction according to the voltage applied to the element, the refraction of the liquid crystal part and the resin part A direction occurs in which the difference in the refractive index becomes smaller, and the light incident along this direction is scattered by the liquid crystal section. Therefore, the light-scattering liquid crystal element is visually perceived as transparent from this direction. On the other hand, when the alignment of the liquid crystal molecules becomes random according to the applied voltage, the liquid crystal part and the resin Since there is no significant change in the refractive index difference between the liquid crystal and the liquid crystal, the incident light is scattered by the liquid crystal. Therefore, the light-scattering liquid crystal element remains opaque regardless of the viewing direction.

[0245] FIG. 24(A) shows a case where the liquid crystal element 4013 of the display device of FIG. 23(A) is replaced with a light scattering type liquid crystal element 401. The light scattering type liquid crystal element 4016 has a liquid crystal portion and a resin portion. The field sequencer includes a composite layer 4009 and electrode layers 4030 and 4031. The elements related to the drive are the same as those in FIG. 23(A), but a light scattering type liquid crystal element 4016 is used. In this case, the alignment film and the polarizing plate are not required. 1, but may be columnar.

[0246] FIG. 24(B) shows a case where the liquid crystal element 4013 of the display device of FIG. 23(B) is replaced with a light scattering type liquid crystal element 401 24(B), the light scattering type liquid crystal element 4016 is replaced with a voltage It operates in a mode where it transmits light when no voltage is applied and scatters light when a voltage is applied. By adopting this configuration, the normal state (the state where no display is made) ) can be used to make a transparent display device. In this case, when the light scattering operation is performed, It is possible to display in color.

[0247] Modified examples of the display device shown in FIG. 24(B) are shown in FIGS. 25(A) to 25(E). In A) to E), for clarity, some elements of FIG. 25(B) are used, and other elements are is omitted and shown in the figure.

[0248] 25(A) shows a structure in which the substrate 4001 functions as a light guide plate. The outer surface of the light guide plate may be provided with an uneven shape. In addition, there is no attenuation of light due to the light guide plate. Therefore, the light emitted from the light emitting element 4342 can be used efficiently.

[0249] FIG. 25(B) shows a configuration in which light is incident from the vicinity of the end of the composite layer 4009. The total reflection at the interface between the composite layer 4009 and the substrate 4001 is By using the resin of the composite layer 4009, light can be emitted from the light-scattering liquid crystal element to the outside. The portion is made of a material having a refractive index greater than that of the substrate 4001 and the substrate 4006 .

[0250] Note that the light-emitting element 4342 may be provided not only on one side of the display device but also on the other side as shown in FIG. Alternatively, the light emitting element 43 may be provided on two sides facing each other. Furthermore, the light emitting element 43 may be provided on three or four sides. By providing 42 on multiple sides, it is possible to compensate for light attenuation and support large-area display elements. It is possible.

[0251] FIG. 25(D) shows a display device in which light emitted from a light emitting element 4342 passes through a mirror 4345. This configuration makes it easier to guide light to the display device from a certain angle. Therefore, total internal reflection can be efficiently achieved.

[0252] FIG. 25(E) shows a configuration having a stack of layers 4003 and 4004 on a composite layer 4009. One of the layer 4003 and the layer 4004 is a support such as a glass substrate, and the other is an inorganic The composite layer 40 may be formed of a film, an organic resin coating film, or a similar material. The resin portion of the layer 4009 is made of a material having a refractive index greater than that of the layer 4004. The layer 4002 uses a material having a refractive index higher than that of the layer 4003 .

[0253] A first interface is formed between composite layer 4009 and layer 4004, and layer 4004 and layer 400 A second interface is formed between the first interface and the second interface. The light that passes through can be totally reflected at the second interface and returned to the composite layer 4009. Therefore, the light emitted by the light emitting element 4342 can be used efficiently.

[0254] The configurations in FIG. 24(B) and FIG. 25(A) to (E) can be combined with each other. can be done.

[0255] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0256] (Embodiment 3) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be used will be described with reference to the drawings.

[0257] The display device of one embodiment of the present invention includes a bottom-gate transistor and a top-gate transistor. The present invention can be fabricated using various types of transistors, such as a transistor having a MOSFET. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0258] [Bottom-gate transistor] FIG. 26(A1) shows a channel protection transistor, which is a type of bottom gate transistor. 26(A1) is a cross-sectional view of the transistor 810 in the channel length direction. The transistor 810 is formed on the substrate 771. The electrode 746 is provided with an insulating layer 772 interposed therebetween. The semiconductor layer 742 is provided. The electrode 746 can function as a gate electrode. The insulating layer 726 is provided as a gate electrode. It can function as a gate insulating layer.

[0259] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. Electrodes 744a and 744b are provided on the insulating layer 726 in contact with a portion of the insulating layer 726. 744a can function as either a source or drain electrode. It can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0260] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs when the electrode 744a and the electrode 744b are formed can be prevented. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor with good electrical characteristics can be realized.

[0261] The transistor 810 includes an electrode 744a, an electrode 744b, and an insulating layer 741. The insulating layer 729 is disposed on the insulating layer 728 .

[0262] When an oxide semiconductor is used for the semiconductor layer 742, at least one of the electrodes 744a and 744b At least in the area in contact with the semiconductor layer 742, oxygen is taken from a part of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material that can generate oxygen vacancies in the semiconductor layer 742. The carrier concentration in the resulting region increases, and the region becomes n-type. + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742, and oxygen vacancies are eliminated. Examples of materials that can be used include tungsten and titanium. do.

[0263] The source and drain regions are formed in the semiconductor layer 742, forming an electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0264] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b, as an n-type semiconductor or a p-type semiconductor. It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0265] The insulating layer 729 has a function of preventing or reducing diffusion of impurities into the transistor from the outside. It is preferable to form the insulating layer 729 using a material having the above structure. You can also do this.

[0266] The transistor 811 shown in FIG. 26A2 has a back gate electrode over the insulating layer 729. The transistor 810 differs from the transistor 810 in that it has a functioning electrode 723. The electrode 723 is an electrode It can be formed using the same materials and methods as 746.

[0267] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can be made to function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the gate electrode, the threshold voltage of the transistor can be controlled. The voltage can be varied to any desired value.

[0268] In addition, both the electrode 746 and the electrode 723 can function as gate electrodes. Therefore, the insulating layer 726, the insulating layer 728, and the insulating layer 729 are gate insulating layers. The electrode 723 can function as a layer between the insulating layer 728 and the insulating layer 729. It may also be provided in.

[0269] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as a "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0270] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, the electrode 74 6 and the electrode 723 are set to the same potential, the region where carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility also increases.

[0271] Therefore, the transistor 811 is a transistor having a large on-state current relative to its area. That is, the area occupied by the transistor 811 is set to According to one embodiment of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0272] In addition, since the gate electrode and back gate electrode are formed from a conductive layer, they can be The function of preventing the electric field generated from acting on the semiconductor layer where the channel is formed (especially static electricity The back gate electrode has an electric field shielding function against the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0273] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This prevents light from entering the semiconductor layer from the side. This can prevent degradation of electrical characteristics such as a shift in the threshold voltage of the transistor. .

[0274] According to one embodiment of the present invention, a highly reliable transistor can be provided. A highly reliable semiconductor device can be realized.

[0275] FIG. 26(B1) shows a channel protection type transistor 82 having a different configuration from that shown in FIG. 26(A1). 8 is a cross-sectional view of the transistor 820 in the channel length direction. It has a similar structure, but differs in that an insulating layer 741 covers the edge of a semiconductor layer 742. In addition, an opening formed by selectively removing a part of the insulating layer 741 that overlaps the semiconductor layer 742 In this portion, the semiconductor layer 742 and the electrode 744a are electrically connected. In another opening formed by selectively removing a portion of the insulating layer 741 that overlaps with the semiconductor layer 42, The insulating layer 741 is electrically connected to the electrode 744b. The overlapping region can function as a channel protection layer.

[0276] The transistor 821 shown in FIG. 26B2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0277] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, when forming the electrode 744a and the electrode 744b, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0278] Also, the transistors 820 and 821 are the same as the transistors 810 and 821. The distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are smaller than the distance between the electrode 744a and the electrode 746 and the electrode 744b. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 is In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0279] Figure 26(C1) shows a channel-etched type, which is one of the bottom-gate type transistors. 1 is a cross-sectional view of a transistor 825 in the channel length direction. Electrodes 744a and 744b are formed without using 41. In addition, a part of the semiconductor layer 742 that is exposed during the formation of the electrode 744b may be etched. On the other hand, since the insulating layer 729 is not provided, productivity of the transistor can be increased.

[0280] The transistor 826 shown in FIG. 26C2 has a back gate electrode over the insulating layer 729. It differs from transistor 825 in that it has a functioning electrode 723 .

[0281] 27(A1) to (C2) show transistors 810, 811, 820, 821, 825, 826 are cross-sectional views in the channel width direction.

[0282] In the structures shown in FIGS. 27(B2) and (C2), the gate electrode and the back gate electrode are connected. The gate electrode and the back gate electrode have the same potential. The gate electrode is sandwiched between the gate electrode and the back gate electrode.

[0283] The length of each of the gate electrode and the back gate electrode in the channel width direction is 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is 726, 741, 728, and 729 are sandwiched between the gate electrode or the back gate electrode. It is a structure that

[0284] With this structure, the semiconductor layer 742 included in the transistor can be used as a gate electrode and a barrier layer. The gate electrode can be electrically surrounded by the electric field of the gate electrode.

[0285] Like the transistor 821 or the transistor 826, the gate electrode and the back gate The electric field of the electrode electrically surrounds the semiconductor layer 742 in which the channel formation region is to be formed. The device structure of the transistor is called the Surrounded channel (S-channel el) structure.

[0286] By using an S-channel structure, either one of the gate electrode and the back gate electrode By both, an electric field is effectively applied to the semiconductor layer 742 to induce a channel. This improves the current driving capability of the transistor and makes it possible to obtain high on-current characteristics. In addition, since it is possible to increase the on-current, it is possible to miniaturize transistors. In addition, the S-channel structure allows for mechanical Strength can be increased.

[0287] [Top-gate transistor] The transistor 842 illustrated in FIG. 28A1 is a top-gate transistor. The transistor 842 is formed by forming the insulating layer 729 and then forming the electrode 744a and the electrode 744b. The transistor 830 and the transistor 840 differ from each other in that the electrode 744a is formed. The electrode 744b is formed by a semiconductor layer in an opening formed in the insulating layer 728 and the insulating layer 729. The conductive layer 742 is electrically connected to the conductive layer 742.

[0288] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the electrode 746 and the remaining insulating layer 726 as a mask, an impurity 755 is introduced into the semiconductor layer 742, The impurity region can be formed in a self-aligned manner in 742. Transistor 842 has an area where insulating layer 726 extends beyond the edge of electrode 746 . The impurity concentration in the region of the semiconductor layer 742 into which the impurity 755 is introduced via the insulating layer 726 is The area is smaller than the area where the impurity 755 is introduced without the insulating layer 726. The layer 742 is provided with a lightly doped dielectric layer (LDD) in an area that does not overlap with the electrode 746. rain) region is formed.

[0289] The transistor 843 shown in FIG. 28A2 has the electrode 723. 2. The transistor 843 has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. can function as a back gate electrode.

[0290] In addition, the transistor 844 shown in FIG. 28(B1) and the transistor 845 shown in FIG. 28(B2) As in the case of the electrode 845, the insulating layer 726 in the area that does not overlap with the electrode 746 may be entirely removed. In addition, the transistor 846 shown in FIG. 28(C1) and the transistor shown in FIG. 28(C2) The insulating layer 726 may remain, as may the insulating layer 847.

[0291] The transistors 842 to 847 are also formed with the electrode 746. As a result, the semiconductor layer 742 is doped with impurities 755 using the mask. According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner. Furthermore, according to one aspect of the present invention, a transistor with good integration properties can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0292] In FIGS. 29(A1) to 29(C2), transistors 842, 843, 844, 845, and 846 are shown. 847 are cross-sectional views in the channel width direction.

[0293] The transistors 843, 845, and 847 are respectively However, the present invention is not limited to this, and the transistor 84 may have an S-channel structure. 3. Transistor 845 and transistor 847 should not be of S-channel structure. That's fine.

[0294] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible.

[0295] (Fourth embodiment) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproduction device equipped with a recording medium, a mobile phone, a mobile phone Game consoles, including those with a camcorder, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copying machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of these electronic devices are shown in Figure 30.

[0296] FIG. 30(A) shows a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, and a microphone 964. 63, speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 9 By using the display device of one embodiment of the present invention for the display portion 965, various images can be displayed. The following display can be performed.

[0297] FIG. 30(B) shows a digital signage having a large display unit 922. The display device of one embodiment of the present invention is used for the display portion 922. Therefore, a high-quality display can be achieved.

[0298] FIG. 30C shows an example of a mobile phone, which includes a housing 951, a display unit 952, an operation button 953, It has an external connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The mobile phone has a touch sensor on the display unit 952. All operations such as touching the display 952 with a finger or a stylus are performed. The housing 951 and the display unit 952 are flexible and can be folded as shown in the figure. By using the display device of one embodiment of the present invention for the display portion 952, A variety of images can be displayed.

[0299] FIG. 30(D) shows a video camera, which includes a first housing 901, a second housing 902, a display unit 903, The operation key 904, the lens 905, the connection part 906, the speaker 907, etc. The lens 904 and the lens 905 are provided in the first housing 901, and the display unit 903 is provided in the second housing 902. By using the display device of one embodiment of the present invention for the display portion 903, various It is possible to display a clear image.

[0300] FIG. 30(E) shows a television, which includes a housing 971, a display unit 973, operation keys 974, and a speaker 975. 75, a communication connection terminal 976, an optical sensor 977, etc. The display device of one embodiment of the present invention is provided in the display portion 973. By using this, various images can be displayed.

[0301] FIG. 30(F) shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera, and a camera body. The display unit 912 has a touch panel function for inputting and outputting information. By using the display device of one embodiment of the present invention for the display portion 912, various images can be displayed. The following display can be performed.

[0302] This embodiment mode can be implemented by appropriately combining with the configurations described in other embodiment modes. It is possible. [Explanation of symbols]

[0303] 10: pixel, 11: circuit block, 12: source driver, 13: gate driver, 14 : selection circuit, 15: power supply circuit, 101: transistor, 102: transistor, 103: Transistor, 104: Capacitor, 105: Capacitor, 106: Capacitor, 107: Liquid crystal Element, 110: circuit block, 121: wiring, 122: wiring, 123: wiring, 124: wiring Wire, 125: Wiring, 126: Wiring, 127: Wiring, 128: Wiring, 132: Wiring, 133 : wiring, 215: display unit, 221a: scanning line driving circuit, 231a: signal line driving circuit, 23 2a: signal line driving circuit, 241a: common line driving circuit, 723: electrode, 726: insulating layer, 7 28: insulating layer, 729: insulating layer, 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 755: impurity, 771: substrate, 772: insulating layer, 81 0: transistor, 811: transistor, 820: transistor, 821: transistor 825: transistor, 826: transistor, 830: transistor, 840: Transistor, 842: Transistor, 843: Transistor, 844: Transistor, 8 45: Transistor, 846: Transistor, 847: Transistor, 901: Housing, 9 02: Housing, 903: Display, 904: Operation keys, 905: Lens, 906: Connection part, 9 07: Speaker, 911: Housing, 912: Display, 913: Speaker, 919: Camera, 921: Pillar, 922: Display unit, 951: Housing, 952: Display unit, 953: Operation button, 9 54: External connection port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: shutter button, 963: microphone, 965: display, 966: operation keys ,967:Speaker,968:Zoom lever,969:Lens,971:Housing,973: Display unit, 974: operation keys, 975: speaker, 976: communication connection terminal, 977: optical sensor 4001: substrate, 4003: layer, 4004: layer, 4005: sealing material, 4006: Substrate, 4008: liquid crystal layer, 4009: composite layer, 4010: transistor, 4011: transistor Transistor, 4013: Liquid crystal element, 4014: Wiring, 4015: Electrode, 4016: Light scattering type Liquid crystal element, 4017: electrode, 4018: FPC, 4019: anisotropic conductive layer, 4020: container Quantum element, 4021: electrode, 4022: transistor, 4023: transistor, 4030 : electrode layer, 4031: electrode layer, 4032: insulating layer, 4033: insulating layer, 4035: spacer 4041: printed circuit board, 4042: integrated circuit, 4102: insulating layer, 4103: insulation layer, 4104: insulating layer, 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 41 31: Coloring layer, 4132: Light-shielding layer, 4133: Insulating layer, 4200: Input device, 4210: Touch panel, 4227: electrode, 4228: electrode, 4237: wiring, 4238: wiring, 4 239: Wiring, 4263: Board, 4272b: FPC, 4273b: IC, 4340a: Backlight unit, 4340b: Backlight unit, 4341: Light guide plate, 434 2: Light-emitting element, 4344: Lens, 4345: Mirror, 4347: Printed circuit board, 434 8: Reflective layer, 4352: Diffuser

Claims

1. The pixel includes first to fourth pixels and first to sixth wirings, the first pixel is adjacent to the third pixel in a first direction in which the first to third wirings extend, and is adjacent to the second pixel in a second direction in which the fourth wiring and the fifth wirings extend; the fourth pixel is adjacent to the second pixel in the first direction and adjacent to the third pixel in the second direction; each of the first to fourth pixels includes a first transistor, a first memory, a second memory, and a liquid crystal element; the first memory includes a second transistor and a first capacitance element; the second memory includes a third transistor and a second capacitive element; In each of the first pixel and the second pixel, a gate of the first transistor electrically connected to the first wiring; one of the source and the drain of the first transistor is electrically connected to the sixth wiring; the other of the source and the drain of the first transistor is electrically connected to one electrode of the liquid crystal element; a gate of the second transistor electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to one electrode of the liquid crystal element via the first capacitor element; a gate of the third transistor electrically connected to the third wiring; one of a source and a drain of the third transistor is electrically connected to one electrode of the liquid crystal element via the second capacitor element; In the first pixel, the other of the source and the drain of the second transistor is electrically connected to the fourth wiring; the other of the source and the drain of the third transistor is electrically connected to the fifth wiring; In the second pixel, the other of the source and the drain of the second transistor is electrically connected to the fifth wiring; the other of the source and the drain of the third transistor is electrically connected to the fourth wiring.

2. The pixel includes first to fourth pixels and first to sixth wirings, the first pixel is adjacent to the third pixel in a first direction in which the first to third wirings extend, and is adjacent to the second pixel in a second direction in which the fourth wiring and the fifth wirings extend; the fourth pixel is adjacent to the second pixel in the first direction and adjacent to the third pixel in the second direction; each of the first to fourth pixels includes a first transistor, a first memory, a second memory, and a liquid crystal element; the first memory includes a second transistor and a first capacitance element; the second memory includes a third transistor and a second capacitive element; In each of the first pixel and the second pixel, a gate of the first transistor electrically connected to the first wiring; one of the source and the drain of the first transistor is electrically connected to the sixth wiring; the other of the source and the drain of the first transistor is electrically connected to one electrode of the liquid crystal element; a gate of the second transistor electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to one electrode of the liquid crystal element via the first capacitor element; a gate of the third transistor electrically connected to the third wiring; one of a source and a drain of the third transistor is electrically connected to one electrode of the liquid crystal element via the second capacitor element; In the first pixel, the other of the source and the drain of the second transistor is electrically connected to the fourth wiring; the other of the source and the drain of the third transistor is electrically connected to the fifth wiring; In the second pixel, the other of the source and the drain of the second transistor is electrically connected to the fifth wiring; the other of the source and the drain of the third transistor is electrically connected to the fourth wiring; a display device in which each of the first to third transistors has a channel formation region formed of an oxide semiconductor;

3. The pixel includes first to fourth pixels and first to sixth wirings, the first pixel is adjacent to the third pixel in a first direction in which the first to third wirings extend, and is adjacent to the second pixel in a second direction in which the fourth wiring and the fifth wirings extend; the fourth pixel is adjacent to the second pixel in the first direction and adjacent to the third pixel in the second direction; each of the first to fourth pixels includes a first transistor, a first memory, a second memory, and a liquid crystal element; the first memory includes a second transistor and a first capacitance element; the second memory includes a third transistor and a second capacitive element; In each of the first pixel and the second pixel, a gate of the first transistor electrically connected to the first wiring; one of the source and the drain of the first transistor is electrically connected to the sixth wiring; the other of the source and the drain of the first transistor is electrically connected to one electrode of the liquid crystal element; a gate of the second transistor electrically connected to the second wiring; one of a source and a drain of the second transistor is electrically connected to one electrode of the liquid crystal element via the first capacitor element; a gate of the third transistor electrically connected to the third wiring; one of a source and a drain of the third transistor is electrically connected to one electrode of the liquid crystal element via the second capacitor element; In the first pixel, the other of the source and the drain of the second transistor is electrically connected to the fourth wiring; the other of the source and the drain of the third transistor is electrically connected to the fifth wiring; In the second pixel, the other of the source and the drain of the second transistor is electrically connected to the fifth wiring; the other of the source and the drain of the third transistor is electrically connected to the fourth wiring; a first transistor, a second transistor, and a third transistor;

Images