Indication device

Abstract

To reduce abnormal driving of the sub pixels.SOLUTION: A display device according to one embodiment of the present disclosure comprises a plurality of sub pixels, a plurality of data lines electrically connected to each of the plurality of sub pixels, and a multiplexer circuit electrically connected to a pair of adjacent data lines among the plurality of data lines, the multiplexer circuit comprising a charge transistor electrically connected to each of the pair of data lines, and a discharge transistor electrically connected to each of the pair of data lines. Thus, the multiplexer circuit comprises the discharge transistor for discharging a voltage of the data line.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present specification relates to a display device, and more particularly to a display device using LEDs (Light Emitting Diodes). [Background technology]

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light-emitting displays (OLEDs), which emit light themselves, and liquid crystal displays (LCDs), which require a separate light source.

[0003] Display devices are now used in a wide range of applications, from computer monitors and TVs to personal portable devices, and research is underway to develop display devices that have a large display area while being reduced in volume and weight.

[0004] In recent years, displays that include LEDs (Light Emitting Diodes) have been attracting attention as the next generation of display devices. LEDs are made of inorganic materials, not organic materials, and are therefore highly reliable and have a longer lifespan than LCDs and OLEDs. LEDs not only have a fast lighting speed, but also have excellent luminous efficiency, strong shock resistance, excellent stability, and can display high-brightness images. Summary of the Invention [Problem to be solved by the invention]

[0005] The problem to be solved by this specification is to provide a display device capable of alternately driving a pair of sub-pixels that emit light of the same hue.

[0006] Another problem to be solved by this specification is to provide a display device that can alternately drive a plurality of sub-pixels by using a multiplexer circuit.

[0007] Another problem to be solved by the present invention is to provide a display device with a simplified structure of a data driver.

[0008] Another problem to be solved by the present invention is to provide a display device with a reduced number of data pads.

[0009] Another problem to be solved by the present invention is to provide a display device in which the number of data pads is reduced, the number of channels is reduced, and the structure of the data driver is simplified.

[0010] Another problem to be solved by the present invention is to provide a display device that reduces costs by simplifying the structures of a data driver and a plurality of data pads. Another problem to be solved by the present specification is to provide a display device that minimizes or reduces abnormal driving failures of sub-pixels by discharging the voltage of data lines connected to sub-pixels that are not in a driving period.

[0011] Another problem to be solved by the present invention is to provide a display device that reduces non-emission defects of some sub-pixels in low gray scale images.

[0012] Another problem to be solved by this specification is to provide a display device that can efficiently use the area of ​​the non-display area by arranging other components in the empty space between the data wiring and the data pad that are not connected to the multiplexer circuit.

[0013] The objects of this specification are not limited to the objects mentioned above, and other objects not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0014] A display device according to an embodiment of the present specification includes a plurality of sub-pixels, a plurality of data lines connected to each of the plurality of sub-pixels, and a multiplexer circuit connected to a pair of adjacent data lines among the plurality of data lines, the multiplexer circuit including a charge transistor connected to each of the pair of data lines and a discharge transistor connected to each of the pair of data lines, and thus the multiplexer circuit includes a discharge transistor capable of discharging the voltage of the data lines, thereby reducing defects in which some of the sub-pixels connected to the data lines are abnormally driven.

[0015] A display device according to another embodiment of the present specification includes a substrate including a display area and a non-display area, a plurality of data lines extending from the non-display area to the display area, a plurality of data pads disposed in the non-display area, and a plurality of multiplexer circuits disposed in the non-display area and connected between the plurality of data lines and the plurality of data pads, wherein each of the plurality of multiplexer circuits includes a plurality of first charge transistors connected to some of the plurality of data lines, a plurality of second charge transistors connected to other of the plurality of data lines, a plurality of first discharge transistors connected to some of the data lines, and a plurality of second discharge transistors connected to the other data lines, wherein the plurality of first charge transistors and the plurality of first discharge transistors can be turned on at different periods, and the plurality of second charge transistors and the plurality of second discharge transistors can be turned on at different periods. Thus, the plurality of sub-pixels connected to some of the data lines and the plurality of sub-pixels connected to other data lines can be alternately driven using the multiplexer circuit.

[0016] Further details of the embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0017] The display device according to the present specification can alternately drive a pair of sub-pixels that emit light of the same hue.

[0018] The display device according to the present invention can alternately drive multiple sub-pixels using a multiplexer circuit.

[0019] The display device according to the present specification can simplify the structure of the data driver.

[0020] The display device according to the present specification can simplify the structure of the display device by reducing the number of data pads.

[0021] The display device according to the present disclosure can reduce the number of data pads and channels, simplify the structure of the data driver, and reduce costs.

[0022] The display device according to the present specification can reduce abnormal driving failure of the sub-pixel by discharging the voltage of the data line.

[0023] The display device according to the present specification can reduce non-emission defects of some sub-pixels in low grayscale images.

[0024] The display device according to the present specification can efficiently use the area of ​​the non-display region by arranging other components in the empty space between the data wiring and the data pads that are not connected to the multiplexer circuit.

[0025] The effects of this specification are not limited to the examples given above, and various other effects are included within this specification. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a schematic configuration diagram of a display device according to an embodiment of the present specification. [Figure 2] FIG. 2 is a schematic block diagram of a sub-pixel and multiplexer circuit of a display device according to an embodiment of the present disclosure; [Figure 3] FIG. 2 is an exemplary circuit diagram of a sub-pixel of a display device according to an embodiment of the present specification. [Figure 4]FIG. 10 is another exemplary circuit diagram of a subpixel of a display device according to an embodiment of the present specification. [Figure 5] FIG. 1 is a circuit diagram of a multiplexer circuit of a display device according to an embodiment of the present specification. [Figure 6] 1 is a driving timing diagram of a multiplexer circuit of a display device according to an embodiment of the present specification. [Figure 7] FIG. 2 is a plan view of a multiplexer circuit of a display device according to an embodiment of the present specification. [Figure 8] FIG. 2 is a cross-sectional view of a multiplexer circuit of a display device according to an embodiment of the present specification. [Figure 9] FIG. 10 is a schematic block diagram of a subpixel and multiplexer circuit of a display device according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0027] The advantages and features of the present invention, and methods for achieving them, will become more apparent from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and may be embodied in various different forms. The embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully convey the scope of the present invention to those skilled in the art.

[0028] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for illustrating the embodiments of this specification are illustrative only and are not intended to limit the scope of this specification. The same reference symbols refer to the same elements throughout this specification. Furthermore, when describing this specification, if it is deemed that a detailed description of related prior art would unnecessarily obscure the gist of this specification, such a detailed description will be omitted. When using words such as "include," "have," and "be made" in this specification, other parts may be added unless "only" is used. When describing an element in the singular, this also includes the plural unless otherwise explicitly stated.

[0029] When interpreting elements, they are interpreted as including a margin of error even if there is no other explicit description.

[0030] When describing a positional relationship, for example, when describing the positional relationship of two parts using "above," "at the top," "below," "next to," etc., one or more other parts may be located between the two parts, as long as "immediately" or "directly" is not used.

[0031] When an element or layer is referred to as "on" another element or layer, it includes the case where the element or layer is directly on top of the other element or layer, or where there are other layers or elements interposed therebetween.

[0032] When a first element is described as being "connected or coupled," "in contact or overlap," or the like, to a second element, it should be interpreted not only as meaning that the first element is "directly connected or coupled," or "in direct contact or overlap" with the second element, but also as meaning that there can be a third element "intervening" between the first and second elements, or that the first and second elements can be "connected or coupled," "in contact or overlap," or the like, with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or coupled," "in contact or overlap," or the like, with each other.

[0033] Furthermore, although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, a first component referred to below may be a second component within the technical concept of this specification.

[0034] Like reference numbers refer to like elements throughout the specification.

[0035] The features of the various embodiments of this specification may be partially or wholly combined or combined with each other, may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the other or may be implemented together in a related relationship.

[0036] In the following, the present specification will be described with reference to the drawings.

[0037] 1 is a schematic diagram of a display device according to an embodiment of the present disclosure, in which, for convenience of explanation, only a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC are shown among various components of the display device 100.

[0038] Referring to FIG. 1, the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate driver GD and the data driver DD.

[0039] The gate driver GD supplies a plurality of scan signals to a plurality of scan lines SL in response to a plurality of gate control signals provided by the timing controller TC. Although one gate driver GD is shown as being spaced apart from one side of the display panel PN in FIG. 1, the number and arrangement of the gate drivers GD are not limited thereto.

[0040] The data driver DD converts image data input from the timing controller TC into data voltages using a reference gamma voltage in response to a plurality of data control signals provided from the timing controller TC, and supplies the converted data voltages to a plurality of data lines DL.

[0041] The timing controller TC aligns externally input image data and supplies it to the data driver DD. The timing controller TC can generate gate control signals and data control signals using externally input synchronization signals, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC can then supply the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0042] The display panel PN is configured to display an image to a user and includes a plurality of sub-pixels SP. A plurality of scan lines SL and a plurality of data lines DL intersect with each other in the display panel PN, and each of the sub-pixels SP is connected to the scan lines SL and the data lines DL. In addition, although not shown in the drawings, each of the sub-pixels SP may be connected to a high-potential power supply line VDD, a low-potential power supply line VSS, a reference line RL, etc.

[0043] A display area AA and a non-display area NA surrounding the display area AA can be defined on the display panel PN.

[0044] The display area AA is an area where an image is displayed on the display device 100. A plurality of sub-pixels SP constituting a plurality of pixels and a circuit for driving the plurality of sub-pixels SP may be arranged in the display area AA. The plurality of sub-pixels SP is the smallest unit constituting the display area AA, and n sub-pixels SP may form one pixel. A light-emitting element 130 and a thin film transistor for driving the light-emitting element 130 may be arranged in each of the plurality of sub-pixels SP. The plurality of light-emitting elements 130 may be defined differently depending on the type of the display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel PN, the light-emitting element 130 may be an LED (Light-emitting Diode) or a micro LED (Micro Light-emitting Diode).

[0045] A plurality of wirings are arranged in the display area AA to transmit various signals to the subpixels SP. For example, the wirings may include a plurality of data wirings DL that supply data voltages to the subpixels SP, and a plurality of scan wirings SL that supply scan signals to the subpixels SP. The scan wirings SL may extend in one direction from the display area AA to be connected to the subpixels SP, and the data wirings DL may extend in a direction different from the one direction from the display area AA to be connected to the subpixels SP. In addition, the display area AA may further include, but is not limited to, low-potential power wirings VSS, high-potential power wirings VDD, and the like.

[0046] The non-display area NA is an area where no image is displayed and may be defined as an area extending from the display area AA. Link wiring and pad electrodes for transmitting signals to the sub-pixels SP of the display area AA, as well as driving ICs such as gate driver ICs and data driver ICs may be arranged in the non-display area NA.

[0047] However, the non-display area NA may be located on the rear surface of the display panel PN, i.e., on a surface without sub-pixels SP, or may be omitted, and is not limited to what is shown in the drawings.

[0048] Meanwhile, drivers such as the gate driver GD, the data driver DD, and the timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD may be implemented in the non-display area NA in a GIP (Gate In Panel) manner, or may be implemented between a plurality of sub-pixels SP in the display area AA in a GIA (Gate In Active Area) manner.

[0049] For example, the data driver DD and the timing controller TC may be formed on a separate flexible film and printed circuit board, and the data driver DD and the timing controller TC may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0050] Furthermore, when the gate driver GD is implemented in the GIP method and the data driver DD and timing controller TC transmit signals to the display panel PN through pad electrodes in the non-display area NA, the area of ​​the non-display area NA for arranging the gate driver GD and pad electrodes needs to be larger than a certain level, which may increase the bezel.

[0051] As another example, if the gate driver GD is mounted within the display area AA using the GIA method, and side wiring SRL is formed to connect signal wiring on the front side of the display panel PN to pad electrodes on the rear side of the display panel PN, and a flexible film and a printed circuit board are bonded to the rear side of the display panel PN, the non-display area NA on the front side of the display panel PN can be reduced. In other words, if the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN in the above manner, it may be possible to implement a zero bezel, i.e., a bezel that is substantially absent.

[0052] Hereinafter, the sub-pixels SP of the display device 100 according to an embodiment of the present specification will be specifically described with reference to FIGS.

[0053] Figure 2 is a schematic block diagram of a subpixel and a multiplexer circuit of a display device according to an embodiment of the present disclosure, Figure 3 is an exemplary circuit diagram of a subpixel of a display device according to an embodiment of the present disclosure, and Figure 4 is another exemplary circuit diagram of a subpixel of a display device according to an embodiment of the present disclosure.

[0054] 2, the subpixels SP include a plurality of first subpixels SP1, a plurality of second subpixels SP2, and a plurality of third subpixels SP3. For example, the first subpixels SP1 may be red subpixels SP, the second subpixels SP2 may be green subpixels SP, and the third subpixels SP3 may be blue subpixels SP, but are not limited thereto.

[0055] A pair of first sub-pixels SP1 may be arranged adjacent to each other, a pair of second sub-pixels SP2 may be arranged adjacent to each other, and a pair of third sub-pixels SP3 may be arranged adjacent to each other, such that the pair of first sub-pixels SP1, the pair of second sub-pixels SP2, and the pair of third sub-pixels SP3 may be arranged in the same row in this order.

[0056] Each of the plurality of sub-pixels SP includes a pixel circuit PC and a light-emitting element 130. The pixel circuit PC is a circuit for driving the light-emitting element 130 and may include a plurality of transistors and capacitors. The pixel circuit PC is connected to various wirings such as a scan line SL, a data line DL, a high-potential power supply line VDD, a low-potential power supply line VSS, a light-emitting control signal line EL, etc., and can be driven by receiving signals from these wirings. The pixel circuit PC supplies a driving current to the light-emitting element 130 to cause the light-emitting element 130 to emit light.

[0057] The light-emitting element 130 can emit light by receiving a driving current from the pixel circuit PC. The light-emitting element 130 may be, for example, a micro LED (Micro Light-emitting Diode) or an LED (Light-emitting Diode). The light-emitting element 130 can be connected between the pixel circuit PC and a high-potential power supply wiring VDD, or between the pixel circuit PC and a low-potential power supply wiring VSS.

[0058] The light emitting element 130 includes a first light emitting element 130R, a second light emitting element 130G, and a third light emitting element 130B. The first light emitting element 130R may be disposed in the first sub-pixel SP1, the second light emitting element 130G may be disposed in the second sub-pixel SP2, and the third light emitting element 130B may be disposed in the third sub-pixel SP3. For example, the first light emitting element 130R may be a red light emitting element 130, the second light emitting element 130G may be a green light emitting element 130, and the third light emitting element 130B may be a blue light emitting element 130, but is not limited thereto.

[0059] Meanwhile, a data line DL is connected to each of the sub-pixels SP. The data line DL includes a first data line DL1, a second data line DL2, and a third data line DL3. For example, the first data line DL1 may be connected to the first sub-pixel SP1, the second data line DL2 may be connected to the second sub-pixel SP2, and the third data line DL3 may be connected to the third sub-pixel SP3.

[0060] The first data line DL1 may include a 1-1 data line DL1a connected to one of a pair of adjacent first sub-pixels SP1 and a 1-2 data line DL1b connected to the other first sub-pixel SP1. The second data line DL2 may include a 2-1 data line DL2a connected to one of a pair of adjacent second sub-pixels SP2 and a 2-2 data line DL2b connected to the other second sub-pixel SP2. The third data line DL3 may include a 3-1 data line DL3a connected to one of a pair of adjacent third sub-pixels SP3 and a 3-2 data line DL3b connected to the other third sub-pixel SP3.

[0061] Meanwhile, when micro LEDs are used as the light emitting elements 130, a plurality of micro LEDs may be formed on a wafer and then transferred onto a substrate of a display panel PN to form the display device 100. However, during the process of transferring a plurality of micro LEDs having minute sizes from the wafer to the display panel PN, a micro LED may not be transferred properly, or the micro LED may be transferred out of position due to an alignment error, resulting in a defective subpixel SP. Therefore, in consideration of the possibility of a defective micro LED transfer, light emitting elements 130 that emit light of the same color may be transferred to a pair of subpixels SP, and the pair of light emitting elements 130 may be alternately driven to prepare for a defective subpixel SP. For example, even if a defect occurs in one of a pair of subpixels SP, each of which includes a light emitting element 130, the other subpixels SP may be driven normally for at least a portion of the driving period, thereby compensating for the defective subpixel SP not to be recognized.

[0062] One of the light emitting elements 130 of the pair of sub-pixels SP may be defined as a main light emitting element 130, and the other light emitting element 130 may be defined as a redundancy light emitting element 130. The redundancy light emitting element 130 may be an extra light emitting element 130 that is transferred in preparation for a defect in the main light emitting element 130. Even if a defect occurs in which the main light emitting element 130 is not transferred or the main light emitting element 130 is transferred out of position due to an alignment error, the redundancy light emitting element 130 can normally emit light. Therefore, by arranging the main and redundancy light emitting elements 130 together, it is possible to reduce degradation of display quality due to a defect in the main or redundancy light emitting element 130.

[0063] 2, one of the first light-emitting elements 130R of the pair of first sub-pixels SP1 may be defined as a main first light-emitting element 130R, and the other may be defined as a redundancy first light-emitting element 130R. One of the second light-emitting elements 130G of the pair of second sub-pixels SP2 may be defined as a main second light-emitting element 130G, and the other may be defined as a redundancy second light-emitting element 130G. One of the third light-emitting elements 130B of the pair of third sub-pixels SP3 may be defined as a main third light-emitting element 130B, and the other may be defined as a redundancy third light-emitting element 130B.

[0064] In the display device 100 according to an embodiment of the present specification, a multiplexer circuit MUX is connected to a pair of data lines DL connected to a pair of sub-pixels SP emitting light of the same color, so that the main light emitting element 130 and the redundancy light emitting element 130 of each of the pair of sub-pixels SP can be alternately driven. Therefore, by connecting the multiplexer circuit MUX to the pair of data lines DL, the main light emitting element 130 and the redundancy light emitting element 130 can be alternately driven, and even if a defect occurs in one of the main and redundancy light emitting elements 130, either the main light emitting element 130 or the redundancy light emitting element 130 can be normally driven during the other driving period.

[0065] A multiplexer circuit MUX connected to a plurality of data lines DL is disposed on the display panel PN. The multiplexer circuit MUX may be connected between one data pad DP and a pair of data lines DL. The data pad DP is a pad electrically connected to a data driver DD and receives a data voltage, and may be formed in a non-display area NA of the display panel PN. The multiplexer circuit MUX may also be formed in the non-display area NA together with the data pad DP. The multiplexer circuit MUX may selectively supply a data voltage applied from one data pad DP to one of the pair of data lines DL. The multiplexer circuit MUX may electrically connect only one of the pair of data lines DL to the data pad DP.

[0066] For example, a pair of first data lines DL1 connected to a pair of adjacent first sub-pixels SP1 may be connected to the same multiplexer circuit MUX, a pair of second data lines DL2 connected to a pair of adjacent second sub-pixels SP2 may be connected to the same multiplexer circuit MUX, a pair of third data lines DL3 connected to a pair of adjacent third sub-pixels SP3 may be connected to the same multiplexer circuit MUX, the 1-1 data lines DL1a and the 1-2 data lines DL1b may be connected to the same multiplexer circuit MUX, the 2-1 data lines DL2a and the 2-2 data lines DL2b may be connected to the same multiplexer circuit MUX, and the 3-1 data lines DL3a and the 3-2 data lines DL3b may be connected to the same multiplexer circuit MUX.

[0067] The multiplexer circuit MUX can supply a data voltage to only one of the pair of first data lines DL1, thereby driving only one of the pair of adjacent first sub-pixels SP1. The multiplexer circuit MUX can supply a data voltage to only one of the pair of second data lines DL2, thereby driving only one of the pair of adjacent second sub-pixels SP2. The multiplexer circuit MUX can supply a data voltage to only one of the pair of third data lines DL3, thereby driving only one of the pair of adjacent third sub-pixels SP3.

[0068] The multiplexer circuit MUX allows the pair of first sub-pixels SP1 to be driven for different periods. Similarly, the pair of second sub-pixels SP2 can be driven for different periods, and the pair of third sub-pixels SP3 can also be driven for different periods. For example, the pair of first sub-pixels SP1 can be driven alternately in units of frames, the pair of second sub-pixels SP2 can be driven alternately in units of frames, and the pair of third sub-pixels SP3 can be driven alternately in units of frames. Therefore, the pair of sub-pixels SP can be alternately driven using the multiplexer circuit MUX.

[0069] Meanwhile, as described above, if the first light emitting element 130R of the pair of first sub-pixels SP1 is defined as the first main light emitting element 130R and the first redundancy light emitting element 130R, respectively, the multiplexer circuit MUX may drive the first main light emitting element 130R in the Nth frame and drive the first redundancy light emitting element 130R in the (N+1)th frame. That is, the first main light emitting element 130R and the first redundancy light emitting element 130R may be driven alternately on a frame-by-frame basis. If a defect occurs in the first main light emitting element 130R of the first main light emitting element 130R and the first redundancy light emitting element 130R, the defect of the first main light emitting element 130R in the Nth frame may be less likely to be recognized due to the first redundancy light emitting element 130R being normally driven in the (N+1)th frame. Similarly, the second light-emitting element 130G of the pair of second sub-pixels SP2 and the third light-emitting element 130B of the pair of third sub-pixels SP3 are also driven alternately in frame units, so that even if defects occur in the second sub-pixels SP2 and the third sub-pixels SP3, compensation can be made so that such defects are not noticeable.

[0070] The multiplexer circuit MUX may include a plurality of transistors to supply a data voltage to only one of a pair of data lines DL, and a more detailed description of the multiplexer circuit MUX will be provided later with reference to FIGS. 5 and 6.

[0071] Meanwhile, the pixel circuit PC of the sub-pixel SP may be configured with various circuits including a plurality of transistors and capacitors. An exemplary circuit of the pixel circuit PC according to an embodiment of this specification will be described below with reference to FIGS. 3 and 4.

[0072] 3, each of the sub-pixels SP includes a pixel circuit PC and a light-emitting element 130 connected to the pixel circuit. For example, an exemplary pixel circuit PC of each of the sub-pixels SP may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0073] First, each of the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6 and seventh transistor T7 of the pixel circuit PC includes a gate electrode, a source electrode and a drain electrode.

[0074] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be N-type transistors or P-type transistors. In an N-type transistor, carriers are electrons, so electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. In a P-type transistor, carriers are holes, so holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. For example, one transistor of the plurality of transistors may be an N-type transistor, and another transistor of the plurality of transistors may be a P-type transistor.

[0075] In the following description, it is assumed that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors, but this is not intended to be limiting.

[0076] The first transistor T1 includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the first scan line SL1, the first source electrode is connected to the data line DL, and the first drain electrode is connected to the first node N1. The first transistor T1 can transmit a data voltage from the data line DL to the first node N1 based on a scan signal on the first scan line SL1. Therefore, the first transistor T1 configured to transmit the data voltage to the pixel circuit PC may also be referred to as a switching transistor.

[0077] In this case, the first transistor T1 of the first subpixel SP1 may be connected to the first data line DL1, the first transistor T1 of the second subpixel SP2 may be connected to the second data line DL2, and the first transistor T1 of the third subpixel SP3 may be connected to the third data line DL3.

[0078] The second transistor T2 includes a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the first scan line SL1, the second source electrode is connected to the second node N2, and the second drain electrode is connected to the third node N3. The second transistor T2 can short-circuit the sixth gate electrode and sixth drain electrode of the sixth transistor T6, thereby establishing a diode connection for the sixth transistor T6. A diode connection means that the gate electrode is short-circuited with the source or drain electrode, causing the transistor to operate like a diode. In this case, the second transistor T2 is implemented as an oxide semiconductor transistor with a low off-state current, thereby reducing current leakage from the sixth gate electrode of the sixth transistor T6.

[0079] The third transistor T3 includes a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode is connected to the emission control signal line EL, the third source electrode is connected to the reference line RL, and the third drain electrode is connected to the first node N1. The third transistor T3 can transmit a reference voltage from the reference line RL to the first node N1 based on the emission control signal of the emission control signal line EL.

[0080] The fourth transistor T4 includes a fourth gate electrode, a fourth source electrode, and a fourth drain electrode. The fourth gate electrode is connected to the light emission control signal line EL, the fourth source electrode is connected to the third node N3, and the fourth drain electrode is connected to the low potential power supply line VSS. The fourth transistor T4 can electrically connect the third node and the low potential power supply line VSS based on the light emission control signal EL, and can allow a driving current to flow from the high potential power supply line VDD to the low potential power supply line VSS.

[0081] The fifth transistor T5 includes a fifth gate electrode, a fifth source electrode, and a fifth drain electrode. The fifth gate electrode is connected to the second scan line SL2, the fifth source electrode is connected to the reference line RL, and the fifth drain electrode is connected to the third node N3. The fifth transistor T5 can provide a reference voltage to the third node N3 based on the scan signal of the second scan line SL2, and can reset the sixth drain electrode of the sixth transistor T6 to the reference voltage via the third node N3.

[0082] The sixth transistor T6 includes a sixth gate electrode, a sixth source electrode, and a sixth drain electrode. The sixth gate electrode is connected to the second node N2, the sixth source electrode is connected to the fourth node N4, and the sixth drain electrode is connected to the third node N3. The sixth transistor T6 is turned on to control the driving current flowing to the light emitting element 130. Therefore, the sixth transistor T6, which controls the driving current supplied to the light emitting element 130, can be defined as a driving transistor.

[0083] The seventh transistor T7 includes a seventh gate electrode, a seventh source electrode, and a seventh drain electrode. The seventh gate electrode is connected to the first scan line SL1, the seventh source electrode is connected to the high potential power line VDD, and the seventh drain electrode is connected to the fourth node N4. The seventh transistor T7 can transmit the high potential power voltage to the fourth node N4 based on the scan signal of the first scan line SL1 and can prevent the light emitting element 130 from emitting light while the data voltage is being charged.

[0084] The first capacitor C1 includes a capacitor electrode connected to the first node N1 and a capacitor electrode connected to the second node N2. The first capacitor C1 can adjust the voltage of the second node N2 using a coupling characteristic, and can fix the voltage applied to the sixth gate electrode of the sixth transistor T6 while the light emitting element 130 emits light, thereby maintaining a constant driving current.

[0085] The second capacitor C2 includes a capacitor electrode connected to the second node N2 and a capacitor electrode connected to the fourth node N4, that is, the second capacitor C2 is connected between the sixth gate electrode and the sixth source electrode of the sixth transistor T6 and between the sixth gate electrode and the first electrode of the light emitting element 130.

[0086] Meanwhile, when the voltage at the first node N1 fluctuates, the voltage at the second node N2 may fluctuate. At this time, the second capacitor C2 connected in series with the first capacitor C1 is coupled to the first capacitor C1, and the voltage at the first node N1 may be transferred to the voltage at the second node N2 according to the capacitance ratio between the first capacitor C1 and the second capacitor C2. Therefore, the second capacitor C2 can be used to reduce the transfer rate of the data voltage from the first node N1 to the second node N2. Furthermore, when the light emitting element 130 is configured with a micro LED having a steep IV curve slope, the second capacitor C2 can be used to reduce the transfer rate of the data voltage, thereby enabling more delicate gray scale expression.

[0087] The third capacitor C3 includes a capacitor electrode connected to the fourth node N4 and a capacitor electrode connected to the high potential power supply line VDD. That is, the third capacitor C3 includes capacitor electrodes connected to the first electrode and the second electrode of the light emitting element 130. The third capacitor C3 increases the capacitance of the light emitting element 130, thereby enabling the light emitting element 130 to emit light with higher brightness.

[0088] The light emitting element 130 includes a first electrode connected to the high potential power supply line VDD and a second electrode connected to the fourth node, and may be connected between the high potential power supply line VDD and the sixth transistor T6.

[0089] 4, another exemplary pixel circuit PC of each of the plurality of sub-pixels SP may be the same as the exemplary pixel circuit PC of FIG. 3 except that it further includes an eighth transistor T8 and the connection structure of the fifth transistor T5 is different. For example, the other exemplary pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0090] The eighth transistor T8 includes an eighth gate electrode, an eighth source electrode, and an eighth drain electrode. The eighth gate electrode is connected to the second scan line SL2, the eighth source electrode is connected to the data line DL, and the eighth drain electrode is connected to the first node N1. The eighth transistor T8 can transmit a data voltage to the first node N1 based on a scan signal on the second scan line SL2. The eighth transistor T8 is configured to partially charge the data voltage to the first capacitor C1 while initializing the voltage of the sixth gate electrode of the sixth transistor T6, which is the driving transistor. By using the eighth transistor T8 to partially charge the data voltage, fluctuations in the voltage of the sixth gate electrode can be reduced.

[0091] A fifth drain electrode of the fifth transistor T5 is connected to the second node N2, and the fifth transistor T5 can transmit a reference voltage to the second node N2 based on the scan signal on the second scan line SL2.

[0092] Therefore, the pixel circuit PC may include a plurality of transistors and a plurality of capacitors to supply a driving current to the light emitting element 130. However, the configuration of the pixel circuit PC may be other circuits instead of the exemplary circuits of FIGS. 3 and 4, and is not limited thereto.

[0093] Hereinafter, the circuitry of the multiplexer circuit MUX of the display device 100 according to one embodiment of the present specification will be described in detail with reference to FIGS.

[0094] 5 is a circuit diagram of a multiplexer circuit of a display device according to an embodiment of the present specification, and FIG 6 is a driving timing diagram of the multiplexer circuit of a display device according to an embodiment of the present specification.

[0095] 5 and 6, a multiplexer circuit MUX connected to a pair of data lines DL includes a first charging transistor CT1, a second charging transistor CT2, a first discharging transistor DCT1, and a second discharging transistor DCT2.

[0096] The first and second charging transistors CT1 and CT2 are transistors for transmitting a data voltage to the data line DL. The first and second charging transistors CT1 and CT2 transmit the data voltage to the data line DL and charge the data line DL with the data voltage. The first charging transistor CT1 connects one of the pair of data lines DL to a data pad DP, and the second charging transistor CT2 connects the other of the pair of data lines DL to the data pad DP.

[0097] The first charging transistor CT1 and the second charging transistor CT2 can electrically connect one of the pair of data lines DL to the data pad DP during different periods. While the first charging transistor CT1 connects the data pad DP to one data line DL, the second charging transistor CT2 is turned off to prevent the data pad DP from being electrically connected to the other data line DL. Conversely, while the second charging transistor CT2 connects the data pad DP to the other data line DL, the first charging transistor CT1 is turned off to prevent the data pad DP from being electrically connected to one data line DL.

[0098] The first charging transistor CT1 may be connected to one of the pair of data lines DL, and the second charging transistor CT2 may be connected to the other data line DL. For example, the first charging transistor CT1 may be connected to the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a, and the second charging transistor CT2 may be connected to the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b. The first charging transistor CT1 may be turned on or off by a first selection signal on the first selection line SEL1, and the second charging transistor CT2 may be turned on or off by a second selection signal on the second selection line SEL2.

[0099] For example, in the multiplexer circuit MUX connected to the pair of first data lines DL1, the source electrode and drain electrode of the first charging transistor CT1 may be connected to the data pad DP and the first-1 data line DL1a, respectively, and the gate electrode may be connected to the first selection line SEL1. In the multiplexer circuit MUX connected to the pair of first data lines DL1, the source electrode and drain electrode of the second charging transistor CT2 may be connected to the data pad DP and the first-2 data line DL1b, respectively, and the gate electrode may be connected to the second selection line SEL2.

[0100] For example, in the multiplexer circuit MUX connected to the pair of second data lines DL2, the source electrode and drain electrode of the first charging transistor CT1 may be connected to the data pad DP and the 2-1 data line DL2a, respectively, and the gate electrode may be connected to the first selection line SEL1. In the multiplexer circuit MUX connected to the pair of second data lines DL2, the source electrode and drain electrode of the second charging transistor CT2 may be connected to the data pad DP and the 2-2 data line DL2b, respectively, and the gate electrode may be connected to the second selection line SEL2.

[0101] For example, in the multiplexer circuit MUX connected to the pair of third data lines DL3, the source electrode and drain electrode of the first charging transistor CT1 may be connected to the data pad DP and the 3-1 data line DL3a, respectively, and the gate electrode may be connected to the first selection line SEL1. In the multiplexer circuit MUX connected to the pair of third data lines DL3, the source electrode and drain electrode of the second charging transistor CT2 may be connected to the data pad DP and the 3-2 data line DL3b, respectively, and the gate electrode may be connected to the second selection line SEL2.

[0102] Meanwhile, the plurality of data lines DL are arranged across the display area AA and may overlap or be adjacent to various components arranged in the display area AA. For example, the data lines DL may overlap or be adjacent to various lines such as the scan lines SL and the light-emitting control signal lines EL. Therefore, the data lines DL overlap other components in the display area AA, and a parasitic capacitor Cp may be formed between the data lines DL and the other components. In this case, the data voltage charged in the data lines DL may not be properly discharged due to the parasitic capacitance of the parasitic capacitor Cp. If the data voltage of the data lines DL is not properly discharged, a defect may occur in which the sub-pixels SP connected to the corresponding data lines DL abnormally emit light even when the light-emitting period is not in progress. Therefore, in the display device 100 according to an embodiment of the present specification, a discharge transistor and a discharge line DCL are connected to each of the plurality of data lines DL to discharge the data voltage charged in the plurality of data lines DL, thereby preventing a defect in which some sub-pixels SP emit light even when the driving period is not in progress.

[0103] Specifically, the first discharge transistor DCT1 and the second discharge transistor DCT2 are transistors for discharging a voltage charged in the data line DL. Each of the first discharge transistor DCT1 and the second discharge transistor DCT2 connects the data line DL and the discharge line DCL to discharge a voltage charged in the data line DL. The first discharge transistor DCT1 can connect one of the pair of data lines DL to the discharge line DCL, and the second discharge transistor DCT2 can connect the other of the pair of data lines DL to the discharge line DCL.

[0104] The first discharge transistor DCT1 may be connected to one of a pair of data lines DL, and the second discharge transistor DCT2 may be connected to the other data line DL. For example, the first discharge transistor DCT1 may be connected to the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a, and the second discharge transistor DCT2 may be connected to the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b. The first discharge transistor DCT1 may be turned on or off by a second selection signal on the second selection line SEL2, and the second discharge transistor DCT2 may be turned on or off by a first selection signal on the first selection line SEL1.

[0105] The first discharge transistor DCT1 and the second discharge transistor DCT2 can connect one of the pair of data lines DL to the discharge line DCL during different periods. While the first discharge transistor DCT1 connects the discharge line DCL to one data line DL, the second discharge transistor DCT2 is turned off to prevent the discharge line DCL from being connected to the other data line DL. While the second discharge transistor DCT2 connects the discharge line DCL to the other data line DL, the first discharge transistor DCT1 is turned off to prevent the discharge line DCL from being connected to the one data line DL. For example, the discharge line DCL may be a line to which a constant voltage is applied, such as a low-potential power line VSS or a reference line RL, but is not limited thereto.

[0106] For example, in a multiplexer circuit MUX connected to a pair of first data lines DL1, the source electrode and drain electrode of the first discharge transistor DCT1 may be connected to the 1-1 data line DL1a and the discharge line DCL, respectively, and the gate electrode may be connected to the second selection line SEL2. In a multiplexer circuit MUX connected to a pair of first data lines DL1, the source electrode and drain electrode of the second discharge transistor DCT2 may be connected to the 1-2 data line DL1b and the discharge line DCL, respectively, and the gate electrode may be connected to the first selection line SEL1.

[0107] For example, in the multiplexer circuit MUX connected to the pair of second data lines DL2, the source electrode and drain electrode of the first discharge transistor DCT1 may be connected to the 2-1 data line DL2a and the discharge line DCL, respectively, and the gate electrode may be connected to the second selection line SEL2. In the multiplexer circuit MUX connected to the pair of second data lines DL2, the source electrode and drain electrode of the second discharge transistor DCT2 may be connected to the 2-2 data line DL2b and the discharge line DCL, respectively, and the gate electrode may be connected to the first selection line SEL1.

[0108] For example, in a multiplexer circuit MUX connected to a pair of third data lines DL3, the source electrode and drain electrode of the first discharge transistor DCT1 may be connected to the 3-1 data line DL3a and the discharge line DCL, respectively, and the gate electrode may be connected to the second selection line SEL2. In a multiplexer circuit MUX connected to a pair of third data lines DL3, the source electrode and drain electrode of the second discharge transistor DCT2 may be connected to the 3-2 data line DL3b and the discharge line DCL, respectively, and the gate electrode may be connected to the first selection line SEL1.

[0109] 6, in the nth frame Frame(n), a first select signal of a turn-on level may be output from the first select line SEL1, and a second select signal of a turn-off level may be output from the second select line SEL2. For example, if the plurality of charge transistors and the plurality of discharge transistors are P-type transistors, a first select signal of a low level may be applied to the turn-on level signal, and a second select signal of a high level may be applied to the turn-off level signal.

[0110] The first charging transistor CT1 may be turned on and the second charging transistor CT2 may be turned off by a first selection signal at a turn-on level and a second selection signal at a turn-off level. The first charging transistor CT1 may electrically connect the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a to the data pad DP. The second charging transistor CT2 may be turned off and disconnect the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b from the data pad DP. Therefore, the multiplexer circuits MUX may transmit the data voltage from the data pad DP only to the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a among the multiple data lines DL during the nth frame Frame(n) period.

[0111] During the nth frame (Frame(n)) period, the second discharge transistor DCT2 may be turned on and the first discharge transistor DCT1 may be turned off by the first selection signal at a turn-on level and the second selection signal at a turn-off level. The turned-on second discharge transistor DCT2 may connect the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b to the discharge line DCL. The voltages charged in the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b may be discharged to the discharge line DCL through the second discharge transistor DCT2. The turned-off first discharge transistor DCT1 may separate the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a from the discharge line DCL. Therefore, it is possible to prevent the data voltages charged in the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a from being discharged.

[0112] Therefore, during the n-th frame period (Frame(n)), the first charge transistor CT1 is turned on to transmit the data voltage from the data pad DP to the sub-pixels SP connected to the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a, respectively. During the n-th frame period (Frame(n)), the second discharge transistor DCT2 is turned on to discharge the voltage charged to the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b, so that the sub-pixels SP connected to the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b do not emit light.

[0113] Next, during a blank period between the nth frame Frame(n) and the n+1th frame Frame(n+1) and a period leading to the n+1th frame Frame(n+1), a first select signal of a turn-off level may be output to the first select line SEL1, and a second select signal of a turn-on level may be output to the second select line SEL2. For example, if the plurality of charge transistors and the plurality of discharge transistors are P-type transistors, a first select signal of a high level may be applied as a turn-off level signal, and a second select signal of a low level may be applied as a turn-on level signal.

[0114] The first charging transistor CT1 may be turned off and the second charging transistor CT2 may be turned on by the first selection signal at a turn-off level and the second selection signal at a turn-on level. The first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b may be electrically connected to the data pad DP by the turned-on second charging transistor CT2. Meanwhile, the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a may be isolated from the data pad DP by the turned-off first charging transistor CT1. Therefore, during the (n+1)th frame (Frame(n+1)) period, the multiplexer circuits MUX may transmit the data voltage from the data pad DP only to the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b among the multiple data lines DL.

[0115] During the (n+1)th frame Frame(n+1) period, the second discharge transistor DCT2 may be turned off and the first discharge transistor DCT1 may be turned on by the first select signal at a turn-off level and the second select signal at a turn-on level. The turned-on first discharge transistor DCT1 may connect the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a to the discharge line DCL. The voltages charged in the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a may be discharged to the discharge line DCL through the first discharge transistor DCT1. The turned-off second discharge transistor DCT2 may isolate the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b from the discharge line DCL. Therefore, it is possible to prevent the data voltages charged in the first-second data line DL1b, the second-second data line DL2b, and the third-second data line DL3b from being discharged.

[0116] Therefore, during the (n+1)th frame period (Frame(n+1)), the second charge transistor CT2 is turned on to transmit the data voltage from the data pad DP to the sub-pixels SP connected to the first-2 data line DL1b, the second-2 data line DL2b, and the third-2 data line DL3b, respectively. During the (n+1)th frame period, the first discharge transistor DCT1 is turned on to discharge the voltage charged to the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a, and the sub-pixels SP connected to the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a are controlled not to emit light.

[0117] Meanwhile, the first selection signal of the first selection line SEL1 and the second selection signal of the second selection line SEL2 may be mutually inverted signals. If the phase of the first selection signal is inverted, it may become the same signal as the second selection signal. The first selection signal and the second selection signal may be mutually opposite in phase. Therefore, the first selection signal and the second selection signal do not need to be output as turn-on level or turn-off level signals at the same time.

[0118] The first charge transistor CT1 and the first discharge transistor DCT1 connected to the same data line DL may be controlled by different selection lines, and the second charge transistor CT2 and the second discharge transistor DCT2 connected to the same data line DL may be controlled by different selection lines. Therefore, the first charge transistor CT1 and the first discharge transistor DCT1 connected to the same data line DL may be turned on at different periods, and the second charge transistor CT2 and the second discharge transistor DCT2 connected to the same data line DL may be turned on at different periods.

[0119] Therefore, in the display device 100 according to an embodiment of the present specification, a discharge transistor is formed in the multiplexer circuit MUX to prevent a defect in which some subpixels SP abnormally emit light. If the multiplexer circuit MUX did not include a discharge transistor but only a charge transistor, the voltage of the data line DL connected to the non-emitting subpixels SP would not be discharged normally, resulting in a defect in which some subpixels SP emit light, as described above. For example, during the n+1th frame Frame(n+1) period when only the first subpixel SP1 connected to the 1-2 data line DL1b emits light, the voltage of the 1-1 data line DL1a would not be discharged normally, as shown by the dotted waveform WV1 in FIG. 6, resulting in a defect in which the first subpixel SP1 connected to the 1-1 data line DL1a also emits light. Therefore, the multiplexer circuit MUX of the display device 100 according to an embodiment of the present specification includes a discharge transistor that selectively connects the voltage of the data line DL to the discharge line DCL, thereby preventing a defect in which some subpixels SP emit light even when the light-emitting period is not in progress.

[0120] Meanwhile, in the display device 100 according to an embodiment of the present specification, only one of a pair of sub-pixels SP emitting light of the same color may be selectively driven, thereby increasing the drive current supplied to the light emitting element 130 of each sub-pixel SP. In this case, a sufficient drive current may be supplied to the light emitting element 130 even for a low gray level image, thereby reducing non-emission defects of the light emitting element 130. For example, assuming that a drive current of 1 A must be supplied to the light emitting element 130 to display a specific low gray level image, the display device 100 according to an embodiment of the present specification may display the specific low gray level image by supplying a drive current of 1 A to the light emitting element 130 of one of the pair of sub-pixels SP. In contrast, if all of the pair of sub-pixels SP are driven simultaneously to display a specific low gray level image, a drive current of 0.5 A may be supplied to the light emitting element 130 of each sub-pixel SP to display the specific low gray level image. Therefore, if all of the pair of sub-pixels SP are driven simultaneously to display an image, the drive current supplied to the light emitting element 130 of each sub-pixel SP may decrease. As a result, the drive current may decrease as the gray level increases, which may result in a defect in which some of the light emitting elements 130 do not emit light normally. Therefore, in the display device 100 according to one embodiment of the present specification, only one subpixel SP out of a pair of subpixels SP that emit light of the same hue can be selectively driven to supply a relatively large driving current to the light-emitting element 130 of each subpixel SP, thereby improving the display quality of low-gradation images.

[0121] Hereinafter, a specific structure of the multiplexer circuit MUX of the display device 100 according to an embodiment of the present specification will be described with reference to FIGS.

[0122] 7 and 8 are plan and cross-sectional views of a multiplexer circuit of a display device according to an embodiment of the present specification.

[0123] 7 and 8, a display panel PN of a display device 100 according to an embodiment of the present disclosure includes a substrate 110. The substrate 110 supports components disposed on the upper portion of the display device 100 and may be an insulating substrate 110. A plurality of sub-pixels SP may be formed on the substrate 110 to display an image. For example, the substrate 110 may be made of glass, resin, or the like. The substrate 110 may also be made of a polymer or plastic. In some embodiments, the substrate 110 may be made of a flexible plastic material.

[0124] A buffer layer 111 is disposed on the substrate 110. The buffer layer 111 may reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be composed of, for example, but not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may be omitted depending on the type of substrate 110 or the type of thin film transistor, and is not limited thereto.

[0125] A multiplexer circuit MUX including a first charging transistor CT1, a second charging transistor CT2, a first discharging transistor DCT1, and a second discharging transistor DCT2 is disposed on the buffer layer 111. The first charging transistor CT1 and the first discharging transistor DCT1 may be disposed adjacent to each other in the column direction, and the second charging transistor CT2 and the second discharging transistor DCT2 may be disposed adjacent to each other in the column direction. The first charging transistor CT1 and the second discharging transistor DCT2 may be disposed adjacent to each other in the row direction, and the second charging transistor CT2 and the first discharging transistor DCT1 may be disposed adjacent to each other in the row direction.

[0126] First, a first charge transistor CT1 is disposed on the buffer layer 111, and includes a first charge active layer CACT1, a first charge gate electrode CGE1, a first charge source electrode CSE1, and a first charge drain electrode CDE1.

[0127] A first charge active layer CACT1 is disposed on the buffer layer 111. The first charge active layer CACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0128] A gate insulating layer 112 is disposed on the first charge active layer CACT1. The gate insulating layer 112 is an insulating layer for electrically insulating the first charge active layer CACT1 from the first charge gate electrode CGE1, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0129] A first charging gate electrode CGE1 is disposed on the gate insulating layer 112. The first charging gate electrode CGE1 may be electrically connected to a first selection line SEL1. The first charging gate electrode CGE1 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0130] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the first charge gate electrode CGE1. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers for protecting the underlying components, and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0131] A first charge source electrode CSE1 and a first charge drain electrode CDE1 are disposed on the second interlayer insulating layer 114. The first charge source electrode CSE1 may be electrically connected to the data pad DP, and the first charge drain electrode CDE1 may be electrically connected to the first-1 data line DL1a, the second-1 data line DL2a, and the third-1 data line DL3a. The first charge source electrode CSE1 and the first charge drain electrode CDE1 may be electrically connected to the first charge active layer CACT1 through contact holes in the second interlayer insulating layer 114, the first interlayer insulating layer 113, and the gate insulating layer 112. The first charge source electrode CSE1 and the first charge drain electrode CDE1 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0132] A second charge transistor CT2 is disposed on the buffer layer 111, and includes a second charge active layer CACT2, a second charge gate electrode CGE2, a second charge source electrode CSE2, and a second charge drain electrode CDE2.

[0133] A second charge active layer CACT2 is disposed on the buffer layer 111. The second charge active layer CACT2 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0134] A gate insulating layer 112 is disposed on the second charge active layer CACT2, and a second charge gate electrode CGE2 is disposed on the gate insulating layer 112. The second charge gate electrode CGE2 may be electrically connected to the second selection wiring SEL2. The second charge gate electrode CGE2 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0135] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the second charge gate electrode CGE2, and the second charge source electrode CSE2 and the second charge drain electrode CDE2 are disposed on the second interlayer insulating layer 114. The second charge source electrode CSE2 may be electrically connected to the data pad DP, and the second charge drain electrode CDE2 may be electrically connected to the first-second data line DL1b, the second-second data line DL2b, and the third-second data line DL3b. The second charge source electrode CSE2 and the second charge drain electrode CDE2 may be electrically connected to the second charge active layer CACT2 through contact holes in the second interlayer insulating layer 114, the first interlayer insulating layer 113, and the gate insulating layer 112. The second charge source electrode CSE2 and the second charge drain electrode CDE2 may be made of a conductive material, such as, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0136] A first discharge transistor DCT1 including a first discharge active layer DCACT1, a first discharge gate electrode DCGE1, a first discharge source electrode DCSE1, and a first discharge drain electrode DCDE1 is disposed on the buffer layer 111.

[0137] A first discharge active layer DCACT1 is disposed on the buffer layer 111. The first discharge active layer DCACT1 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0138] A gate insulating layer 112 is disposed on the first discharge active layer DCACT1, and a first discharge gate electrode DCGE1 is disposed on the gate insulating layer 112. The first discharge gate electrode DCGE1 may be electrically connected to the second selection wiring SEL2. The first discharge gate electrode DCGE1 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0139] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the first discharge gate electrode DCGE1, and a first discharge source electrode DCSE1 and a first discharge drain electrode DCDE1 are disposed on the second interlayer insulating layer 114. The first discharge source electrode DCSE1 may be electrically connected to the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a, and the first discharge drain electrode DCDE1 may be electrically connected to the discharge line DCL. The first discharge source electrode DCSE1 and the first discharge drain electrode DCDE1 may be electrically connected to the first discharge active layer DCACT1 through contact holes in the second interlayer insulating layer 114, the first interlayer insulating layer 113, and the gate insulating layer 112. The first discharge source electrode DCSE1 and the first discharge drain electrode DCDE1 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0140] A second discharge transistor DCT2 is disposed on the buffer layer 111 and includes a second discharge active layer DCACT2, a second discharge gate electrode DCGE2, a second discharge source electrode DCSE2, and a second discharge drain electrode DCDE2.

[0141] A second discharge active layer DCACT2 is disposed on the buffer layer 111. The second discharge active layer DCACT2 may be made of a semiconductor material such as, but not limited to, an oxide semiconductor, amorphous silicon, or polysilicon.

[0142] A gate insulating layer 112 is disposed on the second discharge active layer DCACT2, and a second discharge gate electrode DCGE2 is disposed on the gate insulating layer 112. The second discharge gate electrode DCGE2 may be electrically connected to the first selection wiring SEL1. The second discharge gate electrode DCGE2 may be made of a conductive material, for example, but is not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0143] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the second discharge gate electrode DCGE2, and the second discharge source electrode DCSE2 and the second discharge drain electrode DCDE2 are disposed on the second interlayer insulating layer 114. The second discharge source electrode DCSE2 may be electrically connected to the first-second data line DL1b, the second-second data line DL2b, and the third-second data line DL3b, and the second discharge drain electrode DCDE2 may be electrically connected to the discharge line DCL. The second discharge source electrode DCSE2 and the second discharge drain electrode DCDE2 may be electrically connected to the second discharge active layer DCACT2 through contact holes in the second interlayer insulating layer 114, the first interlayer insulating layer 113, and the gate insulating layer 112. The second discharge source electrode DCSE2 and the second discharge drain electrode DCDE2 may be made of a conductive material, for example, but not limited to, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0144] Next, a first selection wiring SEL1 and a second selection wiring SEL2 are disposed between the gate insulating layer 112 and the first interlayer insulating layer 113. The first selection wiring SEL1 may be electrically connected to the first charge gate electrode CGE1 and the second discharge gate electrode DCGE2. For example, the first selection wiring SEL1, the first charge gate electrode CGE1, and the second discharge gate electrode DCGE2 may be integrated. The second selection wiring SEL2 may be electrically connected to the second charge gate electrode CGE2 and the first discharge gate electrode DCGE1. For example, the second selection wiring SEL2, the second charge gate electrode CGE2, and the first discharge gate electrode DCGE1 may be integrated.

[0145] A discharge wiring DCL is arranged between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The discharge wiring DCL may extend in the row direction and be electrically connected to the first discharge source electrode DCSE1 and the second discharge source electrode DCSE2. The discharge wiring DCL may be arranged between the first charge transistor CT1 and the first discharge transistor DCT1 and between the second charge transistor CT2 and the second discharge transistor DCT2, and extend in the row direction.

[0146] A plurality of data lines DL are disposed on the second interlayer insulating layer 114. The plurality of data lines DL may be electrically connected to the first charge drain electrode CDE1, the second charge drain electrode CDE2, the first discharge drain electrode DCDE1, and the second discharge drain electrode DCDE2, respectively. The first charge drain electrode CDE1 and the first discharge drain electrode DCDE1 may be electrically connected to the same data line DL, and the second charge drain electrode CDE2 and the second discharge drain electrode DCDE2 may be electrically connected to the same data line DL.

[0147] Meanwhile, the greater the channel width of the plurality of charging transistors, the faster the data voltage can be charged to the data line DL. The smaller the channel length of the plurality of charging transistors, the faster the data voltage can be charged to the data line DL. Specifically, the transistor channel is a portion of the active layer overlapping with the gate electrode. The channel width corresponds to the width of the gate electrode, and the channel length corresponds to the length of the channel in the direction from the source electrode to the drain electrode. As the channel width increases or the channel length decreases, the resistance decreases, allowing current to flow more easily. Conversely, as the channel width decreases or the channel length increases, the resistance increases, making it more difficult for current to flow. When the channel width / length value increases, more current can easily flow through the channel. Therefore, the data voltage can be charged to the data line DL more quickly by adjusting the channel width and length of the plurality of charging transistors.

[0148] Therefore, the display device 100 according to an embodiment of the present disclosure includes a multiplexer circuit MUX that transmits a data voltage to only one of a pair of data lines DL, thereby simplifying the structure of the data driver DD and reducing costs. The multiplexer circuit MUX can connect a pair of data lines DL to one data pad DP. Compared to a case where the data lines DL and the data pad DP are connected one-to-one, the display device 100 according to an embodiment of the present disclosure can reduce the number of data pads DP for transmitting data voltages to the plurality of data lines DL by half. Furthermore, since the number of data pads DP is reduced, the number of channels of the data driver DD that transmits data voltages to the plurality of data pads DP can be reduced. Therefore, the structure of the data driver DD can be simplified and costs can be reduced. Therefore, the display device 100 according to an embodiment of the present disclosure includes a multiplexer circuit MUX that connects a plurality of data lines DL to one data pad DP, thereby reducing the number of channels and simplifying the structure of the data driver DD, thereby reducing costs and improving yield.

[0149] 9 is a schematic block diagram of a subpixel and a multiplexer circuit of a display device according to another embodiment of the present specification. The display device 900 of FIG. 9 is substantially the same as the display device 100 of FIGS. 1 to 8 except for the first subpixel SP1 and the first data line DL1, and therefore, a redundant description will be omitted.

[0150] 9, each of the first data lines DL1 may be connected to a corresponding one of the first sub-pixels SP1 to transmit a data voltage. The first data lines DL1 may be directly connected to a corresponding one of the data pads DP to receive the data voltage. Each of the first data lines DL1 may be connected to a different data pad DP to receive the data voltage. In this case, the data voltage may be supplied to all of the first data lines DL1 during one frame period, and all of the first sub-pixels SP1 may be driven simultaneously.

[0151] In contrast, a plurality of second data lines DL2 and a plurality of third data lines DL3 are connected to a multiplexer circuit MUX, so that only some of the second data lines DL2 and third data lines DL3 can be selectively supplied with data voltage during one frame period.

[0152] Meanwhile, the first light emitting element 130R disposed in the first sub-pixel SP1 is a red light emitting element 130, and may be relatively more favorable for low current driving than the second light emitting element 130G and the third light emitting element 130B, which are green and blue light emitting elements 130. For example, even when the same low current is supplied, the first light emitting element 130R, which is a red light emitting element 130, may be driven more easily than the second light emitting element 130G and the third light emitting element 130B, which are green and blue light emitting elements 130, and may be less likely to be undriven. Therefore, a low gray level image may be displayed by simultaneously supplying a data voltage to the first sub-pixel SP1 including the first light emitting element 130R, which is favorable for low current driving.

[0153] Next, a multiplexer circuit MUX may be disposed only in the region between the plurality of second data lines DL2 and the plurality of data pads DP and the region between the plurality of third data lines DL3 and the plurality of data pads DP in the non-display area NA. In contrast, a multiplexer circuit MUX need not be disposed in the region between the plurality of first data lines DL1 and the plurality of data pads DP in the non-display area NA. Therefore, instead of the multiplexer circuit MUX, other components of the display device 900 may be disposed in the region between the plurality of first data lines DL1 and the plurality of data pads DP. For example, an anti-static circuit may be disposed in the region between the plurality of first data lines DL1 and the plurality of data pads DP to protect the display panel PN from static electricity. Therefore, the area of ​​the non-display area NA can be efficiently utilized by utilizing the space between the plurality of first data lines DL1 and the plurality of data pads DP, where the multiplexer circuit MUX is omitted.

[0154] An embodiment of the present invention can also be described as follows.

[0155] According to an aspect of the present invention, a display device includes a plurality of subpixels, a plurality of data wirings connected to each of the plurality of subpixels, and a multiplexer circuit connected to a pair of adjacent data wirings among the plurality of data wirings, and the multiplexer circuit includes a charge transistor connected to each of the pair of data wirings and a discharge transistor connected to each of the pair of data wirings.

[0156] According to another feature of the present specification, the charging transistor may include a first charging transistor connected between one of the pair of data lines and the data pad, and a second charging transistor connected between the other of the pair of data lines and the data pad.

[0157] According to another feature of the present specification, the discharge transistor may include a first discharge transistor connected between one data line and the discharge line, and a second discharge transistor connected between another data line and the discharge line.

[0158] According to another feature of the present specification, the transistor may further include a first selection wiring connected to the gate electrode of the first charging transistor and the gate electrode of the second discharging transistor, and a second selection wiring connected to the gate electrode of the second charging transistor and the gate electrode of the first discharging transistor.

[0159] According to another feature of the present specification, the first selection signal of the first selection wiring and the second selection signal of the second selection wiring may be signals of opposite phases to each other.

[0160] According to another feature of the present specification, during a period in which a first select signal of a turn-on level is applied and a second select signal of a turn-off level is applied, one data line may be connected to a data pad through a first charge transistor, and the other data line may be connected to a discharge line through a second discharge transistor.

[0161] According to another feature of the present specification, during a period in which a second select signal of a turn-on level is applied and a first select signal of a turn-off level is applied, one data line may be connected to a discharge line through a first discharge transistor, and another data line may be connected to a data pad through a second charge transistor.

[0162] According to another feature of the present specification, the plurality of sub-pixels include a pair of adjacent first sub-pixels, a pair of adjacent second sub-pixels, and a pair of adjacent third sub-pixels, and at least some of the pair of first sub-pixels, the pair of second sub-pixels, and the pair of third sub-pixels can be driven in periods different from each other.

[0163] According to another feature of the present specification, the plurality of data wirings may include a 1-1 data wiring and a 1-2 data wiring connected to a pair of first sub-pixels, respectively, and connected to the same multiplexer circuit, a 2-1 data wiring and a 2-2 data wiring connected to a pair of second sub-pixels, respectively, and connected to the same multiplexer circuit, and a 3-1 data wiring and a 3-2 data wiring connected to a pair of third sub-pixels, respectively, and connected to the same multiplexer circuit.

[0164] According to another feature of the present specification, the plurality of data wirings may include a plurality of first data wirings connected to a pair of first sub-pixels, a plurality of second-1 data wirings and a plurality of second-2 data wirings connected to a pair of second sub-pixels and the second data wirings being connected to the same multiplexer circuit, and a plurality of third-1 data wirings and a plurality of third-2 data wirings connected to a pair of third sub-pixels and the same multiplexer circuit.

[0165] According to another aspect of the present invention, a display device includes a substrate including a display area and a non-display area, a plurality of data wirings extending from the non-display area to the display area, a plurality of data pads disposed in the non-display area, and a plurality of multiplexer circuits disposed in the non-display area and connected between the plurality of data wirings and the plurality of data pads, wherein each of the plurality of multiplexer circuits includes a plurality of first charge transistors connected to some of the plurality of data wirings, a plurality of second charge transistors connected to other of the plurality of data wirings, a plurality of first discharge transistors connected to some of the data wirings, and a plurality of second discharge transistors connected to the other data wirings, wherein the plurality of first charge transistors and the plurality of first discharge transistors can be turned on at different periods from each other, and the plurality of second charge transistors and the plurality of second discharge transistors can be turned on at different periods from each other.

[0166] According to another feature of the present specification, each of the plurality of first charging transistors includes a first charging active layer disposed on the substrate, a first charging gate electrode disposed on the first charging active layer, a first charging source electrode disposed on the first charging gate electrode and connected to each of the plurality of data pads, and a first charging drain electrode disposed on the first charging gate electrode and connected to each of some of the data lines; and each of the plurality of second charging transistors includes a second charging active layer disposed on the substrate, a second charging gate electrode disposed on the second charging active layer, a second charging source electrode disposed on the second charging gate electrode and connected to each of the plurality of data pads, and a second charging drain electrode disposed on the second charging gate electrode and connected to each of the other data lines.

[0167] According to another feature of the present specification, each of the plurality of first discharge transistors includes a first discharge active layer disposed on a substrate, a first discharge gate electrode disposed on the first discharge active layer, a first discharge source electrode disposed on the first discharge gate electrode and connected to each of some of the data wirings, and a first discharge drain electrode disposed on the first discharge gate electrode and connected to the discharge wiring; and each of the plurality of second discharge transistors includes a second discharge active layer disposed on the substrate, a second discharge gate electrode disposed on the second discharge active layer, a second discharge source electrode disposed on the second discharge gate electrode and connected to each of the other data wirings, and a second discharge drain electrode disposed on the second discharge gate electrode and connected to the discharge wiring.

[0168] Although the embodiments of the present specification have been described in more detail above with reference to the accompanying drawings, the present specification is not necessarily limited to such embodiments and may be variously modified within the scope of the technical concept of the present specification. Therefore, the embodiments disclosed in the present specification are for illustrative purposes only and do not limit the technical concept of the present specification. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive. [Explanation of symbols]

[0169] 100 display device 110 Substrate 111 Buffer layer 112 Gate insulating layer 130 Light-emitting element

Claims

1. a plurality of sub-pixels; a plurality of data lines electrically connected to the plurality of sub-pixels, respectively; a multiplexer circuit electrically connected to a pair of adjacent data wirings among the plurality of data wirings, The multiplexer circuit a first charging transistor electrically connected between one of the pair of data lines and a data pad; a second charging transistor electrically connected between the other of the pair of data lines and the data pad; a first discharge transistor electrically connected between the one data line and the discharge line; a second discharge transistor electrically connected between the other data line and the discharge line; a first selection wiring electrically connected to the gate electrode of the first charge transistor and the gate electrode of the second discharge transistor; a second selection wiring electrically connected to the gate electrode of the second charge transistor and the gate electrode of the first discharge transistor; Among the plurality of sub-pixels, a pair of sub-pixels connected to the pair of adjacent data lines emits light of the same color, a first selection signal on the first selection wiring and a second selection signal on the second selection wiring that are opposite in phase to each other, and that are configured so that only one of the pair of sub-pixels connected to the pair of adjacent data wirings emits light.

2. 2. The display device of claim 1, wherein during a period in which the first selection signal at a turn-on level is applied and the second selection signal at a turn-off level is applied, the one data line is electrically connected to the data pad through the first charge transistor, and the other data line is electrically connected to the discharge line through the second discharge transistor.

3. 2. The display device of claim 1, wherein during a period in which the second selection signal at a turn-on level is applied and the first selection signal at a turn-off level is applied, the one data line is electrically connected to the discharge line through the first discharge transistor, and the other data line is electrically connected to the data pad through the second charge transistor.

4. The plurality of sub-pixels include: a pair of first sub-pixels adjacent to each other; a pair of second sub-pixels adjacent to each other; a pair of third sub-pixels adjacent to each other, The display device according to claim 1 , wherein at least some of the pair of first sub-pixels, the pair of second sub-pixels, and the pair of third sub-pixels are driven in periods different from each other.

5. The plurality of data wirings are a first data line and a first data line electrically connected to the pair of first sub-pixels, respectively, and electrically connected to the same multiplexer circuit; a second-1 data line and a second-2 data line electrically connected to the pair of second sub-pixels, respectively, and electrically connected to the same multiplexer circuit; 5. The display device according to claim 4, further comprising: a third-1 data wiring and a third-2 data wiring electrically connected to the pair of third sub-pixels, respectively, and electrically connected to the same multiplexer circuit.

6. The plurality of data wirings are a plurality of first data lines electrically connected to the pair of first sub-pixels, respectively; a second-1 data line and a second-2 data line electrically connected to the pair of second sub-pixels, respectively, and electrically connected to the same multiplexer circuit; 5. The display device according to claim 4, further comprising: a third-1 data wiring and a third-2 data wiring electrically connected to the pair of third sub-pixels, respectively, and electrically connected to the same multiplexer circuit.

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