Image forming device

Abstract

To provide an image forming apparatus that can always achieve both settings of an optimal Eye opening voltage and a reduction in power consumption of a DRAM regardless of an operation mode and a state of long-term deterioration of the image forming apparatus.SOLUTION: An image forming apparatus uses a digital circuit system having a memory for processing data, and comprises: a storage unit that, for every combination of an OCD and ODT of the memory, stores, in a memory unit, a table indicating a relationship between an Eye opening margin for separating High or Low in a communication protocol with the memory and the current consumption of the memory; and a setting unit that, on the basis of the table and for every state of the image forming apparatus, sets the Eye opening margin, and at the timing of switching of the state, and sets the combination corresponding to, of the Eye opening margins set to the state after switching, the Eye opening margin in which the current consumption becomes smaller.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an image forming apparatus. [Background technology]

[0002] The Double Data Rate (DDR) protocol for memory communication is becoming faster and more energy-efficient with each new version. This reduces the eye opening, increasing the risk of data and address bits becoming corrupted (e.g., "0" and "1" are swapped) within the transmission path, causing malfunctions.

[0003] In response to this, DDR2 and later versions have adopted on-die termination (ODT), which incorporates termination resistors within the IC chip, in addition to off-chip drivers (OCDs), which act as output resistors. By placing resistors closer to the near or far end, multiple reflections due to impedance mismatch can be prevented. By using OCD and ODT as parameters, the slew rate, reflection, and degree of ringback of the waveform can be adjusted, resulting in a wider eye opening. For example, Patent Document 1 (Patent Document 1) discloses a technology aimed at optimizing the power consumption of dynamic random access memory (DRAM), primarily focusing on the conditions for transitioning to and returning from self-refresh (hereinafter referred to as SR), and cutting off specific control signals using an external circuit during SR. Summary of the Invention [Problem to be solved by the invention]

[0004] Typically, OCD and ODT are uniquely determined during the design phase using a waveform simulator or other device, such as the characteristic impedance of a PWB (Printed Wiring Board). However, in reality, waveforms fluctuate due to manufacturing variations between PWBs, changes in device temperature during operation, and memory load factors such as DRAMs (Dynamic Random Access Memory). Therefore, optimal settings are likely to change dynamically and not be unique. Furthermore, if the eye aperture margin is set too wide to accommodate actual noise effects, it may result in over-specification and excessive power consumption. Furthermore, the technology described in Patent Document 1 can reduce the power consumed by signal lines by modifying the control or circuitry within the scope of the DDR control method specified by JEDEC, but does not optimize power consumption for data signals, which account for the majority of DRAM signal lines.

[0005] The present invention has been made in view of the above, and has as its object to provide an image forming apparatus that can always achieve both optimal eye opening voltage settings and reduced DRAM power consumption, regardless of the operating mode or deterioration state of the image forming apparatus over time. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems and achieve the objects, the present invention provides an image forming apparatus that uses a digital circuit system having a memory for processing data, and is equipped with: a storage unit that stores in a storage unit a table indicating the relationship between an eye opening margin that distinguishes between High and Low in a communication protocol with the memory and the current consumption of the memory, for each combination of OCD and ODT of the memory; and a setting unit that sets the eye opening margin for each state of the image forming apparatus based on the table, and at the timing of state switching, sets the combination corresponding to the eye opening margin that results in the smallest current consumption among the eye opening margins set for the state after switching. [Effects of the Invention]

[0007] According to the present invention, it is possible to always achieve both optimal eye opening voltage settings and reduced memory power consumption, regardless of the operating mode of the image forming apparatus or the state of deterioration over time. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a hardware configuration diagram of an MFP to which an image forming apparatus according to this embodiment is applied. [Figure 2] FIG. 2 is a diagram for explaining an example of a current flowing through a single signal line at logic "L" of DDR4 between a transmitting device and a receiving device in the MFP according to the present embodiment. [Figure 3] FIG. 3 is a diagram for explaining an example of the voltage of a single signal line at logic "L" of DDR4 between a transmitting device and a receiving device in the MFP according to the present embodiment. [Figure 4] FIG. 4 is a diagram for explaining an example of the current and voltage of a single signal line at logic "H" of DDR4 between a transmitting device and a receiving device in the MFP according to the present embodiment. [Figure 5] FIG. 5 is a diagram showing an example of the OCD and ODT settings and fluctuations in current consumption in the MFP according to this embodiment. [Figure 6] FIG. 6 is a block diagram showing an example of a functional configuration that realizes the features of the MFP according to this embodiment. [Figure 7] FIG. 7 is a diagram for explaining an example of Vref Training in the MFP according to the present embodiment. [Figure 8] FIG. 8 is a diagram for explaining an example of a table acquisition process in the MFP according to the present embodiment. [Figure 9] FIG. 9 is a flowchart showing an example of the flow of a table creation process in the MFP according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image forming apparatus will be described in detail below with

[0010] 1 is a hardware configuration diagram of an MFP to which an image forming apparatus according to this embodiment is applied. As shown in FIG. 1, an MFP (Multi-function Peripheral / Product / Printer) 9 includes a controller 910, a short-range communication circuit 920, an engine control unit 930, an operation panel 940, and a network I / F 950.

[0011] Of these, the controller 910 (an example of a digital circuit system) has a CPU 901, which is the main part of the computer, a system memory (MEM-P) 902, a northbridge (NB) 903, a southbridge (SB) 904, an ASIC (Application Specific Integrated Circuit) 906, a local memory (MEM-C) 907, which is a memory unit, an HDD controller 908, and an HD 909, which is also a memory unit, and is configured such that the NB 903 and the ASIC 906 are connected by an AGP (Accelerated Graphics Port) bus 921.

[0012] Of these, the CPU 901 is a control unit that performs overall control of the MFP 9. The NB 903 is a bridge that connects the CPU 901 with the MEM-P 902, the SB 904, and the AGP bus 921, and includes a memory controller that controls reading and writing to and from the MEM-P 902, a PCI (Peripheral Component Interconnect) master, and an AGP target.

[0013] MEM-P902 is an example of a memory for processing data, and is composed of ROM902a, which is memory for storing programs and data that realize the functions of controller 910, and RAM902b, which is used for expanding programs and data and as drawing memory during memory printing. The programs stored in RAM902b may be provided by being recorded in an installable or executable file format on a computer-readable recording medium such as a CD-ROM, CD-R, or DVD.

[0014] The SB 904 is a bridge for connecting the NB 903 with PCI devices and peripheral devices. The ASIC 906 is an integrated circuit (IC) for image processing applications that has hardware elements for image processing and serves as a bridge connecting the AGP bus 921, PCI bus 922, HDD 908, and MEM-C 907. The ASIC 906 includes a PCI target and AGP master, an arbiter (ARB) that forms the core of the ASIC 906, a memory controller that controls the MEM-C 907, multiple direct memory access controllers (DMACs) that perform image data rotation and other operations using hardware logic, and a PCI unit that transfers data between the scanner unit 931 and printer unit 932 via the PCI bus 922. A USB (Universal Serial Bus) interface and an IEEE 1394 (Institute of Electrical and Electronics Engineers) interface may also be connected to the ASIC 906.

[0015] The MEM-C907 is a local memory used as an image buffer for copying and a code buffer. The HD909 is a storage device for storing image data, font data used during printing, and forms. The HD909 controls the reading and writing of data from and to the HD909 under the control of the CPU901. The AGP bus 921 is a bus interface for a graphics accelerator card proposed to speed up graphics processing, and direct high-throughput access to the MEM-P902 enables the graphics accelerator card to operate at high speed.

[0016] Further, the short-distance communication circuit 920 includes a short-distance communication circuit 920a. The short-distance communication circuit 920 is a communication circuit such as NFC (Near Field Communication) or Bluetooth (registered trademark).

[0017] Furthermore, the engine control unit 930 is made up of a scanner unit 931 and a printer unit 932. The operation panel 940 is equipped with a panel display unit 940a, such as a touch panel, that displays current setting values, selection screens, etc. and accepts inputs from the operator, and an operation panel 940b that includes a numeric keypad that accepts setting values ​​for image formation conditions such as density setting conditions and a start key that accepts a copy start command. The controller 910 controls the entire MFP 9, and controls, for example, drawing, communication, input from the operation panel 940, etc. The scanner unit 931 or the printer unit 932 includes an image processing unit that performs error diffusion, gamma conversion, etc.

[0018] The MFP 9 can sequentially switch among the document box function, copy function, printer function, and facsimile function using the application switching key on the operation panel 940. When the document box function is selected, the MFP 9 enters document box mode, when the copy function is selected, the MFP 9 enters copy mode, when the printer function is selected, the MFP 9 enters printer mode, and when the facsimile mode is selected, the MFP 9 enters facsimile mode.

[0019] The network I / F 950 is an interface for performing data communication using the communication network 100. The short-range communication circuit 920 and the network I / F 950 are electrically connected to the ASIC 906 via a PCI bus 922.

[0020] 2 is a diagram illustrating an example of the current of a single signal line at logic "L" of DDR4 between a transmitting device and a receiving device in the MFP according to this embodiment. As shown in FIG. 2, the current at logic "L" (Low) in a steady state between a transmitting device (e.g., the memory controller of the NB903) and a receiving device (e.g., the MEM-P902) can be calculated by simple Ohm's law. For example, if the OCD is set to 40 Ω and the ODT is set to 60 Ω, the operating voltage of DDR4 is 1.2 V, so the current per signal line is calculated to be 12 mA.

[0021] 3 is a diagram illustrating an example of the voltage of a single signal line at logic "L" of DDR4 between a transmitting device and a receiving device in an MFP according to this embodiment. As shown in FIG. 3, the voltage at logic "L" in a steady state between the transmitting device and the receiving device can also be calculated by simple Ohm's law. For example, when the OCD is set to 40 Ω and the ODT is set to 60 Ω, the voltage at logic "L" is 0.48 V.

[0022] FIG. 4 is a diagram illustrating an example of the current and voltage of a single signal line at logic "H" of DDR4 between a transmitting device and a receiving device in an MFP according to this embodiment. As shown in FIG. 4, the steady-state voltage of logic "H" between the transmitting device and the receiving device in a steady state is VDDQ=1.2V, and the steady-state current is 0mA. From the above, it can be seen that the amount of current consumed by communication with the MEM-P902 and the theoretical eye opening voltage vary depending on the settings of the OCD and ODT. Here, the eye opening voltage is the difference between the steady-state voltages of logic "H" and logic "L."

[0023] In other words, the eye opening voltage is the eye opening margin that distinguishes between high and low in communication protocols such as DDR4 with the MEM-P902. In reality, the voltage waveform of the signal line will transiently change in a more complex manner due to factors such as reflections and crosstalk on the signal line, disturbance noise, and the output characteristics of the transmitting device.

[0024] FIG. 5 is a diagram showing an example of the OCD and ODT settings and fluctuations in current consumption in the MFP according to this embodiment. As described above, the OCD and ODT are typically uniquely determined and treated as fixed values ​​during the design phase. However, when considering application to an image forming apparatus such as the MFP 9, the MEM-P 902 is subjected to a high load, causing significant noise in the memory, such as the DRAM, of the MEM-P 902 (i.e., requiring a wide eye opening voltage) only in certain states, such as during startup, recovery from power saving mode, and printing. Therefore, in other states, it is expected that it would be better to adjust the OCD and ODT to reduce DRAM power consumption.

[0025] Therefore, the MFP 9 according to this embodiment has the following two features, which allow for both optimal setting of the eye opening voltage and reduction in power consumption of memories such as DRAM.

[0026] First, as a first feature, the MFP9 according to this embodiment has the function of performing Vref Training for each combination of OCD and ODT of the MEM-P902, acquiring (generating) a table showing the relationship between the eye opening voltage and the current consumption of the MEM-P902, and saving the table in non-volatile memory. Here, Vref Training is a process for determining the relationship between the eye opening voltage and the current consumption of the MEM-P902 for each combination of OCD and ODT of the MEM-P902.

[0027] A second feature of the MFP 9 according to this embodiment is that it has a function of setting the eye opening voltage for each state of the MFP 9 and setting the OCD and ODT to the optimum at the timing when the state of the MFP 9 is switched.

[0028] 6 is a block diagram showing an example of a functional configuration that realizes the features of the MFP according to this embodiment. As shown in FIG. 6, the MFP 9 according to this embodiment has a CPU 901, a storage 601, a memory controller 602, and a memory 603.

[0029] The CPU 901 is a control unit that performs overall control of the MFP 9. The storage 601 includes an HD 909 and is an example of a storage unit that stores various data. The memory 603 includes a MEM-P 902 and is an example of a memory for processing various data.

[0030] The memory controller 602 is realized by the NB 903, and communicates with the memory 603 according to a communication protocol such as DDR4. Specifically, the memory controller 602 has a storage unit 602a and a setting unit 602b.

[0031] The saving unit 602a acquires (generates) a table indicating the relationship between the eye opening margin (eye opening voltage) and the current consumption of the memory 603 for each combination of OCD and ODT in the memory 603. The saving unit 602a then saves the acquired table in the storage 601.

[0032] The storage unit 602a also performs Vref Training, which uses the OCD and ODT of the memory 603 as parameters to adjust (adjust) a reference voltage that can distinguish between High and Low in a communication protocol (for example, DDR4) with the memory 603. The storage unit 602a then determines the range of the adjusted reference voltage as the eye opening margin. In this way, by using a JEDEC standard function as a means for creating an OCD and ODT table in DDR4, it is possible to estimate the eye opening margin corresponding to the combination of OCD and ODT with high reliability and in a short time.

[0033] Furthermore, the storage unit 602a performs Vref Training again after a predetermined period has elapsed since the last Vref Training, based on the startup time and cumulative operating time of the MFP 9, to reacquire a table including the eye opening margin. This prevents changes in the order of the eye opening margin due to deterioration over time of the MFP 9 and temperature rises of the MFP 9. Furthermore, by periodically updating the table, it becomes possible to respond to dynamic fluctuations in the characteristics of the MFP 9, leading to higher reliability of the table.

[0034] The setting unit 602b sets an eye opening margin for each state of the MFP 9 based on a table stored in the storage 601. Furthermore, at the timing of switching the state of the MFP 9, the setting unit 602b sets the combination of OCD and ODT corresponding to the eye opening margin that minimizes the power consumption of the memory 603, among the eye opening margins set for the state after switching.

[0035] This makes it possible to adjust the output resistance (OCD) and internal termination resistance (ODT) of memory 603 such as DRAM according to the state of a device such as the MFP 9. As a result, it is possible to dynamically optimize the power consumption and waveform quality of memory 603. In other words, it is possible to always achieve both an optimal eye aperture margin setting and reduced power consumption of memory 603, regardless of the operating mode of a device such as the MFP 9 or the state of deterioration of the device over time.

[0036] FIG. 7 is a diagram illustrating an example of Vref Training in the MFP according to this embodiment. FIG. 8 is a diagram illustrating an example of table acquisition processing in the MFP according to this embodiment. First, a method for identifying the relationship between the eye opening voltage (eye opening margin) for each combination of OCD and ODT and the current consumption of memory 603 will be explained. In the case of DDR4, this can be easily achieved by applying the Vref Training function. The reference voltage Vref is a voltage that determines the high and low thresholds of a signal transmitted through a signal line. In DDR4, the reference voltage Vref can be adjusted by Vref Training, as shown in FIG. 7.

[0037] Vref Training is a standard feature of DDR4 that adjusts the reference voltage Vref while reading and writing a known data string from and to the memory 603 to determine the range within which High and Low voltages are normally distinguished. The result of conventional Vref Training is to set the reference voltage Vref at the center of this range, but in this embodiment, the storage unit 602a regards this range as the eye opening voltage and comprehensively acquires the eye opening voltage for each combination of OCD and ODT. As a result, the storage unit 602a acquires a ranking (table) of the eye opening voltage and current consumption of the memory 603 for each combination of OCD and ODT, as shown in FIG. 8.

[0038] 9 is a flowchart showing an example of the flow of a table creation process in the MFP according to this embodiment. In a typical embedded hardware configuration used in electronic devices including image forming apparatuses such as the MFP 9, when starting up the MFP 9, the CPU 901 performs startup preparations such as reading startup data (boot loader) from a mask ROM (Read Only Memory) (step S9001). After reading the startup data, the CPU 901 performs initialization processing of the memory 603 such as DRAM, such as leveling (step S9002). This initialization processing follows a method defined by JEDEC and includes Write Leveling, etc.

[0039] Immediately after the initialization process is completed, the storage unit 602a performs Vref Training for all combinations of OCD and ODT in the memory 603. Specifically, the storage unit 602a first changes the OCD and ODT to their minimum values ​​(step S9003). Furthermore, the storage unit 602a sets the mode (state) of the MFP 9 at the time of setting the changed OCD and ODT in a register (step S9004).

[0040] Next, the storage unit 602a performs Vref Training (step S9005). Specifically, the storage unit 602a uses Vref Training to acquire the range (margin) of the reference voltage Vref within which normal reading and writing to and from the memory 603 is possible, i.e., the eye opening voltage. The storage unit 602a also acquires the current consumption of the memory 603 for each combination of OCD and ODT according to Ohm's law. The storage unit 602a then saves a table containing the acquired eye opening voltages and current consumption of the memory 603 in the storage 601 (step S9006). The table may be recorded in any location; however, to prevent an increase in startup time, it may be stored in nonvolatile memory, and the table acquired the first time may be acquired thereafter.

[0041] Next, the storage unit 602a determines whether Vref Training has been performed for all OCDs (step S9007). If Vref Training has not been performed for all OCDs (step S9007: No), the storage unit 602a changes the OCD (step S9008) and returns to step S9004. On the other hand, if Vref Training has been performed for all OCDs (step S9007: Yes), the storage unit 602a determines whether Vref Training has been performed for all ODTs (step S9009).

[0042] If Vref Training has not been performed for all ODTs (step S9009: No), the storage unit 602a changes the ODTs and returns the OCD to the minimum (step S9010), and returns to step S9004. On the other hand, if Vref Training has been performed for all ODTs (step S9009: Yes), the storage unit 602a ends Vref Training.

[0043] After obtaining the table, the setting unit 602b refers to the table when switching the state of the MFP 9, obtains the OCD and ODT combination that consumes the least current from the memory 603 among the eye opening voltages required to stabilize quality in that state, and changes the OCD and ODT settings each time. Note that the eye opening voltage required for each state of the MFP 9 must be determined in advance through repeated evaluations of whether the startup of the MFP 9 is stable, whether abnormal images occur during printing, etc. It is generally known that the eye opening voltage decreases when power consumption increases, so it is advisable to ensure a relatively large margin.

[0044] As described above, the MFP 9 according to this embodiment can adjust the output resistance (OCD) and internal termination resistance (ODT) of the memory 603, such as a DRAM, in accordance with the state of the device, such as the MFP 9. As a result, it is possible to dynamically optimize the power consumption and waveform quality of the memory 603. In other words, it is possible to always achieve both an optimal eye aperture margin setting and reduced power consumption of the memory 603, regardless of the operating mode of the device, such as the MFP 9, or the state of deterioration of the device over time.

[0045] In the above embodiment, the image forming apparatus of the present invention is described as being applied to a multifunction peripheral having at least two of the functions of a copy function, a printer function, a scanner function, and a facsimile function, but the present invention can be applied to any image forming apparatus such as a copier, printer, scanner device, or facsimile device. [Explanation of symbols]

[0046] 9 MFP 601 Storage 602 Memory Controller 602a Storage Department 602b Setting section 603 memory 901 CPU 902 MEM-P 902a ROM 902b RAM 903 NB [Prior art documents] [Patent documents]

[0047] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-218142

Claims

1. An image forming apparatus using a digital circuit system having a memory for processing data, a storage unit that stores a table indicating the relationship between an eye opening margin that distinguishes between High and Low in a communication protocol with the memory and a current consumption of the memory for each combination of an OCD and an ODT of the memory; a setting unit that sets the eye opening margin for each state of the image forming apparatus based on the table, and at a timing when the state is switched, sets the combination corresponding to the eye opening margin that minimizes the current consumption among the eye opening margins set in the state after the switching; An image forming apparatus comprising:

2. 2. The image forming apparatus according to claim 1, wherein the storage unit performs Vref Training using the OCD and the ODT as parameters to adjust a reference voltage that can distinguish between High and Low in a communication protocol with the memory, and determines a range of the reference voltage that can distinguish between High and Low in the communication protocol with the memory as the eye opening margin.

3. 3. The image forming apparatus according to claim 2, wherein the storage unit performs the Vref Training again and acquires the table again after a predetermined period of time has elapsed since the last time the Vref Training was performed, based on the startup time and cumulative operating time of the image forming apparatus.

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