Calculation device

Abstract

To expand a memory space without requiring bank switching.SOLUTION: An arithmetic unit includes an arithmetic processing circuit configured so as to be capable of executing a program and a program memory for storing a program, each instruction in the program has a 16-bit length, the program memory has a first memory area, and a second memory area with which an address upper than that of the first memory area is correlated, the arithmetic processing circuit has a 16-bit program counter for designating an address for reading, and reads an instruction in an address corresponding to a value of the upper 15 bits in the program counter from an object memory area and executes it, and the object memory area is a memory area corresponding to a value of the least significant bit in the program counter within the first memory area and the second memory area.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to a computing device. [Background technology]

[0002] There is an arithmetic device that has a program memory that stores a program, which is a set of instructions, and an arithmetic processing circuit (CPU, etc.) that executes the program. The arithmetic processing circuit specifies the address where the instruction to be read is stored, and reads and executes the instruction at the specified address from the program memory. For example, in a configuration where an address is specified using two 8-bit registers, there are two types of specified addresses. 16 Since it is a type, the maximum program memory size is 64kB (kilobytes). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 53-46537 Summary of the Invention [Problem to be solved by the invention]

[0004] There are cases where memory space expansion is required. One method for expanding memory space is the bank switching method. However, the bank switching method leads to an increase in circuit size and a decrease in instruction efficiency.

[0005] The present disclosure aims to provide an arithmetic device that can expand the memory space of a program memory without requiring bank switching. [Means for solving the problem]

[0006] The arithmetic device according to the present disclosure comprises an arithmetic processing circuit configured to be able to execute a program, and a program memory for storing the program, wherein each instruction in the program is 16 bits long, the program memory has a first memory area and a second memory area associated with a higher address than the first memory area, the arithmetic processing circuit has a 16-bit program counter for specifying an address to be read, and reads and executes an instruction at an address corresponding to the value of the most significant 15 bits of the program counter from the target memory area, wherein the target memory area is the memory area between the first memory area and the second memory area corresponding to the value of the least significant bit of the program counter.

[0007] Another arithmetic device according to the present disclosure includes an arithmetic processing circuit configured to be able to execute a program, and a program memory for storing the program, wherein each instruction in the program has a length of a predetermined number of bits, the predetermined number of bits being J bits, where J=16×2 n-1 , where n is an integer of 2 or more, and the program memory includes first to second n The target memory area has a memory area, and a higher address is associated with the (i+1)th memory area rather than the i-th memory area, and the arithmetic processing circuit has a program counter of the predetermined bits for specifying the address to be read, and reads and executes an instruction at an address corresponding to the value of the upper (Jn) bit of the program counter from the target memory area, and the target memory area is one of the first to second n This memory area corresponds to the value of the lower n bits of the program counter. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a computing device that can expand the memory space of a program memory without requiring bank switching. [Brief explanation of the drawings]

[0009] [Figure 1]FIG. 1 is a schematic block diagram of a computing device according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing the configuration of a program memory bus according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a conceptual diagram of a memory space according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating a program counter and a plurality of general-purpose storage areas provided in a CPU according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a configuration diagram of a program memory according to a reference example (EX_1A). [Figure 6] FIG. 6 is a diagram showing a program counter and a plurality of general-purpose storage areas according to a reference example (EX_1A) and an embodiment (EX_1B) of the present disclosure. [Figure 7] FIG. 7 is a conceptual diagram of the operation of reading an instruction from the program memory according to the reference example (EX_1A). [Figure 8] FIG. 8 is a configuration diagram of a program memory according to an embodiment (EX_1B) of the present disclosure. [Figure 9] FIG. 9 is a conceptual diagram of an operation of reading an instruction from a program memory according to an embodiment (EX_1B) of the present disclosure. [Figure 10] FIG. 10 is a diagram showing the structures of a program counter and a read target address and the relationship between them according to an embodiment (EX_1B) of the present disclosure. [Figure 11] FIG. 11 is a diagram showing how branch destination addressing data is loaded into a program counter in response to a branch instruction, according to an embodiment (EX_1B) of the present disclosure. [Figure 12] FIG. 12 is a configuration diagram of a program memory according to a reference example (EX_2A). [Figure 13] FIG. 13 is a diagram showing a program counter and a plurality of general-purpose storage areas according to a reference example (EX_2A) and an embodiment (EX_2B) of the present disclosure. [Figure 14] FIG. 14 is a conceptual diagram of the operation of reading an instruction from the program memory according to the reference example (EX_2A). [Figure 15] FIG. 15 is a configuration diagram of a program memory according to an embodiment (EX_2B) of the present disclosure. [Figure 16] FIG. 16 is a conceptual diagram of an operation of reading an instruction from a program memory according to an embodiment (EX_2B) of the present disclosure. [Figure 17] FIG. 17 is a diagram showing the structures of a program counter and a read target address and the relationship between them according to an embodiment (EX_2B) of the present disclosure. [Figure 18] FIG. 18 is a diagram showing how branch destination addressing data is loaded into the program counter in response to a branch instruction, according to an embodiment (EX_2B) of the present disclosure. [Figure 19] FIG. 19 is a configuration diagram of a program memory according to an embodiment (EX_3B) of the present disclosure. [Figure 20] FIG. 20 is a conceptual diagram of an operation for reading an instruction from a program memory according to an embodiment (EX_3B) of the present disclosure. [Figure 21] FIG. 21 is a diagram showing the structures of a program counter and a read target address and the relationship between them according to an embodiment (EX_3B) of the present disclosure. [Figure 22] FIG. 22 is a diagram showing how branch destination addressing data is loaded into a program counter in response to a branch instruction, according to an embodiment (EX_3B) of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, identical parts are designated by the same reference numerals, and duplicate descriptions of identical parts will be omitted as a general rule. For the sake of simplicity, this specification may use symbols or reference numerals referring to information, signals, physical quantities, elements, or parts, and may omit or abbreviate the names of the information, signals, physical quantities, elements, or parts corresponding to the symbols or reference numerals. For example, the branch destination address storage area 610 referenced by "610" (see FIG. 11) described below may be written as the branch destination address storage area 610 or abbreviated as the storage area 610, but they all refer to the same thing.

[0011] 1 shows a schematic block diagram of a computing device 10 according to an embodiment of the present disclosure. The computing device 10 is configured using a semiconductor integrated circuit classified as an LSI (Large Scale Integration). The computing device 10 includes a CPU (Central Processing Unit) 20, a program memory 30, a program memory bus 40, a data memory 50, and a data memory bus 60.

[0012] The CPU 20 is an arithmetic processing circuit that performs calculations in units of 8 bits. Therefore, the arithmetic device 10 can be considered to be classified as an 8-bit microcomputer. The CPU 20 is connected to one end of a program memory bus 40, and the program memory 30 is connected to the other end of the program memory bus 40. In other words, the CPU 20 and the program memory 30 are connected to each other via the program memory bus 40.

[0013] The program memory 30 may be a non-volatile storage circuit such as a flash memory, or a volatile storage circuit such as a RAM (Random Access Memory). The program memory 30 stores a program to be executed by the CPU 20. The CPU 20 accesses the program memory 30 via a program memory bus 40. Access to the program memory 30 includes a read access for reading data (data representing instructions) from the program memory 30. The program stored in the program memory 30 consists of a set of instructions (instruction codes) to be executed by the CPU 20. The CPU 20 executes the program by sequentially reading the necessary instructions from the program memory 30 via the program memory bus 40 in synchronization with the CPU 20's operating clock, and then sequentially executing the sequentially read instructions after decoding, etc. In the following description, when the term "program" is used simply, it refers to the program stored in the program memory 30.

[0014] The data memory 50 is a memory provided in the arithmetic device 10 separately from the program memory 30, and is configured to include a ROM (Read only memory) and a RAM (Random access memory). The CPU 20 accesses the data memory 50 via a data memory bus 60. Access to the data memory 50 includes a read access for reading data from the data memory 50 and a write access for writing data to the data memory 50.

[0015] 2, the program memory bus 40 includes an address bus 41 and a data bus 42. The data memory bus 60 also includes an address bus and a data bus, but the configuration of the data memory bus 60 is not shown in FIG.

[0016] 3, a memory space MS is defined for the program memory 30 according to the size of the storage area of ​​the program memory 30. In the memory space MS, a unique address is assigned to every 8 bits (i.e., 1 byte). In the following explanation, an address refers to an address in the memory space MS defined in the program memory 30. Addresses are expressed as numerical values, and when viewed from a certain address of interest, an address indicated by a smaller numerical value is an address on the lower side of the address of interest, and an address indicated by a larger numerical value is an address on the upper side of the address of interest.

[0017] For example, when memory space MS has a storage area of ​​64 kB (kilobytes), the lowest address in memory space MS is "0x0000" and the highest address in memory space MS is "0xffff". In this embodiment, addresses are expressed in hexadecimal numbers as appropriate. The character string "0x" added to the beginning of a numerical value indicating an address indicates that the numerical value following the character string "0x" is a hexadecimal number. Therefore, "0x0000" represents "0" in decimal notation, and "0xffff" represents "65535" in decimal notation.

[0018] A plurality of registers are provided in the CPU 20. Each register is an 8-bit register (i.e., a register having a storage area of ​​8 bits). A program counter PC and one or more general-purpose storage areas are formed by all or part of the plurality of registers provided in the CPU 20 (see FIG. 4). The number of general-purpose storage areas formed is arbitrary, but here it is assumed that a total of eight general-purpose storage areas GPR[0] to GPR[7] are formed.

[0019] The program counter PC stores data for specifying an address to be read (i.e., an address to be accessed for reading). Hereinafter, the address to be read specified by the program counter PC is referred to as a read address. When the arithmetic device 10 is started, the lowest address of the memory space MS is assigned to the program counter PC.

[0020] Below, several specific operational examples, application techniques, modified techniques, etc. will be described in multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments unless otherwise specified and unless there is a contradiction. If there are any matters in each embodiment that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple embodiments shown below can also be applied to any other embodiment (i.e., any two or more of the multiple embodiments can be combined).

[0021] <<Reference example EX_1A>> Reference example EX_1A will be described below for comparison with embodiment EX_1B. In reference example EX_1A and embodiment EX_1B, each instruction executed by the CPU 20 has a 16-bit instruction length. That is, in reference example EX_1A and embodiment EX_1B, each instruction executed by the CPU 20 has a 16-bit length (consisting of 16-bit data).

[0022] The program memory 30 according to the reference example EX_1A will be specifically referred to as program memory 30_1A. FIG. 5 shows the configuration of the program memory 30_1A. The program memory 30_1A has a maximum memory space MS of 64 kB. Here, it is assumed that the program memory 30_1A has a memory space MS of 64 kB. In the program memory 30_1A, the lowest address is "0x0000" and the highest address is "0xffff".

[0023] Since each instruction has a length of 16 bits, the data length of a word, which is the unit of access to the program memory 30_1A, is 16 bits (16-bit length). That is, the CPU 20 according to the reference example EX_1A reads out one instruction to be executed next by reading out 16 bits of data from the program memory 30_1A all at once. Therefore, in the reference example EX_1A, the data bus 42 is formed by 16 wires.

[0024] 6, the program counter PC according to the reference example EX_1A and the embodiment EX_1B will be specifically referred to by the symbol "PC_1." In the reference example EX_1A and the embodiment EX_1B, the program counter PC_1 is configured by a combination of a first and a second register provided in the CPU 20. Since each instruction has a length of 16 bits, the value of the program counter PC_1 is incremented by 2 each time an instruction is executed by the CPU 20 (excluding branch instructions).

[0025] The general-purpose memory area GPR[i] according to reference example EX_1A and embodiment EX_1B will be referred to specifically by the symbol "GPR[i]_1" (i is an integer). In reference example EX_1A and embodiment EX_1B, the general-purpose memory area GPR[1]_1 is configured by a combination of the third and fourth registers provided in the CPU 20, and the general-purpose memory area GPR[2]_1 is configured by a combination of the fifth and sixth registers provided in the CPU 20. The same is true for the general-purpose memory areas GPR[3]_1 to GPR[7]_1.

[0026] As described above, each register provided in the CPU 20 is an 8-bit register (i.e., a register having a storage area for 8 bits). Therefore, the program counter PC_1 and the general-purpose storage areas GPR[0]_1 to GPR[7]_1 each have a storage area of ​​16 bits.

[0027] FIG. 7 shows a conceptual diagram of an instruction read operation (read access) from the program memory 30_1A according to the reference example EX_1A. The upper 15 bits of the program counter PC_1 are represented by the symbol "PC[15:1]." In the reference example EX_1A, the read target address is specified and expressed by 16 bits. In the reference example EX_1A, instructions are read in 16-bit units (i.e., in 2-byte units), so the least significant bit of the program counter PC_1 is always fixed at "0." In other words, the upper 15 bits of the read target address are specified by the value of the upper 15 bits of the program counter PC_1, and the value of the least significant bit of the read target address is always "0."

[0028] For example, if the values ​​of the upper 15 bits of the program counter PC_1 are all “0”, the read target address is “0x0000”. At this time, word data (2 bytes of data) consisting of 1 byte of data at address “0x0000” and 1 byte of data at address “0x0001” is read from the program memory 30_1A as data of one instruction and sent to the CPU 20.

[0029] Alternatively, for example, if the values ​​of the upper 15 bits of the program counter PC_1 are all “1”, the read address is “0xfffe”. At this time, word data (2 bytes of data) consisting of 1 byte of data at address “0xfffe” and 1 byte of data at address “0xffff” is read from the program memory 30_1A as data of one instruction and sent to the CPU 20.

[0030] In the reference example EX_1A, a bank switching method is used to expand the memory space MS beyond 64kB. In the bank switching method, multiple 64kB program memories are prepared, and the program memory to be read is switched appropriately by bank switching. However, since a circuit for bank switching is required, the circuit size becomes considerably larger. In addition, the program description for bank switching becomes complicated, and the compiler changes required to realize bank switching become complicated. Furthermore, since several instructions must be executed for each bank switch, instruction efficiency deteriorates.

[0031] <<Example EX_1B>> An example EX_1B will be described. In the example EX_1B, the memory space MS is expanded to 128 kB (kilobytes) without using bank switching based on the reference example EX_1A. In the reference example EX_1A, the value of the least significant bit of the program counter PC_1 is fixed to "0", and depending on how you look at it, it can be said that the least significant bit is not being used effectively. In the example EX_1B, the memory space MS is expanded to 128 kB by actively using the least significant bit.

[0032] The program memory 30 according to the embodiment EX_1B will be particularly referred to as program memory 30_1B. FIG. 8 shows the configuration of the program memory 30_1B. The program memory 30_1B has a maximum memory space MS of 128 kB. Here, it is assumed that the program memory 30_1B has a memory space MS of 128 kB. In the program memory 30_1B, the lowest address is "0x00000" and the highest address is "0x1ffff".

[0033] The program memory 30_1B is configured to include a first memory area 30_1B_1 and a second memory area 30_1B_2. Each memory area has a storage area of ​​64 kB to which consecutive addresses are associated. If an instruction is considered to be made up of J bits (here, 16 bits), 64 kB is 2 J The second memory area 30_1B_2 corresponds to a 64 kB memory area from address "0x00000" to address "0x0ffff". The second memory area 30_1B_2 corresponds to a 64 kB memory area from address "0x10000" to address "0x1ffff". The second memory area 30_1B_2 corresponds to a 64 kB memory area from address "0x10000" to address "0x1ffff".

[0034] Since each instruction has a 16-bit instruction length, the data length of a word, which is the unit of access to the program memory 30_1B, is 16 bits (16-bit length). That is, the CPU 20 according to the embodiment EX_1B reads out one instruction to be executed next by reading out 16 bits of data from the program memory 30_1B all at once. Therefore, in the embodiment EX_1B, the data bus 42 is formed by 16 wires.

[0035] Since each instruction has a length of 16 bits, the value of the program counter PC_1 is incremented by 2 each time an instruction is executed by the CPU 20. However, when a branch instruction is executed by the CPU 20, a value according to the branch instruction is substituted into the program counter PC_1.

[0036] 9 shows a conceptual diagram of an instruction read operation (read access) from the program memory 30_1B according to the embodiment EX_1B. Referring also to FIG. 10, the program counter PC_1 is made up of bits PC

[15] to PC[0], and the value of bit PC[i] in the program counter PC_1 is represented by the symbol "L[i]". In the program counter PC_1, bit PC

[15] is the most significant bit, bit PC[0] is the least significant bit, and bit PC[i+1] is located on the higher side than bit PC[i] (i is an arbitrary integer). As mentioned above, the most significant 15 bits of the program counter PC_1 (i.e., a collection of bits PC

[15] to PC[1]) are represented by the symbol "PC[15:1]".

[0037] In the embodiment EX_1B, since the program memory 30_1B has a memory space MS of 128 kB, the read target address is specified and expressed in 17 bits. The read target address according to the embodiment EX_1B will be particularly referred to by the symbol "ADR_1".

[0038] 10 shows the structure of the 16-bit program counter PC_1 and the structure of the 17-bit read address ADR_1. The read address ADR_1 consists of bits ADR

[16] to ADR[0], and the value of bit ADR[i] in the read address ADR_1 is represented by the symbol "M[i]". In the read address ADR_1, bit ADR

[16] is the most significant bit, bit ADR[0] is the least significant bit, and bit ADR[i+1] is located on the more significant side than bit ADR[i] (i is an arbitrary integer).

[0039] The value M

[16] of the most significant bit ADR

[16] of the read address ADR_1 is represented by the value L[0] of the least significant bit PC[0] of the program counter PC_1 (i.e., M

[16] = L[0]). The value M[0] of the least significant bit ADR[0] of the read address ADR_1 is fixed to a predetermined value "0". Of the bits of the read address ADR_1, the 15 bits lower than the most significant bit ADR

[16] and higher than the least significant bit ADR[0] are bits ADR[15:1]. The value of bits ADR[15:1] is represented by the value of the most significant 15 bits PC[15:1] of the program counter PC_1. That is, for each integer i that satisfies "1≦i≦15", "M[i] = L[i]" holds.

[0040] Therefore, the CPU 20 according to the embodiment EX_1B selects either the first memory area 30_1B_1 or the second memory area 30_1B_2 based on the value L[0] of the least significant bit of the program counter PC_1. The selected memory area is referred to as the target memory area for convenience. Then, within the target memory area, an address corresponding to the value of the most significant 15 bits PC[15:1] of the program counter PC_1 is set as the read target address. Then, one instruction (two bytes of data) starting from the set read target address is read from the program memory 30_1B and sent to the CPU 20. For the program memory 30_1B, the CPU 20 must specify a total of 16 bits of the read target address ADR_1, excluding the least significant bit. A total of 16 wires for this specification are provided on the address bus 41.

[0041] For example, consider a first case CS_1B in which the value stored in the program counter PC_1 is "0x1234." In the first case CS_1B, the read target address ADR_1 is "0x01234." In the first case CS_1B, since "L[0]=0," the target memory area is the first memory area 30_1B_1. Then, data in addresses "0x01234" and "0x01235" in the first memory area 30_1B_1 is read to the CPU 20 as one instruction. That is, word data (two bytes of data) consisting of one byte of data at address "0x01234" and one byte of data at address "0x01235" is read from the program memory 30_1B and sent to the CPU 20.

[0042] Also, for example, consider a second case CS_1B in which the value stored in the program counter PC_1 is "0x1235." In the second case CS_1B, the read target address ADR_1 is "0x11234." In the second case CS_1B, since "L[0]=1," the target memory area is the second memory area 30_1B_2. Then, data in addresses "0x11234" and "0x11235" in the second memory area 30_1B_2 is read to the CPU 20 as one instruction. That is, word data (two bytes of data) consisting of one byte of data at address "0x11234" and one byte of data at address "0x11235" is read from the program memory 30_1B and sent to the CPU 20.

[0043] The CPU 20 can execute multiple types of instructions. The multiple types of instructions include data transfer instructions, branch instructions, arithmetic instructions, bit manipulation instructions, and control instructions. When a branch instruction is executed, data 620 stored in a memory area 610 is loaded (transferred and written) into a program counter PC_1, as shown in FIG. 11. The memory area 610 is a branch destination address memory area, and the data 620 is branch destination address specification data. The load may be executed only when a condition specified in the branch instruction is satisfied, or may be executed unconditionally.

[0044] The branch destination address storage area 610 is a 16-bit storage area (i.e., has a storage area for 16 bits), and therefore the branch destination address designation data 620 is 16-bit data. The branch destination address is designated by the branch destination address designation data 620. Therefore, when the branch destination address designation data 620 is loaded into the program counter PC_1, the address based on the branch destination address designation data 620 becomes the next read target address ADR_1. As a result, a branch to the address based on the branch destination address designation data 620 is performed.

[0045] An example of a branch instruction is a jump instruction. In one type of jump instruction, data 620 stored in a memory area 610 is loaded into a program counter PC_1 only if a condition specified in the jump instruction is satisfied, or unconditionally. In this case, the memory area 610 is one of the 16-bit general-purpose memory areas GPR[0]_1 to GPR[7]_1 (FIG. 6), and which of the general-purpose memory areas GPR[0]_1 to GPR[7]_1 will be used as the memory area 610 is specified in the jump instruction.

[0046] An example of a branch instruction is a subroutine call instruction. In one type of subroutine call instruction, data 620 stored in a memory area 610 is loaded into a program counter PC_1. In this case, the memory area 610 is one of the 16-bit general-purpose memory areas GPR[0]_1 to GPR[7]_1 (FIG. 6), and which of the general-purpose memory areas GPR[0]_1 to GPR[7]_1 will be used as the memory area 610 is specified in the subroutine call instruction. When a branch is performed by a subroutine call instruction, the CPU 20 saves (stores) the value stored in the program counter PC_1 immediately before loading the data 620 into the program counter PC_1 in a stack area, and then performs address branching. The stack area in the embodiment EX_1B is a 16-bit memory area (i.e., has a memory area equivalent to 16 bits). The stack area may be provided in the data memory 50 or may be composed of two registers in the CPU 20.

[0047] A return instruction from a subroutine also belongs to the branch instruction category. A return instruction from a subroutine is an instruction that is executed after a branch is performed by a subroutine call instruction. In the return instruction from a subroutine, data 620 stored in memory area 610 is also loaded into program counter PC_1, but in this case, memory area 610 is the stack area.

[0048] In addition, a return from interrupt instruction also belongs to the branch instruction. When an interrupt occurs, the value stored in the program counter PC_1 immediately before the interrupt occurs is saved (stored) in the stack area. By the return from interrupt instruction, the CPU 20 returns to the state before the interrupt occurred. During this return, the stack area functions as a memory area 610, and data 620 stored in the memory area 610 is loaded into the program counter PC_1.

[0049] When data 620 is loaded (transferred and written) into the program counter PC_1 in a branch instruction, a branch is made to an address within either the first memory area 30_1B_1 or the second memory area 30_1B_2 depending on the value of the least significant bit of the data 620.

[0050] That is, consider the case where data 620 is loaded into program counter PC_1 by a branch instruction, and as a result of the load, the value "0" is stored in the least significant bit PC[0] of program counter PC_1. In this case, a branch occurs to an address that corresponds to the value of the most significant 15 bits of program counter PC_1 and is within the first memory area 30_1B_1.

[0051] More specifically, for example, when data 620 having a value of "0x1234" is loaded into program counter PC_1 by a branch instruction, the value "0" is stored in the least significant bit PC[0] of program counter PC_1. In this case, the read target address ADR_1 becomes "0x01234", and the next instruction read operation is the same as that in the first case CS_1B described above. When a program designer wants to cause a branch to an address in first memory area 30_1B_1, he or she simply sets the value of the least significant bit of data 620 to "0".

[0052] Conversely, consider a case where data 620 is loaded into program counter PC_1 by a branch instruction, and as a result of the load, the value "1" is stored in the least significant bit PC[0] of program counter PC_1. In this case, a branch occurs to an address that corresponds to the value of the most significant 15 bits of program counter PC_1 and is within the second memory area 30_1B_2.

[0053] More specifically, for example, when data 620 having a value of "0x1235" is loaded into program counter PC_1 by a branch instruction, a value of "1" is stored in the least significant bit PC[0] of program counter PC_1. In this case, the read target address ADR_1 becomes "0x11234", and the next instruction read operation is the same as that in the second case CS_1B described above. When a program designer wants to cause a branch to an address in second memory area 30_1B_2, he or she simply sets the value of the least significant bit of data 620 to "1".

[0054] According to the embodiment EX_1B, the memory space MS can be expanded to 128 kB without increasing the circuit size compared to the memory bank switching method. Furthermore, the compiler change required to change from the reference example EX_1A to the embodiment EX_1B is simple. Furthermore, since bank switching is not required, there is no degradation in instruction efficiency.

[0055] In addition, when upgrading from the configuration of reference example EX_1A to the configuration of embodiment EX_1B, instruction set compatibility is maintained. A further explanation of this is provided below. When considering a change from the configuration of reference example EX_1A to the configuration of embodiment EX_1B, a program designer is concerned about whether a program (binary program) designed for the configuration of reference example EX_1A will operate without problems in the configuration of embodiment EX_1B. In a program (binary program) designed for the configuration of reference example EX_1A, the value of the least significant bit of data 620 should be fixed to "0." Therefore, even if a program (binary program) designed for the configuration of reference example EX_1A is run in the configuration of embodiment EX_1B, the program will operate without problems because branch destinations are limited to the 64 kB space from "0x00000" to "0x0fffe." When developing a new program that attempts to access the extended space beyond "0x10000," the program designer need only consider whether the value of the least significant bit of data 620 should be "0" or "1."

[0056] <<Reference example EX_2A>> The technique for changing the configuration of reference example EX_1A to the configuration of embodiment EX_1B can be used even when the instruction length is other than 16 bits. Consider the case where the instruction length is 32 bits in reference example EX_2A and embodiment EX_2B. First, reference example EX_2A, which is used for comparison with embodiment EX_2B described later, will be described. In reference example EX_2A and embodiment EX_2B, each instruction executed by the CPU 20 has a 32-bit instruction length. That is, in reference example EX_2A and embodiment EX_2B, each instruction executed by the CPU 20 has a 32-bit length (composed of 32-bit data).

[0057] The program memory 30 according to reference example EX_2A will be specifically referred to as program memory 30_2A. FIG. 12 shows the configuration of program memory 30_2A. Program memory 30_2A has a maximum memory space MS of 4 GB (gigabytes). Here, it is assumed that program memory 30_2A has a memory space MS of 4 GB. In program memory 30_2A, the lowest address is "0x00000000", and the highest address is "0xffffffff".

[0058] Since each instruction has a length of 32 bits, the data length of a word, which is the unit of access to the program memory 30_2A, is 32 bits (32-bit length). That is, the CPU 20 according to the reference example EX_2A reads out one instruction to be executed next by reading out 32 bits of data from the program memory 30_2A all at once. Therefore, in the reference example EX_2A, the data bus 42 is formed by 32 wires.

[0059] 13, the program counter PC according to the reference example EX_2A and the embodiment EX_2B will be specifically referred to by the symbol "PC_2." In the reference example EX_2A and the embodiment EX_2B, the program counter PC_2 is configured by a combination of four registers provided in the CPU 20. Since each instruction has a 32-bit instruction length, the value of the program counter PC_2 is incremented by 4 each time an instruction is executed by the CPU 20 (excluding branch instructions).

[0060] The general-purpose memory area GPR[i] according to the reference example EX_2A and the embodiment EX_2B will be specifically referred to by the symbol "GPR[i]_2" (where i is an integer). In the reference example EX_2A and the embodiment EX_2B, each general-purpose memory area is composed of a combination of four registers.

[0061] As described above, each register provided in the CPU 20 is an 8-bit register (i.e., a register having an 8-bit storage area). Therefore, the program counter PC_2 and the general-purpose storage areas GPR[0]_2 to GPR[7]_2 each have a 32-bit storage area.

[0062] FIG. 14 shows a conceptual diagram of an instruction read operation (read access) from program memory 30_2A according to reference example EX_2A. The upper 30 bits of program counter PC_2 are represented by the symbol "PC[31:2]." In reference example EX_2A, the read target address is specified and expressed in 32 bits. In reference example EX_2A, instructions are read in 32-bit units (i.e., in 4-byte units), so the lower 2 bits (the least significant bit and the second lowest bit) of program counter PC_2 are always fixed at "0." In other words, the upper 30 bits of the read target address are specified by the value of the upper 30 bits of program counter PC_2, and the values ​​of the lower 2 bits (the least significant bit and the second lowest bit) of the read target address are always "0."

[0063] For example, if the values ​​of the upper 30 bits of the program counter PC_2 are all “0”, the read target address is “0x00000000”. At this time, a total of four bytes of data starting from the address “0x00000000”, i.e., a total of four bytes of data from the address “0x00000000” to the address “0x00000003”, are read from the program memory 30_2A as data for one instruction and sent to the CPU 20.

[0064] Alternatively, for example, if the values ​​of the upper 30 bits of the program counter PC_2 are all “1”, the read target address is “0xfffffffc”. In this case, a total of 4 bytes of data starting from the address “0xfffffffc”, i.e., a total of 4 bytes of data from the address “0xfffffffc” to the address “0xffffffff”, is read from the program memory 30_2A as data for one instruction and sent to the CPU 20.

[0065] <<Example EX_2B>> An example EX_2B will be described. In the example EX_2B, the memory space MS is expanded to 16 GB (gigabytes) without using bank switching based on the reference example EX_2A.

[0066] The program memory 30 according to the embodiment EX_2B will be particularly referred to as program memory 30_2B. FIG. 15 shows the configuration of the program memory 30_2B. The program memory 30_2B has a maximum memory space MS of 16 GB. Here, it is assumed that the program memory 30_2B has a memory space MS of 16 GB. In the program memory 30_2B, the lowest address is "0x000000000", and the highest address is "0x3ffffffff".

[0067] The program memory 30_2B is configured to include a first memory area 30_2B_1, a second memory area 30_2B_2, a third memory area 30_2B_3, and a fourth memory area 30_2B_4. Each memory area has a storage area of ​​4 GB to which consecutive addresses are associated. If an instruction is considered to be made up of J bits (here, 32 bits), 4 GB is 2 J It corresponds to bytes. A higher address than the i-th memory area is associated with the (i+1)-th memory area. In detail, the first memory area 30_2B_1 is a 4 GB memory area from address "0x000000000" to address "0x0ffffffff". The second memory area 30_2B_2 is a 4 GB memory area from address "0x100000000" to address "0x1ffffffff". The third memory area 30_2B_3 is a 4 GB memory area from address "0x200000000" to address "0x2ffffffff". The fourth memory area 30_2B_4 is a 4 GB memory area from address "0x300000000" to address "0x3ffffffff".

[0068] Since each instruction has a length of 32 bits, the data length of a word, which is the unit of access to the program memory 30_2B, is 32 bits (32-bit length). That is, the CPU 20 according to the embodiment EX_2B reads one instruction to be executed next by reading 32 bits of data from the program memory 30_2B all at once. Therefore, in the embodiment EX_2B, the data bus 42 is formed by 32 wires.

[0069] Since each instruction has a length of 32 bits, the value of the program counter PC_2 is incremented by 4 each time an instruction is executed by the CPU 20. However, when a branch instruction is executed by the CPU 20, a value according to the branch instruction is substituted into the program counter PC_2.

[0070] 16 shows a conceptual diagram of an instruction read operation (read access) from the program memory 30_2B according to the embodiment EX_2B. Referring also to FIG. 17, the program counter PC_2 is made up of bits PC

[31] to PC[0], and the value of bit PC[i] in the program counter PC_2 is represented by the symbol "L[i]". In the program counter PC_2, bit PC

[31] is the most significant bit, bit PC[0] is the least significant bit, and bit PC[i+1] is located on the higher side than bit PC[i] (i is an arbitrary integer). As mentioned above, the upper 30 bits of the program counter PC_2 (i.e., a collection of bits PC

[31] to PC[2]) are represented by the symbol "PC[31:2]".

[0071] In the example EX_2B, since the program memory 30_2B has a memory space MS of 16 GB, the read target address is specified and expressed in 34 bits. The read target address according to the example EX_2B will be particularly referred to by the symbol "ADR_2".

[0072] 17 shows the structure of the 32-bit program counter PC_2 and the structure of the 34-bit read address ADR_2. The read address ADR_2 consists of bits ADR

[33] to ADR[0], and the value of bit ADR[i] in the read address ADR_2 is represented by the symbol "M[i]". In the read address ADR_2, bit ADR

[33] is the most significant bit, bit ADR[0] is the least significant bit, and bit ADR[i+1] is located on the higher side than bit ADR[i] (i is an arbitrary integer).

[0073] The values ​​of the two most significant bits ADR

[33] and ADR

[32] of the read address ADR_2 are expressed by the values ​​of the two least significant bits PC[1] and PC[0] of the program counter PC_2. That is, "M

[33] =L[1]" and "M

[32] =L[0]".

[0074] Of the bits of the read address ADR_2, the values ​​of the two least significant bits ADR[1] and ADR[0] are fixed to a predetermined value "0." That is, they are fixed to "M[1]=M[0]=0."

[0075] Of the bits of the read address ADR_2, the bits ADR[31:2] are lower than the two most significant bits ADR

[33] and ADR

[32] and higher than the two least significant bits ADR[1] and ADR[0], totaling 30 bits. The value of the bits ADR[31:2] is represented by the value of the most significant 30 bits PC[31:2] of the program counter PC_2. That is, for each integer i that satisfies "2≦i≦31", "M[i]=L[i]" holds.

[0076] Therefore, the CPU 20 according to the embodiment EX_2B selects one of the memory areas 30_2B_1 to 30_2B_4 based on the values ​​L[1] and L[0] of the two lowest bits of the program counter PC_2. The selected memory area is referred to as the target memory area for convenience. Then, within the target memory area, an address corresponding to the value of the 30 most significant bits PC[31:2] of the program counter PC_2 is set as the read target address. Then, one instruction (four bytes of data) starting from the set read target address is read from the program memory 30_2B and sent to the CPU 20. Note that, for the program memory 30_2B, the CPU 20 must specify a total of 32 bits of the read target address ADR_2, excluding the two lowest bits (ADR[1] and ADR[0]). A total of 32 wires for this specification are provided on the address bus 41.

[0077] As described above, the CPU 20 can execute multiple types of instructions, including data transfer instructions, branch instructions, arithmetic instructions, bit manipulation instructions, and control instructions. When a branch instruction is executed in the configuration according to the embodiment EX_2B, data 720 stored in a memory area 710 is loaded (transferred and written) into the program counter PC_2, as shown in FIG. 18. The memory area 710 is a branch destination address memory area, and the data 720 is branch destination address specification data. This loading may be performed only if the condition specified in the branch instruction is satisfied, or may be performed unconditionally.

[0078] The branch destination address storage area 710 is a 32-bit storage area (i.e., has a storage area for 32 bits), and therefore the branch destination address designation data 720 is 32-bit data. The branch destination address is designated by the branch destination address designation data 720. Therefore, when the branch destination address designation data 720 is loaded into the program counter PC_2, the address based on the branch destination address designation data 720 becomes the next read target address. As a result, a branch to the address based on the branch destination address designation data 720 is performed.

[0079] An example of a branch instruction is a jump instruction. In one type of jump instruction, data 720 stored in a memory area 710 is loaded into a program counter PC_2 only if a condition specified in the jump instruction is satisfied, or unconditionally. In this case, the memory area 710 is one of the 32-bit general-purpose memory areas GPR[0]_2 to GPR[7]_2 (FIG. 13), and which of the general-purpose memory areas GPR[0]_2 to GPR[7]_2 will be used as the memory area 710 is specified in the jump instruction.

[0080] An example of a branch instruction is a subroutine call instruction. In one type of subroutine call instruction, data 720 stored in a memory area 710 is loaded into a program counter PC_2. In this case, the memory area 710 is one of the 32-bit general-purpose memory areas GPR[0]_2 to GPR[7]_2 (FIG. 13), and which of the general-purpose memory areas GPR[0]_2 to GPR[7]_2 will be used as the memory area 710 is specified in the subroutine call instruction. When a branch is performed by a subroutine call instruction, the CPU 20 saves (stores) the value stored in the program counter PC_2 immediately before loading the data 720 into the program counter PC_2 in the stack area, and then performs address branching. The stack area in the embodiment EX_2B is a 32-bit memory area (i.e., has a memory area equivalent to 32 bits). The stack area may be provided in the data memory 50 or may be composed of four registers in the CPU 20.

[0081] A return instruction from a subroutine also belongs to the branch instruction category. A return instruction from a subroutine is an instruction that is executed after a branch is performed by a subroutine call instruction. In the return instruction from a subroutine, data 720 stored in memory area 710 is also loaded into program counter PC_2, but in this case, memory area 710 is the stack area.

[0082] In addition, a return from interrupt instruction also belongs to the branch instruction. When an interrupt occurs, the value stored in the program counter PC_2 immediately before the interrupt occurs is saved (stored) in the stack area. By the return from interrupt instruction, the CPU 20 returns to the state before the interrupt occurred. During this return, the stack area functions as a memory area 710, and data 720 stored in the memory area 710 is loaded into the program counter PC_2.

[0083] When data 720 is loaded (transferred and written) into the program counter PC_2 in a branch instruction, branching occurs to an address within one of the memory areas 30_2B_1 to 30_2B_4 depending on the value of the two least significant bits of the data 720. The two least significant bits of the data 720 refer to the first least significant bit (i.e., the least significant bit) and the second least significant bit (the bit next to the least significant bit) of the bits of the data 720.

[0084] For example, consider the case where data 720 is loaded into the program counter PC_2 by a branch instruction, and as a result of the load, a value of "0" is stored in each of bits PC[1] and PC[0] of the program counter PC_2. In this case, a branch occurs to an address corresponding to the value of the most significant 30 bits PC[31:2] of the program counter PC_2, which is also an address within the first memory area 30_2B_1. That is, for example, when data 720 having a value of "0x12345670" is loaded into the program counter PC_2 by a branch instruction, a value of "0" is stored in each of bits PC[1] and PC[0] of the program counter PC_2. Then, the read target address ADR_2 becomes an address within the first memory area 30_2B_1, and a branch occurs to an address within the first memory area 30_2B_1 based on the data 720.

[0085] Also, for example, consider a case where data 720 is loaded into the program counter PC_2 by a branch instruction, and as a result of the load, the values ​​"0" and "1" are stored in bits PC[1] and PC[0] of the program counter PC_2, respectively. In this case, a branch occurs to an address corresponding to the value of the most significant 30 bits PC[31:2] of the program counter PC_2, which is also an address within the second memory area 30_2B_2. That is, for example, when data 720 having a value of "0x12345671" is loaded into the program counter PC_2 by a branch instruction, the values ​​"0" and "1" are stored in bits PC[1] and PC[0] of the program counter PC_2, respectively. Then, the read target address ADR_2 becomes an address within the second memory area 30_2B_2, and a branch occurs to an address within the second memory area 30_2B_2 based on the data 720.

[0086] Further, for example, consider a case where data 720 is loaded into the program counter PC_2 by a branch instruction, and as a result of the load, the values ​​"1" and "0" are stored in bits L[1] and L[0] of the program counter PC_2, respectively. In this case, a branch occurs to an address corresponding to the value of the most significant 30 bits PC[31:2] of the program counter PC_2, which is also an address within the second memory area 30_2B_3. That is, for example, when data 720 having a value of "0x12345672" is loaded into the program counter PC_2 by a branch instruction, the values ​​"1" and "0" are stored in bits PC[1] and PC[0] of the program counter PC_2, respectively. Then, the read target address ADR_2 becomes an address within the third memory area 30_2B_3, and a branch occurs to an address within the third memory area 30_2B_3 based on the data 720.

[0087] Further, for example, consider a case where data 720 is loaded into the program counter PC_2 by a branch instruction, and as a result of the load, a value of "1" is stored in each of bits PC[1] and PC[0] of the program counter PC_2. In this case, a branch occurs to an address corresponding to the value of the most significant 30 bits PC[31:2] of the program counter PC_2, which is also an address within the fourth memory area 30_2B_4. That is, for example, when data 720 having a value of "0x12345673" is loaded into the program counter PC_2 by a branch instruction, a value of "1" is stored in each of bits PC[1] and PC[0] of the program counter PC_2. Then, the read target address ADR_2 becomes an address within the fourth memory area 30_2B_4, and a branch occurs to an address within the fourth memory area 30_2B_4 based on the data 720.

[0088] Here, it is assumed that "(M

[33] , M

[32] ) = (L[1], L[0])" holds (see Figure 17), but this can also be modified to hold that "(M

[33] , M

[32] ) = (L[0], L[1])".

[0089] <<Example EX_3B>> An example EX_3B will be described. The instruction length of each instruction executed by the CPU 20 is represented by the symbol "J". That is, each instruction executed by the CPU 20 has a length of J bits (composed of J bits of data). Here, J=16×2 n-1 holds, where n is any natural number. 2 n-1 represents 2 to the (n-1)th power. If "n=1", then "J=16", and if "n=2", then "J=32". Example EX_1B shows a method for expanding memory space MS when "n=1", and example EX_2B shows a method for expanding memory space MS when "n=2". Example EX_3B shows a method for expanding memory space MS after generalizing the value of n.

[0090] The program memory 30 according to the embodiment EX_3B will be referred to as a program memory 30_nB. The configuration of the program memory 30_nB is shown in Fig. 19. The program memory 30_nB has a memory space MS of a predetermined size.

[0091] Since each instruction has a length of J bits, the data length of a word, which is the unit of access to the program memory 30_nB, is J bits (J-bit length). That is, the CPU 20 according to the embodiment EX_3B reads one instruction to be executed next by reading J bits of data all at once from the program memory 30_nB. Therefore, in the embodiment EX_3B, the data bus 42 is formed by J wires.

[0092] Program memory 30_nB is a total of 2 n It has a total of 2 memory areas. n The memory areas are numbered 1 to 2. n It is a memory area. n represents the nth power of 2. The jth memory area in the program memory 30_nB is referred to by the symbol "30_nB_[j]" (j is an integer). In the program memory 30_nB, each memory area has a storage area of ​​a predetermined size to which consecutive addresses are associated. In the program memory 30_nB, the (i+1)th memory area is associated with a higher address than the i-th memory area. Each memory area in the program memory 30_nB is referred to by the symbol "30_nB_[j]" (j is an integer). J It has a storage area of ​​100 bytes.

[0093] The program counter PC according to the embodiment EX_3B will be referred to by the symbol "PC_n". The program counter PC_n has a storage area of ​​J bits. The program counter PC_n is configured by a combination of a plurality of registers provided in the CPU 20. Since each instruction has an instruction length of J bits, the value of the program counter PC_n is incremented by "2" each time an instruction is executed by the CPU 20. n However, when a branch instruction is executed by the CPU 20, a value according to the branch instruction is substituted into the program counter PC_n.

[0094] FIG. 20 shows a conceptual diagram of an instruction read operation (read access) from the program memory 30_nB according to the embodiment EX_3B. The meaning of the symbol "Z" shown in FIG. 20 will become clear from the following description. Referring also to FIG. 21, the program counter PC_n is made up of bits PC[J-1] to PC[0], and the value of bit PC[i] in the program counter PC_n is represented by the symbol "L[i]." In the program counter PC_n, bit PC[J-1] is the most significant bit, bit PC[0] is the least significant bit, and bit PC[i+1] is located higher than bit PC[i] (i is an arbitrary integer). The higher-order (Jn) bits of the program counter PC_1 (i.e., a collection of bits PC[J-1] to PC[n]) are represented by the symbol "PC[J-1:n]."

[0095] In the embodiment EX_3B, the read address is specified and expressed by (J+n) bits. The read address according to the embodiment EX_3B will be specifically referred to by the symbol "ADR_n".

[0096] 21 shows the structure of a J-bit program counter PC_n and the structure of a (J+n)-bit read address ADR_n. The read address ADR_n consists of bits ADR[J+n-1] to ADR[0], and the value of bit ADR[i] in the read address ADR_n is represented by the symbol "M[i]". In the read address ADR_n, bit ADR[J+n-1] is the most significant bit and bit ADR[0] is the least significant bit, and bit ADR[i+1] is located on the more significant side than bit ADR[i] (i is an arbitrary integer).

[0097] The value of the most significant n bits in the read address ADR_n is represented by the value of the least significant n bits in the program counter PC_n. Here, the most significant n bits in the read address ADR_n are the total n bits including the most significant bit and continuing from the most significant bit of the bits of the read address ADR_n, i.e., bits ADR[J+n-1] to ADR[J]. The least significant n bits in the program counter PC_n are the total n bits including the least significant bit and continuing from the least significant bit of the bits of the program counter PC_n, i.e., bits PC[n-1] to PC[0]. The values ​​M[J+n-1] to M[J] are equal to the values ​​L[n-1] to L[0], respectively. For example, if "n=3", then "(M

[66] , M

[65] , M

[64] )=(L[2], L[1], L[0])".

[0098] The value of the lowest n bits in the read address ADR_n is fixed at a predetermined value "0". Here, the lowest n bits in the read address ADR_n are the total n bits including the least significant bit and continuing from the least significant bit of the bits in the read address ADR_n, that is, bits ADR[n-1] to ADR[0]. Therefore, the values ​​M[n-1] to M[0] are all fixed at "0".

[0099] Of the bits of the read address ADR_n, a total of (Jn) bits that are lower than the above-mentioned upper n bits (ADR[J+n-1] to ADR[J]) and higher than the above-mentioned lower two bits (ADR[n-1] to ADR[0]) are bits ADR[J-1:n]. The value of bits ADR[J-1:n] is represented by the value of the upper (Jn) bits of program counter PC_n. The upper (Jn) bits of program counter PC_n are bits PC[J-1:n]. That is, for each integer i that satisfies "n≦i≦J-1", "M[i]=L[i]" holds.

[0100] Therefore, the CPU 20 according to the embodiment EX_3B calculates the address of the memory areas 30_nB_[1] to 30_nB_[2] based on the values ​​L[n-1] to L[0] of the lower n bits of the program counter PC_n. n ] is selected. For convenience, the memory area selected here is referred to as the target memory area. Then, within the target memory area, an address according to the value of the upper (Jn) bit of the program counter PC_n, that is, an address according to the values ​​L[J-1] to L[n] of bits PC[J-1] to PC[n], is set as the read target address. Then, one instruction (2 n byte's worth of data) is read from the program memory 30_nB and sent to the CPU 20. For the program memory 30_nB, it is necessary for the CPU 20 to specify a total of J bits of the read address ADR_n excluding the lower n bits (ADR[n-1] to ADR[0]). A total of J wires for this specification are provided on the address bus 41.

[0101] As described above, the CPU 20 can execute a variety of instructions, including data transfer instructions, branch instructions, arithmetic instructions, bit manipulation instructions, and control instructions. When a branch instruction is executed in the configuration according to embodiment EX_3B, data 820 stored in a memory area 810 is loaded (transferred and written) into a program counter PC_n, as shown in FIG. 22. The memory area 810 is a branch destination address memory area, and the data 820 is branch destination address specification data. The load may be executed only when a condition specified in the branch instruction is satisfied, or may be executed unconditionally.

[0102] The branch destination address storage area 810 is a J-bit storage area (i.e., has a storage area for J bits), and therefore the branch destination address designation data 820 is J-bit data. The branch destination address is designated by the branch destination address designation data 820. Therefore, when the branch destination address designation data 820 is loaded into the program counter PC_n, the address based on the branch destination address designation data 820 becomes the next read target address. As a result, a branch to the address based on the branch destination address designation data 820 is performed.

[0103] An example of a branch instruction is a jump instruction. In one type of jump instruction, data 820 stored in a memory area 810 is loaded into a program counter PC_n only if a condition specified in the jump instruction is satisfied, or unconditionally. In this case, the memory area 810 is one of the J-bit general-purpose memory areas GPR[0] to GPR[7], and which of the general-purpose memory areas GPR[0] to GPR[7] will be used as the memory area 810 is specified in the jump instruction.

[0104] An example of a branch instruction is a subroutine call instruction. In one type of subroutine call instruction, data 820 stored in a memory area 810 is loaded into a program counter PC_n. In this case, the memory area 810 is one of the J-bit general-purpose memory areas GPR[0] to GPR[7], and which of the general-purpose memory areas GPR[0] to GPR[7] will be used as the memory area 810 is specified in the subroutine call instruction. When a branch is performed by a subroutine call instruction, the CPU 20 saves (stores) the value stored in the program counter PC_n immediately before loading the data 820 into the program counter PC_n in a stack area, and then performs address branching. The stack area in embodiment EX_3B is a J-bit memory area (i.e., has a memory area for J bits). The stack area may be provided in the data memory 50 or may be composed of multiple registers in the CPU 20.

[0105] A return instruction from a subroutine also belongs to the branch instruction category. A return instruction from a subroutine is an instruction that is executed after a branch is performed by a subroutine call instruction. In the return instruction from a subroutine, data 820 stored in memory area 810 is also loaded into program counter PC_n, but in this case, memory area 810 is a stack area.

[0106] In addition, a return from interrupt instruction also belongs to the branch instruction. When an interrupt occurs, the value stored in the program counter PC_n immediately before the interrupt occurs is saved (stored) in the stack area. By the return from interrupt instruction, the CPU 20 returns to the state before the interrupt occurred. During this return, the stack area functions as a memory area 810, and data 820 stored in the memory area 810 is loaded into the program counter PC_n.

[0107] When data 820 is loaded (transferred and written) into the program counter PC_n in a branch instruction, the data is stored in the memory areas 30_nB_[1] to 30_nB_[2] according to the value of the lower n bits of the data 820. n The n lowest bits of the data 820 are the n bits of the data 820 that include the least significant bit and are consecutive from the least significant bit.

[0108] Here, the value stored in the lowest n bits of the program counter PC_n is represented by the symbol "Z". The value Z is a single numerical value represented by the lowest n bits of the program counter PC_n, i.e., the total of n bits PC[n-1] to PC[0]. For example, if "n=2", the value Z is represented by 2 bits and therefore represents an integer value between 0 and 3, and if "n=3", the value Z is represented by 3 bits and therefore represents an integer value between 0 and 7. In other words, the value Z is represented by the first value to the second value. n The value will be one of the following: 1st value ~ 2nd value n The values ​​are different from each other. For example, if "n=2", the first value to the second value nThe values ​​are the first to fourth values, and the first to fourth values ​​are 0 to 3, respectively. For example, if "n=3", the first to second values ​​are n The values ​​are the first to eighth values, and the first to eighth values ​​are 0 to 7, respectively.

[0109] The value Z may be a value stored in the lowest n bits of the program counter PC_n as a result of loading data 820 into the program counter PC_n by a branch instruction. Consider a case where the value Z matches the k-th value due to a branch instruction. That is, consider a case where the value Z stored in the lowest n bits of the program counter PC_n as a result of loading data 820 into the program counter PC_n by a branch instruction matches the k-th value. Here, k is 1 or greater and 2 n The following integers:

[0110] In this case, branching occurs to an address corresponding to the value of the upper (Jn) bit of the program counter PC_n (i.e., an address corresponding to the values ​​L[J-1] to L[n]) and within the kth memory area 30_nB_[k].

[0111] Here, it is assumed that the values ​​M[J+n-1] to M[J] correspond to the values ​​L[n-1] to L[0], respectively (see FIG. 21). However, the correspondence between the values ​​M[J+n-1] to M[J] and the values ​​L[n-1] to L[0] can be modified. For example, if "n=3", then "(M

[66] , M

[65] , M

[64] ) = (L[2], L[1], L[0])" or "(M

[66] , M

[65] , M

[64] ) = (L[0], L[1], L[2])" may also be used.

[0112] <<Example EX_4>> Example EX_4 will be explained.

[0113] Each circuit element constituting the arithmetic device 10 is formed in the form of a semiconductor integrated circuit, and the semiconductor integrated circuit is enclosed in a housing (package) made of resin to form a semiconductor device. However, a circuit equivalent to the circuit in the arithmetic device 10 may be formed using multiple discrete components.

[0114] Although it is assumed that the CPU 20 is an arithmetic processing circuit that performs calculations in units of 8 bits, the CPU 20 may be an arithmetic processing circuit that performs calculations in units of bits other than 8 bits (for example, 16 bits or 32 bits).

[0115] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

[0116] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0117] An arithmetic device according to one aspect of the present disclosure (Example EX_1B, see Figures 8 to 11) comprises an arithmetic processing circuit (20) configured to be able to execute a program, and a program memory (30_1B) for storing the program, each instruction in the program having a length of 16 bits, the program memory having a first memory area (30_1B_1) and a second memory area (30_1B_2) associated with a higher address than the first memory area, the arithmetic processing circuit having a 16-bit program counter (PC_1) for specifying an address to be read, reading and executing an instruction at an address corresponding to the value of the most significant 15 bits (PC[15:1]) of the program counter from the target memory area, the target memory area being a memory area of ​​the first memory area or the second memory area corresponding to the value of the least significant bit (L[0]) of the program counter (first configuration).

[0118] This makes it possible to expand the memory space of the program memory without the need for bank switching. Compared to the bank switching method, this method allows memory space to be expanded without increasing the circuit size, and compiler changes required for such expansion are also simple. Furthermore, since bank switching is not required, there is no degradation in instruction efficiency. Furthermore, instruction set compatibility is maintained when expanding memory space.

[0119] Regarding the arithmetic device according to the first configuration (see FIG. 11), in the arithmetic processing circuit, 2 is added to the program counter each time an instruction other than a branch instruction is executed, and when the branch instruction is executed, stored data (620) in a 16-bit memory area (610) for specifying a branch destination address is loaded into the program counter, and branching to an address in either the first memory area or the second memory area is performed depending on the value of the least significant bit of the stored data (second configuration).

[0120] This makes it possible to easily branch to the expanded memory space with a branch instruction.

[0121] The arithmetic device according to the second configuration may be configured such that, when the branch instruction is executed by the arithmetic processing circuit, if a first value (e.g., "0") is stored in the least significant bit of the program counter as a result of loading the stored data into the program counter, the arithmetic processing circuit branches to an address in the first memory area that corresponds to the value of the most significant 15 bits (PC[15:1]) of the program counter, and if a second value ("1") is stored in the least significant bit of the program counter as a result of loading the stored data into the program counter, the arithmetic processing circuit branches to an address in the second memory area that corresponds to the value of the most significant 15 bits (PC[15:1]) of the program counter (third configuration).

[0122] This makes it possible to easily branch to the expanded memory space with a branch instruction.

[0123] In the arithmetic device according to the third configuration (see FIG. 10), the arithmetic processing circuit reads an instruction at a read target address (ADR_1) from the program memory and executes it; The read target address may be a 17-bit address, the value of the most significant bit (M

[16] ) of the read target address is represented by the value of the least significant bit (L[0]) of the program counter, the value of the least significant bit (M[0]) of the read target address is fixed at a predetermined value, and the value of a total of 15 bits (M

[15] to M[1]) that are lower than the most significant bit and higher than the least significant bit of the read target address are represented by the value of the most significant 15 bits (L

[15] to L[1]) of the program counter (fourth configuration).

[0124] An arithmetic device according to another aspect of the present disclosure (Example EX_3B, see FIGS. 19 to 22) includes an arithmetic processing circuit (20) configured to be able to execute a program, and a program memory (30_nB) for storing the program, wherein each instruction in the program has a length of a predetermined number of bits, the predetermined number of bits being J bits, and J=16×2n-1 , where n is an integer of 2 or more, and the program memory includes first to second n Memory area (30_nB_[1]~30_nB_[2 n ]), and a higher address is associated with the (i+1)th memory area rather than the i-th memory area, and the arithmetic processing circuit has a program counter (PC_n) of the predetermined bits for specifying an address to be read, and reads and executes an instruction at an address corresponding to the value of the upper (Jn) bit (PC[J-1:n]) of the program counter from the target memory area, and the target memory area is one of the first to second n The memory area is configured to be a memory area according to the value of the lower n bits of the program counter (fifth configuration).

[0125] This makes it possible to expand the memory space of the program memory without the need for bank switching. Compared to the bank switching method, this method allows memory space to be expanded without increasing the circuit size, and compiler changes required for such expansion are also simple. Furthermore, since bank switching is not required, there is no degradation in instruction efficiency. Furthermore, instruction set compatibility is maintained when expanding memory space.

[0126] Regarding the arithmetic device according to the fifth configuration (see FIG. 22), in the arithmetic processing circuit, Each time an instruction other than a branch instruction is executed, the program counter is incremented by 2. n is added, When the branch instruction is executed, stored data (820) in the storage area (810) of the predetermined bits for specifying the address of the branch destination is loaded into the program counter, and the first to second bits are selected according to the value (Z) of the lower n bits of the stored data. n A configuration (sixth configuration) in which the instruction branches to an address within one of the memory areas may also be used.

[0127] This makes it possible to easily branch to the expanded memory space with a branch instruction.

[0128] In the arithmetic device according to any one of the first to fifth configurations, when the branch instruction is executed by the arithmetic processing circuit, if the value (Z) stored in the lower n bits of the program counter after loading the stored data into the program counter is a k-th value, a branch is made to an address in the k-th memory area that corresponds to the value of the upper (Jn) bits of the program counter, and k is greater than or equal to 1 and less than or equal to 2. n It may also be a configuration (seventh configuration) in which the integers are as follows:

[0129] This makes it possible to easily branch to the expanded memory space with a branch instruction.

[0130] In the arithmetic device according to any one of the first to fifth configurations (see FIG. 21), the arithmetic processing circuit reads and executes an instruction at a read target address (ADR_n) from the program memory, the read target address being a (J+n)-bit address, the value of the upper n bits of the read address (M[J+n-1] to M[J]) is represented by the value of the lower n bits of the program counter (L[n-1] to L[0]); The value of the lowest n bits (M[n-1] to M[0]) of the address to be read may be fixed at a predetermined value (e.g., "0"), and the value of a total of (Jn) bits (M[J-1] to M[n]) that are lower than the highest n bits and higher than the lowest n bits in the address to be read may be represented by the value of the highest (Jn) bits (L[J-1] to L[n]) in the program counter (8th configuration).

[0131] In the arithmetic device according to any of the fifth to eighth configurations, n may represent an integer equal to or greater than 1. When "n=1", the arithmetic devices according to the fifth to eighth configurations are equivalent to the arithmetic devices according to the first to fourth configurations, respectively. [Explanation of symbols]

[0132] 10 Arithmetic unit 20 CPU 30, 30_1A, 30_1B, 30_2A, 30_2B, 30_nB program memory 30_1B_1, 30_1B_2, 30_2B_1~30_2B_4, 30_nB_[1]~30_nB_[2 n ] memory area 40 Program Memory Bus 41 Address Bus 42 Data Bus 50 data memories 60 data memory bus PC, PC_1, PC_2, PC_n Program Counter ADR_1, ADR_2, ADR_n Read address GPR[i], GPR[i]_1, GPR[i]_2, general-purpose storage area 610, 710, 810 Branch destination address storage area 620, 720, 820 Branch destination address specification data

Claims

1. an arithmetic processing circuit configured to be able to execute a program; a program memory for storing the program; each instruction in the program has a length of 16 bits; the program memory has a first memory area and a second memory area associated with a higher address than the first memory area, the arithmetic processing circuit has a 16-bit program counter for specifying an address to be read, and reads and executes an instruction at an address corresponding to the value of the most significant 15 bits of the program counter from a target memory area; The target memory area is one of the first memory area and the second memory area, which corresponds to the value of the least significant bit of the program counter. , computing device.

2. In the arithmetic processing circuit, Each time an instruction other than a branch instruction is executed, 2 is added to the program counter, When the branch instruction is executed, data stored in a 16-bit memory area for specifying a branch destination address is loaded into the program counter, and the program branches to an address in either the first memory area or the second memory area depending on the value of the least significant bit of the stored data.

2. The computing device according to claim 1 .

3. When the branch instruction is executed by the arithmetic processing circuit, when a first value is stored in the least significant bit of the program counter by loading the stored data into the program counter, branching to an address in the first memory area that corresponds to the value of the most significant 15 bits of the program counter, When a second value is stored in the least significant bit of the program counter by loading the stored data into the program counter, a branch is made to an address in the second memory area that corresponds to the value of the most significant 15 bits of the program counter.

3. The computing device according to claim 2.

4. the arithmetic processing circuit reads out an instruction at a read target address from the program memory and executes it; The read target address is a 17-bit address, the value of the most significant bit of the read address is represented by the value of the least significant bit of the program counter; the value of the least significant bit of the read address is fixed at a predetermined value; The value of a total of 15 bits lower than the most significant bit and higher than the least significant bit in the read target address is represented by the value of the most significant 15 bits in the program counter.

4. The computing device according to claim 1.

5. an arithmetic processing circuit configured to be able to execute a program; a program memory for storing the program; each instruction in the program has a predetermined bit length; The predetermined number of bits is J bits, where J=16×2 ｎ－１ , where n represents an integer of 2 or more; The program memory includes first to second ｎ a memory area, and a higher address is associated with the (i+1)th memory area than with the i-th memory area; the arithmetic processing circuit has a program counter of the predetermined number of bits for specifying an address to be read, and reads and executes an instruction at an address corresponding to the value of the most significant (Jn) bits of the program counter from a target memory area; The target memory area is the first to second ｎ Among the memory areas, a memory area corresponding to the value of the lower n bits of the program counter is , computing device.

6. In the arithmetic processing circuit, Each time an instruction other than a branch instruction is executed, the program counter is incremented by 2. ｎ is added, When the branch instruction is executed, the stored data in the storage area of ​​the predetermined bits for specifying the branch destination address is loaded into the program counter, and the first to second ｎ Branch to an address within one of the memory regions 6. The computing device according to claim 5.

7. When the branch instruction is executed by the arithmetic processing circuit, when the value stored in the lower n bits of the program counter after loading the stored data into the program counter is the kth value, branching to an address corresponding to the value of the upper (J-n) bits of the program counter and within the kth memory area; k is equal to or greater than 1 and equal to 2 ｎ is an integer less than or equal to The computing device according to claim 6 .

8. the arithmetic processing circuit reads out an instruction at a read target address from the program memory and executes it; The read target address is a (J+n)-bit address, the value of the upper n bits of the read address is represented by the value of the lower n bits of the program counter; the value of the lower n bits of the read target address is fixed at a predetermined value; The value of a total of (J-n) bits lower than the most significant n bits and higher than the least significant n bits in the read target address is represented by the value of the most significant (J-n) bits in the program counter.

8. The computing device according to claim 5, wherein:

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