Power Converter

Abstract

To provide a power converter capable of estimating thermal resistance without using a power supply for heating and without deteriorating characteristic of a semiconductor element.SOLUTION: A power converter 1 is provided with a plurality of arms each formed by connecting an N-channel MOSFET 2 and 3 in series. A turn-on voltage and thermal resistance estimation unit 13 detects a temperature Tjint or Twint, a drain voltage VDS, and a flowing current ID before the FET3 heat up via a temperature detection unit 6, a voltage detection unit 7, and a current detection unit 8. A drive unit 9 applies a drive signal to a gate of the FET3 under a condition to restrict a calorific value to a specified value or less, to heat up the FET3, Then, the drive unit detects a temperature Tj or Tw, a drain voltage VDS, and a flowing current ID after heating up to estimate a thermal resistance on the basis of the temperature Tj or Tw, the drain voltage VDS, and the flowing current ID before and after the heating up.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a power converter having a plurality of arms, each of which has two semiconductor elements connected in series. [Background technology]

[0002] For example, semiconductor elements such as power MOSFETs used in power converters such as inverters may experience fatigue failure due to thermal stress, or deformation due to thermal cycling, which can cause deterioration of heat dissipation, leading to overheating and thermal breakdown. To prevent this, measures are taken to ensure the design by conducting reliability tests on semiconductor elements to ensure a reliability margin, and to evaluate the degree of degradation of the heat dissipation path of the semiconductor element by measuring the thermal resistance of the heat dissipation path, thereby preventing element breakdown. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2017-195714 Summary of the Invention [Problem to be solved by the invention]

[0004] One method for measuring the thermal resistance of a heat dissipation path involves preheating a semiconductor element and then estimating the thermal resistance from the thermal response during the cooling process. Patent Document 1 discloses the use of a separate power supply for heating or a drive power supply, but does not specifically describe measures to be taken in the event of deterioration due to heat generation. Furthermore, Patent Document 1 performs transient thermal measurements, which require a complex derivation and a high-response voltage measurement system on the order of nanoseconds to microseconds.

[0005] The present invention has been made in consideration of the above circumstances, and its object is to provide a power converter that can estimate thermal resistance without using a heating power source and without degrading the characteristics of semiconductor elements. [Means for solving the problem]

[0006] According to the power converter of claim 1, there are provided a plurality of arms in which two semiconductor elements are connected in series. When one of the two semiconductor elements is set as a target element for estimating thermal resistance, the thermal resistance estimation unit detects the temperature, voltage between the conduction terminals, and current flowing through the target element when it is not generating heat, and the heat generation control unit applies a drive signal to the conduction control terminal of the target element under the condition that the amount of heat generated is limited to a certain value or less, causing the element to generate heat. The target element is The temperature, voltage between the conducting terminals, and current flowing in the heated state are detected, and the thermal resistance is estimated based on the temperature difference, voltage between the conducting terminals, and current flowing due to the heat generation.

[0007] This configuration allows thermal resistance to be estimated without using a heating power source. Furthermore, even when the target element is heated, the target element is driven under conditions that limit the amount of heat generated to a certain level, so thermal resistance can be estimated while keeping degradation of the semiconductor element's characteristics to a level that can be ignored given the specifications.

[0008] and, Claim 1 or 2 According to the power converter described in the present specification, the heat control unit controls the drive voltage of the target element to be equal to or higher than the threshold voltage and lower than the full-on voltage so as to maintain the temperature of the target element in a constant state when the target element is heated (see claim 1). 1 ) or high frequency PWM control (claim 2 This allows the amount of heat generated by the target element to be limited to a certain level.

[0009] Claim 4 According to the described power converter, when detecting the voltage across the terminals of the sense resistor connected to the detection terminal of the semiconductor element, the current detection unit virtually grounds the detection terminal using the virtual ground unit. With this configuration, by canceling the terminal voltage of the sense resistor using the virtual ground, it is possible to avoid narrowing the range of the drive voltage of the semiconductor element and improve control accuracy. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a functional block diagram illustrating a configuration of a circuit that drives semiconductor elements that constitute a power converter according to a first embodiment. [Figure 2] Diagram showing the circuit configuration of the drive unit [Figure 3] A diagram showing the voltages and currents applied to each element of the upper and lower arms for one phase [Figure 4] 1 is a timing chart showing changes in voltage, current, and temperature according to an operation for estimating thermal resistance; [Figure 5] A diagram showing the relationship between the temperature rise and the number of heating cycles corresponding to the life of a part, derived from the Eyring model. [Figure 6] FIG. 4 is a diagram showing a second embodiment. [Figure 7] Diagram showing the circuit configuration of the drive unit [Figure 8] FIG. 10 is a diagram illustrating a sequence for reducing the time required to estimate the thermal resistance of each element in the upper and lower arms for three phases according to the third embodiment. [Figure 9] FIG. 11 is a diagram (part 1) showing the change in the amount of heat generated by a semiconductor element in the fourth embodiment, which aims to reduce the time required for estimating thermal resistance. [Figure 10] Diagram showing the change in heat generation of semiconductor devices (part 2) to shorten the time required to estimate thermal resistance [Figure 11] FIG. 10 is a diagram showing the time required to estimate thermal resistance when the first, third, and fourth embodiments are implemented in a superimposed manner, in comparison with the prior art. [Figure 12] FIG. 10 is a functional block diagram illustrating a configuration of a circuit that drives semiconductor elements that constitute a power converter according to a fifth embodiment. [Figure 13] FIG. 10 is a functional block diagram showing a configuration of a circuit that drives semiconductor elements that constitute a power converter according to a sixth embodiment. [Figure 14] FIG. 1 shows a configuration for controlling gate voltage by feeding back a current value including a current detection unit. [Figure 15] FIG. 13 is a diagram illustrating a sequence for shortening the time required to estimate the thermal resistance of each of the upper and lower arm FETs according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] (First embodiment) As shown in Fig. 3, the power converter 1 of this embodiment has a series circuit of voltage-driven semiconductor elements, such as N-channel MOSFETs 2 and 3. The series circuit is connected between a high-voltage power supply 4 and ground. The voltage of the high-voltage power supply 4 is, for example, about 200 V to 650 V. Note that the actual power converter 1 is a three-phase inverter, and the above-mentioned series circuits are connected in parallel for three phases.

[0012] 1, a drive circuit 5 that drives the FET 3 is configured as, for example, an IC, and includes a temperature detection unit 6, a voltage detection unit 7, a current detection unit 8, and a drive unit 9. Note that the FET 2 is not shown in FIG. 1. In this embodiment, the FET 3 is the target element whose thermal resistance is to be estimated.

[0013] The temperature sensor 10 is, for example, a diode arranged to detect the temperature of the FET 3, and the temperature detection unit 6 detects the terminal voltage of the diode. The temperature detected by the temperature sensor 10 is referred to as T j The input terminal of the voltage detection unit 7 is connected to the drain of the FET 3 via a diode serving as a voltage sensor 11. That is, the voltage detection unit 7 detects the drain-source voltage of the FET 3, which is the voltage between the conductive terminals, via the voltage sensor 11. Hereinafter, the drain-source voltage will be simply referred to as the drain voltage.

[0014] The current sensor 12 detects the current flowing through the source of the FET 3. The sensor signal of the current sensor 12 is input to the current detection unit 8. The output signals of the temperature detection unit 6, the voltage detection unit 7, and the current detection unit 8 are input to the on-voltage / thermal resistance estimation unit 13. The on-voltage / thermal resistance estimation unit 13 also receives the sensor signal of the water temperature sensor 14. The water temperature sensor 14 detects the temperature of the cooling water circulating in the heat pipe to cool the FETs 2 and 3. The temperature detected by the water temperature sensor 14 is referred to as T w Let's say.

[0015] The output signal of the current detection unit 8 is also input to the drive unit 9. As shown in FIG. 2, the drive unit 9, which corresponds to the heat generation control unit, includes, for example, an operational amplifier 15. A reference voltage is applied to the non-inverting input terminal of the operational amplifier 15 from a variable reference voltage source 16, and the inverting input terminal is connected to the output of the current detection unit 8. The output terminal of the operational amplifier 15 is connected to the gate of the FET 3. The operational amplifier 15 feedback-controls the gate voltage of the FET 3 so that the current flowing through the FET 3 is constant.

[0016] Next, the operation of this embodiment will be described. As shown in FIGS. GS is the gate voltage of FET3, V GS対向 is the gate voltage of FET2. At time (a), the gate voltage V GS対向 Only the threshold voltage V th When a voltage level that significantly exceeds this is applied, for example, the normal drive voltage that turns FET3 fully on during normal operation, a voltage V equivalent to the voltage of the high-voltage power supply 4 is applied between the drain and source of FET3. DS The on-state voltage and thermal resistance estimation unit 13 calculates the temperature T detected by the water temperature sensor 14 at a subsequent time point (b). w If the water temperature sensor 14 is not used, the temperature T detected by the temperature sensor 10 at that time is acquired. j Obtain the initial temperature T jint Let's say.

[0017] At time (c), the gate voltage V GS , the threshold voltage V th When a voltage exceeding this level and lower than the normal drive voltage is applied, the drain current I D As a result, the FET 3 is heated. Then, at a time point (d) when it is estimated that the temperature rise of the FET 3 has saturated, the on-state voltage / thermal resistance estimation unit 13 estimates that the temperature T j , voltage V DS and current I D Get.

[0018] Then, the on-state voltage / thermal resistance estimation unit 13 calculates the thermal resistance R of the FET 3 using the following equation (1): th Estimate. R th =(T j -T w ) / (V DS ×I D ) …(1) Furthermore, the temperature T w Instead of the initial temperature T jint When using equation (2), R th =(T j -T jint ) / (V DS ×I D ) …(2)

[0019] At the time point (d), the temperature T j The degree to which this is set, that is, the allowable heat generation amount of FET 3, differs depending on the frequency at which the thermal resistance is estimated and design parameters such as the product life of the power converter 1. For example, if the thermal resistance estimation frequency is set to once per day and the product life is 15 years, then the thermal resistance will be estimated 5,479 times until the product life is reached.

[0020] Temperature acceleration models used to estimate the lifetime of semiconductors include, for example, the Arrhenius model and the Eyring model. In the Eyring model, the lifetime L is expressed by equation (3), where L is the lifetime, A is the constant, ΔT is the temperature difference, and n is the temperature acceleration coefficient. L=A(ΔT) -n …(3)

[0021] Using equation (3), if the number of life cycles at the derating temperature difference ΔT1 is L1 and the number of cycles performed at the reliability test temperature difference ΔT2 is L2, the temperature difference acceleration coefficient αΔT is given by equation (4). αΔT=L1 / L2=(ΔT2 / ΔT1) n …(4) From this, the number of execution cycles L2 is L2=L1(ΔT2 / ΔT1) -n …(5) This becomes:

[0022] The temperature acceleration coefficient n differs depending on the material of the module containing the semiconductor element, but for example, if it is set to "3" and the number of life cycles L1 = 1.2 million cycles at a temperature difference ΔT = 120°C is used as the standard, the percentage of the influence on the life cycle number and the estimated thermal resistance when the temperature difference ΔT is changed is shown in Figure 5. Depending on how much margin is set, under the above conditions, It is estimated that ΔT = approximately 60℃ is desirable.

[0023] As described above, according to this embodiment, the power converter 1 includes multiple arms in which N-channel MOSFETs 2 and 3 are connected in series. The on-voltage / thermal resistance estimator 13 detects the temperature, drain voltage, and current before the FET 3 generates heat via the temperature detector 6, voltage detector 7, and current detector 8. The driver 9 applies a drive signal equal to or greater than a threshold voltage to the gate of the FET 3 under conditions that limit the amount of heat generated to a certain level, causing the FET 3 to generate heat. The on-voltage / thermal resistance estimator 13 then detects the temperature, drain voltage, and current after the FET 3 generates heat, and estimates the thermal resistance based on the temperature, drain voltage, and current before and after the FET 3 generates heat. Specifically, the on-voltage / thermal resistance estimator 13 estimates the thermal resistance based on the temperature, drain voltage, and current before and after the FET 3 generates heat. Specifically, the on-voltage / thermal resistance estimator 13 estimates the thermal resistance using equation (1) or (2).

[0024] This configuration allows thermal resistance to be estimated without using a heating power source. Furthermore, even when FET 3 is heated, FET 3 is driven under conditions that limit the amount of heat generated to a certain level or less. This allows thermal resistance to be estimated while keeping degradation of FET 3's characteristics to a level that can be ignored within specifications. The driver 9 then controls the drive voltage of FET 3 to be equal to or greater than the threshold voltage and less than the full-on voltage so as to maintain a constant current value through FET 3. This allows the amount of heat generated by FET 3 to be limited to a certain level or less. Furthermore, by using equation (1) or (2), steady-state thermal resistance can be easily estimated, even with a voltage measurement system that has a low response of the order of milliseconds or more.

[0025] (Second embodiment) In the following, the same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof will be omitted, and the different parts will be described. As shown in FIG. 6, in the second embodiment, the gate voltage V GS The on-period and off-period, i.e., the duty ratio, is adjusted to output a PWM signal. The frequency of the PWM signal can be achieved without modulating the carrier frequency used for PWM control when controlling the switching of FETs 2 and 3 during normal operation of power converter 1. However, if the heat dissipation characteristics of the module cause large ripples in the temperature change, making it difficult to estimate the thermal resistance, switching must be performed at a frequency higher than the carrier frequency. As shown in Figure 7, driver 21, which replaces driver 9, is composed of a square wave generating circuit 22 and a comparator 23.

[0026] The square wave generating circuit 22 has a known configuration and is connected to a power supply V cc and ground, a series circuit of resistors R1 and R2 connected between their common connection point and ground, and resistors R3 and R4 and a capacitor C1 connected in series between their common connection point and ground, and an operational amplifier 24 whose common connection point is connected to its non-inverting input terminal, whose inverting input terminal is connected to the common connection point of the resistor R4 and the capacitor C1, and whose output terminal is connected to the common connection point of the resistors R3 and R4.

[0027] The non-inverting input terminal of the comparator 23 is connected to the common connection point of the resistor element R4 and the capacitor C1, and the inverting input terminal is connected via the resistor element R5 corresponding to the sense resistor to the drain of the current sensing FET of the FET 3. In the second embodiment configured as described above, the same effects as in the first embodiment can be obtained.

[0028] (Third embodiment) The third embodiment is an example of control that shortens the total time required to estimate the thermal resistance of all of the semiconductor elements that make up a power converter. As shown in Figure 8, in the case of a three-phase inverter, six semiconductor elements are bridge-connected. In the figure, the semiconductor elements are represented by IGBT symbols. If the thermal resistance of each of these six semiconductor elements is estimated individually, as shown on the left side of the figure, it would take six times the time required to estimate the thermal resistance of one semiconductor element.

[0029] For example, the thermal resistance method shown in the first embodiment can be implemented for each phase in parallel. Therefore, as shown on the right side of the figure, if the thermal resistance of the semiconductor element in the upper arm of each phase is estimated first, and the thermal resistance of the semiconductor element in the lower arm is estimated second, estimation of all elements can be completed in twice the reference time.

[0030] (Fourth embodiment) The fourth embodiment is also an example of control for shortening the time required to estimate the thermal resistance. For example, as shown in FIG. 9, in the first embodiment, a constant gate voltage V GS When the gate is charged with a substantially constant current by applying a constant current, it takes 10 seconds for the heat generation amount of the element to reach a saturation value P.

[0031] In contrast, as shown in Figure 10, when the gate voltage V GS By increasing the initial value of , the current used to charge the gate is increased. By setting the heat generation amount at this time to, for example, 1.6P, the temperature of FET3 increases more rapidly. As a result, if the time required for the heat generation amount to reach the saturation value P becomes 2.5 seconds, the time required to estimate the thermal resistance of one semiconductor element becomes 1 / 4.

[0032] FIG. 11 shows an image of how the estimation time is shortened when the first or second embodiment is applied, when the third embodiment is applied in addition to the first or second embodiment, and when the fourth embodiment is further applied in addition to the first or second embodiment, when the conventional technology is applied as a reference, when estimating the thermal resistance of all six semiconductor elements.

[0033] (Fifth embodiment) 12, in a drive circuit 31 of the fifth embodiment, instead of the voltage sensor 11, a series circuit of high-voltage capacitors 32 and 33 is connected between the drain of the FET 3 and the ground. The input terminal of the voltage detection unit 7 is connected to a common connection point of the capacitors 32 and 33. Moreover, instead of the current sensor 12, a resistive element 34 is connected between the drain of the current sensing FET of the FET 3 and the ground. The input terminal of the current detection unit 8 is connected to the drain.

[0034] That is, the voltage detection unit 7 detects the drain voltage of the FET 3 divided by the capacitors 32 and 33. The resistive element 34 is a so-called sense resistor used for overcurrent detection, etc. The sense resistor is used to measure the current I D If the current sensor 12 is detected, there is no need to use the current sensor 12. Therefore, the entire system can be configured at low cost and in a small space.

[0035] (Sixth embodiment) As shown in Fig. 13, the drive circuit 41 of the sixth embodiment has a configuration in which a virtual ground unit 42 is added to the drive circuit 31 of the fifth embodiment. The virtual ground unit 42 is made up of an operational amplifier 43 and a voltage source 44. The inverting input terminal of the operational amplifier 43 is connected to the drain of the current sensing FET, i.e., the upper end of the resistor element 34, and the output terminal is connected to the lower end of the resistor element 34 and the input terminal of a current detection unit 45. The non-inverting input terminal is connected to ground. The positive terminal of the voltage source 44 is connected to ground, and the negative terminal is connected to the ground terminal of the operational amplifier 43.

[0036] 14 constitutes a level shift circuit, and level-shifts the upper end voltage of the resistance element 34 that is virtually grounded by the virtual ground part 42, and inputs it to the drive part 9. Note that in FIG. 14, the virtual ground part 42 is shown symbolically.

[0037] In the driver 31 of the fifth embodiment, the voltage applied to the gate of the FET 3 drops by the terminal voltage of the resistor element 34. In addition, in a configuration in which the gate voltage is controlled based on the current value, the terminal voltage changes depending on the gate voltage, which deteriorates the control accuracy. Therefore, as in the driver 41 of the sixth embodiment, the upper end voltage of the resistor element 34 is virtually grounded, thereby reducing the control accuracy. spirit The degree can be improved.

[0038] (Seventh embodiment) As shown in FIG. 15, the seventh embodiment shows a sequence for shortening the time required to estimate the thermal resistance of the upper and lower arm FETs 2 and 3. To estimate the thermal resistance, it is necessary to heat up the FET to be estimated in advance. Note that the gate voltage "ON" in the figure indicates the normal drive voltage that puts the FET into a full-on state, and the gate voltage "~V th ” is the threshold voltage V th This shows the heat response voltage that exceeds the normal driving voltage and is lower than the normal driving voltage. th The state in which a gate voltage of ~V is applied to FET2 is called "State 1." th The state in which the gate voltage ON is applied to FET3 is defined as "state 2."

[0039] In the seventh embodiment, the FETs 2 and 3 are both switched from the OFF state to "State 1", and the pre-heating temperature T j0 Then, FET2 and FET3 are both turned OFF again and the state transitions to "State 2". At the beginning of the transition, the temperature T of FET3 before heating is measured. j0 Measure.

[0040] The transition from "State 2" to "State 1" takes place after a period in which both FET2 and FET3 are turned off. At the beginning of the transition, the temperature T of FET2, which has been heated by "State 2", j Then, the state transitions from "State 1" to "State 2" after a period in which both FET2 and FET3 are turned off. At the beginning of the transition, the temperature T of FET3, which has been heated by "State 1", is measured.j Then, turn off both FET2 and FET3 to complete the sequence. As described above, according to the seventh embodiment, the sequence for estimating the thermal resistances of the upper and lower arm FETs 2 and 3 can be completed in a short time.

[0041] (Other embodiments) The semiconductor element is not limited to a FET, but may be any voltage-driven element. Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0042] In the drawing, 1 indicates a power converter, 2 and 3 indicate N-channel MOSFETs, 5 indicates a drive circuit, 6 indicates a temperature detection unit, 7 indicates a voltage detection unit, 8 indicates a current detection unit, 9 indicates a drive unit, 10 indicates a temperature sensor, 12 indicates a current sensor, 13 indicates an on-voltage / thermal resistance estimation unit, and 14 indicates a water temperature sensor.

Claims

1. A power converter including a plurality of arms in which two voltage-driven semiconductor elements (2, 3) are connected in series, a temperature detection unit (6, 10, 14) for detecting the temperature of the semiconductor element; a voltage detection unit (7) for detecting a voltage between the conductive terminals of the semiconductor element; a current detection unit (8, 45) for detecting a current flowing through the semiconductor element; If one of the two semiconductor elements is a target element (3) whose thermal resistance is to be estimated, Detecting the temperature, voltage between conductive terminals, and current flowing through the target element when it is not generating heat; When a drive signal is applied to the conduction control terminal of the other semiconductor element to turn it fully on, a heat generation control unit (9) for applying a drive signal to a conduction control terminal of the target element under the condition that the heat generation amount of the target element is limited to a certain value or less, thereby causing the target element to generate heat; and a thermal resistance estimation unit (13) for detecting the temperature, voltage between the conduction terminals, and current flowing in the state in which the target element generates heat, and estimating the thermal resistance based on the temperature difference, voltage between the conduction terminals, and current flowing due to the heat generation, The heat generation control unit is a power converter that controls the drive voltage of the target element to be equal to or higher than a threshold voltage and lower than a full-on voltage so as to maintain a constant temperature of the target element in a heated state.

2. A power converter including a plurality of arms in which two voltage-driven semiconductor elements (2, 3) are connected in series, a temperature detection unit (6, 10, 14) for detecting the temperature of the semiconductor element; a voltage detection unit (7) for detecting a voltage between the conductive terminals of the semiconductor element; a current detection unit (8, 45) for detecting a current flowing through the semiconductor element; If one of the two semiconductor elements is a target element (3) whose thermal resistance is to be estimated, Detecting the temperature, voltage between conductive terminals, and current flowing through the target element when it is not generating heat; When a drive signal is applied to the conduction control terminal of the other semiconductor element to turn it fully on, a heat generation control unit (21) for applying a drive signal to a conduction control terminal of the target element under the condition that the heat generation amount of the target element is limited to a certain value or less, thereby causing the target element to generate heat; and a thermal resistance estimation unit (13) for detecting the temperature, voltage between the conduction terminals, and current flowing in the state in which the target element generates heat, and estimating the thermal resistance based on the temperature difference, voltage between the conduction terminals, and current flowing due to the heat generation, The heat generation control unit is a power converter that PWM controls the drive voltage of the target element at a frequency equal to or higher than the carrier frequency used for PWM control when controlling the switching of the semiconductor element during normal operation, so as to maintain a constant temperature when the target element is heated.

3. 3. The power converter according to claim 1, wherein the temperature detection unit (6, 10) defines the temperature in the non-heat-generating state as the temperature detected before the heat generation control unit applies a drive signal to the conduction control terminal of the target element.

4. the semiconductor element includes a detection terminal for detecting a current flowing therethrough; When detecting the voltage between the terminals of the sense resistor (34) connected to the detection terminal, the current detection unit (45) 3. The power converter according to claim 1, further comprising a virtual ground section (42) that virtually grounds the detection terminal.

5. When estimating the thermal resistance of the two semiconductor elements connected in series, the thermal resistance estimation unit detects a temperature in a state where the target element generates heat and the other semiconductor element does not generate heat; 3. The power converter according to claim 1, wherein after the target element has stopped generating heat and cooled down, the temperature of the target element is detected while the other semiconductor element is generating heat and is not generating heat.

6. 3. The power converter according to claim 1, wherein the thermal resistance estimator estimates the thermal resistances of the two series-connected semiconductor elements of the plurality of arms in parallel and simultaneously.

7. 3. The power converter according to claim 1, wherein the thermal resistance estimation unit controls the temperature of the target element to reach the target temperature more quickly by increasing an initial current flow amount when the target element starts to generate heat.

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