Protection of the channel layer in three-terminal vertical memory structures.

Abstract

A channel material is conformally deposited along the sidewalls of one or more etched features of a mold stack in the fabrication of a three-terminal memory device. The channel material is deposited in recessed and non-recessed regions of the one or more etched features. A sacrificial liner is deposited over the channel material. A directional etch removes the sacrificial liner from the non-recessed regions of the one or more etched features. An isotropic etch removes the channel material from the non-recessed regions of the one or more etched features, leaving the channel material and sacrificial liner intact in the recessed regions. The sacrificial liner is removed, leaving the channel material intact and isolated with minimal loss of channel material due to over-etching.

Description

[Background technology]

[0001] [Incorporated by reference] A PCT application is being filed concurrently herewith as part of this application, and each application identified in that concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes.

[0002] Advances in semiconductor device fabrication are increasing the number of memory devices on a chip. Not only have advances been made to scale to smaller and smaller features for increased density, but also to arrange memory devices from two-dimensional (2D) to three-dimensional (3D) architectures. In 2D memory, memory cells are arranged side-by-side on a single die layer. In 3D memory, more planes of memory cells can be stacked on top of each other within a given footprint of a limited die size, which can lead to increased capacity and performance.

[0003] The Background provided herein is intended to generally present the contents of the present disclosure. Work by the presently named inventors within the scope of what is described in this Background, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] Certain embodiments herein relate to a method for forming an isolation channel layer for a vertically integrated memory array, the method including: (i) etching one or more features through a mold stack disposed over a semiconductor substrate, the mold stack including a plurality of film stacks, the plurality of film stacks being vertically stacked, adjacent film stacks being separated by a dielectric layer, each film stack including a source region, a drain region, and an oxide layer between the source and drain regions. The method further includes: (ii) selectively etching at least a portion of the oxide layer in each of the film stacks to form a recessed region in each of the film stacks; (iii) conformally depositing a channel material along sidewalls of the one or more features; (iv) depositing a sacrificial liner covering the channel material along the sidewalls of the one or more features; (v) etching the sacrificial liner covering the channel material in an area outside the recessed region; and (vi) selectively etching at least the channel material along the sidewalls of the one or more features outside the recessed region to define an isolation channel layer between the source and drain regions of each film stack.

[0005] In some embodiments, the method further includes (vii) removing a sacrificial liner overlying the isolation channel layer after selectively etching at least the channel material outside the recessed regions. In some embodiments, the isolation channel layer has a topographical deviation of about 10% or less from a reference surface after removing the sacrificial liner. In some embodiments, each film stack further includes a conductor layer adjacent to the drain region and sandwiched between the drain region and the dielectric layer, the dielectric layer serving to electrically isolate adjacent film stacks from each other. In some embodiments, etching the sacrificial liner in the area outside the recessed regions includes directional etching the sacrificial liner with an etch contrast of at least 10:1 relative to the channel material. In some embodiments, protrusions from the sidewalls of the one or more features function as a mask to protect the recessed regions during directional etching of the sacrificial liner. In some embodiments, selectively etching at least the channel material in the area outside the recessed regions includes isotropically etching the channel material with an etch contrast of at least 25:1 relative to the sacrificial liner. In some embodiments, the isotropic etching of the channel material is performed with an etch contrast relative to the dielectric layer of at least 10: 1. In some embodiments, a sacrificial liner is conformally deposited on the channel material along sidewalls of the one or more features.

[0006] Another aspect of the disclosed embodiments relates to a memory device including: (i) a plurality of three-terminal memory cells, each memory cell including a source terminal connected to a source region, a drain terminal connected to a drain region, an oxide layer between the source region and the drain region, an isolation channel layer on a surface of the oxide layer and providing an interconnection between the source region and the drain region, a gate terminal, and a memory film between the isolation channel layer and the gate terminal; and (ii) a plurality of dielectric layers each separating adjacent three-terminal memory cells, the plurality of three-terminal memory cells further including the plurality of dielectric layers vertically stacked.

[0007] In some embodiments, the plurality of three-terminal memory cells comprises more than 20 three-terminal memory cells. In some embodiments, the isolation channel layer comprises polysilicon. In some embodiments, the isolation channel layer of a first memory cell is insulated from a second memory cell adjacent to the first memory cell. In some embodiments, the memory film comprises a ferroelectric layer, a charge trapping layer, or a spin-orbit torque memory stack. In some embodiments, the isolation channel layer is positioned in a recessed region of the oxide layer, the recessed region being defined by a portion of the oxide layer that is laterally recessed relative to the source region, the drain region, and one or more sidewalls of the plurality of dielectric layers. [Brief explanation of the drawings]

[0008] [Figure 1A] FIG. 1A is a schematic diagram of an exemplary fabrication approach for a vertically integrated two-terminal memory array in an xy cross-point architecture.

[0009] [Figure 1B] FIG. 1B is a schematic diagram of an exemplary fabrication approach for a vertically integrated two-terminal memory array in an xz cross-point architecture.

[0010] [Figure 1C] FIG. 1C is a schematic diagram of an exemplary fabrication approach for a vertically integrated two-terminal memory array in a 3D vertically stacked architecture.

[0011] [Figure 2A] FIG. 2A is a schematic diagram of an exemplary three-terminal memory device having a ferroelectric layer.

[0012] [Figure 2B] FIG. 2B is a schematic diagram of an exemplary three-terminal memory device having a charge trapping layer.

[0013] [Figure 2C]FIG. 2C is a schematic diagram of an exemplary three-terminal memory device having a spin-orbit torque (SOT) memory stack.

[0014] [Figure 3] FIG. 3 is a schematic diagram of an exemplary vertically integrated three-terminal memory array according to some embodiments.

[0015] [Figure 4] FIG. 4 is a flow diagram of an exemplary method for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments.

[0016] [Figure 5A] 5A-5D are cross-sectional schematic views of various stages in an exemplary process for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments. [Figure 5B] 5A-5B are cross-sectional schematic views of various stages in an exemplary process for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments. [Figure 5C] 5A-5C are cross-sectional schematic views of various stages in an exemplary process for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments. [Figure 5D] 5A-5D are cross-sectional schematic views of various stages in an exemplary process for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments. [Figure 5E] 5E are cross-sectional schematic views of various stages in an exemplary process for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments. [Figure 5F] 5F are cross-sectional schematic views of various stages in an exemplary process for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments. [Figure 5G]5G are cross-sectional schematic views of various stages in an exemplary process for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments.

[0017] [Figure 6A] 6A-6C are cross-sectional schematic diagrams of enlarged views of various stages in an exemplary process for forming an isolation channel layer using a multilayer sacrificial liner according to some embodiments. [Figure 6B] 6A and 6B are cross-sectional schematic diagrams of enlarged views of various stages in an exemplary process for forming an isolation channel layer using a multilayer sacrificial liner according to some embodiments. [Figure 6C] 6A-6C are cross-sectional schematic diagrams of enlarged views of various stages in an exemplary process for forming an isolation channel layer using a multilayer sacrificial liner according to some embodiments. [Figure 6D] 6A-6D are cross-sectional schematic diagrams of enlarged views of various stages in an exemplary process for forming an isolation channel layer using a multilayer sacrificial liner according to some embodiments. [Figure 6E] 6E-6E are cross-sectional schematic diagrams of enlarged views of various stages in an exemplary process for forming an isolation channel layer using a multilayer sacrificial liner according to some embodiments.

[0018] [Figure 7] FIG. 7 is a schematic diagram of an exemplary process chamber for performing one or more operations of the disclosed embodiments.

[0019] [Figure 8] FIG. 8 is a schematic diagram of an exemplary process tool for performing one or more operations of the disclosed embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0020] In this disclosure, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will understand that the term "partially fabricated integrated circuit" can refer to a silicon wafer at any of many stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. The following detailed description assumes that the present disclosure is practiced on a wafer. However, the disclosure is not so limited. Workpieces can be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that can utilize the present disclosure include various articles such as printed circuit boards.

[0021] Introduction High-density, high-capacity memory has become a major factor driving the widespread adoption of portable electronic devices. As electronic devices shrink, strategies for fabricating complex and efficient memory cells are adopted to maximize the density of memory cells within a memory device. 3D memory architectures address the challenges associated with 2D memory architectures by stacking memory cells vertically. However, 3D memory architectures are primarily limited to two-terminal memory devices. As used herein, a two-terminal memory device refers to a memory device with two or fewer explicit local terminals. For example, a memory device can have an input terminal (e.g., a word line) and an output terminal (e.g., a bit line).

[0022] There are various approaches for vertically integrating memory cells into high-density memory arrays for 2D memory architectures. One approach is by arranging the memory cells in a cross-point array configuration. Generally, a cross-point array refers to a memory array having memory cells located and electrically connected at the intersections between a first set of conductive lines (e.g., word lines) and a second set of conductive lines (e.g., bit lines) that overlap and intersect the first set of conductive lines.

[0023] FIG. 1A shows a schematic diagram of an exemplary fabrication approach for a vertically integrated two-terminal memory array in an xy cross-point architecture. A first set of conductive lines 101 extends in the y-direction, and a second set of conductive lines 102 extends in the x-direction. The second set of conductive lines 102 overlies the first set of conductive lines 101. The conductive lines 101 / 102 are conductors configured to carry electrical signals, such as voltage or current pulses, between memory cells. Although not shown in FIG. 1A , the first set of conductive lines 101 may be separated from the second set of conductive lines 102 by one or more active elements and / or one or more isolation layers that form part of each memory cell. To scale up the two-terminal memory array in an xy cross-point architecture, repeated conductive lines 103 may be stacked on top of the second set of conductive lines 102. In other words, another set of conductive lines may extend in the y direction above the first and second conductive lines 101 / 102, and another set of conductive lines may extend in the x direction. Each pair of conductive lines extending in the x and y directions forms a deck. While fabricating a vertically integrated two-terminal memory array in an xy cross-point architecture may be advantageous for low aspect ratio etching and critical dimensions scalable down to 10 nm, fabricating a vertically integrated two-terminal memory array in an xy cross-point architecture may be prohibitively cost-prohibitive, especially beyond four or six decks. For example, lithographically patterning and fabricating each deck may require two or more etching steps and two or more deposition steps, making scaling up a vertically integrated two-terminal memory array cost-prohibitive.

[0024] FIG. 1B shows a schematic diagram of an exemplary fabrication approach for a vertically integrated two-terminal memory array in an x-z ​​cross-point architecture. A set of vertical conductive lines 111 extends in the z-direction, and a set of horizontal conductive lines 112 extends perpendicular to the first set of vertical conductive lines 111. It will be understood that a set of horizontal conductive lines 112 extends in the x-direction, while a set of horizontal conductive lines 112 may extend in the y-direction. The vertical conductive lines 111 and horizontal conductive lines 112 are interleaved to form a grid pattern (i.e., rows and columns). The conductive lines 111 / 112 are conductors configured to carry electrical signals, such as voltage or current pulses, between memory cells. Although not shown in FIG. 1B , the vertical conductive lines 111 may be separated from the horizontal conductive lines 112 by one or more active elements and / or one or more isolation layers that form part of each memory cell. To scale up a two-terminal memory array in an x-z ​​cross-point architecture, multiple rows and columns can be added to provide more memory cells. The number of rows or columns can correspond to the number of decks. Fabrication of vertically integrated two-terminal memory arrays in an xz cross-point architecture can result in costs that scale down with the number of decks, but such fabrication may be limited by issues associated with vertical line etching and the risk of pattern collapse due to stack etching. This may limit the number of decks to approximately five or less. Lithographic patterning and fabrication of a memory array in an xz cross-point architecture may require two etching steps and two deposition steps.

[0025] FIG. 1C shows a schematic diagram of an exemplary fabrication approach for a vertically integrated two-terminal memory array in a 3D vertically stacked architecture. A set of horizontal conductive lines 121 can be provided as a series of stacks in the x and y directions, and one or more vertical conductive lines 122 extending in the z direction can be provided. Rather than having multiple lithography steps per layer, one or more holes / recesses can be formed through all layers at once, and the one or more holes / recesses can be filled with concentric layers. Scaling up a vertically integrated two-terminal memory array in a 3D vertically stacked architecture can be achieved by adding more horizontal conductive lines 121. The density of a vertically integrated two-terminal memory array can be increased by adding more vertical conductive lines 122. The conductive lines 121 / 122 are conductors configured to carry electrical signals, such as voltage or current pulses, between memory cells. Although not shown in FIG. 1C, the horizontal conductive lines 121 can be separated from the vertical conductive lines 122 by one or more active devices and / or one or more isolation layers that form part of each memory cell. For example, a memory cell may include concentric layers of switching and selection layers that encase portions of the vertical conductive lines 122. Fabrication of vertically integrated two-terminal memory arrays in a 3D vertically stacked architecture can result in reduced costs and enable tens or hundreds of decks upon scaling up. However, such fabrication may be limited by challenges associated with high-aspect ratio etching and conformal deposition of film layers along sidewalls. Only one etching step and one deposition step may be required to pattern and fabricate a memory array in a 3D vertically stacked architecture.

[0026] The present disclosure relates to a three-terminal memory device, rather than a two-terminal memory device. For example, a three-terminal memory device may have two input terminals and one output terminal. A typical two-terminal memory device may include a source / drain terminal and a gate terminal. Many existing 3-D NAND memory devices are two-terminal memory devices with common source / drain terminals (i.e., with source / drain terminals connected to each other). A typical three-terminal memory device may include a source terminal, a drain terminal, and a gate terminal. The source terminal, drain terminal, and gate terminal are each separately connected and can be separately accessed within the memory device.

[0027] Various types of three-terminal memory devices can be implemented in this disclosure. Nonvolatile memory retains its stored memory even when power is not applied. Many different types of nonvolatile memory include transistors, where the gates are electrically isolated. There can be various methods for charging the gates. Figures 2A-2C show different examples of planar three-terminal memory devices having source, drain, and gate terminals.

[0028] FIG. 2A shows a schematic diagram of an exemplary three-terminal memory device having a ferroelectric layer. A planar memory device 210 includes an active layer 211, which includes a source region 212, a drain region 213, and a channel region 214. The channel region 214 can include a semiconductor material that allows electrons to flow between the source region 212 and the drain region 213. A source terminal 215 is connected to the source region 212, and a drain terminal 216 is connected to the drain region 213. A gate terminal 217 is disposed above the channel region 214, and a ferroelectric layer 218 is sandwiched between the gate terminal 217 and the channel region 214. The ferroelectric layer 218 includes a ferroelectric material that can have two distinct polarization states and can be characterized by reversible spontaneous polarization in the absence of an electric field. The spontaneous polarization of a ferroelectric material represents a hysteresis effect and can be used as a memory function in creating a ferroelectric random access memory (FeRAM).

[0029] FIG. 2B shows a schematic diagram of an exemplary three-terminal memory device with a charge trapping layer. A planar memory device 220 includes an active layer 221, which includes a source region 222, a drain region 223, and a channel region 224. The channel region 224 can include a semiconductor material that allows electrons to flow between the source region 222 and the drain region 223. A source terminal 225 is connected to the source region 222, and a drain terminal 226 is connected to the drain region 223. A gate terminal 227 is disposed above the channel region 224, and a charge trapping layer 228 is sandwiched between the gate terminal 227 and the channel region 224. The charge trapping layer 228 includes an insulating film for storing electrons, rather than a metal or semiconductor film. The insulating film can include a material such as silicon nitride, and the charge trapping layer 228 uses the variable charge between the gate terminal 227 and the channel region 224 to change the threshold voltage of the planar memory device 220. The charge trapping layer 228 can be used to create non-volatile memory in NOR and NAND flash memories.

[0030] FIG. 2C shows a schematic diagram of an exemplary three-terminal memory device having a spin-orbit torque memory stack. A planar memory device 230 includes an active layer 231, which includes a source region 232, a drain region 233, and a channel region 234. The channel region 234 can include a semiconductor material that allows electrons to flow between the source region 232 and the drain region 233. A source terminal 235 is connected to the source region 232, and a drain terminal 236 is connected to the drain region 233. A gate terminal 237 is disposed above the channel region 234, and a spin-orbit torque (SOT) memory stack 238 is sandwiched between the gate terminal 237 and the channel region 234. Similar to spin-transfer torque (STT), spin-orbit torque relies on the use of a spin-polarized current applied to a magnetic tunnel junction to switch magnetic states. The spin-orbit torque memory stack 238 includes a magnetic tunnel junction, which includes at least two ferromagnetic layers separated by a nonmagnetic insulator. The first ferromagnetic layer includes a reference layer designed to function as a free magnetic layer, and the second ferromagnetic layer is designed to have a fixed magnetization direction. In the three-terminal planar memory device 230, the reference layer of the spin-orbit torque memory stack 238 is located above a conductor that functions as a metal electrode write line. The spin-orbit torque memory stack 238 can be used to create non-volatile memory in magnetic random access memory (MRAM) that can have higher performance capabilities than typical spin-transfer torque MRAM.

[0031] The FeRAM, NOR flash memory, NAND flash memory, or spin-orbit torque RAM embodiments shown in Figures 2A-2C are exemplary only and are not intended to limit the present disclosure. It will be understood that the present disclosure may include other three-terminal memory devices known in the art and not shown in Figures 2A-2C. Nevertheless, such three-terminal memory devices in the present disclosure may include at least a channel layer or channel region that provides for the flow of electrons between the source and drain terminals.

[0032] As mentioned above, two-terminal memory devices can be arranged in a 3D memory array. Examples of vertically integrated 3D memory arrays include an xy cross-point architecture, an xz cross-point architecture, and a 3D vertically stacked architecture. Three-terminal memory devices offer more terminals and broader applications than two-terminal memory devices. However, there are many challenges in fabricating or implementing three-terminal memory devices in a 3D memory array.

[0033] Protection of the channel layer in the fabrication of three-terminal memory devices. This disclosure relates to the vertical integration of three-terminal memory devices in a 3D vertically stacked architecture. Arranging three-terminal memory cells in a 3D vertically stacked architecture offers the advantage of cost reduction, in addition to the ability to fabricate tens or hundreds of decks upon scale-up. However, film etching and deposition become increasingly difficult and / or non-uniform at higher aspect ratios, which can create challenges in the fabrication of vertically integrated three-terminal memory devices. Specifically, fabrication of the channel layer in a vertically integrated three-terminal memory device in a 3D vertically stacked architecture can result in electrical shorts and / or damage. Electrical shorts can occur due to undesired electrical interconnections resulting from non-isolated channel layers that electrically contact adjacent memory cells. Electrical shorts occur when memory cells in a 3D memory array are not electrically isolated from each other. Damage to the channel layer can result from over-etching portions of the channel layer, which introduces topographical differences and discontinuities along the channel layer, thereby reducing performance. For example, over-etching resulting in a loss of 10% or less of the channel material can be considered negligible damage, whereas over-etching resulting in a loss of more than 10% of the channel material can be considered moderate to severe damage. Overetching that results in more than 30% loss of channel material can be considered severe damage, and such damage can have a significant impact on the performance of 3D memory arrays.

[0034] FIG. 3 illustrates a schematic diagram of an exemplary vertically integrated three-terminal memory array according to some embodiments. The vertically integrated three-terminal memory array 300 is arranged in a 3D vertically stacked architecture. While shown in 2D, it will be understood that the layers and components illustrated in the vertically integrated three-terminal memory array 300 may extend into and out of a page. The vertically integrated three-terminal memory array 300 includes a plurality of three-terminal memory cells 310. The plurality of three-terminal memory cells 310 may be vertically stacked on top of each other in a 3D vertically stacked arrangement. In some embodiments, the plurality of three-terminal memory cells 310 includes more than 10 three-terminal memory cells, more than 20 three-terminal memory cells, or more than 30 three-terminal memory cells. Each of the plurality of three-terminal memory cells 310 is electrically isolated from each other. In some embodiments, a plurality of electrical insulating layers 320 each separate adjacent three-terminal memory cells 310 from each other. Each of the plurality of electrically insulating layers 320 may comprise an electrically insulating material such as silicon dioxide, silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxycarbonitride, etc. In some implementations, the plurality of electrically insulating layers 320 may also be referred to as a plurality of dielectric layers.

[0035] Each three-terminal memory cell 310 includes an oxide layer 311, a source region 312, a drain region 313, a channel layer 314, a source terminal 315, a drain terminal 316, a gate terminal 317, and a memory film 318. In some implementations, the source region 312 and the drain region 313 may be formed within the oxide layer 311, or the source region 312 and the drain region 313 may be formed on particular sides of the oxide layer 311. The source region 312 and the drain region 313 may be separated by at least a portion of the oxide layer 311. The source terminal 315 is in electrical contact with the source region 312, and the drain terminal 316 is in electrical contact with the drain region 313. The oxide layer 311 is between the source region 312 and the drain region 313. The channel layer 314 spans between the source region 312 and the drain region 313 and enables the flow of electrons between the source terminal 315 and the drain terminal 316. The channel layer 314 may be formed on the surface of the oxide layer 311. The memory film 318 is positioned on the channel layer 314, and the gate terminal 317 is positioned on the memory film 318, such that the memory film 318 is sandwiched between the channel layer 314 and the gate terminal 317. In some implementations, the memory film 318 overlies the channel layer 314. The composition of the memory film 318 may depend on the nonvolatile memory properties of the three-terminal memory cell 310. In some implementations, the memory film 318 may include a ferroelectric layer as shown in FIG. 2A, a charge trapping layer as shown in FIG. 2B, or a spin-orbit torque memory stack as shown in FIG. 2C. In some implementations, the channel layer 314 is positioned in a recessed region of the oxide layer 311. The portion of the oxide layer 311 separating the source region 312 and the drain region 313 may be laterally recessed relative to the sidewalls of the source region 312, the drain region 313, and / or the electrical insulation layer 320 to define the recessed region.

[0036] Each of the source terminal 315, the drain terminal 316, and the gate terminal 317 includes a conductive material. In some implementations, the conductive material can include, but is not limited to, molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, zinc, neodymium, platinum, and alloys thereof. For example, the conductive material can include tungsten. In some implementations, the conductive material can include a conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0037] In some implementations, the channel layer 314 has an average thickness of about 30 nm or less, about 20 nm or less, about 15 nm or less, or between about 2 nm and about 15 nm. In some implementations, the channel layer 314 comprises a semiconductor material. Examples of semiconductor materials in the channel layer 314 include, but are not limited to, polysilicon (poly-Si), silicon (Si), germanium (Ge), silicon-germanium (Si-Ge), carbon (C), boron nitride (BN), molybdenum disulfide (MoS), and oxide semiconductor materials such as zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO), germanium oxide (GeO), and indium gallium zinc oxide (IGZO). In some implementations, the channel layer 314 comprises polysilicon. The channel layer 314 spans between the source region 312 and the drain region 313 of each memory cell 310. The channel layer 314 is isolated for each memory cell 310, meaning that the channel layer 314 is insulated (i.e., not directly electrically connected) from adjacent memory cells 310. For example, the channel layer 314 of a first memory cell is insulated from a second memory cell adjacent to the first memory cell. In some implementations, the channel layer 314 is substantially flat or smooth, and a flatter or more uniform surface may correlate with a higher degree of crystallinity. In some implementations, the channel layer 314 can have a topographical deviation of about 10% or less from the reference plane of the channel layer 314. In some implementations, the average thickness of the channel layer 314 after various etching operations is sufficient to provide electrical interconnection between the source region 312 and the drain region 313, and the average thickness of the channel layer 314 is at least 5 nm. The channel layer 314 of the present disclosure can be isolated with minimal loss of channel material by protecting the channel layer 314 with a series of selective etches and sacrificial liner depositions described below. In some embodiments, loss of channel material can be minimized by maintaining the channel layer 314 so that the average thickness of the channel layer 314 is at least 5 nm. In some embodiments, the channel layer 314 may also be referred to as an isolation channel layer.

[0038] In the present disclosure, a channel material may be deposited in the recessed and non-recessed regions of one or more etched features. A sacrificial liner is deposited on the channel material. A directional etch removes the sacrificial liner from the non-recessed regions of one or more etched features, leaving the sacrificial liner in the recessed regions of one or more etched features. An isotropic etch removes the channel material from the non-recessed regions of one or more etched features, leaving the channel material and sacrificial liner intact in the recessed regions. The sacrificial liner is then removed from the recessed regions, leaving the channel material in the recessed regions intact, isolated, and undamaged by overetching.

[0039] FIG. 4 illustrates a flow diagram of an exemplary method for forming a channel layer during fabrication of a vertically integrated three-terminal memory array according to some embodiments. The operations of process 400 may be performed in a different order and / or with different, fewer, or additional operations. The operations of process 400 may be performed using the apparatus or tools illustrated in FIGS. 7 and 8. In some embodiments, the operations of process 400 may be implemented, at least in part, according to software stored on one or more non-transitory computer-readable media. The operations of process 400 may correspond to the stages illustrated in FIGS. 5A-5G and 6A-6E, which illustrate cross-sectional schematic views of various stages in an exemplary process for forming a channel layer during fabrication of a vertically integrated memory array according to some embodiments.

[0040] In block 410 of process 400, one or more features are etched through a mold stack disposed on a semiconductor substrate. The mold stack includes multiple film stacks. The multiple film stacks are vertically stacked, with adjacent film stacks separated by a dielectric layer. Each film stack includes a source region, a drain region, and an oxide layer between the source and drain regions. In some implementations, the dielectric layer includes an electrically insulating material such as silicon carbide, silicon oxynitride, or silicon oxycarbide. The dielectric layer functions to separate each film stack from another. In other words, the dielectric layer functions to electrically isolate adjacent film stacks from one another. The multiple film stacks may include multiple repeating film stacks, and the number of repeating film stacks may be 5 or more, 10 or more, 15 or more, or 25 or more. In some implementations, the oxide layer may include silicon oxide, silicon oxycarbide, silicon oxynitride, or other suitable electrically insulating oxide. The source and drain regions may be separated by at least a portion of the oxide layer. In some embodiments, the source and drain regions can be positioned on particular sides of the oxide layer. Each of the source and drain regions can comprise a semiconductor material such as doped polysilicon, implanted silicon, epitaxial silicon, or silicon-germanium. In some embodiments, each film stack further comprises a conductor layer adjacent to the drain region, the conductor layer being sandwiched between the drain region and the dielectric layer. In some embodiments, the conductor layer comprises a conductive material such as molybdenum, titanium nitride, or tungsten.

[0041] One or more features are etched through the mold stack. As used herein, "feature" may refer to a "negative feature" or an "etched feature," including, but not limited to, a trench, a hole, a via, a gap, a cavity, a recessed area, etc. These terms may be used interchangeably in this disclosure. An example of a feature is a trench. Features typically have an aspect ratio (depth to lateral dimension). Features with a high aspect ratio can have an aspect ratio of depth to lateral dimension of about 10:1 or more, about 15:1 or more, about 20:1 or more, about 25:1 or more, about 30:1 or more, or about 50:1 or more.

[0042] To etch one or more features, a mask can be placed over the mold stack. The mask can be patterned using conventional lithography techniques to define where the one or more features are to be etched. In some implementations, a patterned hard mask or photoresist is positioned over the top surface of the mold stack to define the one or more features to be etched. In some implementations, a non-selective plasma etch can be performed to etch the mold stack. The non-selective plasma etch can have a chemistry that etches the material of the mold stack at the same or substantially similar etch rate. The reaction chamber used for the non-selective plasma etch can be, for example, a Flex™ reaction chamber from the 2300™ Flex™ product family available from Lam Research, Inc. of Fremont, California.

[0043] 5A shows a cross-sectional schematic of a feature etched through a mold stack. While mold stack 500 shows only three film stacks 510 repeating the same layer / component, it will be understood that mold stack 500 can include four or more film stacks 510 in a 3D vertically stacked architecture. For example, mold stack 500 can include more than 15 repeating film stacks 510, more than 20 repeating film stacks, more than 30 repeating film stacks, or more than 50 repeating film stacks.

[0044] Mold stack 500 includes multiple film stacks 510, each including a source region 511, a drain region 512, and an oxide layer 513 between the source region 511 and the drain region 512. The source region 511 and the drain region 512 can have the same or similar composition. In some embodiments, each film stack 510 further includes a conductor layer 514 adjacent to the drain region 512. In some embodiments, each film stack 510 further includes a dielectric layer 515 adjacent to the source region 511. While each film stack 510 shows four different films, it will be understood that, assuming the source region 511 and the drain region 512 are identical, in some embodiments, each film stack 510 in mold stack 500 can have three or fewer different films. For example, each film stack 510 can be free of the conductor layer 514 or the dielectric layer 515.

[0045] The dielectric layer 515 can function to electrically isolate the multiple film stacks 510 from one another. While the dielectric layer 515 may be described as part of each film stack 510, it will be understood that in some implementations, the dielectric layer 515 may be described as separate from the film stacks 510 to divide or separate the film stacks 510 from one another. In Figure 5A, the dielectric layer 515 is positioned over the source region 511, which is positioned over the oxide layer 513, which is positioned over the drain region 512, which is positioned over the conductor layer 514.

[0046] 5A, each of source region 511 and drain region 512 can include doped polysilicon, dielectric layer 515 can include silicon oxycarbide, oxide layer 513 can include silicon oxide, and conductor layer 514 can include tungsten. Thus, each film stack 510 in mold stack 500 can include SiOC / doped poly-Si / SiO2 / doped poly-Si / W. However, it will be understood that in some other implementations, there may be fewer or more films in each film stack 510.

[0047] As another example (not shown), each of source region 511 and drain region 512 can include doped polysilicon, dielectric layer 515 can include silicon oxycarbide, and oxide layer 513 can include silicon oxide. Thus, each film stack 510 in mold stack 500 can include SiOC / doped poly-Si / SiO2 / doped poly-Si.

[0048] As yet another example (not shown), each of source region 511 and drain region 512 can include silicon nitride, dielectric layer 515 can include silicon oxycarbide, and oxide layer 513 can include silicon oxide. Thus, each film stack 510 in mold stack 500 can include SiOC / SiN / SiO2 / SiN. It will be understood that silicon nitride can be replaced with a different material, such as titanium nitride, in subsequent operations. It will be understood that the foregoing configurations are merely exemplary and that other configurations for mold stack 500 may be possible.

[0049] The etched feature 516 extends through the mold stack 500, including the dielectric layer 515, source region 511, oxide layer 513, drain region 512, and conductor layer 514 of each film stack 510. The etched feature 516 can be formed by vertical etching. In some embodiments, the etched feature 516 can be a hole or trench created by non-selective plasma etching. In some embodiments, the etched feature 516 can have a high aspect ratio. In some embodiments, the depth-to-width aspect ratio of the etched feature is about 10:1 or greater.

[0050] Returning to FIG. 4 , in block 420 of process 400, at least a portion of the oxide layer is selectively etched in each of the film stacks to form recessed regions in each of the film stacks. The oxide material in the oxide layer is selectively etched at a substantially faster rate than other materials in the mold stack, or at least compared to the dielectric layers of the mold stack. The substantially faster rate may be at least 5 times, at least 7 times, at least 10 times, or at least 50 times greater than the etch rate of the other materials. Thus, the oxide material is selectively etched without etching or substantially etching other materials in the mold stack, or at least without etching or substantially etching the dielectric layers of the mold stack. When selectively etching the oxide layer, the etch proceeds laterally, removing oxide material from the oxide layer. It will be appreciated that selectively etching the oxide layer may also laterally remove portions of the source and drain regions in certain embodiments. Selectively etching the oxide layer removes at least a desired thickness of the oxide layer from the sidewalls of one or more features. In this manner, each iteration of the oxide layer in one or more features of the mold stack has an expanded gap relative to other layers of the mold stack. The expanded gap corresponds to a recessed region in each of the film stacks. A channel layer is subsequently deposited in the recessed region. In some embodiments, the thickness of the oxide layer removed from the sidewalls of the one or more features is between about 1 nm and about 30 nm, between about 1 nm and about 20 nm, or between about 1 nm and about 10 nm. The thickness of the oxide layer removed from the sidewalls of the one or more features is sufficient to deposit at least the channel layer and the sacrificial liner in the recessed region.

[0051] In some embodiments, selectively etching at least a portion of the oxide layer is performed using a fluorine-based etchant. The oxide material can be etched with high selectivity relative to other materials of the mold stack by using the fluorine-based etchant. For example, the fluorine-based etchant can include hydrogen fluoride (HF). In some embodiments, the fluorine-based etchant includes an HF vapor etchant or an HF wet clean. In some embodiments, selectively etching the oxide material of the oxide layer is performed with an etch contrast of at least 10:1 relative to other materials of the mold stack or at least 10:1 relative to dielectric layers of the mold stack. "Etch contrast" can correspond to the ratio of etch rates between materials during an etching operation, where an etch contrast of 5:1 refers to an etch rate of a first material that is five times faster than a second material.

[0052] In some implementations, selectively etching at least a portion of the oxide layer to form recessed regions defines protrusions in each film stack in areas outside the recessed regions. Each "protrusion" results from a portion of the recessed sidewall, including the sidewall that recedes from the oxide layer, with the remaining portion of the sidewall not receding from the selective etching defining the protrusion. The protrusions from the sidewalls define a lateral overhang of one or more materials from the mold stack above the recessed region. The area outside the recessed region constitutes a non-recessed region in one or more features. The protrusions can protrude laterally into one or more features by an amount equal to the thickness of the removed oxide layer. The protrusions can include at least a dielectric layer of the mold stack. In some examples, the selective etching of the oxide layer can also remove portions of the source and drain regions, so the source and drain regions are not necessarily part of the protrusions. In some implementations, the protrusions can include the dielectric layer, source, and drain regions of the mold stack. In some implementations, the protrusions can include the dielectric layer, source, drain, and conductor layers of the mold stack.

[0053] FIG. 5B shows a cross-sectional schematic view of the etched feature of FIG. 5A, in which a recessed region 520 is formed by selectively etching a portion of the oxide layer from the sidewall of the etched feature. A recessed region 520 is defined in each film stack 510 by laterally removing a portion of the oxide layer 513 from the sidewall of the etched feature 516. The recessed region 520 can be formed by horizontal etching. In some implementations, the recessed region 520 is a lateral recess created by selective wet or dry etching. The selective wet or dry etching removes the oxide material of the oxide layer 513 at a substantially faster rate than the material of the source region 511, the drain region 512, the conductor layer 514, and the dielectric layer 515 of the mold stack 500. Thus, the selective wet or dry etching is selective to the source region 511, the drain region 512, the conductor layer 514, and the dielectric layer 515, but is non-selective to the oxide layer 513. Oxide layer 513 is partially etched laterally without substantially etching dielectric layer 515. In some implementations, oxide layer 513 is partially etched laterally without substantially etching source region 511, drain region 512, conductor layer 514, and dielectric layer 515. Protrusion 517 is defined after selectively etching a portion of oxide layer 513 from the sidewalls of etched feature 516, with remaining material from the unetched sidewalls protruding laterally above recessed region 520 to define protrusion 517. As shown in FIG. 5B , protrusion 517 can include source region 511, drain region 512, conductor layer 514, and dielectric layer 515.

[0054] Returning to FIG. 4 , in block 430 of process 400, a channel material is conformally deposited along the sidewalls of one or more features. In some embodiments, the channel material can be deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD). In some embodiments, the channel material can be a suitable semiconductor material such as polysilicon, silicon, germanium, silicon-germanium, carbon, boron nitride, molybdenum disulfide, or an oxide semiconductor material such as indium gallium zinc oxide (IGZO). For example, the channel material can include lightly doped polysilicon. In some embodiments, the average thickness of the channel material is about 30 nm or less, about 20 nm or less, about 15 nm or less, or about 2 nm to about 15 nm. The channel material is deposited in the recessed regions on the exposed surface of the oxide layer and is also deposited on at least the source region, the drain region, and the exposed surface of the dielectric layer. In some embodiments, the channel material is further deposited on the exposed surface of the conductor layer. The channel material is continuous or conformal along the mold stack in one or more features.

[0055] 5C shows a cross-sectional schematic view of the etched feature of FIG. 5B, with a channel material conformally deposited along the sidewalls of the etched feature. Channel material 530 is formed along the sidewalls of etched feature 516 and is continuous along the sidewalls of etched feature 516. Channel material 530 lines the sidewalls of etched feature 516 without substantially filling etched feature 516. Channel material 530 is formed in recessed region 520 on oxide layer 513. Channel material 530 is also formed on source region 511, drain region 512, conductor layer 514, and dielectric layer 515 of each film stack 510. In some embodiments, channel material 530 comprises polysilicon. In some embodiments, channel material 530 comprises silicon, germanium, silicon-germanium, carbon, boron nitride, molybdenum disulfide, or indium gallium zinc oxide.

[0056] Returning to FIG. 4 , in block 440 of process 400, a sacrificial liner is deposited to cover the channel material along the sidewalls of one or more features. The sacrificial liner may be composed of a material that has a different etch selectivity than the channel material. Stated differently, the sacrificial liner has a large etch contrast with respect to the channel material. For example, the sacrificial liner may have an etch contrast of at least 10:1, at least 20:1, at least 30:1, or at least 50:1 with respect to the channel material when subjected to a subsequent directional etching process.

[0057] In some embodiments, the sacrificial liner comprises carbon, silicon oxide, silicon nitride, germanium, or silicon-germanium. The sacrificial liner can comprise any material that can protect the channel material during etching and can be removed without damaging the underlying channel material. In some embodiments, the sacrificial liner can be conformally deposited on the channel material such that the thickness of the sacrificial liner is substantially uniform along the sidewalls of one or more features. However, in some other embodiments, the sacrificial liner can be semi-conformally or non-conformally deposited on the channel material such that the thickness of the sacrificial liner is non-uniform along the sidewalls of one or more features. In some embodiments, the average thickness of the sacrificial liner is about 1 nm to about 50 nm, about 2 nm to about 20 nm, or about 3 nm to about 15 nm.

[0058] The sacrificial liner can be easily etched by a subsequent directional etching process, such as an ion beam etching process or an ion-enhanced chemical etching process described below. Thus, the sacrificial liner can be etched at a faster rate than the underlying materials during the directional etching process, including the channel material and / or the mold stack material. However, the sacrificial liner can be selective to an isotropic etching process that selectively removes the channel material. The isotropic etching process that follows the directional etching process removes the channel material at a faster rate than the sacrificial liner. The sacrificial liner includes a material that etches with a high etch contrast (e.g., at least 10:1) relative to the channel material during the subsequent directional etching process, while the channel material etches with a high etch contrast (e.g., at least 10:1) relative to the material of the sacrificial liner during the subsequent isotropic etching process to selectively remove the channel material. The sacrificial liner functions to protect the channel material in the recessed regions of one or more features during the directional etching and isotropic etching processes.

[0059] In some implementations, the sacrificial liner includes multiple layers of material. For example, the multiple layers of material can function to facilitate removal of the sacrificial liner from the sidewalls of one or more features. In some implementations, the sacrificial liner includes a bilayer of oxide and carbide. The oxide can adhere to the channel material, and the carbide can be disposed on the oxide. The oxide can easily peel and lift off from the channel material during oxygen-based stripping, thereby facilitating removal of the sacrificial liner. For example, the oxide can include silicon oxide, and the carbide can include silicon carbide.

[0060] FIG. 5D shows a cross-sectional schematic view of the etched feature of FIG. 5C , in which a sacrificial liner is deposited on the channel material of the etched feature. The sacrificial liner 540 is conformally or semi-conformally deposited along the sidewalls of the etched feature 516. The sacrificial liner 540 is continuous along the mold stack 500 within one or more features 516. The sacrificial liner 540 covers the channel material 530 and protects it from damage (e.g., excessive overetching of the channel material 530) in the recessed areas 520 during etching. The sacrificial liner 540 comprises a material having a different etch selectivity than the channel material 530. In some implementations, the sacrificial liner 540 comprises an oxide, a carbide, or a combination thereof. For example, the sacrificial liner 540 comprises a bilayer of an oxide and a carbide.

[0061] Returning to FIG. 4 , in block 450 of process 400, the sacrificial liner covering the channel material is etched in areas outside the recessed regions. However, the sacrificial liner covering the channel material within the recessed regions remains intact. Removal of the sacrificial liner in areas outside the recessed regions can be performed by directional etching. The directional etching can provide etchant "vertically" through one or more features while minimizing etchant "horizontally" penetrating into the recessed regions. Protrusions from the sidewalls of one or more features can act as masks to protect the recessed regions during directional etching of the sacrificial liner. The protrusions prevent the etchant from etching the material within the recessed regions, including the channel material. Such protrusions include a layer of a mold stack above each recessed region, and the protrusions are located in areas outside the recessed regions. The protrusions include a layer of a mold stack that protrudes laterally from the sidewalls of one or more features. The protrusions act as overhangs that mask the sacrificial liner and the channel material within the recessed regions during directional etching. In some implementations, the protrusions can comprise at least a dielectric layer of the mold stack. Non-recessed regions or areas outside of the recessed regions can comprise protrusions. In some implementations, the recessed regions can comprise at least an oxide layer of the mold stack.

[0062] In some embodiments, the directional etching can include ionized chemical species or ionized plasma species, and an electromagnetic field is applied to direct the ionized chemical species or ionized plasma species toward the bottom of one or more features. Thus, the directional etching can be performed by ion beam etching (IBE) or ion-enhanced chemical etching. However, it will be understood that other suitable etching techniques may be applied with directionality, with reactive species typically being accelerated or delivered toward the bottom of one or more features. In some embodiments, the Kiyo™ reactor manufactured by Lam Research, Inc. of Fremont, California, is an example of a suitable reactor that can be used to perform directional etching.

[0063] The protrusions in one or more features act as a mask, blocking reactive species from etching the sacrificial liner and the channel material in the recessed areas. However, during the directional etch, the sacrificial liner deposited along the protrusions is etched with a high etch contrast relative to the channel material. In some embodiments, the sacrificial liner is etched with an etch contrast of at least 10:1, at least 20:1, at least 30:1, or at least 50:1 relative to the channel material during the directional etch. The directional etch is performed until all of the sacrificial liner is removed from the protrusions of one or more features, meaning that all of the sacrificial liner is removed from the areas outside the recessed areas while leaving the sacrificial liner and channel material in the recessed areas intact. The sacrificial liner is removed without destroying or eroding material from the protrusions. This effectively opens one or more features with minimal material loss in the mold stack or channel material. As used herein, minimal material loss can refer to a loss of about 10% or less of material. In some embodiments, the top of the mold stack can include an oxide layer or other mask layer that acts as a mask during the directional etch. The mask layer can include, for example, the channel material and the oxide material of the oxide layer backed with a sacrificial liner, which is removed from the mask layer without destroying or attacking the oxide material of the mask layer.

[0064] FIG. 5E shows a cross-sectional schematic view of the etched feature of FIG. 5D, in which the sacrificial liner is removed from the non-recessed regions by directional etching. The directional etch is applied vertically through the etched feature 516, opening the etched feature 516 in the non-recessed regions 550. Specifically, the directional etch removes the sacrificial liner 540 along the protrusions 517 that protrude laterally in the etched feature 516, which protrude laterally in the non-recessed regions 550 of the etched feature 516. The directional etch is selective to the channel material and non-selective to the sacrificial liner. Therefore, the directional etch removes little of the channel material 530 along the protrusions 517. Furthermore, the channel material 530 and the sacrificial liner 540 are not etched in the recessed regions 520 of the etched feature 516 following the directional etch. The protrusions 517 in the non-recessed regions 550 act as a mask to prevent the recessed regions 520 from being etched during the directional etch.

[0065] Returning to FIG. 4 , in block 460 of process 400, the channel material is selectively etched along the sidewalls of one or more features in areas outside the recessed regions to define an isolation channel layer between the source and drain regions of each film stack. The channel material in the recessed regions remains intact, but the channel material outside the recessed regions is removed. The removal of the channel material in the areas outside the recessed regions is performed by an isotropic etch selective to the sacrificial liner and mold stack. The isotropic etch can provide an etchant non-directionally (i.e., “vertically” and “horizontally”) through the one or more features, where the etchant interacts with the material exposed along the sidewalls of the one or more features. The sacrificial liner in the recessed regions prevents the channel material from being etched in the recessed regions.

[0066] During the isotropic etch, the channel material is etched with a high etch contrast relative to the sacrificial liner and mold stack. In some embodiments, the channel material is etched with an etch contrast of at least 25:1, at least 50:1, at least 75:1, or at least 100:1 relative to the sacrificial liner during the isotropic etch. In some embodiments, the channel material is etched with an etch contrast of at least 10:1, at least 20:1, at least 30:1, or at least 50:1 relative to the mold stack during the isotropic etch, or at least to the dielectric layer of the mold stack during the isotropic etch. The mold stack includes materials in the source region, drain region, dielectric layer, and / or conductor layer. In some embodiments, the isotropic etch includes wet etching, and the wet etch chemistry can depend on the semiconductor material of the channel material being removed. In some embodiments, the isotropic etch includes plasma etching, and the plasma etch chemistry can depend on the semiconductor material of the channel material being removed. The isotropic etch chemistry depends on the channel material being removed. In one example, a fluorine-based etchant such as hydrogen fluoride (HF) can be used to remove oxide semiconductor materials. In another example, peroxide can be used to remove germanium. Also, hydrogen-based or fluorine-based plasmas can be used to remove germanium or silicon-germanium. In yet another example, atomic layer etching processes can be used to remove various oxide materials.

[0067] The channel material deposited along the laterally protruding protrusions in one or more features is etched by an isotropic etch. However, after the isotropic etch, the sacrificial liner and channel material in the recessed regions of each film stack remain intact, or at least substantially intact. In some implementations, a small portion of the channel material in the recessed regions is etched, and the small portion may constitute part of the channel material deposited along the surfaces of the source and drain regions in the recessed regions. However, for each film stack, the channel material is continuous along at least the surface of the oxide layer in the recessed regions, providing a connection between the source and drain regions. This channel material in the recessed regions defines an isolation channel layer. The channel material is discontinuous between adjacent film stacks, meaning that the channel material is not connected (i.e., not isolated) between memory cells in the memory array. In other words, the channel material only contacts the source and drain regions of the corresponding film stack. The sidewalls of one or more features in areas outside the recessed regions are substantially free of channel material.

[0068] FIG. 5F shows a cross-sectional schematic view of the etched feature of FIG. 5E, in which the channel material is removed from the non-recessed regions by an isotropic etch. An isotropic etch is applied to the etched feature 516 to remove the channel material 530 from the non-recessed regions 550 of the etched feature 516. Specifically, the isotropic etch removes the channel material 530 along laterally protruding protrusions 517 in the etched feature 516. In some implementations, the channel material 530 is removed from the dielectric layer 515 of the mold stack 500. The isotropic etch is selective to the sacrificial liner 540 and the mold stack 500, but non-selective to the channel material 530. However, the isotropic etch does not remove the channel material 530 in the recessed regions 520 of the etched feature 516, or at least does not remove the channel material 530 in the recessed regions 520 on the oxide layer 513 spanning the source region 511 and the drain region 512 due to the presence of the sacrificial liner 540. The sacrificial liner 540 is not etched in the recessed regions 520 of the etched features 516, but acts as a protective layer that prevents the channel material 530 from being etched in the recessed regions 520. The channel material 530 in the recessed regions 520 is isolated by the film stack 510, thereby forming a channel layer.

[0069] Returning to FIG. 4, process 400 further includes removing a sacrificial liner overlying the isolation channel layer. After selectively etching the channel material from areas outside the recessed regions, the sacrificial liner is removed. In some implementations, the sacrificial liner is removed by a plasma etching or wet etching process. In some implementations, the plasma etching or wet etching can be selective to the isolation channel layer but non-selective to one or more materials of the sacrificial liner. For example, the plasma etching or wet etching process can target one or more materials of the sacrificial liner, such as an oxide material, for lift-off from the channel material, thereby removing the entire sacrificial liner. This leaves an isolation channel layer in each film stack exposed by one or more features. The isolation channel layer is insulated from adjacent film stacks to avoid electrical shorts due to undesired electrical interconnections between memory cells. The isolation channel layer minimizes loss of channel material. Minimal loss of channel material can be achieved by retaining a sufficient amount of channel material so that the average thickness of the isolation channel layer is at least 5 nm, between about 5 nm and about 30 nm, or between about 5 nm and about 20 nm. In some embodiments, etching operations such as the directional etching at block 450 and the isotropic etching at block 460 do not damage the isolation channel layer in that there is no resulting significant phase difference, non-uniformity, or discontinuity along the isolation channel layer. In some embodiments, the isolation channel layer can have a topographical deviation of about 10% or less from a reference plane. The isolation channel layer can be continuous between and directly contact the source and drain regions. In some embodiments, the isolation channel layer has an average thickness of about 5 nm or more after removal of the sacrificial liner. For example, the isolation channel layer has an average thickness of about 5 nm to about 20 nm.

[0070] With the isolation channel layer exposed in one or more features, subsequent deposition and patterning operations can be performed in one or more features to complete the fabrication of a vertically integrated three-terminal memory array. In some implementations, materials in a memory film stack can be deposited on the isolation channel layer of each film stack, and the materials in the memory film stack can include a ferroelectric layer as shown in FIG. 2A, a charge trapping layer as shown in FIG. 2B, or a spin-orbit torque stack as shown in FIG. 2C. Furthermore, in some implementations, a gate electrode or gate terminal can be deposited on the memory film stack and aligned with the isolation channel layer, and the memory film stack is between the isolation channel layer and the gate terminal. Additionally, in some implementations, a source terminal can be deposited on the source region and connected to the source region, and a drain terminal can be deposited on the drain region and connected to the drain region. A vertically integrated three-terminal memory array can be fabricated in one or more features by the 3D vertical stacking of the present disclosure, and the channel layer in each memory cell of the memory array is electrically isolated and undamaged (e.g., minimal loss of channel material).

[0071] FIG. 5G shows a cross-sectional schematic view of the etched feature of FIG. 5F with the sacrificial liner removed. A dry or wet cleaning operation can be applied to remove the sacrificial liner 540 from the etched feature 516. The dry or wet cleaning operation removes the sacrificial liner 540 from the channel material 530 in the recessed regions 520, leaving the channel material 530 exposed in the recessed regions 520. After removal of the sacrificial liner 540, there is minimal loss of the channel material 530. The channel material 530 is continuous along the oxide layer 513 between the source and drain regions 511 and 512 for each film stack 510, resulting in an isolation channel layer. The channel material 530 provides contact with the source and drain regions 511 and 512.

[0072] 6A-6E illustrate enlarged cross-sectional schematic diagrams of various stages in an exemplary process for forming an isolation channel layer using a multilayer sacrificial liner according to some embodiments. A channel material 530 is deposited along the sidewalls of an etched feature 516 of a mold stack 500, as shown in FIG. 6A. As shown in FIG. 6B, rather than depositing a sacrificial liner comprised of a single material, a multilayer sacrificial liner 640 is deposited on the channel material 530. The multilayer sacrificial liner 640 includes a first layer 642 of oxide deposited on the channel material 530, followed by a second layer 644 of carbon deposited on the first layer 642 of oxide. The first layer 642 of oxide interlocks with the channel material 530, exposing the second layer 644 of carbon. After a directional etch selective to the channel material 530, at least the second layer 644 of carbon is removed from areas outside the recessed regions 520 (i.e., the non-recessed regions 550), as shown in FIG. 6C. After an isotropic etch selective to the second layer of carbon 644, at least the first layer of oxide 642 and the channel material 530 are removed from the non-recessed regions 550, as shown in FIG. 6D. Due to the protection of the second layer of carbon 644 and the first layer of oxide 642, the channel material 530 remains largely intact in the recessed regions 520. After a lift-off operation targeting the first layer of oxide 642, the first layer of oxide 642 and the second layer of carbon 644 are removed from the recessed regions 620, thereby removing the multilayer sacrificial liner 640 of FIG. 6E. The channel material 530 remains exposed in the recessed regions 520 after the lift-off operation of FIG. 6E.

[0073] Device FIG. 7 shows a schematic diagram of one embodiment of an atomic layer deposition (ALD) and / or chemical vapor deposition (CVD) process station 700 having a process chamber body 702 for maintaining a low-pressure environment. Multiple process stations 700 may be included in a common low-pressure process tool environment. For example, FIG. 14 illustrates an exemplary embodiment of a multi-station processing tool. In some embodiments, one or more hardware parameters of the ALD process station 700 (including those described in detail below) can be programmatically adjusted by one or more computer controllers 750.

[0074] The process station 700 is in fluid communication with a reactant delivery system 701a for delivering process gases to a distribution showerhead 706. The reactant delivery system 701a includes a mixing vessel 704 for blending and / or conditioning process gases, such as a silicon precursor gas or a second reactant gas (e.g., an oxygen-containing reactant, a carbon-containing reactant, etc.), for delivery to the showerhead 706. One or more mixing vessel inlet valves 720 can control the introduction of process gases into the mixing vessel 704. A plasma may also be delivered to the showerhead 706 or may be generated in the process station 700. The reactant delivery system 701a can be configured to deliver process gases to a substrate disposed in the process station 700.

[0075] As an example, one embodiment of FIG. 7 includes a vaporization point 703 for vaporizing a liquid reactant supplied to a mixing vessel 704. In some embodiments, the vaporization point 703 may be a heated vaporizer. Saturated reactant vapor generated from such a vaporizer may condense in downstream delivery piping. Exposure of incompatible gases to the condensed reactant may generate small particles. These small particles may clog the piping, interfere with valve operation, or contaminate the substrate. Some approaches to addressing these issues involve purging and / or evacuating the delivery piping to remove residual reactant. However, purging the delivery piping may increase process station cycle time and reduce process station throughput. Therefore, in some embodiments, the delivery piping downstream of the vaporization point 703 may be heat traced. In some examples, the mixing vessel 704 may also be heat traced. In one non-limiting example, the piping downstream of vaporization point 703 has an elevated temperature profile ranging from about 100° C. to about 150° C. at mixing vessel 704 .

[0076] In some embodiments, the liquid precursor or reactant may be vaporized in a liquid injector. For example, the liquid injector can inject pulses of the liquid reactant into a carrier gas stream upstream of the mixing vessel. In one embodiment, the liquid injector can vaporize the reactant by flashing the liquid from a higher pressure to a lower pressure. In another example, the liquid injector can atomize the liquid into dispersed microdroplets, which are then vaporized in a heated delivery pipe. Smaller droplets can vaporize faster than larger droplets, reducing the delay between liquid injection and complete vaporization. Faster vaporization can reduce the length of piping downstream from the vaporization point 703. In one scenario, the liquid injector can be attached directly to the mixing vessel 704. In another scenario, the liquid injector can be attached directly to the showerhead 706.

[0077] In some embodiments, a liquid flow controller (LFC) can be provided upstream of the vaporization point 703 to control the mass flow rate of the liquid being vaporized and delivered to the process station 700. For example, the LFC can include a thermal mass flow meter (MFM) located downstream of the LFC. The plunger valve of the LFC can then be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM. However, stabilizing the liquid flow using feedback control can take one second or more. This can extend the time for flowing the liquid reactant. Therefore, in some embodiments, the LFC can be dynamically switched between feedback control mode and direct control mode. In some embodiments, this can be accomplished by disabling the sense tubes of the LFC and the PID controller.

[0078] The showerhead 706 distributes gases toward the substrate 712. In the embodiment shown in Figure 7, the substrate 712 is shown positioned below the showerhead 706 and resting on a pedestal 708. The showerhead 706 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gases to the substrate 712.

[0079] In some embodiments, the pedestal 708 can be raised or lowered to expose the substrate 712 to the volume between the substrate 712 and the showerhead 706. It will be appreciated that in some embodiments, the height of the pedestal can be programmatically adjusted by a suitable computer controller 750.

[0080] In another scenario, adjusting the height of pedestal 708 may allow for varying the plasma density during a plasma activation cycle in an embodiment process in which a plasma is ignited. At the end of a process step, pedestal 708 may be lowered to allow removal of substrate 712 from pedestal 708 during another substrate transfer step.

[0081] In some embodiments, the pedestal 708 may be temperature controlled via a heater 710. In some embodiments, the pedestal 708 may be heated to a temperature of at least about 250°C, or in some embodiments, about 300°C, for example, less than about 250°C, during deposition of the channel material and / or sacrificial liner as described in the disclosed embodiments. In some embodiments, the pedestal is set to a temperature between about 50°C and about 300°C, for example, between about 200°C and about 275°C. In some embodiments, the pedestal is set to a temperature between about 50°C and about 300°C. In some embodiments, the pedestal is set to a temperature between about 200°C and about 275°C.

[0082] Additionally, in some embodiments, pressure control for the process station 700 may be provided by a butterfly valve 718. As shown in the embodiment of Figure 7, the butterfly valve 718 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control for the process station 700 may also be adjusted by varying the flow rate of one or more gases introduced to the process station 700.

[0083] In some embodiments, the position of the showerhead 706 can be adjusted relative to the pedestal 708 to vary the volume between the substrate 712 and the showerhead 706. Furthermore, it will be understood that the vertical position of the pedestal 708 and / or the showerhead 706 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 708 may include a rotation axis for rotating the orientation of the substrate 712. It will be understood that in some embodiments, one or more of these exemplary adjustments can be implemented programmatically by one or more suitable computer controllers 750.

[0084] In some embodiments that can utilize a plasma as described above, the showerhead 706 and pedestal 708 are in electrical communication with a radio frequency (RF) power source 714 and matching network 716 to power the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 714 and matching network 716 can operate at any suitable power to form a plasma having a particular composition of radical species. Examples of suitable powers are included above. Similarly, the RF power source 714 can provide RF power at any suitable frequency. In some embodiments, the RF power source 714 can be configured to control high-frequency and low-frequency RF power sources independently of each other. Exemplary low-frequency RF frequencies can include, but are not limited to, frequencies between 0 kHz and 500 kHz. Exemplary high frequency RF frequencies may include, but are not limited to, frequencies between 1.8 MHz and 2.45 GHz, or greater than about 13.56 MHz, or greater than 27 MHz, or greater than 180 MHz, or greater than 60 MHz. It will be appreciated that any suitable parameters may be adjusted, either discretely or continuously, to provide plasma energy for surface reactions.

[0085] In some embodiments, the plasma can be monitored in situ by one or more plasma monitors. In one scenario, plasma power can be monitored by one or more voltage and current sensors (e.g., VI probes). In another scenario, plasma density and / or process gas concentrations can be measured by one or more optical emission spectroscopy (OES) sensors. In some embodiments, one or more plasma parameters can be programmatically adjusted based on measurements from such in-situ plasma monitors. For example, OES sensors can be used in a feedback loop to provide programmatic control of plasma power. It will be appreciated that in some embodiments, other monitors can be used to monitor the plasma and other process characteristics. Such monitors can include, but are not limited to, infrared (IR) monitors, acoustic monitors, and pressure transducers.

[0086] In some embodiments, instructions to the controller 750 may be controlled via input / output control (IOC) sequence instructions. In one example, instructions for setting conditions for a process step may be included in the corresponding recipe step of the process recipe. In some cases, process recipe steps may be arranged in a sequence such that all instructions for a process step are executed simultaneously with that process step. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe step. For example, a first recipe step may include instructions for setting the flow rate of an inert gas and / or reactant gas (e.g., a first precursor such as a silicon precursor), instructions for setting the flow rate of a carrier gas (such as argon), and a time delay instruction for the first recipe step. A second, subsequent recipe step may include instructions for adjusting or stopping the flow rate of an inert gas and / or reactant gas, instructions for adjusting the flow rate of a carrier gas or purge gas, and a time delay instruction for the second recipe step. A third recipe step may include instructions for adjusting the flow rate of a second reactant gas, instructions for adjusting the flow rate of a carrier gas or purge gas, and a time delay instruction for the third recipe step. The fourth subsequent recipe step may include instructions to adjust or stop the flow of inert and / or reactant gases, instructions to adjust the flow of carrier or purge gases, and time delay instructions for the fourth recipe step. It will be understood that these recipe steps may be further subdivided and / or repeated in any suitable manner within the scope of the disclosed embodiments.

[0087] As described above, one or more process stations may be included in a multi-station processing tool. FIG. 8 shows a schematic diagram of one embodiment of a multi-station processing tool 800 including an inbound load lock 802 and an outbound load lock 804, either or both of which may include a remote plasma source. A robot 806 is configured to move wafers at atmospheric pressure from a cassette loaded via a pod 808 to the inbound load lock 802 through an atmospheric pressure port 810. The wafer is placed by the robot 806 on a pedestal 812 of the inbound load lock 802, the atmospheric pressure port 810 is closed, and the load lock is pumped down. If the inbound load lock 802 includes a remote plasma source, the wafer may undergo remote plasma processing in the load lock before being introduced into the processing chamber 814. Additionally, the wafer may also be heated in the inbound load lock 802 to remove moisture and absorbed gases, for example. The chamber transfer port 816 to the processing chamber 814 is then opened and another robot (not shown) moves the wafer into the reactor and places it on a pedestal in the first station shown in the reactor for processing. While the embodiment shown in Figure 8 includes a load lock, it will be understood that in some embodiments the wafer may enter the process station directly.

[0088] The illustrated processing chamber 814 includes four process stations, numbered 1 through 4 in the embodiment shown in FIG. 8 . Each station has a heated pedestal (shown at 818 for station 1) and a gas line inlet. It will be understood that in some embodiments, each process station may have a different purpose or multiple purposes. For example, in some embodiments, a process station may be switchable between an ALD process mode and a plasma-enhanced ALD process mode. Additionally or alternatively, in some embodiments, the processing chamber 814 may include one or more corresponding pairs of ALD and plasma-enhanced ALD process stations. While the illustrated processing chamber 814 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0089] 8 illustrates one embodiment of a wafer handling system 890 for transferring wafers within the processing chamber 814. In some embodiments, the wafer handling system 890 can transfer wafers between various process stations and / or between process stations and load locks. It will be understood that any suitable wafer handling system may be used. Non-limiting examples include a wafer carousel and a wafer handling robot.

[0090] It will be appreciated that in some embodiments, a low-pressure transfer chamber may be included in a multi-station processing tool to facilitate transfer between multiple processing chambers. In the embodiment shown in Figure 8, a multi-station processing tool 800 includes multiple processing chambers 814 that include multiple process stations (numbered 1 through 4). The processing chambers 814 interface with a low-pressure transfer chamber that includes a robot 806 configured to transfer substrates between the processing chambers 814 and load locks. An atmospheric pressure substrate transfer module 810 including an atmospheric pressure robot is configured to facilitate transfer of substrates between the load locks and pods 808.

[0091] 8 also illustrates one embodiment of a system controller 850 used to control the process conditions and hardware states of the process tool 800. The system controller 850 can include one or more memory devices 856, one or more mass storage devices 854, and one or more processors 852. The processor 852 can include a CPU or computer, analog and / or digital input / output connections, stepper motor controller boards, etc.

[0092] In some embodiments, system controller 850 controls all of the activity of process tool 800. System controller 850 executes system control software 858, which is stored on mass storage device 854, loaded into memory device 856, and executed on processor 852. Alternatively, control logic may be hard-coded into controller 850. For these purposes, application-specific integrated circuits, programmable logic devices (e.g., field-programmable gate arrays, or FPGAs), or the like may be used. In the following description, wherever "software" or "code" is used, functionally equivalent hard-coded logic may be used instead. System control software 858 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by process tool 800. System control software 858 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of the process tool components used to perform the various process tool processes. The system control software 858 may be coded in any suitable computer-readable programming language.

[0093] In some embodiments, the system control software 858 may include input / output control (IOC) sequence instructions for controlling the various parameters described above. In some embodiments, other computer software and / or programs stored on the mass storage device 854 and / or memory device 856 associated with the system controller 850 may be used. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0094] The substrate positioning program may include program code for process tool components used to load the substrate onto the pedestal 818 and control the spacing between the substrate and other parts of the process tool 800 .

[0095] The process gas control program can include code for controlling gas composition (e.g., silicon precursor gases described herein, carbon-containing gases, carrier gases, and purge gases) and flow rates to stabilize the pressure of the process station, and optionally, code for flowing gases through one or more process stations prior to deposition. The pressure control program can include code for controlling the pressure of the process station by, for example, adjusting a throttle valve in the exhaust system of the process station, gas flow to the process station, etc.

[0096] The heater control program may include code for controlling the current to a heating unit used to heat the substrate, or the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0097] The plasma control program may include code for setting RF power levels applied to process electrodes of one or more process stations according to embodiments herein.

[0098] The pressure control program can include code for maintaining pressure within the reaction chamber according to embodiments herein.

[0099] In some embodiments, there may be a user interface associated with the system controller 850. The user interface may include a display screen, a graphical software display of equipment and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0100] In some embodiments, the parameters adjusted by the system controller 850 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to the user in the form of a recipe and may be entered using a user interface.

[0101] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 850 from various process tool sensors. Signals for controlling the process can be output at analog and digital output connections of the process tool 800. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms can be used with data from these sensors to maintain process conditions.

[0102] The system controller 850 can provide program instructions for carrying out the deposition processes described above. The program instructions can control various process parameters such as DC power levels, RF bias power levels, pressure, temperature, etc. The instructions can control the parameters for operating the deposition of a film stack according to various embodiments described herein.

[0103] System controller 850 typically includes one or more memory devices and one or more processors configured to execute instructions such that the apparatus performs methods according to the disclosed embodiments. Machine-readable media containing instructions for controlling process operations according to the disclosed embodiments may be coupled to system controller 850.

[0104] In some embodiments, the system controller 850 is part of a system, such as may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (e.g., wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operation before, during, and after semiconductor wafer or substrate processing. Such electronics may be referred to as a "controller" and may control various components or subcomponents of one or more systems. The system controller 850 may be programmed to control any of the processes disclosed herein, depending on the processing conditions and / or system type. Such processes may include process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer transfer to and from the tool, and wafer transfer to and from other transfer tools and / or load locks connected or interfaced with the particular system.

[0105] Broadly, system controller 850 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers, that execute program instructions (e.g., software). Program instructions may be instructions communicated to system controller 850 in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to implement one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0106] In some embodiments, the system controller 850 may be part of, coupled to, or a combination of a computer integrated with, coupled to, or otherwise networked to the system. For example, the system controller 850 may be in the “cloud” or all or part of a fab host computer system. This allows for remote access to wafer processing. The computer may provide remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set processing steps following a current process, or initiate a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 850 receives instructions in the form of data. Such data may identify parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that system controller 850 is configured to interface with or control. Thus, as described above, system controller 850 may be distributed, for example, by including one or more individual controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein).An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0107] Exemplary systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a tracking chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0108] As described above, depending on the process step or steps being performed by the tool, system controller 850 may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports in a semiconductor fabrication factory.

[0109] conclusion In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with specific embodiments, it will be understood that they are not intended to limit the disclosed embodiments.

[0110] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Therefore, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details set forth herein. The present disclosure includes the following application examples: [Application example 1] 1. A method for forming an isolation channel layer, comprising: (i) etching one or more features through a mold stack disposed over a semiconductor substrate, the mold stack comprising a plurality of film stacks, the plurality of film stacks being vertically stacked, adjacent film stacks being separated by a dielectric layer, each film stack comprising a source region, a drain region, and an oxide layer between the source region and the drain region; (ii) selectively etching at least a portion of the oxide layer in each of the film stacks to form recessed regions in each of the film stacks; (iii) conformally depositing a channel material along sidewalls of the one or more features; (iv) depositing a sacrificial liner covering the channel material along the sidewalls of the one or more features; (v) etching the sacrificial liner covering the channel material in areas outside the recessed regions; (vi) selectively etching at least the channel material along the sidewalls of the one or more features outside the recessed regions to define an isolation channel layer between the source region and the drain region of each film stack; A method comprising: [Application example 2] The method according to Application Example 1, (vii) selectively etching at least the channel material outside the recessed area and then removing the sacrificial liner overlying the isolation channel layer. The method further comprises: [Application example 3] The method according to Application Example 2, The method, wherein the isolation channel layer has a topographical deviation of about 10% or less from a reference surface after removing the sacrificial liner. [Application example 4] The method according to Application Example 1, Each film stack further comprises a conductor layer adjacent to the drain region and sandwiched between the drain region and the dielectric layer, the dielectric layer serving to electrically isolate the adjacent film stacks from each other. [Application example 5] The method according to Application Example 1, The method, wherein etching the sacrificial liner in the area outside the recessed region comprises directionally etching the sacrificial liner with an etch contrast of at least 10:1 relative to the channel material. [Application Example 6] The method according to Application Example 5, a protrusion from the sidewall of the one or more features acts as a mask to protect the recessed area during the directional etching of the sacrificial liner. [Application Example 7] The method according to Application Example 1, The method, wherein selectively etching at least the channel material in the area outside the recessed region comprises isotropically etching the channel material with an etch contrast of at least 25:1 relative to the sacrificial liner. [Application Example 8] The method according to Application Example 7, The method wherein isotropically etching the channel material is performed with an etch contrast of at least 10:1 relative to the dielectric layer. [Application Example 9] The method according to Application Example 1, The method, wherein the channel material comprises a semiconductor material and the sacrificial liner comprises a carbide material and / or an oxide material. [Application Example 10] The method according to Application Example 9, 1. The method of claim 1, wherein the semiconductor material comprises polysilicon, and the sacrificial liner comprises a first layer of oxide disposed on the semiconductor material and a second layer of carbide disposed on the first layer of oxide. [Application Example 11] The method according to any one of Application Examples 1 to 10, The method, wherein the sacrificial liner is conformally deposited on the channel material along the sidewalls of the one or more features. [Application Example 12] The method according to any one of Application Examples 1 to 10, The method, wherein the plurality of membrane stacks comprises more than 20 repeating membrane stacks. [Application Example 13] The method according to any one of Application Examples 1 to 10, wherein the sidewalls of the one or more features in the area outside the recessed region are substantially free of channel material after selectively etching at least the channel material. [Application Example 14] The method according to any one of Application Examples 1 to 10, The method wherein the isolation channel layer has an average thickness of about 5 nm to about 20 nm. [Application Example 15] (i) a plurality of three-terminal memory cells, each memory cell comprising: a source terminal connected to the source region; a drain terminal connected to the drain region; an oxide layer between the source and drain regions; an isolation channel layer on the surface of the oxide layer, the isolation channel layer providing an interconnection between the source region and the drain region; Gate terminal, and a memory film between the isolation channel layer and the gate terminal; a plurality of three-terminal memory cells each including (ii) a plurality of dielectric layers each separating adjacent three-terminal memory cells, the plurality of three-terminal memory cells comprising a plurality of vertically stacked dielectric layers; A memory device comprising: [Application Example 16] The device according to Application Example 15, The device, wherein the plurality of three-terminal memory cells comprises more than 20 three-terminal memory cells. [Application Example 17] The device according to Application Example 15, the isolation channel layer comprises polysilicon. [Application Example 18] The device according to Application Example 15, The device, wherein the isolation channel layer of a first memory cell is insulated from a second memory cell adjacent to the first memory cell. [Application Example 19] The device according to any one of Application Examples 15 to 18, The device, wherein the memory film comprises a ferroelectric layer, a charge trapping layer, or a spin-orbit torque memory stack. [Application Example 20] The device according to any one of Application Examples 15 to 18, the isolation channel layer is positioned in a recessed region of the oxide layer, the recessed region being defined by a portion of the oxide layer that is laterally recessed relative to sidewalls of the source region, the drain region, and one or more of the plurality of dielectric layers.

Claims

1. 1. A method for forming an isolation channel layer, comprising: (i) etching one or more features through a mold stack disposed on a semiconductor substrate, the mold stack comprising a plurality of film stacks, the plurality of film stacks being vertically stacked, adjacent film stacks being separated by a dielectric layer, each film stack comprising a source region, a drain region, and an oxide layer between the source region and the drain region; (ii) selectively etching at least a portion of the oxide layer in each of the film stacks to form recessed regions in each of the film stacks; (iii) conformally depositing a channel material along sidewalls of the one or more features; (iv) depositing a sacrificial liner covering the channel material along the sidewalls of the one or more features; (v) etching the sacrificial liner covering the channel material in areas outside the recessed regions; (vi) selectively etching at least the channel material along the sidewalls of the one or more features outside the recessed regions to define an isolation channel layer between the source and drain regions of each film stack; A method comprising:

2. 10. The method of claim 1, (vii) selectively etching at least the channel material outside the recessed areas and then removing the sacrificial liner overlying the isolation channel layer. The method further comprises:

3. 3. The method of claim 2, The method, wherein the isolation channel layer has a topographical deviation of about 10% or less from a reference surface after removing the sacrificial liner.

4. 10. The method of claim 1, Each film stack further comprises a conductor layer adjacent to the drain region and sandwiched between the drain region and the dielectric layer, the dielectric layer serving to electrically isolate the adjacent film stacks from each other.

5. 10. The method of claim 1, The method, wherein etching the sacrificial liner in the area outside the recessed region comprises directionally etching the sacrificial liner with an etch contrast of at least 10:1 relative to the channel material.

6. 6. The method of claim 5, A method wherein protrusions from the sidewalls of the one or more features act as a mask to protect the recessed areas during the directional etching of the sacrificial liner.

7. 10. The method of claim 1, The method, wherein selectively etching at least the channel material in the area outside the recessed region comprises isotropically etching the channel material with an etch contrast of at least 25:1 relative to the sacrificial liner.

8. 8. The method of claim 7, The method wherein isotropically etching the channel material is performed with an etch contrast of at least 10:1 relative to the dielectric layer.

9. 10. The method of claim 1, The method, wherein the channel material comprises a semiconductor material and the sacrificial liner comprises a carbide material and / or an oxide material.

10. 10. The method of claim 9, 1. The method of claim 1, wherein the semiconductor material comprises polysilicon, and the sacrificial liner comprises a first layer of oxide disposed on the semiconductor material and a second layer of carbide disposed on the first layer of oxide.

11. The method according to any one of claims 1 to 10, The method, wherein the sacrificial liner is conformally deposited on the channel material along the sidewalls of the one or more features.

12. The method according to any one of claims 1 to 10, The method, wherein the plurality of membrane stacks comprises more than 20 repeating membrane stacks.

13. The method according to any one of claims 1 to 10, wherein the sidewalls of the one or more features in the area outside the recessed region are substantially free of channel material after selectively etching at least the channel material.

14. The method according to any one of claims 1 to 10, The method, wherein the average thickness of the isolation channel layer is from about 5 nm to about 20 nm.

15. (i) a plurality of three-terminal memory cells, each memory cell comprising: a source terminal connected to the source region; a drain terminal connected to the drain region; an oxide layer between the source and drain regions; an isolation channel layer on a surface of the oxide layer and providing an interconnection between the source region and the drain region, the isolation channel layer being positioned in a recessed region of the oxide layer; a gate terminal defined in a region between the source terminal and the drain terminal; and a memory film between the isolation channel layer and the gate terminal; a plurality of three-terminal memory cells each including (ii) a plurality of dielectric layers, each separating adjacent three-terminal memory cells, wherein each of the plurality of three-terminal memory cells and each of the plurality of dielectric layers are stacked alternately in a vertical direction; A memory device comprising:

16. 16. The device of claim 15, The device, wherein the plurality of three-terminal memory cells comprises more than 20 three-terminal memory cells.

17. 16. The device of claim 15, the isolation channel layer comprises polysilicon.

18. 16. The device of claim 15, A device wherein the isolation channel layer of a first memory cell is insulated from a second memory cell adjacent to the first memory cell.

19. A device according to any one of claims 15 to 18, The device, wherein the memory film comprises a ferroelectric layer, a charge trapping layer, or a spin-orbit torque memory stack.

20. A device according to any one of claims 15 to 18, the recessed region is defined by a portion of the oxide layer that is laterally recessed relative to sidewalls of the source region, the drain region, and one or more of the plurality of dielectric layers.

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