Advanced quantum processing systems and methods

Abstract

Quantum processing devices and methods are disclosed for shuttling a qubit between a pair of processing elements. Specifically, the disclosed method for shuttling a qubit from a first processing element to a second processing element in a quantum processing device including multiple processing elements includes shuttling the qubit from the first processing element to the second processing element in a manner that applies an optimal bias configuration between the first processing element and the second processing element to minimize the time spent by the qubit at one or more state transition points between the first processing element and the second processing element.

Description

[Technical Field]

[0001] Aspects of the present disclosure are directed to advanced processing devices that include arrays of quantum processing elements, and in particular, but not exclusively, to architectures for performing quantum processing and transporting quantum information along arrays of quantum processing elements. [Background technology]

[0002] Development is underway to implement new types of advanced processing devices that can perform powerful computations using approaches different from current processors. Such advanced processing devices promise computational capabilities far greater than current devices. For example, quantum processors are being developed that can perform computations according to the rules of quantum mechanics. Approaches to realizing qubits, the basic computational unit of quantum processors, and devices to implement quantum architectures have been explored with varying levels of success.

[0003] The most promising route to large-scale universal quantum computing involves quantum error correction, a technique that enables the processing of quantum information using realistic noisy qubits, provided that the noise is below a fault-tolerant threshold.

[0004] Some quantum error correction methods, such as "surface codes," allow for error thresholds of up to 1%. Such error levels can be achieved using large numbers of qubits. However, to perform any meaningful operation with surface codes, large numbers of qubits are required, thus exceeding 10 8 There is a need for a platform that can be scaled up to a large number of qubits, such as 1. The need for such a large number of qubits creates challenges in the field of quantum computing for even the most promising platforms.

[0005] To build an "error-correcting quantum computer," scalable architectures are needed. Such architectures ideally incorporate large numbers of qubits located relatively close to each other and operating in concert to perform error-correcting quantum computations. In addition, these architectures must be manufacturable. Summary of the Invention

[0006] According to a first aspect of the present disclosure, there is provided a method for shuttling a quantum bit from a first processing element to a second processing element in a quantum processing device, the quantum processing device including a plurality of processing elements, the method including applying an optimal bias configuration between the first processing element and the second processing element to shuttle the quantum bit from the first processing element to the second processing element so as to minimize time spent by the quantum bit at one or more state transition points between the first processing element and the second processing element.

[0007] The quantum processing device may further include one or more transport elements located between the first processing element and the second processing element, and the method may further include applying an optimal bias configuration between pairs of the one or more transport elements so that the time spent by the quantum bit is minimized between the one or more transport elements and / or at one or more state transition points between the processing element and the transport element.

[0008] In some embodiments, each of the one or more transport elements has a quiescent bias point at which the coherence time of the qubit is maximum, and shuttling the qubit from the first processing element to the second processing element includes applying an optimal bias configuration to each of the one or more transport elements at the quiescent bias point so that the qubit is quiescent.

[0009] In some embodiments, the quiescent bias point is obtained by tuning the interplay of qubit spin-orbit effects and qubit tunneling effects.

[0010] The method may further include determining an accumulated phase rotation introduced to the qubit as it shuttles from the first processing element to the second processing element, and correcting the accumulated phase rotation introduced to the qubit once it is shuttled to the second processing element.

[0011] In yet other embodiments, the method further includes correcting phase errors or rotations in the qubits by performing dynamic decoupling while the qubits are being shuttled to the second processing element and / or once the qubits are shuttled to the second processing element.

[0012] In addition, the quantum processing device may also include one or more exchange-coupled gates disposed between pairs of processing elements or pairs of transport elements, which can be configured to control the time it takes for a quantum bit to transition from one element to another.

[0013] In another aspect of the present disclosure, a quantum processing device is provided that includes a plurality of quantum processing elements configured to operate as qubits and a plurality of quantum processing elements configured to transport quantum information between the qubits by shuttling electrons or holes, wherein the quantum processing elements are arranged in a predetermined geometric shape.

[0014] Each quantum processing element may be associated with a corresponding electrode, and in order to shuttle electrons or holes between a pair of adjacent processing elements, an optimal bias voltage is applied between the pair of corresponding electrodes to shuttle the quantum bit between the pair of adjacent processing elements in a manner that minimizes the time spent by the electron or hole at a state transition point between the pair of processing elements.

[0015] In some embodiments, one or more exchange-coupled gates may be located between pairs of quantum processing elements, the one or more exchange-coupled gates configured to reduce the potential barrier between the pair of adjacent processing elements when shuttling to minimize the time spent by electrons or holes at a state transition point.

[0016] When a qubit is idle (i.e., not being shuttled), the voltage applied to the electrode of the corresponding processing element is at the quiescent bias point where the qubit's coherence time is highest (typically just below the voltage bias required to transfer the qubit from one processing element to another).

[0017] Shutting a qubit between adjacent processing elements involves applying an optimal bias voltage to each of a pair of quantum processing elements such that the electron or hole is at rest at the quiescent bias point.

[0018] In some embodiments, the quiescent bias point is obtained by tuning the interplay of qubit spin-orbit effects and qubit tunneling effects.

[0019] In some embodiments, the quantum processing device may be a silicon-based device, and in some particular examples, it may be a silicon MOS device. In such systems, the processing elements are quantum dots with electrons or holes encoding qubits. Furthermore, the processing elements and / or transport elements may form an N X M matrix, where N and M are integer values.

[0020] In a third aspect of the present disclosure, there is provided a method for shuttling a qubit from a first processing element to a second processing element in a quantum processing device, the quantum processing device including a plurality of processing elements, each of the processing elements having a quiescent bias point at which a coherence time of the qubit is maximized, and shuttling the qubit from the first processing element to the second processing element includes applying an optimal bias configuration between the first processing element and the second processing element such that the qubit is quiescent on each of one or more transport elements at the quiescent bias point.

[0021] In some embodiments, the optimal bias configuration allows the qubit to shuttle between the first and second processing elements in less than 60 nanoseconds. [Brief explanation of the drawings]

[0022] [Figure 1A] Schematic of a large-scale quantum computing device. [Figure 1B] 1 is a schematic diagram of a top view of a scalable quantum processing device, in accordance with some embodiments of the present disclosure. [Figure 2A] 1 shows a schematic diagram of a pair of quantum dots according to some embodiments of the present disclosure. [Figure 2B] 1 shows a schematic diagram of a pair of quantum dots according to some embodiments of the present disclosure. [Figure 3] 1 is a flowchart illustrating an exemplary method for calibrating a scalable quantum processing device according to some embodiments of the present disclosure. [Figure 4] 10 is a stability diagram illustrating the detuning axis according to an embodiment of the present disclosure. [Figure 5] Graph illustrating qubit frequency as a function of detuning axis. [Figure 6] Graph illustrating coherence time as a function of detuning axis. [Figure 7] 1 is a flowchart illustrating an exemplary method for performing a two-qubit operation using qubits that are remotely located relative to a processing element. [Figure 8] Pulse schematic illustrating ramp rate experiments. [Figure 9] 10 is a graph illustrating qubit coherence as a function of ramp time. [Figure 10] 10 is a graph illustrating qubit fidelity as a function of ramp time. [Figure 11] 1A and 1B are pulse schematics illustrating gradually applied ESR pulses and the corresponding states of the detuning axis and qubit states. [Figure 12] 1A-1C are pulse schematics illustrating spectroscopic experiments, according to some embodiments of the present disclosure. [Figure 13] Schematic of the quantum state tomography experiment. [Figure 14] Diagram of the Bloch sphere of the reconstructed spin states. [Figure 15] Schematic showing a pulse sequence with dynamic decoupling for fidelity characterization. [Figure 16] Graph showing echo fringes along with fitting results. [Figure 17] Graph showing normalized echo amplitude as a function of ramp transfer number. [Figure 18] Schematic diagram showing the pulse schematic used to measure the ramp time dependence. [Figure 19] Graph showing pure transfer error as a function of ramp time. DETAILED DESCRIPTION OF THE INVENTION

[0023] While the invention is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the drawings and detailed description are not intended to limit the invention to the particular forms disclosed. The intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0024] There are many engineering challenges associated with scalable quantum computing architectures. One challenge is associated with maintaining the coherence of static or idle qubits (i.e., stored qubits of information). Qubit coherence typically decreases over time due to various factors such as charge noise and electrical noise.

[0025] Another issue for scalable quantum computing architectures is the design constraints associated with nearest-neighbor interactions in quantum information processing codes. Typically, qubits can only interact with their nearest neighbors. The farther apart qubits are, the lower the coupling between them. For this reason, most scalable silicon-based quantum computing architectures require qubits to be closely packed (typically less than 50 nanometers from each other). Such closely spaced qubits often introduce other problems. Because each qubit requires a control electrode and charge-sensing element (which are also closely packed), crosstalk between qubits is common. This means that signals provided to control one qubit can unintentionally affect neighboring qubits.

[0026] Yet another problem associated with scalable quantum computing architectures relates to the transportation of qubits. In quantum processing, qubits often need to interact with other qubits that are not their nearest neighbors. In such cases, the qubit needs to be transported to a location close to the other qubits (so that they can interact), and then the qubit needs to be sent back to its original location. It is widely understood that transporting or shuttling qubits over such long distances will cause decoherence within the qubits, which is undesirable.

[0027] Aspects of the present disclosure attempt to address one or more of these challenges. In particular embodiments, the systems and methods described herein extend the coherence of a single qubit by storing it in a configuration with minimal impact from charge and electrical noise. To this end, the inventors of the present disclosure have identified an optimal bias configuration for the processing element that renders the qubit's precession frequency insensitive to small changes in bias voltage, minimizes the effect of charge and electrical noise on the decoherence of the qubit state, and results in higher fidelity. Specifically, the optimal bias configuration for a qubit to rest at a particular location is determined to be adjacent to and just before the bias voltage required to transport the qubit from one location to another. This optimal bias configuration is referred to in this disclosure as the "rest bias point," and the bias voltage at which the qubit shuttles from one location to another is referred to in this disclosure as the "transition bias" and "state transition point."

[0028] In yet another aspect of the present disclosure, methods and systems described herein enable long-distance communication between qubits by transporting / shutting qubits from one location to another with minimal loss of coherence. Specifically, the inventors of the present disclosure have determined that decoherence during transport / shuttle of qubits from one location to another can be minimized by ensuring that the time spent by the qubit in a transition bias configuration or state transition point configuration is kept to a minimum. Specifically, the inventors have determined that shortening the detuning ramp time for a qubit to transition from one location to another minimizes decoherence and achieves high-fidelity shuttle of the qubit. By ensuring that the qubit is stationary at a stationary bias point site and transitions from one site to another with a short detuning ramp time, aspects of the present disclosure enable qubits to be transported over long distances with minimal loss of coherence.

[0029] In other aspects of the present disclosure, the described systems and methods help relax design constraints associated with nearest-neighbor interactions in quantum information processing codes, allowing qubits to be further apart while still allowing the qubits to interact with each other. Because qubits can be coherently shuttled from one site to another using the techniques described above, it is possible to have sparsely spaced processing elements in scalable quantum processing devices with distributed transport elements. The transport elements can be used to transport qubits from one processing element to another. Such sparse spacing of processing elements helps reduce crosstalk in the system while allowing interactions between far-away qubits.

[0030] It will be understood that the quiescent bias points and state transition points may vary for different qubits within the same scalable quantum processing architecture and will most likely differ from the quiescent bias points and state transition points of other scalable quantum processing architectures. However, such bias values ​​do not change over time. Thus, a scalable quantum processing device may be calibrated sporadically or periodically to determine the quiescent bias points and state transition points of each pair of sites within the scalable quantum processing device. These determined points may then be used whenever the scalable quantum processing device is needed to perform a computation.

[0031] In addition to the above, the inventors of the present disclosure have determined that the phase error caused by transporting / shutting a qubit from one site to another not only remains the same each time the qubit is transported / shuttle from the first site to the second site, but is also correctable.

[0032] These and other aspects of the disclosure are now described in detail in the following sections.

[0033] Examples of scalable quantum processing devices In particular embodiments, aspects of the present disclosure may be implemented in a modular quantum processing device, such as that shown in FIG. 1A. Specifically, FIG. 1A shows multiple qubit arrays or quantum processing modules 102 (each containing multiple processing elements or qubits 104) coupled to each other via long-range qubit couplers 106. Furthermore, local connection electronics 108 distribute these quantum processing modules 102. In FIG. 1A, the local connection / classical electronics are located in the qubit plane. Alternatively, such electronics modules 108 may be located on a separate chip and connected to the qubit modules 102 via flip-chip or other similar techniques. The classical electronics may include analog-to-digital converters, digital-to-analog converters, and vector modulation, such that a minimal number of control lines are required to interface with the outside world. An example of such an architecture is described with reference to Figure 4 in the npi Quantum Information Article, LMK Vandersypen et al, "Interfacing spin qubits in quantum dots and donors—hot, dense, and coherent," which is incorporated herein by reference.

[0034] Furthermore, in some embodiments, the quantum processing device (which may be one of modules 102 shown in FIG. 1A) on which the methods of the present disclosure are performed includes a plurality of processing elements interspersed with a plurality of transport elements. The processing elements and transport elements may, in some embodiments, be arranged in an N X M matrix (N and M are integer values).

[0035] 1B shows a simplified top view of such a quantum processing device 102. Processing elements 110 are depicted as solid dots in FIG. 1B, and transport elements 112 are depicted as unfilled dots. The placement of processing elements 110 and transport elements 112 can be such that processing elements 110 are located at a sufficient distance from each other to prevent crosstalk (which frequently occurs in known architectures in which quantum processing devices include processing elements but not transport elements).

[0036] In some embodiments, processing element 110 includes a silicon / dielectric interface and an electrode arrangement suitable for confining one or more electrons or holes in the silicon near the interface to form one or more quantum dots operable as one or more quantum bits. Transport element 112 is configured similarly to a quantum dot, except that it does not operate as a quantum bit. Instead, the quantum bits come to rest in transport element 112 via tunneling from an adjacent processing or transport element.

[0037] The quantum processing device 102 also includes a plurality of control elements (not shown) arranged around the processing elements. The control elements include switches that interact with the electrodes to enable quantum operations. Multiple control lines are connected to the control elements, allowing simultaneous operation of multiple processing elements.

[0038] 2 shows a simplified diagram of a quantum processing device / module 200 (including processing elements 110 and transport elements 112) as shown in FIG. 1B. FIG. 2A is a top view, and FIG. 2B is a vertical cross-sectional view. In the described embodiment, quantum processing device 200 includes a silicon substrate 202 and a dielectric layer 204, which in this example is silicon dioxide. Isotopically enriched silicon 28 Si can be used, which can be an epitaxial layer grown on a conventional silicon substrate.

[0039] Quantum processing device 200 may include spin qubits, i.e., qubits encoded with the spin of electrons or holes. Implementation of spin qubits in silicon / silicon dioxide systems increases spin coherence compared to most compound semiconductors due to reduced hyperfine coupling of the qubit to nuclear spins in the host crystal. Typically, electrostatic fields are used to confine a small number of electrons within a quantum dot to generate the qubit.

[0040] To that end, quantum processing device 200 includes a first electrode 206 operable to form quantum dots 210 proximate an interface 205 between a silicon substrate 202 and a dielectric layer 204. Figure 2B illustrates a region 210 in which either electrons or holes may be confined. With a sufficiently positive voltage applied to electrode 206, electrons are confined within region 210 and coupled to dielectric layer 204. Meanwhile, with a sufficiently negative voltage applied to electrode 206, holes are confined within region 210 and respectively adjacent to dielectric layer 204.

[0041] For example, a single electron can be confined to region 210, thus forming a confined quantum dot. A single quantum bit can be encoded on the spin of an isolated electron. Alternatively, a quantum bit can be encoded using the spin of an electron or hole within a single quantum dot. Additional electrode structures can also be used to aid in quantum dot confinement. In alternative embodiments, a single quantum bit can be encoded on the spin of one or more electrons or holes in each of one or more quantum dots. Additional elements can also be introduced at the interface to promote electron confinement, such as doped or dielectric regions. Additionally, the overall concentration of electrons at the interface can be modified using insulating global electrodes above or below the interface.

[0042] A second electrode 207 associated with transport element 112 is operable to allow the processing element qubit to be transported from region 210 to region 211 (typically via tunneling). The potential difference (or voltage bias) between first electrode 206 and second electrode 207 determines whether the qubit remains in region 210 or moves to region 211. As explained above, the voltage bias required to shuttle a qubit from processing element 110 to transport element 112 is called the transition bias or “state transition point.” If the potential difference applied between electrodes 206 and 207 is positive and sufficient to cause the qubit to tunnel, the qubit formed under electrode 206 shuttles to region 211 under electrode 207. Alternatively, if the potential difference applied between electrodes 206 and 207 is negative and sufficient to cause the qubit to tunnel, the qubit under region 211 moves back to region 210. The value of the transition bias required to tunnel a qubit from one quantum dot to another depends on the potential barrier between the two quantum dots, the distance between the two quantum dots, etc.

[0043] In addition to processing element 110 and transport element 112, quantum processing device 200 may also include a charge sensing element that reads out the state of a qubit formed below electrode 206 when the qubit is resting below electrode 206, tunneling into region 211, or resting below electrode 207. In the exemplary portion of a quantum processing device shown in FIG. 2 , such a charge sensing element is depicted as a single-electron transistor (SET) 208 adjacent to processing element 110 and transport element 112. In other embodiments, various charge sensing elements, such as quantum point contact (QPC) sensors, tunnel junction sensors, or gate-based distributed sensors, may be used on the same plane as the processing element and transport element, or on a different plane than the processing element and transport element, without departing from the scope of the present disclosure.

[0044] In addition, quantum processing device 200 may also include control elements (not shown) for controlling the spin of the qubits. The control elements emit magnetic microwave signals, also known as electron spin resonance or ESR signals, and RF signals, also known as nuclear magnetic resonance or NMR signals, for controlling the spin of the qubits. In exemplary systems, the control elements may be transmission lines, global control elements, either as part of the architecture shown in Figures 1 and / or 2, or on a different plane or chip from the processing / transport elements.

[0045] In some embodiments, quantum processing device 200 may also include exchange-coupling gates (not shown), also referred to as J-gates, between pairs of processing elements, pairs of transport elements, or pairs of processing and transport elements. Exchange-coupling gates are typically configured to adjust the exchange coupling between two qubit sites, specifically to reduce or increase the potential barrier between adjacent qubit sites, thereby decreasing or increasing the time it takes for an electron or hole to transfer from one qubit site to the other.

[0046] In the scalable quantum computing architectures described herein, multiple qubit devices configured according to the principles discussed above and illustrated in Figures 1B and 2, or configured as a modular interconnected structure as shown in Figure 1A, operate together to perform error-correcting quantum computations.

[0047] Method for calibrating a quantum processing device As discussed above, to enable coherent quiescence and shuttlering, the systems and methods of the present disclosure calibrate quantum processing devices to identify the parameters necessary to store and shuttle qubits with minimal coherence loss.

[0048] 3 illustrates an exemplary method 300 for doing so, that is, for identifying parameters for storing and shuttling a qubit between two locations with minimal coherence. Method 300 is described with respect to a pair of quantum dots, e.g., a processing element 110 quantum dot and a transport element 112 quantum dot. However, it will be understood that the method can be repeated for all other pairs of nearest-neighbor quantum dots in the quantum processing device, including between other adjacent processing elements 110 and transport elements 112, between adjacent transport elements 112, and between adjacent processing elements 110.

[0049] The method begins in step 302, where a stationary point between a pair of adjacent quantum dots is determined, for example, between quantum dot 210 of processing element 110 and quantum dot 212 of transport element 112. In certain embodiments, this is determined by first determining the transition point between the two quantum dots.

[0050] As explained above to transport electrons or holes from one quantum dot to another, e.g., from region 210 to region 211, a voltage difference is applied to the two electrodes 206 and 207 such that electrons or holes confined under one electrode move by tunneling to the region under the other electrode. Regions 210 and 211 are referred to in this disclosure as quantum dot site A and quantum dot site B, respectively.

[0051] In one example, the difference between the gate voltage of electrode 207 and the transition voltage between the dots is defined as the detuning ε. As the detuning value changes (i.e., as the gate voltage of electrode 207 changes), the energy difference between the spin states localized at each site changes. In another example, the detuning axis can be defined as and swept through the combination of the gate voltages of electrodes 206 and 207 (and even the J-gates, if used).

[0052] FIG. 4 shows a stability diagram 400 illustrating an example of such detuning. The x-axis represents the gate voltage applied to Site B, and the y-axis represents the gate voltage applied to Site A, 207 and 206, respectively. Line 402 defines the detuning axis used for qubit transfer. A charge-sensing element (e.g., SET 208) can be used to a) sense the charge at Site A and Site B, b) determine whether the qubit is at rest at Site A or Site B, c) determine when the qubit shuttles between the two sites, and d) determine the transition point. For example, when the qubit tunnels from Site A to Site B, a blip is seen in the SET current, and the charge state of Site A changes from full to empty. Such a blip is interpreted as the qubit shuttles from Site A to Site B.

[0053] In one example, to determine the transition point, the detuning value ε is increased and the corresponding charge at site A is sensed. The point on the detuning axis where a blip in sensed charge is observed is determined to be the transition point, which is defined as ε=0 and is indicated by dot 404 in FIG. 4.

[0054] Once the transition point is determined, the rest point can be determined. As explained above, the rest point is the point on the detuning axis where there is minimal impact from charge noise and electrical noise on the qubit. In one embodiment, this rest point can be determined based on determining the precession frequency and ESR frequency of the qubit as a function of the detuning axis 402. For example, the detuning axis value can be increased and the qubit frequency can be detected.

[0055] FIG. 5 shows a graph 500 illustrating the precession frequency and ESR frequency of a qubit (along the y-axis) as a function of the detuning axis (x-axis). As can be seen in graph 500, as the detuning value increases toward ε=0, i.e., the transition point, the qubit's precession frequency and ESR frequency steadily increase and then drop sharply when the detuning axis is ε=0, i.e., when the qubit shuttles to site B. The detuning value at which an abrupt change in the precession frequency and ESR frequency is detected is determined to be the transition point. Furthermore, the detuning value at which the qubit frequency becomes insensitive to charge noise-induced detuning variations as a result of competition between the Stark shift and tunneling hybridization is identified as the stationary point for that site.

[0056] In another example, the rest point can be determined by measuring the coherence time of a qubit at different positions along the detuning axis (e.g., using a Hahn echo experiment). The point along the detuning axis where the qubit's coherence time is greatest is determined to be the rest point for that site. Figure 6 shows a graph 600 illustrating this. As can be seen, based on a particular experiment and a particular site, it was determined that the qubit's coherence time at that site was greatest (approximately 300 microseconds) at a detuning value of approximately -0.5 mV, which is determined to be the rest point for that site.

[0057] Returning to method 300, once the stationary points have been determined for each of the two sites, in step 304 a determination of the phase rotation that occurs as the qubit shuttles between site A and site B is made.

[0058] Generally speaking, when a qubit shuttles, the transported electrons or holes experience electric and magnetic disturbances that affect the spin and phase of the electrons / holes, causing decoherence within the corresponding qubit.

[0059] Furthermore, because electrons or holes are trapped under the dielectric layer 204, which may have microscopic variations in structure, the qubits in one quantum dot may behave differently from the qubits in another quantum dot.

[0060] Because of these known challenges, it was widely believed that transporting a qubit from one quantum dot to another would cause severe spin and phase decoherence within the qubit. However, the inventors of the present disclosure have studied the effects of such errors on the movement of a qubit from one site (e.g., a processing element 110 quantum dot) to another site (e.g., a transport element 112 quantum dot) and have determined that errors caused by such qubit movements (when performed rapidly and between stationary points) not only remain the same over time, but are also correctable. Specifically, it was determined that when transported using a determined stationary point and a short ramp time, the qubit suffered only small polarization errors, but could in some cases suffer phase errors.

[0061] In one embodiment, effects on the qubit caused by shuttling between two sites (such as rotation, decoherence, depolarization, and leakage) can be determined using quantum state tomography of the qubit spin after transfer. Effects on the qubit phase caused by shuttling between two sites (such as phase rotation and dephasing) can also be determined by measuring the Ramsey fringes of the qubit spin after transfer. The potentially small effects of the shuttle process can be amplified by repeating the process. In one example, a qubit can be initialized with a particular spin at site A (and preferably at a determined rest spot) and then shuttled to site B and back multiple times. Each time the qubit is shuttled to site B, the qubit's spin phase can be determined by projecting the qubit along multiple axes. In addition, the phase of the qubit spin can also be determined after a predetermined rest time without shuttling the qubit back and forth. This can be used to determine the phase rotation caused by shuttling the qubit between a site A and site B pair.

[0062] Once the rest points for each site have been determined, and the transition points and phase rotations caused by shuttling the qubit between the two sites have been determined, method 300 ends.

[0063] Subsequently, when quantum processing device 100 is utilized for quantum computing and a two-qubit operation needs to be performed between qubits located on two distant processing elements, one of the qubits can be shuttled from its original location to the location of the other qubit, and then shuttled back once the two-qubit operation has been performed.

[0064] 7 illustrates an exemplary method 700 for performing a two-qubit operation using qubits located on two processing elements 110 that are spaced apart from one another. In the exemplary method described here, it is assumed that the two processing elements 110 are separated by five transport element 112 quantum dots. However, it will be understood that this is merely an example, and that in implementations, the number of transport elements 112 through which a qubit must shuttle may vary.

[0065] The method begins at step 702, where the qubit spin in a first processing element is maintained at a quiescent point for that processing element 110. The quiescent point may be calculated using method 300.

[0066] In step 704, the voltage bias between the first processing element 110 and its adjacent transport element 112 is ramped to the quiescent point of the adjacent transport element such that the qubit tunnels from the first processing element 110 to the adjacent transport element 112. In particular embodiments, the ramp time for this is small enough (e.g., about 50 ns) to minimize the time spent by the qubit at the state transition point. In other embodiments, the ramp time can be further reduced to the nanosecond or sub-nanosecond scale to further minimize the time spent by the qubit at the state transition point.

[0067] In step 706, it is determined whether more shuttles are needed, for example because one or more transport elements 112 exist between the current transport element 112 and the second processing element 110. If it is determined that more shuttles are needed, method step 704 is repeated.

[0068] However, with each subsequent iteration of step 704, the voltage bias between the current transport element 112 and the next transport element 112 is ramped up to the rest point of the next transport element so that the quantum bit tunnels from the current transport element to the next transport element.

[0069] This process is repeated until, in step 706, it is determined that no more shuttles are required. The method then proceeds to step 708, where a given two-bit operation is performed between the shuttled qubit and the qubit that is stationary at the second processing element. In particular embodiments, if any phase rotation occurs during the shuttle from the first processing element to the second processing element, an accumulated phase rotation is calculated (e.g., based on the known phase rotation of each intermediate shuttle), and the accumulated phase rotation is corrected before the qubit operation is performed.

[0070] Once the operation is complete, the shuttle qubit can be shuttled back to the first processing element using a process similar to that described with reference to steps 704 and 706. Once the qubit returns to the first processing element, it is again corrected for the accumulated phase rotation determined during the return shuttle.

[0071] Experimental results The experiments were carried out in a system similar to that shown in FIG.

[0072] Experiment 1: Ramp rate dependence The ramp time is the time it takes to detune the bias voltage between Site A and Site B to switch from the quiescent bias point at Site A to the quiescent bias point at Site B.

[0073] The inventors of the present disclosure have determined that faster ramp rates exhibited the greatest qubit coherence and qubit fidelity when shuttling between Site A and Site B.

[0074] Figure 8 shows the pulse schematic 800 for this experiment. Specifically, the qubit superposition state is prepared by applying a half-π ESR pulse to the qubit, followed by multiple ramp and projected ESR pulses to shuttle the qubit from site A to site B.

[0075] This was performed multiple times with various ramp times. The coherence and fidelity of the qubit were then measured for various ramp times. Figure 9 shows a graph 900 showing the measured coherence (y-axis) as a function of ramp time (x-axis) for a single return pass. As can be seen in Figure 9, coherence is negatively correlated with ramp time, i.e., as ramp time increases, the coherence of the qubit decreases.

[0076] Figure 10 shows a graph 1000 illustrating qubit fidelity as a function of ramp time. From Figure 10, it can be seen that fidelity is greatest for shorter ramp times (approximately 0-80 ns) or faster ramp rates, and decreases as ramp time increases (e.g., above 100 ns in this example).

[0077] Experiment 2: Confirmation that the polarization of a qubit can be transported between sites with high fidelity. In any experiment to verify whether the qubit polarization can be transferred between sites with high fidelity, the main concern is that the energy levels of the opposing spins at site A and site B eventually coincide when the detuning axis value ε is equal to the Zeeman splitting, promoting the spin-flip tunneling process from site A to site B due to the spin-orbit field generated by the electron motion or the slight site difference in the spin quantization axis. To avoid the formation of such degeneracy points, the tunnel coupling can be enhanced above the Zeeman energy, for example, by using a J-gate. Another advantage of a large tunnel coupling is that it suppresses state leakage due to nonadiabatic tunneling and allows for faster ramp rates.

[0078] During the experiment, spins (initialized in either the down or up state) are repeatedly transferred between sites to amplify the polarization error to a measurable level. See Figure 11, which shows the pulse schematic used for the polarization transfer fidelity experiment. 368 ns long π pulses are cycled on (X) and off (I) to prepare both spin-up and spin-down initial states and measure the probability of finding the spin-up and spin-down states. The total time of the detuning ramp pulse section increases by 56 ns for each detuning ramp from one site to another. The detuning ramps are applied at 56 ns intervals to ensure that the spins are transferred to the other site.

[0079] In one example, the spin-dependent polarization transfer fidelity F_pol ↑ and F_pol ↓ , n consecutive transfer ramps, F_pol ↑,n (or 1-F_pol ↑,n ) and F_pol ↓,n (or 1-F_pol ↓,n ) is obtained from the probability of finding a spin state that is the same (or opposite) as the input state. Such a probability can be modeled as follows, treating the transfer-induced spin flip as a memoryless process:

number

[0080] Value F_pol ↑ and the value F_pol ↓ Once calculated, the polarization transfer fidelity for the spin-up and spin-down cases is given by

number

[0081] Experiment 3: Determine whether qubit coherence is maintained after shuttle We also used Ramsey-type spectroscopy techniques to determine whether qubit coherence is maintained after transferring the qubit between sites. Figure 12 shows the pulse schematic used for the spectroscopy experiment. At site A, spins prepared in the down state are first rotated halfway, then held for a rest time t until a second half-π pulse projects the phase to the polarization (up or down). dwell During this time, the phase accumulates during the inter-dot detuning pulse.

[0082] In this technique, the qubit spin is first prepared in an equal superposition of up and down states using a half-π ESR pulse (on resonance with the Larmor frequency at site A). The detuning ε is then performed on the nanosecond timescale from ε (in site A) to ε (either site A or site B), with t dwell The phase acquired during the detour to the detuning axis value ε2 is then projected onto the spin polarization by a second half-π ESR pulse.

[0083] From this experiment, the time t spent at detuning value ε2 dwell The oscillation of the final spin-up probability (Pup) as a function of the rest time t dwell We determine that the spin is visible regardless of ε2, suggesting that the entire process is phase coherent. Importantly, the qubit frequency begins to change rapidly for ε2>0 and saturates at approximately 30 MHz (consistent with the qubit resonance frequency difference between the sites seen in Figure 5), indicating that the electron is indeed fully transferred to site B in the saturation region (ε2>5 mV). This leads to the conclusion that spin can be transported to another site while maintaining phase coherence.

[0084] The Ramsey-type spectroscopy technique described above allows for precise measurement of the qubit precession frequency as a function of voltage (see Figure 5), allowing for the establishment of an understanding of qubit dispersion in tunnel-coupled quantum dot arrays.

[0085] Ramsey-type spectroscopy measures the energy splitting between instantaneous eigenstates, so we can ignore the contribution from the small spin-flip tunneling period and estimate the qubit precession frequency f using a simple four-step model as follows: Q can be predicted.

number

number

[0086] Experiment 4: The effect of tunneling on a qubit Quantum state tomography experiments are performed to determine the effect of tunneling on the qubit. Specifically, quantum state tomography is performed on the spin state with and without intersite transfer.

[0087] As shown schematically in Figure 13, the electron spin state before transfer

number

[0088] Ten types of pre-measurement controls (eight half-p rotations (controlled through the microwave phase f), identity (I), and π rotation (X) operations with varying phases) are used to measure the ground state for the next spin-up readout.

number

[0089] Additionally, interleaved measurements of spin-up probabilities with spins prepared in the down or up state improve the fidelity of state preparation and measurement.

number

number

[0090] The density matrix ρ of the spin states before and after the transfer is then reconstructed from the modified spin-up probability Pv using maximum likelihood estimation after 4,000 iterations for each of the 10 measurement basis states. Figure 14 shows a Bloch sphere diagram 1400 of the reconstructed spin states before and after the inter-site transfer process. Projections onto the xy, yz, and zx planes are also displayed. The primary net effect of the transfer process is a phase shift Δφ, which is rooted in the site dependence of the qubit frequency. The inset in Figure 14 shows the amplitude (height) and phase (color) of the density matrix elements of the individual states. For example, without transfer, states 1402 and 1404 have zero phase rotation, while state 1406 has a phase of -π / 2 to -π, and state 1408 has a phase of π / 2 to π. In the transfer, states 1410 and 1412 have a phase of zero, while state 1414 has a phase of 0 to -π / 2, and state 1416 has a phase of 0 to π / 2.

[0091] The density matrix of the spin state before or after the transfer, ρ, is restricted to be non-negative Hermitian and is expressed through the complex matrix L:

number

number

number

number

[0092] This further verifies that the inter-site qubit transfer can be viewed as a phase rotation gate, whose rotation angle △φ can be related to the ε-dependent qubit frequency (governed by the site-dependent Zeeman energy). We can compare the reconstructed spin state after the transfer with the ideal case (i.e., the ideal phase gate with the exact

number

number

number

[0093] To eliminate the phase error in a single transport process from the SPAM error, a sequence in which the transport ramp pulse is repeated many times between state preparation and measurement is employed. The remaining spin coherence can be evaluated using Ramsey interferometry. This protocol amplifies the phase error and leads to a decay of the phase oscillation amplitude with the number of transport cycles n. If the error probabilities of successive transports are uncorrelated, the amplitude decay is exponential.

[0094] Furthermore, to improve the transfer fidelity and investigate the noise spectrum, a dynamic decoupling step is introduced into the ramp sequence. The protocol shown in Figure 15 is adopted, where a decoupling π pulse is applied between two identical transfer ramp sequences. The echo fringes (see Figure 16) are measured by sweeping the angle φ of the projection axis, revealing that the fringe phase does not change with the transfer cycle, as expected. The amplitude decay of the echo fringes (see Figure 17) as a function of n ramp transfers is given by

number

[0095] This inefficiency of the dynamic decoupling pulse is due to the fact that the underlying error mechanism 29 This suggests that the noise is not dominated by either the spontaneous slow flip of Si nuclear spins or conventional charge noise with a 1 / f-type spectrum (e.g., quantum dot-level fluctuations).

[0096] Furthermore, we performed experiments by varying the ramp rate, as shown in Figure 18. In particular, the ramp time was varied while the rest time at a particular qubit site was fixed. Using this technique, we investigated the effect of the detuning ramp rate and verified that slower ramp rates degrade the transfer fidelity (see Figure 19). This rules out any nonadiabatic effects; the employed detuning ramp rate is already adiabatic relative to the tunneling energy gap and valley splitting. A theoretical framework based on nonadiabatic effects induced by 1 / f detuning noise correctly captures the qualitative ramp time dependence (the slower the ramp, the longer the time spent in the unfavorable inter-dot transition region, leading to noise-induced excitation). The experimental data are best explained by considering an overall shift in infidelity of approximately 1.5%, independent of the ramp rate. This may indicate the presence of some source of error per transfer that is not caused by the time spent in the inter-dot transition region.

[0097] The observed coherence loss of approximately 2% per transfer corresponds to spin transfer between approximately 50 sites before phase coherence decays to 1 / e, or a distance of approximately 2 mm (assuming 40 nm site spacing). If only spin polarization is required (e.g., for qubit readout), electrons can be transported across 2500 sites, or approximately 100 mm, before polarization decays to 1 / e for spin-up. While this precision in spin transfer asserts that coherent coupling between distant spins is achievable, fault-tolerant quantum computing architectures relying on qubit transfer require device settings tailored to enhance transfer fidelity. From the above experiments, the following desirable features can be identified: the ability to electrostatically control inter-dot tunneling rates to ensure adiabatic passage; reduced Larmor frequency differences at adjacent sites, achievable by controlling spin-orbit coupling or by operating at lower magnetic fields; and improved fabrication processes resulting in less charge noise.

[0098] Although the above systems and methods refer to silicon metal oxide semiconductor (MOS) quantum dots, it will be understood that the systems and methods of the present disclosure can also be applied to silicon-germanium systems.

[0099] 1 and 2 are merely examples of suitable scalable quantum computing architectures in which aspects of the present invention may be implemented, and it will be understood that the disclosed embodiments may be implemented in any other suitable architecture.

[0100] As used herein, the term "comprises" (and grammatical variations thereof) is used in the inclusive sense of "having" or "including" and not in the sense of "consisting only of."

[0101] It will be appreciated by those skilled in the art that many variations and / or modifications may be made to the invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

Claims

1. 1. A method for shuttling a qubit from a first processing element to a second processing element in a quantum processing device, the quantum processing device including a plurality of processing elements and a control member, the qubit being encoded with the spin of one or more electrons or holes forming one or more quantum dots, the method performed by the control member comprising: applying a bias configuration between the first processing element and the second processing element via corresponding electrodes connected to the control member to shuttle the quantum bit from the first processing element to the second processing element at a time faster than a quantum bit dephasing time.

2. 10. The method of claim 1, wherein the quantum processing device further comprises one or more transport elements located between the first processing element and the second processing element, the one or more transport elements comprising one or more quantum dots and not operating as qubits, the method further comprising applying a bias configuration between pairs of the one or more transport elements such that the time spent by the qubit at one or more state transition points between the one or more transport elements and / or between a processing element and a transport element is less than a dephasing time of the qubit.

3. 3. The method of claim 2 , wherein each of the one or more transport elements has a quiescent bias point at which a coherence time of the qubit is maximum, and wherein shuttling the qubit from the first processing element to the second processing element comprises applying the bias configuration to each of the one or more transport elements such that the qubit is quiescent at the quiescent bias point.

4. determining a cumulative phase rotation introduced to the qubit as it shuttles from the first processing element to the second processing element; correcting the accumulated phase rotation introduced into the qubit once it has been shuttled to the second processing element; The method of any one of claims 1 to 3, further comprising:

5. The method of claim 3 , wherein the quiescent bias point is obtained by tuning the interplay of qubit spin-orbit effects and qubit tunneling effects.

6. The method of any one of claims 1 to 5, wherein the quantum processing device is a silicon-based system.

7. The method of claim 6 , wherein the quantum processing device is a silicon MOS system.

8. The method of claim 7 , wherein the plurality of processing elements are quantum dots having electrons or holes that encode the qubits.

9. 9. The method of claim 1, further comprising correcting a phase error or rotation in the qubit by performing dynamic decoupling while the qubit is being shuttled to the second processing element and / or once the qubit is shuttled to the second processing element.

10. The method of any one of claims 1 to 9, wherein the plurality of processing elements form an N x M matrix, where N and M are integer values.

11. 11. The method of claim 1, wherein the quantum processing device further comprises one or more exchange-coupled gates disposed between pairs of processing elements or pairs of transport elements, the exchange-coupled gates being configurable to control the time it takes for the qubit to transition from one element to another.

12. 1. A quantum processing device, comprising: a plurality of quantum processing elements configured to operate as qubits, each qubit encoded with the spin of one or more electrons or holes forming one or more quantum dots; a plurality of quantum transport elements configured to transport quantum information between qubits by shuttling electrons or holes; Including, A quantum processing device, wherein each quantum processing element is associated with a corresponding electrode, and a bias voltage is applied between the corresponding electrodes to shuttle the electron or hole between a pair of adjacent quantum processing elements, thereby shuttling the quantum bit between the pair of adjacent quantum processing elements at a time faster than the quantum bit's phase relaxation time.

13. 13. The quantum processing device of claim 12, further comprising one or more exchange-coupled gates between pairs of quantum processing elements, the one or more exchange-coupled gates configured to reduce a potential barrier between the pair of adjacent quantum processing elements when shuttling to cause the time spent by the electrons or holes at a state transition point to be less than a dephasing time of the qubit.

14. 14. The quantum processing device of claim 12 or 13, wherein when a qubit is in an idle state, a voltage applied to a corresponding quantum processing element maintains the qubit at a quiescent bias point where the coherence time of the qubit is at a maximum.

15. 15. The quantum processing device of claim 14, wherein shuttling the qubit between adjacent quantum processing elements comprises applying the bias voltage such that the electron or hole is at rest in each of the pair of quantum processing elements at the quiescent bias point.

16. 16. The quantum processing device of claim 14 or 15, wherein the quiescent bias point is obtained by tuning the interplay of qubit spin-orbit effects and qubit tunneling effects.

17. 17. The quantum processing device of any one of claims 12 to 16, wherein the quantum processing device is a silicon-based system.

18. 20. The quantum processing device of claim 17, wherein the quantum processing device is a silicon MOS system.

19. 20. The quantum processing device of claim 18, wherein the qubit is a quantum dot.

20. 20. The quantum processing device of any one of claims 12 to 19, wherein the plurality of quantum processing elements form an N x M matrix, where N and M are integer values.

21. 1. A method for shuttling a qubit from a first processing element to a second processing element in a quantum processing device, the quantum processing device including a plurality of processing elements and a control member, the method being performed by the control member, each of the processing elements having a quiescent bias point at which a coherence time of the qubit is maximized, and shuttling the qubit from the first processing element to the second processing element includes applying a bias configuration between the first processing element and the second processing element via corresponding electrodes connected to the control member such that the qubit is quiescent on each of one or more transport elements at the quiescent bias point.

22. 22. The method of claim 21 , wherein the bias configuration causes the qubit to shuttle between the first processing element and the second processing element in less than 60 nanoseconds.

Images