Silicon nanostructures with porous silicon layers and porous silicon nanowires

Abstract

To provide a silicon nanostructure capable of inhibiting expansion and preventing electric loss by a structure comprising porous structure combined with a silicon nanowire and a structure comprising a silicon nanowire bonded to a porous layer.SOLUTION: Disclosed is a silicon nanostructure including a silicon porous layer 2 having a plurality of first pores 4, and one or more of a porous silicon nanowire 3 having a plurality of second pores 6 consecutively bonded to the silicon porous layer 2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a silicon nanostructure comprising a silicon porous layer and porous silicon nanowires. [Background technology]

[0002] Demand for lithium-ion secondary batteries is increasing year by year as an essential device for electric vehicles and the autonomous decentralization of information acquisition devices (IoT) for "Society 5.0." To achieve higher performance, it is necessary to use crystalline silicon, which has a large theoretical capacity, as the negative electrode material for lithium-ion batteries. However, alloying silicon with lithium increases the volume and causes peeling, which has hindered practical use.

[0003] It has been widely shown that nanostructuring is the key to solving this problem, but nanosilicon developed in the field of semiconductors has high performance, and although various structures and methods exist, it is difficult to apply conventional technology directly to anode materials.

[0004] Conventional nanostructures require conductive additives because they are in powder form, and there is a problem of reduced cycle characteristics due to differences in expansion coefficients with silicon. Furthermore, there is no bonding between the nanostructures, resulting in high resistance. On the other hand, there have been reports of porous amorphous silicon achieving high capacity and high cycle times, but the amorphous, film-like structure causes problems with electrical loss and volume loss (see Figures 12(a) and (b)).

[0005] In addition, research has been reported on forming silicides by combining them with carbon, oxygen, and other metals to improve cycle characteristics. However, although the formation of silicides leads to improved cycle characteristics, it also poses the problem of a decrease in discharge capacity.

[0006] Patent Document 1 describes silicon nanowires such as multi-layer nanoporous silicon wires having a porous and non-porous structure as nanostructures.

[0007] Non-Patent Document 1 describes that when crystalline silicon is used, the cycle characteristics are significantly deteriorated after 20 cycles. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Patent Publication No. 2013-527103 [Non-patent literature]

[0009] [Non-Patent Document 1] Y. Liu, T. Matsumura, N. Imanishi, A. Hirano, T. Ichiwaka, Y. Takeda, Electrochem. Solid-State Lett. 8 (2005) A599. Summary of the Invention [Problem to be solved by the invention]

[0010] Nanoparticle structures and porous structures have the problems described above, and nanowire structures have the problem of leaving the substrate (e.g., Cu substrate) behind (see Figure 11(c)). Therefore, the object of the present invention is to provide a silicon nanostructure that can suppress expansion and prevent electrical loss by combining a porous structure with silicon nanowires and by using a structure in which silicon nanowires are bonded onto a porous layer. [Means for solving the problem]

[0011] The present invention, which solves the above problems, is as follows. (1) A silicon nanostructure characterized by comprising a silicon porous layer having a plurality of first pores and one or more porous silicon nanowires having a plurality of second pores continuously connected to the silicon porous layer. The first pores and / or the second pores and the plurality of first pores and / or the plurality of second pores can be said to form a porous structure. (2) The porous silicon nanowire is a silicon nanostructure according to (1), characterized in that it is a collection of porous silicon nanowires having separated portions. (3) The silicon nanostructure according to (1) or (2), wherein the first porous material has an average pore size of 1 nm to 100 nm. (4) The silicon nanostructure according to any one of (1) to (3), wherein the second porous material has an average pore size of 1 nm to 200 nm. (5) The silicon nanostructure according to any one of (1) to (4), wherein the diameter of the porous silicon nanowire is 10 to 1000 nm. (6) The silicon nanostructure according to any one of (1) to (5), wherein the silicon porous layer has a thickness of 1 to 100 μm. [Effects of the Invention]

[0012] The silicon nanostructure according to the present invention can be used as an anode material for secondary batteries that suppresses expansion and prevents electrical loss. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a schematic diagram (cross-sectional view) showing (a) a silicon nanostructure according to one embodiment of the present invention, (b) the introduction of a solid charge carrier into a porous silicon nanowire structure (hereinafter sometimes simply referred to as a "nanowire structure") among silicon nanostructures, and (c) the reduction of the interface resistance between Si and Li+ in the nanowire structure. [Figure 2] The non-destructive and high-capacity mechanism is shown in (a) the case of a porous structure and (b) the case of a nanowire structure (cross-sectional view). [Figure 3]The outline of the manufacturing method for silicon nanostructures is divided into (a) silver fabrication (electroless plating), (b) silicon nanowire fabrication (metal-assisted chemical etching), and (b-2) porous layer formation, and is shown in a schematic diagram (cross-sectional view). [Figure 4] FIG. 1 shows the type of silicon, experimental conditions, and etching time for each step of the two-step method for producing silicon nanostructures. [Figure 5] 1A to 1C are diagrams illustrating the steps of a two-step method for producing silicon nanostructures. [Figure 6] (a) Type of silicon, experimental conditions, plating time / etching time for each step of the one-step method for fabricating silicon nanostructures [Figure 7] 1A to 1C are diagrams illustrating the steps of a method for producing silicon nanostructures (one step). [Figure 8] Figure 1 shows SEM images of the surface of (a) a silicon porous layer and porous silicon nanowires continuously bonded to it, (b) a porous silicon nanowire (enlarged view), (c) a silicon porous layer (enlarged view), and (d) a porous silicon nanowire, all produced by a two-step process. [Figure 9] FIG. 1 shows (a) a silicon porous layer and porous silicon nanowires continuously bonded to it in one step, and (b) an SEM image of (a) looking toward the porous silicon nanowires. [Figure 10] FIG. 2 is a diagram schematically illustrating the configuration of a cell used in cycle performance evaluation. [Figure 11] FIG. 10 is a diagram showing measurement results of cycle characteristics evaluation. [Figure 12] 1A and 1B are diagrams showing schematic diagrams of conventional silicon nanostructure examples, including (a) nanoparticles (in the case of powder), (b) nanowires (in the case of powder), and (c) nanowires (in the case of alignment). DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention is not limited to the following embodiments, and changes, modifications, and improvements can be made without departing from the scope of the invention.

[0015] 1(a), the silicon nanostructure 1 comprises a silicon porous layer 2 having a plurality of first pores 4, and spaced apart porous silicon nanowires 3, 3' having a plurality of second pores 6 continuously connected to the silicon porous layer 2. The porous silicon nanowires (hereinafter sometimes referred to as "silicon nanowires") 3, 3' are connected approximately perpendicularly to the silicon porous layer 2, and therefore form a porous silicon nanowire layer 13 due to the length L of the porous silicon nanowires 3, 3'.

[0016] The first pores 4 have openings that open outward from the silicon porous layer 2 on the surface of the silicon porous layer 2. Because FIG. 1(a) is a cross-sectional view, one of the first pores 4 looks like a void in the silicon porous layer 2, but it has an opening as described above. The same is true for the second pores 6.

[0017] For example, Li + When the silicon nanostructure 1 contains Li, it can be used as the negative electrode of a lithium-ion battery. + is absorbed by the silicon that is the material of the silicon porous layer 2 and the porous silicon nanowires 3 and 3', forming an alloy of LiSi, which is charged, causing the silicon to expand, which is extremely inconvenient for lithium-ion batteries as it causes a deterioration in their characteristics.

[0018] In the case of the first porous (micropore) 4 having an opening 4a (the second porous 6 having an opening 6a) as in the porous structure shown in FIG. 2(a), a portion 2a of the silicon porous layer (a portion 3a of the porous silicon nanowire) is Li +Even if the silicon porous layer absorbs and expands, the expanded silicon porous layer portion 2a (porous silicon nanowire portion 3a) fills the first pore 4 (second pore 6), and the silicon porous layer portion 2a (porous silicon nanowire portion 3a) is not destroyed. Since it is not destroyed in this way, the silicon porous layer portion 2a (porous silicon nanowire portion 3a) is not destroyed. + This makes it possible to achieve a high capacity.

[0019] As shown in Figure 2(b), the mechanism by which a silicon nanowire structure achieves non-destructive and high capacity is as follows. Inter-silicon nanowire voids 10 are formed between the porous silicon nanowires 3, 3'. The inter-silicon nanowire voids 10 function in a similar manner to the first pores 4 described in the porous structure, and this is why the silicon nanowire structure achieves a non-destructive and high capacity mechanism. Therefore, for a collection of porous silicon nanowires with spaced apart portions, the larger the spaced apart portions, the more advantageous it is for achieving non-destructive and high capacity. Furthermore, the porous silicon nanowires 3', 3 can achieve non-destructive and high capacity by having second pores 6.

[0020] Specifically, before charging, the combined porosity of the second porous 6 and the voids 10 between the silicon nanowires is 100%, but after charging, the porosity becomes 0%, meaning there is no loss of space. This is because the second porous 6 and the voids 10 between the silicon nanowires are filled when swelling due to charging is complete.

[0021] The first porous region 4 has an average pore size of preferably 1 nm to 100 nm, more preferably 5 to 30 nm, from the viewpoint of preventing silicon from absorbing lithium and expanding or peeling off. The second porous region 6 has an average pore size of preferably 1 nm to 200 nm, more preferably 5 to 30 nm, from the viewpoint of preventing silicon from absorbing lithium and expanding or peeling off.

[0022] From the viewpoint of supporting the silicon nanowires and maintaining them as a film, the thickness t of the silicon porous layer 2 is preferably 1 to 100 μm, and more preferably 1 to 50 μm. The diameter D of the porous silicon nanowires is preferably 10 to 1000 nm, more preferably 50 to 500 nm, from the viewpoint of increasing the surface area and preventing expansion and peeling.

[0023] As shown in Figure 1(a), when a silicon nanostructure 1 is provided with an electrode substrate 20 on the surface of the silicon porous layer 2 opposite the porous silicon nanowires 3(3'), a current path to the electrode substrate 20 can be secured. This is because the silicon particles in the porous silicon nanowires 3(3') are bonded together, and the silicon porous layer 2 and the porous silicon nanowires 3(3') are continuously bonded together. In other words, by combining various nanostructures, destruction of the nanostructures is prevented, and electrical loss due to destruction of the nanostructures can be reduced.

[0024] As shown in FIG. 1(b), when the electrolyte 21 is a solid electrolyte, the solid electrolyte is introduced into the gaps 10 between the silicon nanowires. + Since the silicon is absorbed into the silicon to form an alloy of LiSi, the Li is absorbed into the filled second porous portion 6. + can be diffused and charged.

[0025] As shown in Figure 1(c), silicon and Li + The interface resistance may be reduced by forming a low resistance material at the interface between the first and second electrodes. Known materials such as Al2O3 and TiO2 can be used as the low resistance material.

[0026] Silicon nanostructure 1 can be manufactured by first preparing silver using the electroless plating method shown in Figure 3(a), and then fabricating silicon nanowires (structures) using metal-assisted chemical etching shown in Figure 3(b). In the silver fabrication process, a silicon wafer is immersed in a solution of hydrogen fluoride (HF) and silver nitrate (AgNo3). The main reaction shown in Figure 3(a) occurs in the solution, and Ag is adsorbed onto the surface of the silicon wafer (Figures (a-1) and (a-3)). The surface can be observed in an SEM photograph of the top view, as shown in Figure (a-2).

[0027] In the process of producing silicon nanowires, the main reaction shown in Figure 3(b) occurs, and Ag + Oxidation of silicon occurs due to the oxidation of silver. In other words, silicon can be partially oxidized by the redox reaction between silicon and silver, and silicon disappears in the oxidized areas, so the remaining parts form nanowires (Figure (b-1)). In an SEM photograph of the nanowires viewed from the side, silicon nanowires could be observed, as shown in Figure (b-2). In this case, the etching direction is vertical on the p(100) substrate.

[0028] By carrying out the following process on the diagram (b-1') which is a schematic representation of the diagram (b-1), the silicon porous layer 2 can be formed. The silicon porous layer 2 is formed by thinning the thickness of the silver. As the etching progresses, the thickness of the silver is thinned to about 5 nm, and the silicon porous layer 2 is formed. [Example]

[0029] (Fabrication of silicon nanostructures) There are two methods for manufacturing silicon nanostructures 1: two-step and one-step. The two-step method creates a structure by varying the conditions for forming silicon nanowires and the silicon porous layer. On the other hand, the one-step method creates both the silicon nanowires and the silicon porous layer under the same conditions. In other words, the one-step method creates porosity when the silver is reduced in a single solution, while the two-step method forcibly creates porosity using a porosity-forming solution.

[0030] As shown in Figure 4, the two-step process for fabricating silicon nanostructure 1 includes the steps of preparing silver particles, preparing silicon nanowire arrays, separating the silicon nanowire array thin film from the silicon substrate, and removing the silver from the silicon nanowire array thin film. The silicon type, experimental conditions, and etching time for each step are shown in Figure 4. In all steps, the silicon type was n-type, the resistivity was ≦0.001 Ω*cm, the thickness was 200 μm, and the surface orientation was 100.

[0031] For the silver particle fabrication process, the experimental conditions were 40 ml of HO, 10 ml of HF, and 120 mg of AgNO, with an etching time of ≥ 15 seconds (30 seconds). For the silicon nanowire array fabrication process, the experimental conditions were 400 ml of HO, 100 ml of HF, and 9-80 ml of HO, with an etching time of ≥ 10 minutes (10 minutes). For the separation of the silicon nanowire array thin film from the silicon substrate, the experimental conditions were 40 ml of HO, 8 ml of HF, and 8.35 ml of HO, with an etching time of 5 minutes. For the removal of silver from the silicon nanowire array thin film, the experimental conditions were 10 ml of HNO, 50 ml of HO, with an etching time of 20 minutes. Note that the values ​​in parentheses for the etching times indicate the time for the example.

[0032] Figure 5(a) shows a silicon wafer, (b) to (e) show the steps from producing silver particles to separating the silicon nanowire array thin film from the silicon substrate, and (f) and (g) show the steps of removing silver from the silicon nanowire array thin film.

[0033] As shown in Figure 6(a), the one-step process for fabricating silicon nanostructures involves the steps of fabricating silver particles, fabricating silicon nanowires, and then growing the silicon nanowires from a silicon substrate. Arrayed thin films In all processes, the silicon type was n-type, the resistivity was ≦0.001Ω*cm, the thickness was 200μm, and the surface orientation was 100.

[0034] In the process of preparing silver particles, the experimental conditions were H2O: 40 ml, HF: 10 ml, AgNO3: 120 mg, and the etching time was ≥ 15 s (30 s). Arrayed thin films In the separation process, the experimental conditions were H2O: 400 ml, HF: 100 ml, H2O2: 80 ml, and the etching time was ≥ 10 mins.

[0035] Figure 7(a) shows a silicon wafer, (b) to (d) show the steps from producing silver particles to separating the silicon nanowire array thin film from the silicon substrate, and (e) and (f) show the steps of removing silver from the silicon nanowire array thin film.

[0036] The following is a comparison of the one-step and two-step fabrication of silicon nanostructure 1. When fabricated in one step, the length L of the porous silicon nanowires is 10 μm or less. Longer nanowires have a larger surface area and less resistance associated with the solid-liquid phase transfer of lithium ions, making them suitable for high-power applications. On the other hand, shorter nanowires are less susceptible to structural collapse associated with the insertion and extraction of lithium ions, making them advantageous for longer life.

[0037] In the two-step manufacturing method (Figure 4), the silicon nanowire array fabrication process used 400 ml of H2O, 100 ml of HF, and 50.1 ml of H2O2, with an etching time of 10 minutes, and the silicon nanowire array thin film separation process used 40 ml of H2O, 8 ml of HF, and 8.35 ml of H2O2, with an etching time of 5 minutes to produce silicon nanostructure 11 (Example 1). In addition, in the one-step manufacturing method (Figure 6), the etching time for the silver particle production process is 30 seconds, and the silicon nanowire production process and the silicon nanowire production from the silicon substrate are Arrayed thin films In the separation process, the etching time was set to 10 minutes to produce silicon nanostructures 21 (Example 2).

[0038] (Structural analysis of silicon nanostructures) As shown in Figures 7(a) to (d), SEM images were taken of silicon nanostructures 11 (Example 1) fabricated by metal-assisted etching.

[0039] The silicon nanostructure 11 (Example 1) shown in FIG. 8(a) comprises a silicon porous layer 12 with a thickness d1(t) of 5.48 μm and a porous silicon nanowire layer 23 with a thickness d2 of 3.23 μm. The thickness d2 of the porous silicon nanowire layer 23 was determined as the thickness at L1, the estimated maximum length of the porous silicon nanowire. The diameter d3 of the porous silicon nanowire 13 shown in FIG. 8(b) was 75.3 nm. The diameter d5 of the opening of the first pore 14 shown in FIG. 8(c) was 16.9 nm, and the spacing d4 between the multiple observed first pores was 7.30 nm. As shown in FIG. 8(d), the second pores could be observed as dark regions between the whitish silicon structures of the porous silicon nanowire, e.g., second pores 16. The diameter of the opening of the second pore 16 was several nm to 10 nm, compared to the 10 nm scale.

[0040] The silicon nanostructure 21 (Example 2) shown in Figure 9(a) comprises a silicon porous layer 12' having a thickness d7(t) of 1.818 µm and a porous silicon nanowire layer 23' having a thickness d8 of 8.455 µm. The thickness d8 of the porous silicon nanowire layer 23' was determined as the thickness at L2, the estimated longest length of the porous silicon nanowire. A 4.092 µm-long porous silicon nanowire was observed around the porous silicon nanowire of length L2, but this is likely due to the porous silicon nanowire being broken and shortened during SEM image analysis. In Figure 9(b), for example, a collection of porous silicon nanowires observed in a roughly mountain-like shape with the tip of length L2 as the peak appears dark. Furthermore, the valleys of the multiple roughly mountain-shaped collections of porous silicon nanowires appear whitish, and these areas correspond to the surface of the silicon porous layer 12' on the porous silicon nanowire side.

[0041] (Creating the negative electrode) The components were mixed thoroughly in a mass ratio of Si (silicon nanostructure, Example 1):carbon black:PVDF (polyvinylidene fluoride) = 6:3:1 to prepare a negative electrode (WE, Example 3). The active material amount was 0.792 mg, and the total electrode weight was 1.980 mg.

[0042] As shown in Figure 10, the cell 30 used to evaluate cycle characteristics comprises an upper housing 32, a lower housing 34, and a pressing unit 31. The upper housing 32 has an upper flange 32a and a through-hole 32b, the pressing unit 31 has a pressing pin 31a, and the lower housing 34 has a lower flange 34a and a pin 34b. The CE (metallic Li, anode electrode) 40 and the WE (prepared electrode, negative electrode) 41, with a separating glass fiber filter 35 sandwiched between them, are fixed to the upper surface of the lower housing 34 by pressing a pressing block 33 set above the CE downward with the pressing pin 31a. Electricity (charging and discharging) is applied to the cell 30 via conductors 38 and 39.

[0043] (Cycle characteristics of negative electrode) The downward pressure on the pressure block 33 was achieved by screwing a wing nut 41 onto the pin 34b. The pressure on the pressure part 31 to the upper housing 32 was achieved via an O-ring 36, and the pressure on the upper flange 32a to the lower flange 34a was achieved via an O-ring 37. The cycle characteristics were evaluated using 1M LiPF6 (EC (ethylene carbonate):DEC (diethyl carbonate) = 1:1 (mass ratio)) as the potential solution.

[0044] The cycle characteristics were evaluated by repeating 200 cycles, with one cycle being a charge at 400 mA / g and then a discharge for the cell 30. + is stored in the negative electrode, and Li + is released from the negative electrode. As shown in Figure 11, the capacity per amount of active material charged at the same potential decreased from the 1st to 40th charging cycles (the degree of decrease gradually decreased from the 1st to the 40th charging cycle), but the capacity per amount of active material charged at the same potential fluctuated from the 40th to the 200th cycle. That is, the 200th cycle was greater than the 100th cycle and greater than or equal to the 60th cycle.

[0045] On the other hand, for discharge, the capacity per amount of active material at the same 0V potential decreased from the first charge cycle to the 40th charge cycle, but from the 40th charge cycle to the 200th charge cycle, the capacity per amount of active material at the same 0V potential remained almost the same. The capacity at the first charge cycle, at a potential of 3V, was 190mAhg. -1 The capacity after 200 charging cycles is 144mAhg -1 Therefore, the capacity retention rate from the 1st to 200th charging cycle was 144mAhg. -1 / 190mAhg -1 =0.76, which means that the property retention rate was 76% at the initial stage, demonstrating that this material is useful.

[0046] By the way, with a bulk silicon anode, the capacity at the first charging cycle is 3260mAhg. -1Although it is expensive, the capacity after the second charging cycle is 1170mAhg -1 The capacity retention rate from the first charging cycle to the second charging cycle is 1170mAhg. -1 / 3260mAhg -1 =0.36, and it has been reported that the characteristic maintenance rate is extremely low at 36% in the very early stages (Journal of Power Sources 163 (2007) 1003-1039). [Industrial Applicability]

[0047] Higher capacity secondary batteries are expected to be used in high-power devices such as electric vehicles. Higher capacity also makes it possible to miniaturize the batteries themselves, which could lead to applications in IoT devices and drones. [Explanation of symbols]

[0048] 1, 11, 21: Silicon nanostructures 2, 12, 12´: silicon porous layer 2a: Part of the silicon porous layer 3, 3´, 13: Porous silicon nanowires 3a: A portion of a porous silicon nanowire 4, 14: First porous 4a: First porous opening 6, 16: Second porous 6a: Opening of second porous 10: Inter-nanowire voids 20: Electrode substrate 21: Electrolyte 23, 23´: Porous silicon nanowire layer 30: Cell 31: Pressing part 31a: Press pin 32: Upper housing 32a: Upper flange 32b: Through hole 33: Pressing block 34: Lower housing 34a: Lower flange 34b: Pin 35: Separation glass fiber filter 36, 37: O-ring 38, 39: Conductor 40: Anode electrode (metallic Li) 41: Negative electrode (prepared electrode) D: diameter of the porous silicon nanowire L, L1, L2: Length of the porous silicon nanowire t: thickness of the silicon porous layer d1, d7: thickness of the silicon porous layer d2, d8: thickness of the porous silicon nanowire layer d3: diameter of porous silicon nanowire d4: Spacing between first pores d5: diameter of the opening of the first pore

Claims

1. A silicon nanostructure comprising a silicon porous layer having a plurality of first pores and one or more porous silicon nanowires having a plurality of second pores continuously connected to the silicon porous layer, wherein the first pores are formed substantially uniformly throughout the silicon porous layer.

2. The silicon nanostructure of claim 1 , wherein the porous silicon nanowires are a collection of porous silicon nanowires having spaced apart portions.

3. 3. The silicon nanostructure according to claim 1, wherein the first porous layer has an average pore size of 1 nm to 100 nm.

4. 4. The silicon nanostructure according to claim 1, wherein the second porous layer has an average pore size of 1 nm to 200 nm.

5. The silicon nanostructure according to any one of claims 1 to 4, wherein the diameter of the porous silicon nanowire is 10 to 1000 nm.

6. The silicon nanostructure according to any one of claims 1 to 5, wherein the silicon porous layer has a thickness of 1 to 100 µm.

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