Measuring device and measuring method

Abstract

To provide a measuring device and a measuring method that are used for testing a device to be measured having a communication function.SOLUTION: A measuring device 600 includes: a clock generating unit that generates a sampling clock having a sampling cycle longer than a symbol cycle in a pattern under measurement including a predetermined number of symbols; a sampling unit that samples the pattern under measurement that is repeatedly input according to the sampling clock; and a measuring unit that measures a sampling result of the sampling unit according to the sampling clock of timing corresponding to symbol transition whose jitter is to be measured in the pattern under measurement that is repeatedly input.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a measurement device and a measurement method. [Background technology]

[0002] In testing a device under test (DUT) with communications capabilities, a measuring instrument measures the jitter of the signal under test transmitted by the DUT. For example, for high-speed Ethernet (registered trademark) standards such as 200 GAUI and 400 GAUI, a jitter measurement method is defined. In this standard, the DUT outputs a PRBS13Q pattern, a type of pseudo-random pattern, as the signal under test. The measuring instrument is required to measure the jitter of symbol transitions corresponding to a specific pattern in the sequence of the PAM-4 (4 Pulse Amplitude Modulation) signal under test transmitted by the DUT. Summary of the Invention

[0003] A first aspect of the present invention provides a measurement device. The measurement device may include a clock generating unit that generates a sampling clock having a sampling period longer than a symbol period in a pattern under measurement that includes a predetermined number of symbols. The measurement device may include a sampling unit that samples a repeatedly input pattern under measurement in accordance with the sampling clock. The measurement device may also include a measurement unit that measures a sampling result of the sampling unit in accordance with the sampling clock at a timing corresponding to a symbol transition that is the target of jitter measurement in the repeatedly input pattern under measurement.

[0004] The sampling period may have a period that is an integer multiple of two or more of the symbol period.

[0005] The sampling period may have a period that is a first integer multiple of the symbol period, and the first integer and the predetermined number of symbols may be relatively prime to each other.

[0006] The clock generating section may include a frequency dividing section that divides the frequency of a clock signal having one period equal to the symbol period to generate a sampling clock.

[0007] The clock generating section may include a shift section that can switch whether or not to shift the sampling clock by one symbol period.

[0008] The measurement device may further include a jitter calculation unit that calculates EOJ (Even Odd Jitter) based on the measurement results of the measurement unit when the sampling clock is shifted by one symbol period and the measurement results of the measurement unit when the sampling clock is not shifted.

[0009] The measurement apparatus may further include a trigger generating section that generates a trigger at a timing when a predetermined symbol pattern occurs in the input pattern to be measured. The measurement section may measure the sampling result in response to the trigger.

[0010] The trigger generating section may generate the trigger when a sampling pattern corresponding to a predetermined number of consecutive sampling clocks in the pattern under measurement matches a predetermined comparison pattern.

[0011] The trigger generating section may generate a trigger in response to the sampling pattern matching any one of a plurality of comparison patterns.

[0012] The measurement apparatus may further include a synchronization pattern generator configured to generate a synchronization pattern synchronized with the sampling pattern in the pattern under measurement. The trigger generator may generate a trigger in response to a match between the synchronization pattern and the comparison pattern.

[0013] The synchronization pattern generating section may include a pseudo-random pattern generating section that generates a pseudo-random pattern identical to a pattern obtained by thinning out a pseudo-random pattern used to generate the pattern under measurement using a sampling clock. The synchronization pattern generating section may include a pattern synchronizing section that synchronizes the pseudo-random pattern generated by the pseudo-random pattern generating section with a pattern extracted from the pattern under measurement in accordance with a predetermined number of consecutive sampling clocks.

[0014] The pattern under measurement may include symbols of a multi-level signal having three or more levels. The measurement apparatus may further include a threshold generating section that generates a threshold value corresponding to a symbol transition for which jitter is to be measured. The sampling section may sample the pattern under measurement using the threshold value.

[0015] The threshold generating section may generate a threshold for extracting, from the pattern under test, the pseudo-random pattern used to generate the pattern under test, in a training mode in which the pseudo-random pattern generated by the pseudo-random pattern generating section is synchronized with the pseudo-random pattern extracted from the pattern under test.

[0016] A second aspect of the present invention provides a measurement method. The measurement method may comprise a measurement device generating a sampling clock having a sampling period longer than a symbol period in a pattern under measurement including a predetermined number of symbols. The measurement method may comprise the measurement device sampling a repeatedly input pattern under measurement in accordance with the sampling clock. The measurement method may comprise the measurement device measuring a sampling result of the pattern under measurement in accordance with the sampling clock having a timing corresponding to a symbol transition for which jitter is to be measured in the repeatedly input pattern under measurement.

[0017] The above summary of the invention does not list all of the features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0018] [Figure 1] 1 shows an example of the configuration of a DUT 100 that outputs a pattern under test that includes a pseudo-random pattern. [Figure 2] An example of a signal under test sent by the DUT 100 is shown. [Figure 3] 10 is a table showing Gray code conversion by the mapping unit 130. [Figure 4] The relationship between the symbol transitions of a PAM-4 signal and the threshold level is shown. [Figure 5] 1 shows an example of a symbol pattern that is the target of jitter measurement. [Figure 6] 1 shows the configuration of a measurement device 600 according to this embodiment. [Figure 7] 6 shows the configuration of a clock generating section 620 according to this embodiment. [Figure 8] 1 shows the configuration of a shift section 700 according to this embodiment. [Figure 9] 6 shows the configuration of a sampling section 640 according to this embodiment. [Figure 10] 6 shows the configuration of a synchronization pattern generating section 650 according to the present embodiment. [Figure 11] 6 shows the configuration of a trigger generation unit 660 according to the present embodiment. [Figure 12] 10 is a timing chart showing an example of the operation of the synchronization pattern generating section 650 and the trigger generating section 660 according to the present embodiment. [Figure 13] 6 shows the configuration of a threshold generator 670 according to this embodiment. [Figure 14] 6 shows the configuration of a measurement unit 680 according to this embodiment. [Figure 15] An example of a method for measuring EOJ (Even Odd Jitter) is shown below. [Figure 16] This shows a first example of a method for identifying symbol transitions used for measuring EOJ from the repetition of a pattern to be measured. [Figure 17] A second example of a method for identifying symbol transitions used for measuring EOJ from repetitions of a pattern to be measured is shown below. [Figure 18] 14 shows the configuration of a counter unit 1410 according to this embodiment. [Figure 19] 19 shows the configuration of a synchronization pattern generating section 1900 according to a first modified example of this embodiment. [Figure 20] 10 shows the configuration of a trigger generating section 2000 according to a second modified example of this embodiment. [Figure 21] 22 illustrates an example computer 2200 in which aspects of the present invention may be embodied, in whole or in part. DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0020] 1 shows an example of the configuration of a DUT 100 (device under test 100) that outputs a pattern under test that includes a pseudo-random pattern. As an example, the DUT 100 in this figure outputs a PRBS13Q pattern under test, which is used for measuring jitter at 200 GAUI and 400 GAUI. The DUT 100 includes a PRBS generator 110, a PRBS generator 120, a mapping section 130, and an encoding section 140.

[0021] The PRBS generator 110 generates a pseudo-random pattern for the most significant bit (MSB) of the multi-level (in this example, four-level PAM-4) transmission data sent by the DUT 100. In the example shown in the figure, the PRBS generator 110 is a 13-bit pseudo-random pattern generator that repeatedly generates an 8191-bit pseudo-random pattern. The PRBS generator 110 outputs the pseudo-random pattern one bit at a time to the mapping unit 130 for each symbol period corresponding to a high-frequency clock signal, such as 26.5625 GHz.

[0022] The PRBS generator 120 generates a pseudo-random pattern for the least significant bit (LSB) of the multi-level (in this example, four-level PAM-4) transmission data sent by the DUT 100. In the example shown in the figure, the PRBS generator 120 is a 13-bit pseudo-random pattern generator that repeatedly generates an 8191-bit pseudo-random pattern. Here, the PRBS generator 120 generates a pseudo-random pattern by shifting the pseudo-random pattern output by the PRBS generator 110 by 4096 bits. Like the PRBS generator 110, the PRBS generator 120 outputs the pseudo-random pattern to the mapping unit 130 one bit at a time for each symbol period.

[0023] The mapping unit 130 is connected to the PRBS generator 110 and the PRBS generator 120. The mapping unit 130 receives multi-level transmission data including the most significant bit from the PRBS generator 110 and the least significant bit from the PRBS generator 120, and maps it to symbols to be output by the DUT 100. In the example shown in the figure, the mapping unit 130 converts the transmission data into a Gray code and maps it to a symbol code.

[0024] The encoding unit 140 is connected to the mapping unit 130. The encoding unit 140 encodes the symbol code received from the mapping unit 130 into a multi-level signal. In the example shown in the figure, the encoding unit 140 encodes the symbol code into a symbol of a PAM-4 signal having four signal levels. The encoding unit 140 transmits the encoded symbol of the multi-level signal for each symbol period. This allows the encoding unit 140 to repeatedly transmit a measured pattern, which is, for example, PRBS13Q.

[0025] In the above example, the DUT 100 repeatedly transmits a PRBS13Q pattern under test that uses a PAM-4 signal as the symbols. Alternatively, the DUT 100 may repeatedly transmit another pattern under test that includes a predetermined number of symbols.

[0026] In the above example, the DUT 100 has built-in PRBS generators 110 and 120 and has the function of sending out a pattern under test such as PRBS13Q. Alternatively, if the DUT 100 does not have the PRBS generators 110 and 120, the PRBS generators 110 and 120 may be provided on the side of a measuring device that measures the jitter of the DUT 100, and transmit data may be supplied to the DUT 100.

[0027] 2 shows an example of a signal under test transmitted by DUT 100. DUT 100 repeatedly transmits the same pattern under test, including a predetermined number of symbols, one symbol per symbol period, as the signal under test. In this example, the repeatedly transmitted PRBS13Q pattern under test is represented in chronological order as PRBS[0], PRBS[1], .... Each PRBS13Q pattern under test consists of 8191 symbols, represented in chronological order as S[0], S[1], ..., S

[8190] .

[0028] 3 is a table showing the Gray code conversion performed by the mapping unit 130. The mapping unit 130 converts the transmission data, including the most significant bit (MSB) output by the PRBS generator 110 and the least significant bit (LSB) output by the PRBS generator 120, into a Gray code as shown in the table in this figure, thereby converting the data into a multi-valued symbol code that can take on four values, 0 to 3.

[0029] 4 shows the relationship between symbol transitions and threshold levels of a PAM-4 signal. The encoding unit 140 encodes Gray code 0 from the mapping unit 130 into a symbol with a voltage level V0. Similarly, the encoding unit 140 encodes Gray codes 1 to 3 from the mapping unit 130 into a symbol with a voltage level V1. 0~3 Encode each of the symbols into

[0030] Each successive symbol represents a voltage level V 0~3Therefore, in measuring the jitter of a specific symbol transition, the midpoint between the voltage level of the symbol before the transition and the voltage level of the symbol after the transition is set as the threshold level, and the timing at which the signal value of the symbol crosses the threshold level is measured. For example, in measuring a symbol transition from a symbol at voltage level V0 to a symbol at voltage level V3, the threshold level is set to ( V Set it to (V3) / 2.

[0031] Thus, when measuring symbol transitions between symbols of a multilevel signal, it is necessary to appropriately switch the threshold depending on the symbol transition.In contrast, when measuring symbol transitions between symbols of a binary signal, the threshold can be kept constant at a voltage midway between the high-level voltage and the low-level voltage.

[0032] Figure 5 shows an example of a symbol pattern that is the target of jitter measurement. In this example, the symbol patterns that are the target of jitter measurement as defined by the 200 GAUI and 400 GAUI standards are shown along with reference patterns. The table in this figure shows the "description," "PAM4 symbol sequence," "first symbol position," "transition start position," and "threshold level" for each pattern indicated by each label in the "Label" column.

[0033] As explained in the "Explanation," the pattern marked "REF" is a reference pattern that the DUT 100 transmits at the beginning of the pattern under measurement. That is, the DUT 100 transmits a pattern of length 7, marked "3333333," in the "PAM4 symbol sequence" from the beginning of each pattern under measurement (the "first symbol position" is 1).

[0034] As explained in the "Explanation," the pattern labeled "R03" indicates the pattern targeted for jitter measurement of the rising edge jitter from symbol 0 to symbol 3. "R03" is the pattern labeled "10000330" in the "PAM4 Symbol Sequence" and begins at the 1830th symbol position (equivalent to S

[1829] ) in PRBS13Q. The symbol transition targeted for jitter measurement is the symbol transition from the last "0" of "10000" to the first "3" of "330," with the transition starting at the 1834th symbol position. Because "R03" is the symbol transition from symbol 0 to symbol 3, the threshold used for jitter measurement is (V0 + V3) / 2 (see Figure 4). Similarly, Figure 5 specifies one symbol transition targeted for jitter measurement in the PRBS13Q measurement pattern for all types of symbol transitions where the symbol value changes between two consecutive symbols.

[0035] FIG. 6 shows the configuration of a measurement apparatus 600 according to this embodiment. A measurement apparatus for measuring jitter in a DUT 100 is required to identify the timing of symbol transitions corresponding to the pattern shown in FIG. 5 from a pattern under test having a symbol period synchronized with a high-speed clock signal, and, if the symbol is a multi-level signal, to detect the signal under test at a threshold level corresponding to the symbol transition. Performing such operations at a processing speed equivalent to a high-speed clock signal would result in a large circuit scale for the measurement apparatus. Therefore, the measurement apparatus 600 according to this embodiment is capable of measuring the jitter of symbol transitions included in the pattern under test using a sampling clock that is slower than the clock signal having the symbol period.

[0036] The measurement apparatus 600 is connected to the DUT 100. The measurement apparatus 600 includes a clock generating section 620, a sampling section 640, a synchronization pattern generating section 650, a trigger generating section 660, a threshold generating section 670, a measuring section 680, and a jitter calculating section 690. The clock generating section 620 generates a sampling clock having a sampling period longer than the symbol period of a pattern under measurement that includes a predetermined number of symbols. The sampling period may be an integer multiple of two or more of the symbol period. In this embodiment, the clock generating section 620 generates the sampling clock by dividing a clock signal whose period is the symbol period of the pattern under measurement.

[0037] In this embodiment, the clock generating section 620 generates a sampling clock obtained by dividing the clock signal by 2×M, where M is 16, for example. The clock generating section 620 may receive the clock signal supplied to the DUT 100 and use it to generate the sampling clock. Alternatively, the clock generating section 620 may recover a clock signal from the signal under test output by the DUT 100 using clock recovery, and use the recovered clock signal to generate the sampling clock.

[0038] The sampling section 640 is connected to the DUT 100, the clock generating section 620, and the threshold generating section 670. The sampling section 640 samples the pattern under test that is repeatedly input from the DUT 100 in response to the sampling clock from the clock generating section 620. Measured When each signal under measurement of the pattern is a multi-valued signal, the sampling section 640 samples the pattern under measurement using the threshold generated by the threshold generating section 670 .

[0039] Here, if the sampling period is a first integer multiple (2 or more) of the symbol period, the sampling section 640 samples the symbols of the pattern under measurement at intervals of the first integer multiple. Therefore, the sampling section 640 can sample the pattern under measurement at multiple locations while shifting the sampling intervals by the first integer multiple. The clock generating section 620 may determine the sampling period so that all symbol transitions to be measured for jitter, as shown in FIG. 5, are included in the locations that can be sampled in this way.

[0040] Here, the clock generating unit 620 can determine this first integer so that it is relatively prime to the number of symbols included in one cycle of the pattern under test. In this case, the sampling unit 640 can sample all symbols once while the pattern under test is repeated the first integer number of times. In this example of the present embodiment, the sampling unit 640 repeatedly inputs a pattern under test having 8191 symbols and samples a symbol of the signal under test every 32 (=2×M). In this case, when the sampling unit 640 samples S[0], S

[32] , ..., S

[8160] in the first cycle of the pattern under test, it samples the 8160+32=1st symbol S[1] in the second cycle of the pattern under test as the 8160+32nd symbol. In the same way, the sampling unit 640 shifts the position of the symbol to be sampled by one each time the pattern under test is repeated, thereby being able to sample all symbols while the pattern under test is repeated 32 times.

[0041] The synchronization pattern generating section 650 is connected to the clock generating section 620 and the sampling section 640. The synchronization pattern generating section 650 uses the sampling clock from the clock generating section 620 to generate a synchronization pattern synchronized with a sampling pattern corresponding to a predetermined number of consecutive sampling clocks in the pattern under measurement. This synchronization pattern specifies, by its pattern, which symbol position in the pattern under measurement corresponds to the symbol sampled by the sampling section 640.

[0042] The trigger generating section 660 is connected to the clock generating section 620 and the synchronization pattern generating section 650. The trigger generating section 660 generates a trigger at the timing when a predetermined symbol pattern such as that shown in FIG. 5 appears in the input pattern to be measured. In this embodiment, the trigger generating section 660 generates a trigger in response to the matching of a sampling pattern to be sampled by the sampling section 640 with a predetermined comparison pattern. Here, the trigger generating section 660 uses the synchronization pattern output by the synchronization pattern generating section 650 as the sampling pattern to be sampled by the sampling section 640, and generates a trigger in response to the matching of the synchronization pattern with the comparison pattern.

[0043] The threshold generating section 670 is connected to the trigger generating section 660. The threshold generating section 670 is provided to dynamically switch the threshold when the pattern under measurement includes symbols of a multi-level signal having three or more levels. In response to the trigger generated by the trigger generating section 660, the threshold generating section 670 generates a threshold whose level corresponds to the symbol transition whose jitter is to be measured.

[0044] The measuring section 680 is connected to the sampling section 640 and the trigger generating section 660. The measuring section 680 measures the sampling results of the sampling section 640 in response to a sampling clock having a timing corresponding to a symbol transition that is the target of jitter measurement in the repeatedly input pattern to be measured. By measuring the sampling results of the sampling section 640 in response to a trigger generated by the trigger generating section 660, the measuring section 680 can select and measure only the sampling results that correspond to the symbol transition that is the target of jitter measurement.

[0045] The jitter calculating section 690 is connected to the measuring section 680. The jitter calculating section 690 may be dedicated hardware implemented by a dedicated circuit designed for jitter calculation, or may be a dedicated computer. Alternatively, the jitter calculating section 690 may be a computer such as a personal computer (PC), a tablet computer, a smartphone, a workstation, a server computer, or a general-purpose computer, as illustrated in FIG. 21 . The jitter calculating section 690 calculates the jitter of the pattern under measurement based on the measurement results of the measuring section 680. The jitter calculating section 690 may also control each component in the measuring apparatus 600, such as the clock generating section 620 and the synchronization pattern generating section 650, to finally calculate the jitter of the pattern under measurement.

[0046] The measurement apparatus 600 described above can measure the jitter of the symbol transitions of the measurement target included in the pattern under test using a sampling clock that is slower than a high-speed clock signal having a symbol period. Furthermore, when the signal under test is a multi-level signal, the measurement apparatus 600 can include a threshold generator 670 that can generate a threshold value of a level corresponding to the symbol transition of the measurement target.

[0047] 7 shows the configuration of a clock generating unit 620 according to this embodiment. The clock generating unit 620 includes a shifting unit 700, a frequency dividing unit 730, and a variable delay circuit 740. The shifting unit 700 receives a clock signal. The clock signal has one symbol period, and each symbol period is composed of an H (high) level period and an L (low) level period. The shifting unit 700 includes a circuit that enables switching between shifting the sampling clock finally output by the clock generating unit 620 by one symbol period.

[0048] In this embodiment, shift section 700 includes a 1 / 2 frequency divider 710 and a selector 720. 1 / 2 frequency divider 710 divides the frequency of the clock signal by 2, thereby outputting a 1 / 2 frequency divider clock signal that switches between H level and L level every symbol period. Furthermore, 1 / 2 frequency divider 710 outputs an inverted 1 / 2 frequency divider clock signal that is the inverted 1 / 2 frequency divider clock signal. The inverted 1 / 2 frequency divider clock signal is at L level in symbol periods in which the 1 / 2 frequency divider clock signal is at H level, and is at H level in symbol periods in which the 1 / 2 frequency divider clock signal is at L level.

[0049] Selector 720 is connected to divide-by-2 frequency divider 710. Selector 720 selects whether to output the divided-by-2 clock signal or the inverted divided-by-2 clock signal, in accordance with the shift instruction signal input from jitter calculation section 690. When selector 720 outputs the inverted divided-by-2 clock signal, it outputs a clock signal whose transition timing from L level to H level is shifted by one symbol period compared to when selector 720 outputs the divided-by-2 clock signal.

[0050] The frequency divider unit 730 is connected to the shifter unit 700. The frequency divider unit 730 further divides the clock signal output by the shifter unit 700 by M, thereby outputting a clock signal divided by 2M. The variable delay circuit 740 is connected to the frequency divider unit 730. The variable delay circuit 740 delays the clock signal input from the frequency divider unit 730 by an amount corresponding to the delay amount setting from the jitter calculator unit 690, and outputs the delayed signal as a sampling clock. In this way, the variable delay circuit 740 can sweep the sampling clock within a range of, for example, about the symbol period, to measure jitter, thereby enabling sampling of the signal under measurement at each phase.

[0051] 8 shows an example of a circuit configuration of the shift section 700 according to this embodiment. The 1 / 2 frequency divider 710 may be implemented by a D-FF (D flip-flop) having a D input, a clock input, a Q output, and an inverted Q output. By inputting the inverted Q output to the D input of the 1 / 2 frequency divider 710, the Q output is inverted every time the clock signal rises (transitions from L level to H level). As a result, the Q output of the 1 / 2 frequency divider 710 switches between H level and L level in that order every time the clock signal rises for each symbol period. The inverted Q output of the 1 / 2 frequency divider 710 is the inverted value of the Q output.

[0052] The selector 720 selects the Q output or the inverted Q output in response to the shift instruction signal from the jitter calculation unit 690. As a result, the selector 720 outputs a shifted clock signal whose phase has been shifted by an appropriate symbol period in response to the shift instruction signal.

[0053] 9 shows the configuration of the sampling section 640 according to this embodiment. The sampling section 640 includes a comparator 910 and a D-FF 920.

[0054] The comparator 910 compares the signal under measurement from the DUT 100 with the threshold value from the threshold generating section 670. The comparator 910 according to this embodiment outputs a comparison result that is H level when the level of the signal under measurement is higher than the threshold level, and L level when the level of the signal under measurement is lower than the threshold level.

[0055] The D-FF 920 is connected to the comparator 910. The D-FF 920 latches the comparison result of the comparator 910 in response to the rising edge of the sampling clock, and outputs it as a comparison result signal.

[0056] 10 shows the configuration of the synchronization pattern generation section 650 according to this embodiment. The synchronization pattern generation section 650 includes a sampling pattern acquisition section 1000, a pseudo-random pattern generation section 1010, and a pattern synchronization section 1020.

[0057] The sampling pattern acquisition unit 1000 includes a shift register configured with a plurality of cascaded D-FFs. The sampling pattern acquisition unit 1000 sequentially shifts the comparison result signals captured in the shift register in response to the sampling clocks to acquire sampling patterns A[0] to A

[12] (also indicated as "A[12-0]") corresponding to a predetermined number of consecutive sampling clocks in the pattern under measurement. In this embodiment, the sampling pattern acquisition unit 1000 stores comparison result signals for 13 symbols in response to the pseudo-random pattern generation unit 1010 generating a PRBS using 13-bit D-FFs in the same way as the PRBS generator 110.

[0058] The pseudo-random pattern generating unit 1010 includes a shift register configured with a plurality of cascaded D-FFs, and a circuit including a plurality of exclusive OR (XOR) elements that feeds back the outputs of two or more D-FFs to the first-stage D-FF of the shift register. The pseudo-random pattern generating unit 1010 generates a pseudo-random pattern identical to the pattern obtained by thinning out the pseudo-random pattern used to generate the pattern under measurement using a sampling clock. The pseudo-random pattern generating unit 1010 of this embodiment generates a pseudo-random pattern B[12-0] identical to the pattern obtained by thinning out the pseudo-random pattern generated by the PRBS generator 110 at 2M symbol intervals.

[0059] The pattern synchronization section 1020 is connected to the sampling pattern acquisition section 1000 and the pseudo-random pattern generation section 1010. In a training mode in which the pseudo-random pattern generated by the pseudo-random pattern generation section 1010 is synchronized with a pseudo-random pattern extracted from a pattern under measurement, the pattern synchronization section 1020 performs processing to synchronize the sampling pattern output by the sampling pattern acquisition section 1000 with the pseudo-random pattern generated by the pseudo-random pattern generation section 1010. Specifically, the pattern synchronization section 1020 synchronizes the pseudo-random pattern generated by the pseudo-random pattern generation section 1010 with a pattern extracted from the pattern under measurement according to a predetermined number (13 in this embodiment) of consecutive sampling clocks.

[0060] The pattern synchronization unit 1020 has an AND gate 1030, a match detection circuit 1040, and an OR gate 1050. The AND gate 1030 functions as a clock gate by outputting the logical product of the sampling clock and the output of the OR gate 1050 as the clock for the pseudo-random pattern generation unit 1010. Specifically, when the output of the OR gate 1050 is logic H, the AND gate 1030 supplies the sampling clock to the pseudo-random pattern generation unit 1010. When the output of the OR gate 1050 is logic L, the AND gate 1030 sets the output of the AND gate 1030 to logic L and stops supplying the sampling clock to the pseudo-random pattern generation unit 1010.

[0061] The match detection circuit 1040 outputs a pattern match signal that is logic H if the sampling pattern A[12-0] output by the sampling pattern acquisition unit 1000 matches the pseudo-random pattern B[12-0] output by the pseudo-random pattern generation unit 1010, and is logic L if they do not match. In the training mode in which the mode setting value is logic L, the OR gate 1050 outputs logic L while the pattern match signal is logic L, and stops the supply of the sampling clock to the pseudo-random pattern generation unit 1010. Here, as will be described later with reference to FIG. 13 , in the training mode, the threshold generation unit 670 sets a threshold so that the sampling unit 640 can extract the pseudo-random pattern output by the PRBS generator 110 from the pattern under measurement.

[0062] As a result, in training mode, the pseudo-random pattern B[12-0] of the pseudo-random pattern generation unit 1010 remains the same, while the sampling pattern A[12-0] of the sampling pattern acquisition unit 1000 changes in accordance with the sampling clock. The sampling pattern A[12-0] of the sampling pattern acquisition unit 1000 is a value obtained by thinning out the pseudo-random pattern output by the PRBS generator 110 in accordance with the sampling clock. Here, the sampling pattern obtained by thinning out the pseudo-random pattern generated by the PRBS generator 110 at 2M symbol intervals and sampling the number of bits possessed by the PRBS generator 110 is generated in the same order as the pseudo-random pattern generated by the pseudo-random pattern generation unit 1010.

[0063] As sampling pattern A[12-0] of sampling pattern acquisition unit 1000 changes, it eventually matches pseudo-random pattern B[12-0]. In response, the pattern match signal becomes logic H, causing the output of OR gate 1050 to also become logic H, and a sampling clock is supplied to pseudo-random pattern generation unit 1010. Here, sampling pattern A[12-0] is the pseudo-random pattern generated by PRBS generator 110 thinned out at 2M symbol intervals, and changes in the same order as the pseudo-random pattern generated by pseudo-random pattern generation unit 1010. Therefore, from this point on, pseudo-random pattern generation unit 1010 can output, at the timing of the sampling clock, a pseudo-random pattern that matches the pattern obtained by thinning out the pseudo-random pattern of PRBS generator 110 included in the measured pattern at 2M symbol intervals, as synchronization pattern B[12-0].

[0064] Once synchronization is established in training mode, the jitter calculation unit 690 sets the mode setting value to logic H to enter measurement mode. In measurement mode, the pseudo-random pattern generation unit 1010 always outputs a synchronization pattern that is synchronized with a pattern obtained by thinning out the pseudo-random pattern of the PRBS generator 110 at 2M symbol intervals. Therefore, the threshold generation unit 670 may change the threshold in accordance with the symbol transition that is the target of jitter measurement. As a result, the sampling pattern acquired by the sampling pattern acquisition unit 1000 may differ from the pattern obtained by thinning out the pseudo-random pattern of the PRBS generator 110 at 2M symbol intervals.

[0065] In the training mode, the synchronization pattern generating section 650 according to this embodiment synchronizes the sampling pattern of the pseudo-random pattern of the PRBS generator 110 extracted from the pattern under measurement with the pseudo-random pattern of the pseudo-random pattern generating section 1010. As a result, even if the threshold generating section 670 changes the threshold in the measurement mode, the synchronization pattern generating section 650 can output a synchronization pattern synchronized with the thinned-out pseudo-random pattern of the PRBS generator 110 included in the pattern under measurement.

[0066] FIG. 11 shows the configuration of a trigger generation unit 660 according to this embodiment. The trigger generation unit 660 includes D-FF1, D-FF2, D-FF3, and multiple logic elements. D-FF1 receives a fixed logic H at its D input, a signal that rises when the synchronization pattern from the synchronization pattern generation unit 650 matches the reference pattern at its clock input, and an inverted value of the mode setting value from the jitter calculation unit 690 at its reset input. During training mode, in which the mode setting value is logic L, D-FF1 enters a reset state, setting its Q output, which serves as a start signal, to logic L. As a result, the AND gate that receives the sampling clock and start signal stops supplying the sampling clock to D-FF2 and D-FF3 during training mode.

[0067] After switching from training mode to measurement mode, D-FF1 sets the start signal to logic H in response to the synchronization pattern B[12-0] matching the reference pattern corresponding to "REF" in FIG. 5. This causes D-FF1 to start supplying sampling clocks to D-FF2 and D-FF3. Note that synchronization pattern B[12-0] is synchronized with a thinned-out pattern of the pseudo-random pattern output by the PRBS generator 110. Therefore, the trigger generation unit 660 uses, as the reference pattern REF[12-0] to be compared with synchronization pattern B[12-0], a pattern corresponding to a thinned-out pattern of the pseudo-random pattern of the PRBS generator 110 up to the timing when the reference pattern in FIG. 5 starts.

[0068] D-FF2 inputs a match signal to its D input that goes to logic H when the synchronization pattern B[12-0] matches any of the multiple patterns P[0] to P

[12] and goes to logic L when the synchronization pattern does not match any of the multiple comparison patterns P[0] to P

[12] . After the reference pattern is detected in measurement mode, D-FF2 latches the match signal and outputs it from its Q output at the timing when the sampling clock is inverted. Here, the multiple patterns P[0] to P

[12] correspond to the sampling patterns at the timing of the symbol transition to be measured in "R03," "F30," etc. in FIG. 5, respectively. As with the reference pattern, the trigger generation unit 660 uses, for each of the multiple patterns P[0] to P

[12] , a pattern corresponding to the set of MSBs of each symbol of the sampling pattern at the timing of the symbol transition to be measured in "R03," etc.

[0069] After the reference pattern is detected in the measurement mode, D-FF3 latches the comparison pattern match signal output by D-FF1 at the timing of the sampling clock, and outputs it from the Q output as a trigger signal.

[0070] 12 is a timing chart showing an example of the operation of the synchronization pattern generation section 650 and the trigger generation section 660 according to this embodiment. This diagram shows waveforms over time in the horizontal direction for the sampling clock, synchronization pattern, start signal, sampling clocks supplied to D-FF2 and D-FF3, match signal, output of D-FF2, and trigger signal.

[0071] When the synchronization pattern matches the reference pattern REF[12-0] at time t2, D-FF1 sets the start signal to logic H and starts supplying the sampling clock to D-FF2 and D-FF3. When the synchronization pattern matches the pattern P[0] at time t4, the match signal becomes logic H. D-FF2 latches the logic H match signal at the timing of an inverted sampling clock, and D-FF3 latches the output of D-FF2 at the timing of the sampling clock and sets the trigger signal to logic H at time t5, which is the next cycle of the sampling clock.

[0072] The trigger generating section 660 described above can use a synchronization pattern to generate a trigger when a sampling pattern corresponding to a predetermined number of consecutive sampling clocks in the pattern under measurement matches any one of a plurality of comparison patterns, which are patterns in the signal under measurement corresponding to the timing of each symbol transition to be measured.

[0073] 13 shows the configuration of the threshold generator 670 according to this embodiment. The threshold generator 670 includes a shift register 1300, a selector 1310, a selector 1320, and a DAC 1330. The shift register 1300 stores selected threshold values ​​for each symbol transition as shown in FIG. 5 in the order in which the symbol transitions appear. In this embodiment, there are six types of thresholds, and therefore the shift register 1300 stores a 3-bit selected value for each symbol transition. The selected threshold values ​​are, for example, as follows: value 0 indicates the threshold (V0+V1) / 2 between symbol values ​​0-1; value 1 indicates the threshold (V1+V2) / 2 between symbol values ​​1-2; value 2 indicates the threshold (V2+V3) / 2 between symbol values ​​2-3; value 3 indicates the threshold (V0+V2) / 2 between symbol values ​​0-2; value 4 indicates the threshold (V1+V3) / 2 between symbol values ​​1-3; and value 5 indicates the threshold (V0+V3) / 2 between symbol values ​​0-3.

[0074] 5, there are 12 symbol transitions to be measured, so shift register 1300 stores 12 threshold selection values ​​in the order in which they appear in sampling by the sampling clock. Then, shift register 1300 shifts the threshold selection value to be output each time a logic H trigger signal is input, and when the last selection value is output, it returns to the first selection value.

[0075] In the training mode, the selector 1310 selects a selection value S12 (=value 1) that selects a threshold value (V1+V2) / 2 for sampling the pseudo-random pattern output by the PRBS generator 110. Here, the pseudo-random pattern output by the PRBS generator 110 is converted to a Gray code and then encoded into the MSB of each symbol. Therefore, during the training mode, the threshold generator 670 sets the threshold value to (V1+V2) / 2, thereby enabling sampling of the pseudo-random pattern output by the PRBS generator 110. In the measurement mode, the selector 1310 selects the selection value output by the shift register 1300.

[0076] The selector 1320 selects a digital threshold value corresponding to the selected value from among a plurality of digital threshold values ​​D01, D12, D23, D02, D13, and D03 in accordance with the selected value from the selector 1310. The DAC 1330 converts the selected digital threshold value into an analog threshold value and outputs the analog threshold value.

[0077] The threshold generator 670 described above can generate thresholds for extracting, from the measured pattern, the pseudo-random pattern used to generate the measured pattern in the training mode. Also, in the measurement mode, the threshold generator 670 can generate thresholds corresponding to each symbol transition to be measured by switching the thresholds every time a trigger signal is input.

[0078] 14 shows the configuration of a measurement unit 680 according to this embodiment. The measurement unit 680 includes a counter selection unit 1400, a plurality of counter units 1410-0 to 11, a counter unit 1420, and a count stop detection unit 1430. Each time a trigger signal is received, the counter selection unit 1400 outputs a count clock to a counter unit 1410 that measures the corresponding symbol transition among the plurality of counter units 1410-0 to 11. The counter selection unit 1400 may cause counter unit 1410-0 to count in response to a first trigger, and may cause counter unit 1410-1 to count in response to a second trigger, and so on, causing each counter unit 1410 to count one by one in the same manner.

[0079] Counter units 1410-0 to 1410-11 are provided corresponding to the respective symbol transitions targeted for jitter measurement. In this embodiment, as shown in FIG. 5, there are 12 symbol transitions targeted for measurement, and therefore 12 counter units 1410 are provided. Counter units 1410-0 to 11 are reset before the start of measurement mode. After the start of measurement mode, counter unit 1410-0 counts the comparison result signal for the symbol transition corresponding to the first trigger. Specifically, counter unit 1410-0 does not count up the value when the comparison result signal is 0, but counts up the value when the comparison result signal is 1. Counter unit 1410-1 counts the comparison result signal for the symbol transition corresponding to the second trigger. Similarly, counter unit 1410-11 counts the comparison result signal for the symbol transition corresponding to the 12th trigger. Then, when counter unit 1410 goes through one cycle due to the repetition of the pattern under measurement, counter unit 1410-0 counts the comparison result signal for the symbol transition corresponding to the 13th trigger, which corresponds to the same symbol position as the symbol transition corresponding to the first trigger in the pattern under measurement. Similarly, counter units 1410-0 to 1410-11 count the comparison result signal in order for each trigger, and after counter unit 1410-11, the counting continues from counter unit 1410-0.

[0080] Counter unit 1420 is reset before the start of measurement mode. Counter unit 1420 receives the same count clock as counter unit 1410-11 and counts the number of count clocks. When the count value of counter unit 1420 reaches a preset count number, count stop detection unit 1430 sets a count stop signal to logic H, causing counter units 1410-0 to 11 to stop counting.

[0081] The measuring unit 680 described above allows each counter unit 1410 to sample the comparison results of symbol transitions at the symbol positions corresponding to that counter unit 1410 in the repeatedly input measured pattern, for example, 100,000 times each. For example, if the count value is 35,000 for a symbol transition from symbol 0 to 3, then 65,000 times (65%) of the sampling clock pulses are counted as the pre-transition state, and 35,000 times (35%) are counted as the post-transition state. Here, for a symbol transition in which the symbol value decreases, such as a symbol transition from symbol 3 to 0, the pre-transition state is counted as 1, and the post-transition state is counted as 0. Therefore, by subtracting the count value from the count number of 100,000, the proportion of times the sampling clock pulses are after the symbol transition can be calculated.

[0082] The jitter calculation section 690 repeatedly performs the above counting 100,000 times while changing the delay amount of the variable delay circuit 740 in small increments, thereby obtaining a jitter histogram for all types of symbol transitions (12 types in this embodiment). The jitter histogram indicates the proportion of the time after the transition at each phase.

[0083] The jitter calculating section 690 may add up the jitter histograms for all types of symbol transitions to calculate a jitter histogram for all symbol transitions. Then, the jitter calculating section 690 calculates, from the jitter histograms for all symbol transitions, whether the BER (Bit Error Rate) is equal to or less than a value determined by a standard (for example, 10-4 ) may be calculated. The peak-to-peak jitter value corresponds to the J4U jitter value at 200 GAUI and 400 GAUI, and the RMS jitter value corresponds to the JRMS jitter value at 200 GAUI and 400 GAUI.

[0084] 15 shows an example of a method for measuring EOJ (Even Odd Jitter). For example, for 200 GAUI and 400 GAUI, EOJ is measured assuming that the DUT 100 outputs each symbol by interleaving multiple transmitters. EOJ measurement involves (1) measuring the average symbol transition time at intervals three times the pattern length (8191 symbols) of the PRBS13Q pattern to be measured, and (2) measuring the average symbol transition time at intervals twice the pattern length (8191 symbols) of the PRBS13Q pattern to be measured.

[0085] 15 shows the measurement method (1). For a certain symbol transition i, the measurement apparatus 600 calculates the average value T i,3 Furthermore, for that symbol transition i, the measurement apparatus 600 measures the average value T i,4 Measure.

[0086] The lower part of Fig. 15 shows the measurement method (2). For a certain symbol transition i, the measurement apparatus 600 calculates the average value T i,1Furthermore, for that symbol transition i, the measurement apparatus 600 measures the average value T of the symbol transition times of the second PRBS13Q that follows, the fourth PRBS13Q that follows twice the pattern length, the sixth PRBS13Q that follows twice the pattern length, and each PRBS13Q thereafter at intervals of twice the pattern length. i,2 Measure.

[0087] The jitter calculation unit 690 calculates the EOJ of the symbol transition i. i is calculated using the following formula (1). EOJ i =|(T i,2 -T i,1 )-(T i,4 -T i,3 )| (1) The jitter calculation unit 690 calculates the jitter for each symbol transition. i EOJ i The largest EOJ i is calculated as the EOJ of the pattern under test sent by the DUT 100.

[0088] 16 shows a first example of a method for identifying symbol transitions used in measuring EOJ from repetitions of a pattern under test. The measurement apparatus 600 uses the T shown in the upper part of FIG. i,3 and T i,4 The symbol transitions used to measure are sampled in the pattern shown in this figure.

[0089] In this embodiment, the measurement apparatus 600 samples a PRBS13Q pattern to be measured, which has 8191 symbols, at 2M (=32) symbol intervals. Therefore, the measurement apparatus 600 can sample symbol transition i at a specific symbol position in the pattern to be measured every 2M repetitions of the pattern to be measured. In this figure, the repeatedly input pattern to be measured is represented as PRBS[0], PRBS[1], ..., and 2M repetitions of the pattern to be measured are arranged horizontally. In this figure, the measurement apparatus 600 samples symbol transition i at every 2M repetitions of the leftmost pattern to be measured, PRBS[0], PRBS

[32] , PRBS

[64] , ....

[0090] As shown in the upper part of Figure 15, T i,3 The symbol transition i to be measured appears at the first and fourth positions in the six repetitions of the pattern to be measured. In Fig. 16, if the measured pattern PRBS[0] corresponds to the first (0 mod 6+1=1) of the six repetitions of the pattern to be measured, the symbol transition i sampled by PRBS

[32] corresponds to the third (32 mod 6+1=3) of the six repetitions of the pattern to be measured. As shown in the upper part of Fig. 15, the third measured pattern is not used.

[0091] Next, the symbol transition i sampled by PRBS

[64] corresponds to the fifth (64 mod 6+1=5) measured pattern in six repetitions of the measured pattern. As shown in the upper part of Figure 15, the fifth measured pattern is T i,4 Similarly, symbol transition i sampled with PRBS

[96] corresponds to the first (96 mod 6+1=1) of the six repetitions of the measured pattern, and T i,3 is used to measure the value, and so on.

[0092] In this way, the measurement apparatus 600 calculates the T of the first pattern to be measured with respect to the upper side of FIG. i,3 and T of the fifth pattern under test i,4 15. On the other hand, from only the leftmost measured pattern in FIG. 16, the symbol transition i corresponding to T i,4 and T of the fourth pattern under test i,3 It is not possible to sample the symbol transition i corresponding to

[0093] Therefore, the jitter calculating section 690 calculates the T i,4 and T of the fourth pattern under test i,3In order to sample symbol transition i corresponding to symbol i, the shift instruction signal is used to instruct the sampling clock to be shifted by one symbol period. When the sampling clock is shifted back by one symbol period, measurement apparatus 600 can sample symbol transition i in the pattern under test that precedes the pattern under test in which symbol transition i was sampled before the sampling clock was shifted. For example, in FIG. 16 , measurement apparatus 600 can sample symbol transition i in PRBS

[31] , PRBS

[63] , PRBS

[95] , ...

[0094] The symbol transition i sampled by PRBS

[31] corresponds to the second (31 mod 6+1=2) measured pattern in six repetitions of the measured pattern. As shown in the upper part of Figure 15, the second measured pattern is T i,4 The symbol transition i sampled with PRBS

[63] corresponds to the fourth (63 mod 6+1=4) of the six repetitions of the measured pattern, and T i,3 The symbol transition i sampled with PRBS

[95] corresponds to the sixth (95 mod 6+1=6) of the six repetitions of the measured pattern, and T i,3 and T i,4 It is not used to measure

[0095] In this way, the measurement apparatus 600 shifts the sampling clock by one symbol period to obtain the T i,4 and T of the fourth pattern under test i,3 The symbol transition i corresponding to

[0096] 17 shows a second example of a method for identifying symbol transitions used in measuring EOJ from repetitions of a pattern under test. i,1 and T i,2The symbol transitions used to measure are sampled in the pattern shown in this figure.

[0097] 16, in this figure, the repeatedly input measurement patterns are represented as PRBS[0], PRBS[1], ..., and 2M measurement patterns are arranged horizontally. The measurement apparatus 600 samples symbol transition i using the measurement patterns PRBS[0], PRBS

[32] , PRBS

[64] , ..., which are located at the leftmost position and are every 2M times.

[0098] As shown in the bottom of Figure 15, T i,1 The symbol transition i to be measured appears at the first, third, and fifth positions in the six repetitions of the pattern to be measured. In FIG. 17, if the pattern to be measured PRBS[0] corresponds to the first (0 mod 6+1=1) of the six repetitions of the pattern to be measured, the symbol transition i sampled with PRBS

[32] corresponds to the third (32 mod 6+1=3) of the six repetitions of the pattern to be measured. Also, the symbol transition i sampled with PRBS

[64] corresponds to the fifth (64 mod 6+1=5) of the six repetitions of the pattern to be measured. All of these are represented by T as shown in the lower part of FIG. i,1 Similarly, from the leftmost pattern to be measured in Figure 17, i,1 Only the symbol transition i used to measure can be sampled.

[0099] The jitter calculation section 690 calculates the T i,217, the measurement apparatus 600 instructs to shift the sampling clock by one symbol period in order to sample symbol transition i corresponding to PRBS

[31] , PRBS

[63] , PRBS

[95] , .... When the sampling clock is shifted back by one symbol period, the measurement apparatus 600 can sample symbol transition i in the pattern under test that precedes the pattern under test in which symbol transition i was sampled before the sampling clock was shifted. For example, in FIG. 17, the measurement apparatus 600 can sample symbol transition i in PRBS

[31] , PRBS

[63] , PRBS

[95] , ....

[0100] The symbol transition i sampled by PRBS

[31] corresponds to the second (31 mod 6+1=2) of the six repetitions of the measured pattern. As shown in the bottom of Figure 15, the second measured pattern is T i,2 The symbol transition i sampled with PRBS

[63] corresponds to the fourth (63 mod 6+1=4) of the six repetitions of the measured pattern, and T i,2 The symbol transition i sampled with PRBS

[95] corresponds to the sixth (95 mod 6+1=6) of the six repetitions of the measured pattern, and T i,2 Used to measure.

[0101] In this way, the measurement apparatus 600 shifts the sampling clock by one symbol period, thereby obtaining the T i,2 The symbol transition i corresponding to

[0102] Fig. 18 shows the configuration of a counter unit 1410 according to this embodiment. In order to realize the EOJ measurement method shown in Fig. 16 and Fig. 17, each counter unit 1410 shown in Fig. 14 may have the configuration shown in this figure.

[0103] The counter section 1410 shown in this figure includes an interleaving section 1810 and multiple counters 1820-0 to 2. The interleaving section 1810 switches among the counters 1820-0 to 2 that count the comparison result signals every time symbol i is sampled from the pattern under measurement. The interleaving section 1810 may switch among the counters 1820-0 to 2 every time a count clock is input from the counter selecting section 1400.

[0104] The plurality of counters 1820-0 to 1820-2 count the comparison result signals in response to being selected by the interleaving unit 1810. In this embodiment, the counter unit 1410 includes three counters 1820. The counter 1820-0 counts the comparison result signal for the symbol transition i sampled from PRBS[0], PRBS

[96] , .... As a result, the counter 1820-0 counts the comparison result signal for the symbol transition i sampled from PRBS[0], PRBS

[96] , .... i,3 It should be noted that if the sampling clock is shifted by one symbol period, the counter 1820-0 can count the comparison result signal for the symbol transition i used to measure T i,4 The comparison result signal for the symbol transition i used to measure can be counted.

[0105] Counter 1820-1 counts the comparison result signal for symbol transition i sampled from PRBS

[32] , PRBS

[0128] , .... As a result, counter 1820-1 counts T i,3 and T i,4 It should be noted that if the sampling clock is shifted by one symbol period, the counter 1820-1 can count the comparison result signal for the symbol transition i that is not used in any of the measurements of T i,3 The comparison result signal for the symbol transition i used to measure can be counted.

[0106] Counter 1820-2 counts the comparison result signal for symbol transition i sampled from PRBS

[64] , PRBS

[0160] , .... As a result, counter 1820-2 counts Ti,4 It should be noted that if the sampling clock is shifted by one symbol period, the counter 1820-2 can count the comparison result signal for the symbol transition i used to measure T i,3 and T i,4 , the comparison result signals for symbol transitions i that are not used in any of the measurements of .

[0107] In the case of the measurement method of FIG. 17, the counters 1820-0 to 1820-2 are all T i,1 Furthermore, when the sampling clock is shifted by one symbol period, the counters 1820-0 to 1820-2 count the comparison result signal for the symbol transition i used to measure T i,2 Count the comparison result signals for the symbol transition i used to measure .

[0108] The adder 1830 calculates and outputs the sum of the count values ​​of the multiple counters 1820-0 to 1820-2. i,1 or T i,2 The total count value for symbol transition i used to measure .times. ...

[0109] The measurement apparatus 600 uses the counter unit 1410 shown in this figure to calculate T i,3 and T i,4 16. Then, the measurement apparatus 600 shifts the sampling clock by one symbol period to measure T i,3 and T i,4の Using these measurements, the jitter calculator 690 calculates T i,3 and T i,4 can be calculated.

[0110] 17. Furthermore, the measurement apparatus 600 uses the counter unit 1410 shown in this figure to calculate T i,1 17. Then, the measurement apparatus 600 shifts the sampling clock by one symbol period to measure T i,2 Using these measurements, the jitter calculator 690 calculates T i,1 and T i,2 can be calculated.

[0111] In this way, the jitter calculation section 690 can calculate the EOJ based on the measurement results of the measurement section 680 when the sampling clock is shifted by one symbol period and the measurement results of the measurement section 680 when the sampling clock is not shifted.

[0112] 19 shows the configuration of a synchronization pattern generating section 1900 according to a modification of this embodiment. In this modification, the measurement apparatus 600 measures jitter for all symbol transitions. Therefore, when the sampling pattern matches the reference pattern, the measurement apparatus 600 generates triggers corresponding to all subsequent symbols. The measurement apparatus 600 according to this modification includes a synchronization pattern generating section 1900 and a trigger generating section 2000 instead of the synchronization pattern generating section 650 and the trigger generating section 660.

[0113] The synchronization pattern generating section 1900 is connected to the clock generating section 620 and the sampling section 640. The synchronization pattern generating section 650 uses the sampling clock from the clock generating section 620 to generate a synchronization pattern synchronized with a sampling pattern corresponding to a predetermined number of consecutive sampling clocks in the pattern under measurement.

[0114] The synchronization pattern generating section 1900 includes a shift register configured with a plurality of cascaded D-FFs. The synchronization pattern generating section 1900 sequentially shifts the comparison result signals captured in the shift register in response to the sampling clock, thereby acquiring sampling patterns A[0] to A

[12] corresponding to a predetermined number of consecutive sampling clocks in the pattern under measurement. In this embodiment, the synchronization pattern generating section 1900, like the sampling pattern acquiring section 1000, stores comparison result signals for 13 symbols.

[0115] 20 shows the configuration of a trigger generation unit 2000 according to a modification of this embodiment. The trigger generation unit 2000 is connected to the clock generation unit 620 and the synchronization pattern generation unit 1900. The trigger generation unit 2000 generates triggers for all sampling clocks after the timing at which the sampling pattern supplied as the synchronization pattern matches the reference pattern.

[0116] The trigger generating unit 2000 has a D-FF4, a D-FF5, and a plurality of logic elements. The D-FF4 is similar to the D-FF1 in the trigger generating unit 660 shown in Fig. 11, and inputs a fixed logic H to the D input and a synchronization pattern to the clock input. occurrence 5. D-FF4 receives a signal that rises when the synchronization pattern from the jitter calculation unit 1900 matches the reference pattern, and receives the inverted value of the mode setting value from the jitter calculation unit 690 as its reset input. D-FF4 is in a reset state during training mode, when the mode setting value is logic L, and sets the Q output, which serves as a start signal, to logic L. After switching from training mode to measurement mode, D-FF4 sets the start signal to logic H in response to the synchronization pattern B[12-0] matching the reference pattern corresponding to "REF" in FIG. 5.

[0117] D-FF5 inputs the start signal from D-FF4 into its D input and inputs the inverted value of the sampling clock into its clock input. D-FF5 latches the start signal output by D-FF4 at the timing of the inverted sampling clock and outputs it from its Q output as start signal' in the diagram. The AND gate connected to the Q output of D-FF5 takes the logical product of start signal' and the sampling clock, and generates a trigger at every sampling clock from the timing of the sampling clock next to the timing at which the reference pattern was detected in the sampling pattern in measurement mode.

[0118] In this modification, the threshold generating section 670 generates thresholds at levels corresponding to symbol transitions in the pattern under measurement in response to all sampling clocks, so that the shift register 1300 shown in Fig. 13 may be configured to store selected threshold values ​​for the total number of symbols in the pattern under measurement (8191 in this embodiment). In the measurement apparatus 600 according to the modification described above, all symbol transitions in the repeatedly input pattern under measurement can be used as targets for jitter measurement.

[0119] Various embodiments of the present invention may be described with reference to flowcharts and block diagrams, where the blocks may represent (1) stages of a process in which operations are performed or (2) sections of an apparatus responsible for performing the operations. Particular stages and sections may be implemented by dedicated circuitry, programmable circuitry provided with computer-readable instructions stored on a computer-readable medium, and / or a processor provided with computer-readable instructions stored on a computer-readable medium. Dedicated circuitry may include digital and / or analog hardware circuitry, and may include integrated circuits (ICs) and / or discrete circuits. Programmable circuitry may include reconfigurable hardware circuitry, including logical AND, OR, XOR, NAND, NOR, and other logical operations, flip-flops, registers, memory elements such as field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), and the like.

[0120] A computer-readable medium may include any tangible device capable of storing instructions that are executed by an appropriate device, such that the computer-readable medium having instructions stored thereon comprises an article of manufacture containing instructions that can be executed to create means for performing the operations specified in the flowcharts or block diagrams. Examples of computer-readable media may include electronic, magnetic, optical, electromagnetic, and semiconductor storage media. More specific examples of computer-readable media may include floppy disks, diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), electrically erasable programmable read-only memory (EEPROM), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disc (DVD), Blu-ray disc, memory stick, integrated circuit card, and the like.

[0121] The computer readable instructions may include either assembler instructions, Instruction Set Architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, JAVA®, C++, etc., and conventional procedural programming languages ​​such as the “C” programming language or similar programming languages.

[0122] The computer-readable instructions may be provided to a processor or programmable circuitry of a programmable data processing apparatus, such as a general-purpose computer, special-purpose computer, or other computer, either locally or over a wide-area network (WAN) such as a local area network (LAN), the Internet, etc., which executes the computer-readable instructions to create means for performing the operations specified in the flowcharts or block diagrams. Examples of processors include computer processors, processing units, microprocessors, digital signal processors, controllers, microcontrollers, etc.

[0123] 21 illustrates an example of a computer 2200 in which aspects of the present invention may be embodied, in whole or in part. Programs installed on the computer 2200 may cause the computer 2200 to function as or perform operations associated with an apparatus or one or more sections of the apparatus according to embodiments of the present invention, and / or to perform a process or steps of a process according to embodiments of the present invention. Such programs may be executed by the CPU 2212 to cause the computer 2200 to perform specific operations associated with some or all of the blocks of the flowcharts and block diagrams described herein.

[0124] A computer 2200 according to this embodiment includes a CPU 2212, a RAM 2214, a graphics controller 2216, and a display device 2218, which are interconnected by a host controller 2210. The computer 2200 also includes input / output units such as a communication interface 2222, a hard disk drive 2224, a DVD-ROM drive 2226, and an IC card drive, which are connected to the host controller 2210 via an input / output controller 2220. The computer also includes legacy input / output units such as a ROM 2230 and a keyboard 2242, which are connected to the input / output controller 2220 via an input / output chip 2240.

[0125] The CPU 2212 operates according to programs stored in the ROM 2230 and RAM 2214, thereby controlling each unit. The graphics controller 2216 acquires image data generated by the CPU 2212 into a frame buffer or the like provided in the RAM 2214 or into the graphics controller 2216 itself, and causes the image data to be displayed on the display device 2218.

[0126] The communications interface 2222 communicates with other electronic devices via a network. The hard disk drive 2224 stores programs and data used by the CPU 2212 in the computer 2200. The DVD-ROM drive 2226 reads programs or data from the DVD-ROM 2201 and provides the programs or data to the hard disk drive 2224 via the RAM 2214. The IC card drive reads programs and data from an IC card and / or writes programs and data to an IC card.

[0127] The ROM 2230 stores therein a boot program or the like that is executed by the computer 2200 upon activation, and / or programs that depend on the hardware of the computer 2200. The input / output chip 2240 may also connect various input / output units to the input / output controller 2220 via a parallel port, a serial port, a keyboard port, a mouse port, etc.

[0128] The programs are provided by a computer-readable medium such as a DVD-ROM 2201 or an IC card. The programs are read from the computer-readable medium, installed in the hard disk drive 2224, RAM 2214, or ROM 2230, which are also examples of computer-readable media, and executed by the CPU 2212. Information processing described in these programs is read by the computer 2200, and brings about cooperation between the programs and the various types of hardware resources described above. An apparatus or method may be configured by realizing information manipulation or processing in accordance with the use of the computer 2200.

[0129] For example, when communication is performed between the computer 2200 and an external device, the CPU 2212 may execute a communication program loaded into the RAM 2214 and instruct the communication interface 2222 to perform communication processing based on the processing described in the communication program. Under the control of the CPU 2212, the communication interface 2222 reads transmission data stored in a transmission buffer processing area provided in the RAM 2214, the hard disk drive 2224, the DVD-ROM 2201, or a recording medium such as an IC card, and transmits the read transmission data to the network, or writes reception data received from the network to a reception buffer processing area or the like provided on the recording medium.

[0130] The CPU 2212 may also cause all or a necessary portion of a file or database stored on an external recording medium such as the hard disk drive 2224, the DVD-ROM drive 2226 (DVD-ROM 2201), an IC card, etc. to be read into the RAM 2214, and perform various types of processing on the data on the RAM 2214. The CPU 2212 then writes back the processed data to the external recording medium.

[0131] Various types of information, such as various types of programs, data, tables, and databases, may be stored on the recording medium and may undergo information processing. The CPU 2212 may perform various types of processing on data read from the RAM 2214, including various types of operations, information processing, conditional judgment, conditional branching, unconditional branching, information search / replacement, etc., as described throughout this disclosure and specified by the instruction sequences of the programs, and write the results back to the RAM 2214. The CPU 2212 may also search for information in a file, database, etc. on the recording medium. For example, if multiple entries each having an attribute value of a first attribute associated with an attribute value of a second attribute are stored on the recording medium, the CPU 2212 may search for an entry that matches a condition specified by the attribute value of the first attribute from among the multiple entries, read the attribute value of the second attribute stored in the entry, and thereby obtain the attribute value of the second attribute associated with the first attribute that satisfies a predetermined condition.

[0132] The above-described programs or software modules may be stored in a computer-readable medium on or near the computer 2200. A recording medium such as a hard disk or RAM provided in a server system connected to a dedicated communication network or the Internet can also be used as a computer-readable medium, thereby providing the programs to the computer 2200 via the network.

[0133] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention.

[0134] It should be noted that the execution order of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and that the processes can be performed in any order unless the output of a previous process is used in a subsequent process. Even if the operational flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, this does not mean that the processes must be performed in this order. [Explanation of symbols]

[0135] 100 DUT, 110 PRBS generator, 120 PRBS generator, 130 mapping unit, 140 encoding unit, 600 measuring device, 620 clock generation unit, 640 sampling unit, 650 synchronization pattern generation unit, 660 trigger generation unit, 670 threshold generation unit, 680 measurement unit, 690 jitter calculation unit, 700 shift unit, 710 2-frequency divider, 720 selector, 730 frequency division unit, 740 variable delay circuit, 910 comparator, 920 D-FF, 1000 sampling pattern acquisition unit, 1010 pseudo-random pattern generation unit, 1020 pattern synchronization unit, 1030 AND gate, 1040 coincidence detection circuit, 1050 OR gate, 1300 shift register, 1310 selector, 1320 selector, 1330 DAC, 1400 Counter selection unit, 1410-0 to 11 counter unit, 1420 counter unit, 1430 count stop detection unit, 1810 interleave unit, 1820-0 to 2 counter, 1830 adder, 1900 synchronization pattern generation unit, 2000 trigger generation unit, 2200 computer, 2201 DVD-ROM, 2210 host controller, 2212 CPU, 2214 RAM, 2216 graphics controller, 2218 display device, 2220 input / output controller, 2222 communication interface, 2224 hard disk drive, 2226 DVD-ROM drive, 2230 ROM, 2240 input / output chip, 2242 keyboard

Claims

1. a clock generating unit that generates a sampling clock having a sampling period longer than a symbol period in a pattern to be measured that includes a predetermined number of symbols; a sampling unit that samples the repeatedly input pattern to be measured in accordance with the sampling clock; a trigger generating unit that generates a trigger when a sampling pattern corresponding to a predetermined number of consecutive sampling clocks in the pattern under measurement matches a predetermined comparison pattern that starts from a specific symbol position corresponding to a specific symbol transition between two consecutive symbols that are the target of jitter measurement in the repeatedly input pattern under measurement; a measurement unit that measures the sampling result of the specific symbol transition in response to the trigger; A measuring device comprising:

2. 2. The measurement device according to claim 1, wherein the sampling period is an integer multiple of the symbol period, which is two or more.

3. the sampling period has a period that is a first integer multiple of the symbol period; 3. The measurement device of claim 2, wherein the first integer and the predetermined number of symbols are relatively prime.

4. 4. The measurement device according to claim 1, wherein the clock generating section includes a frequency dividing section that divides a frequency of a clock signal having one period equal to the symbol period to generate the sampling clock.

5. 5. The measuring device according to claim 4, wherein the clock generating section includes a shift section that can switch between shifting the sampling clock by one symbol period and not shifting the sampling clock.

6. 6. The measurement device according to claim 5, further comprising a jitter calculation unit that calculates EOJ (Even Odd Jitter) based on a measurement result of the measurement unit when the sampling clock is shifted by one symbol period and a measurement result of the measurement unit when the sampling clock is not shifted.

7. The measurement device according to claim 1 , wherein the trigger generating section generates a trigger in response to the sampling pattern matching any one of the plurality of comparison patterns.

8. a synchronization pattern generating unit that generates a synchronization pattern synchronized with the sampling pattern in the pattern under measurement, The measurement device according to claim 1 , wherein the trigger generating section generates the trigger in response to the synchronization pattern matching the comparison pattern.

9. The synchronization pattern generation unit a pseudo-random pattern generating unit for generating a pseudo-random pattern identical to a pseudo-random pattern obtained by thinning out the pseudo-random pattern used to generate the pattern to be measured using a sampling clock; a pattern synchronization unit that synchronizes the pseudo-random pattern generated by the pseudo-random pattern generation unit with a pattern extracted from the pattern to be measured in accordance with a predetermined number of consecutive sampling clocks; 9. The measuring device according to claim 8, further comprising:

10. the pattern under test includes symbols of a multi-level signal having three or more levels, a threshold generator configured to generate a threshold value corresponding to the specific symbol transition for which jitter is to be measured; The sampling unit samples the pattern to be measured using the threshold value.

10. The measuring device according to claim 9.

11. 11. The measurement apparatus according to claim 10, wherein the threshold generating section generates a threshold for extracting, from the pattern under measurement, the pseudo-random pattern used to generate the pattern under measurement, in a training mode in which the pseudo-random pattern generated by the pseudo-random pattern generating section is synchronized with the pseudo-random pattern extracted from the pattern under measurement.

12. The measurement device generates a sampling clock having a sampling period longer than a symbol period in a pattern to be measured including a predetermined number of symbols; the measurement device samples the repeatedly input pattern to be measured in accordance with the sampling clock; the measurement device generates a trigger in response to a match between a sampling pattern corresponding to a predetermined number of consecutive sampling clocks in the pattern under test and a predetermined comparison pattern starting from a specific symbol position corresponding to a specific symbol transition between two consecutive symbols for which jitter is to be measured in the repeatedly input pattern under test; the measurement device measures the sampling result of the particular symbol transition in response to the trigger; A measurement method comprising:

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