Broadband intermediate-frequency heterogeneous integrated communication transceiving micro module and three-dimensional packaging method

Abstract

The invention designs a broadband intermediate-frequency heterogeneous integrated communication transceiving micro module and a three-dimensional packaging method, and belongs to the technical field of advanced packaging. The micro module comprises a TSV silicon adapter plate, a Fan-out module, an HTCC ceramic substrate and a digital chip. The TSV silicon adapter plate adopts a high-resistance silicon substrate, and a coaxial shielding TSV structure is arranged on the TSV silicon adapter plate and comprises an inner layer signal through hole and an outer layer grounding layer. A frequency synthesizer chip and a radio frequency chip are embedded in the Fan-out module, and high-density horizontal interconnection is realized through a plurality of redistribution layers. The HTCC ceramic substrate is of a multi-layer laminated structure, and an impedance matching network is arranged in the HTCC ceramic substrate. The three-dimensional packaging method comprises the steps of TSV silicon adapter plate preparation, Fan-out module processing, digital chip stacking and system-level integration. High-density packaging of the radio frequency chip and the digital chip is achieved through the three-dimensional heterogeneous integrated architecture, and low-loss transmission of broadband signals is guaranteed through the coaxial shielding TSV structure and the impedance matching network.

Description

Technical Field

[0001] This invention relates to the field of advanced packaging technology, specifically to a broadband intermediate frequency heterogeneous integrated communication transceiver micro-module and a three-dimensional packaging method. Background Technology

[0002] With the rapid development of wireless communication technology, intermediate frequency (IF) communication systems have been widely used in satellite communication, radar detection, and mobile communication. IF communication systems need to transmit and receive radio frequency (RF) signals over a wide frequency band, placing increasingly higher demands on system miniaturization, high integration, and low-loss characteristics. Traditional communication transceiver systems typically use printed circuit boards (PCBs) as the system carrier, discretely mounting RF chips, digital chips, and passive components on the PCB, interconnecting these components through board-level traces. This board-level integration method suffers from long interconnection distances and large parasitic parameters, making it difficult to meet the requirements of high-frequency broadband signal transmission.

[0003] To improve system integration, the industry has developed system-in-package (SiP) technology, integrating multiple chips and devices into a single package. Traditional SiP technology primarily uses wire bonding to achieve electrical interconnection between the chip and the substrate; however, wire bonding suffers from high parasitic inductance, affecting the transmission quality of high-frequency signals. Through-silicon via (TSV) technology, as a three-dimensional interconnect technology, enables vertical chip stacking and short-distance interconnection; however, traditional TSV structures lack effective electromagnetic shielding, resulting in significant crosstalk between adjacent vias and high insertion loss for high-frequency signals. Fan-out packaging technology enables high-density redistribution of chips; however, traditional fan-out packaging uses dielectric materials with high dielectric constants, leading to significant dielectric loss at high frequencies, limiting its application in broadband RF systems. In mixed RF and digital systems, it is necessary to integrate RF chips and digital chips manufactured using different processes into the same module. RF chips are typically manufactured using compound semiconductor processes such as gallium arsenide (GaAs) or gallium nitride (GaN), while digital chips are typically manufactured using silicon-based CMOS processes; the two types of chips differ in material properties and packaging requirements. Existing packaging technologies struggle to simultaneously meet the heterogeneous integration requirements of RF and digital chips. Interconnects between RF and digital chips typically require long traces, increasing signal transmission losses. Furthermore, differences in the coefficients of thermal expansion between different materials can generate stress during temperature changes, impacting package reliability. In system-level integration, current technologies lack effective impedance matching designs, resulting in significant reflections between RF and digital signals at interfaces with different impedances, affecting signal transmission integrity. Simultaneously, the lack of effective isolation between different signal types leads to crosstalk between high-speed digital and RF signals, reducing the system's signal-to-noise ratio. Moreover, with increasing system power consumption, thermal management of the package becomes a critical factor limiting system performance; the heat dissipation capabilities of existing packaging structures are insufficient for high-power-density systems.

[0004] Therefore, a new packaging technology is needed to solve the problems of existing technologies in high-frequency transmission loss, heterogeneous integration, impedance matching and thermal management. Summary of the Invention

[0005] To address the problems existing in the background art, the present invention provides a broadband intermediate frequency heterogeneous integrated communication transceiver micro-module, comprising:

[0006] The TSV silicon adapter board uses a high-resistivity silicon substrate. The high-resistivity silicon substrate has a coaxial shielded TSV structure. The coaxial shielded TSV structure includes an inner signal via and an outer ground layer surrounding the inner signal via. The inner signal via is filled with a conductive material, and an insulating layer is provided between the inner wall of the inner signal via and the conductive material.

[0007] The Fan-out module includes an RF receiver module and an RF transmitter module. The RF receiver module contains a frequency synthesizer chip and an RF receiver chip. The RF transmitter module contains a frequency synthesizer chip and an RF transmitter chip. The Fan-out module has a multi-layer redistribution layer (RDL) that is electrically connected to each chip.

[0008] The HTCC ceramic substrate has a multilayer stacked structure. Its upper surface is provided with a TSV adapter board mounting area and a Fan-out module mounting area. The TSV silicon adapter board is connected to the TSV adapter board mounting area through a first solder ball array. The Fan-out module is connected to the Fan-out module mounting area through a second solder ball array. The HTCC ceramic substrate integrates an impedance matching network. The bottom of the HTCC ceramic substrate is provided with external interconnect terminals.

[0009] A digital chip is disposed on the upper surface of the TSV silicon adapter board, and vertical signal transmission is achieved with the HTCC ceramic substrate through the coaxial shielded TSV structure.

[0010] In a preferred embodiment, the RF receiver module contains one frequency synthesizer chip and one RF receiver chip, and the RF transmitter module contains two frequency synthesizer chips and one RF transmitter chip; the bottom of the Fan-out module is provided with a third solder ball array, which is electrically connected to the multilayer RDL and used to achieve signal interconnection with the HTCC ceramic substrate.

[0011] In a preferred embodiment, the impedance matching network includes a microstrip line used for impedance matching between radio frequency signals and digital signals; the TSV silicon adapter board is also provided with a DDR memory and an IPD passive network, which are electrically connected to the digital chip through the coaxial shielded TSV structure.

[0012] This invention also provides a three-dimensional packaging method for a broadband intermediate frequency heterogeneous integrated communication transceiver micro-module, comprising the following steps:

[0013] S1. TSV silicon adapter board fabrication: A high-resistivity silicon substrate is selected, and a through-hole array is formed on the high-resistivity silicon substrate by deep reactive ion etching process. After depositing an insulating layer on the inner wall of the through-hole, conductive material is filled. After surface planarization treatment, traces and pads are formed on the surface of the high-resistivity silicon substrate, and a ground layer is formed around the signal through-hole to form a coaxial shielded TSV structure, thus obtaining the TSV silicon adapter board.

[0014] S2, Fan-out module fabrication: The frequency synthesizer chip and the radio frequency chip are embedded in an organic dielectric, and multi-layer RDL wiring is formed by laser drilling and electroplating processes. After plastic encapsulation, a solder ball array is formed to obtain the Fan-out module.

[0015] S3. Digital chip stacking: The digital chip is mounted on the upper surface of the TSV silicon adapter board, and the electrical connection between the digital chip and the TSV silicon adapter board is achieved by flip-chip bonding process.

[0016] S4. System-level integration: Prepare an HTCC ceramic substrate with a built-in impedance matching network, mount the TSV silicon adapter board and the Fan-out module to the corresponding mounting areas of the HTCC ceramic substrate, and interconnect them by reflow soldering. Form external interconnection terminals on the bottom of the HTCC ceramic substrate to obtain a broadband intermediate frequency heterogeneous integrated communication transceiver micro-module.

[0017] In the preferred embodiment, step S1 specifically includes:

[0018] S11. Deep Silicon Etching: A high-resistivity silicon substrate is selected, and a via array is formed on the high-resistivity silicon substrate by deep reactive ion etching (DRIE) process. During etching, the aspect ratio R is controlled as R=H / D, where R is the aspect ratio; H is the etching depth (μm); and D is the via diameter (μm). The aspect ratio R ranges from 8 to 12.

[0019] S12, Insulating layer deposition: A SiO2 insulating layer is deposited on the inner wall of the through hole using plasma-enhanced chemical vapor deposition (PECVD).

[0020] S13. Conductive material filling: Copper is filled into the through-hole using a pulse electroplating process. During pulse electroplating, a forward current density Jf and a reverse current density Jr are set, and the current density ratio K = Jr / Jf is controlled, where K is the current density ratio; Jr is the reverse current density (A / dm³). 2 Jf represents the forward current density (A / dm). 2 The current density ratio K ranges from 1.5 to 3.

[0021] S14. Surface planarization: Chemical mechanical polishing (CMP) is performed on the surface of the filled silicon substrate.

[0022] S15. Surface metallization: A metal layer is deposited using a sputtering process, and traces and pads are formed by photolithography and etching. A ground layer is formed around the signal vias to form a coaxial shielded TSV structure, resulting in a TSV silicon adapter board.

[0023] In the preferred embodiment, step S2 specifically includes:

[0024] S21. Chip embedding: Positioning and embedding the RF receiver chip, RF transmitter chip and frequency synthesizer chip into a low-loss organic medium;

[0025] S22, RDL wiring: Laser drilling is used to form micro-vias on the organic medium, and copper plating is used to form multi-layer RDL wiring. The number of wiring layers n ranges from 3 to 5 layers.

[0026] S23, Molding and Ball Placement: The chip and RDL wiring are encapsulated using encapsulation plastic, and a solder ball array is formed on the bottom to obtain the Fan-out module.

[0027] In the preferred embodiment, step S3 specifically includes:

[0028] S31. Digital chip mounting: At least one digital chip from the FPGA, broadband programmable RF transceiver, or RF direct acquisition transceiver is mounted on the upper surface of the TSV silicon adapter board by flip-chip bonding process.

[0029] S32. Interconnection of peripheral devices: The DDR memory and IPD passive network are mounted on the TSV silicon adapter board, and the electrical connection with the digital chip is achieved through the coaxial shielded TSV structure to form a chip stack structure.

[0030] In the preferred embodiment, step S4 specifically includes:

[0031] S41. HTCC ceramic substrate preparation: HTCC ceramic substrate is prepared by multilayer green ceramic tape stacking process, and an impedance matching network composed of microstrip lines is formed in the HTCC ceramic substrate.

[0032] S42, Mounting: Place the first solder ball in the TSV adapter board mounting area of ​​the HTCC ceramic substrate and mount the TSV silicon adapter board; place the second solder ball in the Fan-out module mounting area and mount the Fan-out module.

[0033] S43. Reflow Soldering: Reflow soldering is performed in a vacuum environment. During soldering, the peak temperature Tp and the peak holding time tp are controlled, where Tp is the peak soldering temperature (°C); tp is the peak holding time (s); the value of Tp ranges from 255 to 265°C, and the value of tp ranges from 30 to 90s.

[0034] S44. External terminal formation: External interconnection terminals are formed on the bottom of the HTCC ceramic substrate to obtain a broadband intermediate frequency heterogeneous integrated communication transceiver micro-module.

[0035] In a preferred embodiment, the following wiring rules are adopted when forming the impedance matching network in step S41:

[0036] The RF ADC input traces are matched using differential impedance Z1, the RF DAC output traces are matched using differential impedance Z2, the remaining differential signal lines are matched using differential impedance Z3, and the single-ended signal lines are matched using single-ended impedance Z0. Here, Z1 is the ADC input differential impedance (Ω); Z2 is the DAC output differential impedance (Ω); Z3 is the impedance of the remaining differential signals (Ω); and Z0 is the single-ended signal impedance (Ω). Z1 is 50Ω, Z2 is 100Ω, Z3 is 100Ω ± 5%, and Z0 is 50Ω.

[0037] During routing, at least one grounding hole is set on each side of the differential via. GPIO signal lines, SPI signal lines, ADC / DAC input traces, reference clock signals, and SYSREF signals are routed using layered isolation.

[0038] In a preferred embodiment, step S44 is followed by:

[0039] S45. Heat dissipation packaging: The cover plate is bonded to the HTCC ceramic substrate using thermally conductive adhesive. The coating thickness hg of the thermally conductive adhesive is determined according to the heat dissipation requirements, where hg is the thickness of the thermally conductive adhesive (μm). The value of hg ranges from 100 to 300 μm, thus completing the packaging of the broadband intermediate frequency heterogeneous integrated communication transceiver micro-module.

[0040] The beneficial effects achieved by this invention are as follows:

[0041] This invention employs a three-dimensional heterogeneous integration architecture combining a TSV silicon interposer, a fan-out module, and an HTCC ceramic substrate. This architecture achieves high-density integration of digital and RF chips in both the vertical and horizontal directions, overcoming the interconnection density limitations of traditional two-dimensional planar packaging. Vertical stacking significantly shortens the interconnection distance between chips, thereby reducing parasitic parameters along the signal transmission path. Compared to traditional system-in-package (SiP) technologies, this three-dimensional heterogeneous integration architecture achieves higher functional integration within a smaller package volume, meeting the miniaturization and high integration requirements of modern communication systems. Simultaneously, the three-dimensional stacking structure allows digital and RF signals to be transmitted via the shortest path, effectively improving the transmission quality of high-frequency signals.

[0042] The TSV silicon adapter board of this invention adopts a coaxial shielded TSV structure, including an inner signal via located at the center and an outer ground layer surrounding the signal via. This coaxial shielding structure draws on the electromagnetic shielding principle of coaxial cables, with the outer ground layer forming a surrounding electromagnetic shield for the inner signal via. Due to the shielding effect of the ground layer, electromagnetic coupling between adjacent signal vias is effectively suppressed, thereby reducing crosstalk between channels. Simultaneously, the coaxial structure has excellent impedance control characteristics, which can keep the characteristic impedance of the signal vias stable, reducing signal reflection caused by impedance discontinuities. Therefore, the coaxial shielded TSV structure can effectively reduce the insertion loss of high-frequency signals on the vertical interconnect path and improve signal transmission integrity.

[0043] The Fan-out module of this invention employs embedded chip and multilayer RDL routing technology to embed the RF chip and frequency synthesizer chip within a low-loss organic dielectric, and achieves interconnection between the chips through a high-density redistribution layer. Compared to traditional wire bonding packaging, embedded chip packaging eliminates the parasitic inductance introduced by bonding wires, shortens the interconnection distance between chips, and facilitates high-frequency signal transmission. Multilayer RDL routing technology enables complex signal routing within a limited package area, improving the chip's input / output port expansion capabilities. The application of low-loss organic dielectric materials reduces dielectric loss of high-frequency signals along the horizontal transmission path, allowing the Fan-out module to support higher frequency signal transmission. This packaging method gives the RF front-end module better high-frequency characteristics and higher integration density.

[0044] This invention employs a multilayer HTCC ceramic substrate as a system-level carrier, integrating an impedance matching network within the ceramic substrate. Low-reflection transmission of RF and digital signals is achieved through a combination of differential and single-ended impedance matching wiring rules. HTCC ceramic materials possess advantages such as stable dielectric constant, high thermal conductivity, and good matching of thermal expansion coefficients with silicon materials, providing excellent electrical performance and thermal management capabilities as a system-level carrier. The impedance matching network built into the ceramic substrate achieves matching transitions between different impedance interfaces via microstrip lines, reducing signal reflections at the RF and digital interfaces and ensuring signal transmission integrity over a wide bandwidth. The layered isolation wiring design places different types of signals on different wiring layers, isolated by a ground plane, effectively reducing crosstalk between signals and improving the system's electromagnetic compatibility performance. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the overall three-dimensional structure of the micro-module. Sub-figure (a) is a plan view showing the stacking relationship of each layer, and sub-figure (b) is a side cross-sectional view showing the cross-sectional structure of the TSV adapter board, Fan-out module and ceramic substrate.

[0046] Figure 2 This is a schematic diagram of a TSV silicon adapter board. Sub-figure (a) is a process flow diagram, showing the key steps from deep silicon etching to surface metallization. Sub-figure (b) is an enlarged view of the coaxial TSV structure, showing the inner signal line and outer ground line structure.

[0047] Figure 3 This is a Fan-out module diagram, where sub-diagram (a) shows the top, top, and side views of the frequency synthesizer and RF transmitting module, sub-diagram (b) shows the corresponding views of the frequency synthesizer and RF receiving module, and sub-diagram (c) is a cross-sectional view of the RDL (Redistribution Layer), showing the wiring hierarchy;

[0048] Figure 4 This is a schematic diagram of heterogeneous integration of HTCC ceramic substrate, showing the mounting and interconnection method of multilayer ceramic substrate and its TSV adapter board and Fan-out module;

[0049] Figure 5 This is a comparison chart of high-frequency performance tests. Sub-chart (a) shows the curve of insertion loss (S21) changing with frequency, and sub-chart (b) shows the curve of return loss (S11) changing with frequency.

[0050] Figure 6 This is a graph showing the results of thermal reliability analysis, displaying the temperature field distribution cloud map of the system at a given ambient temperature. Detailed Implementation

[0051] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. In addition, the forms of the various structures described in the following embodiments are merely illustrative. The present invention is not limited to the structures described in the following embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Reference Figures 1 to 4 The broadband intermediate frequency heterogeneous integrated communication transceiver micro-module provided by this invention adopts a three-dimensional packaging architecture that integrates TSV and Fan-out heterogeneous integration. For example... Figure 1 As shown in the plan view of sub-figure a, the micro-module has a hierarchical stacked structure, consisting of an HTCC ceramic substrate, a TSV silicon adapter board, a fan-out module, and a digital chip from bottom to top. Figure 1 As shown in the side cross-sectional view in sub-Figure b, the TSV silicon interposer and Fan-out module are respectively disposed on the upper surface of the HTCC ceramic substrate, and the digital chips are stacked on top of the TSV silicon interposer to form a three-dimensional heterogeneous integrated structure. This architecture achieves vertical interconnection of digital chips through TSV, high-density horizontal interconnection of RF chips through Fan-out, and low-loss signal transmission and thermal management at the system level through the HTCC ceramic substrate.

[0053] TSV (Through Silicon Via) silicon interposers are key structures for vertical signal transmission between digital chips and HTCC ceramic substrates. TSV, or Through Silicon Via, is a three-dimensional interconnect technology that forms through-holes in a silicon substrate and fills them with conductive material. The TSV silicon interposer of this invention uses a high-resistivity silicon substrate as the substrate material. High-resistivity silicon refers to single-crystal silicon material with high resistivity, which effectively reduces the loss of radio frequency signals during transmission in the silicon substrate. A coaxial shielded TSV structure is provided on the high-resistivity silicon substrate. This structure includes an inner signal via located at the center and an outer ground layer surrounding the inner signal via. The inner signal via is filled with conductive material, preferably electroplated copper, for transmitting high-frequency signals. An insulating layer, preferably made of silicon dioxide, is provided between the inner wall of the inner signal via and the conductive material to achieve electrical isolation between the signal via and the silicon substrate. Figure 2 As shown in sub-figure b, this coaxial shielding structure is similar to that of a coaxial cable. The inner layer is the signal line and the outer layer is the ground layer. The ground layer forms electromagnetic shielding for the signal line, which can effectively suppress crosstalk between adjacent vias and reduce insertion loss during signal transmission.

[0054] Fan-out modules are used to achieve high-density integration and signal expansion of RF chips. Fan-out, or fan-out packaging, is an advanced packaging technology that embeds the chip in an organic dielectric and expands the pins through a redistribution layer. The Fan-out module of this invention includes an RF receiver module and an RF transmitter module. The RF receiver module embeds a frequency synthesizer chip and an RF receiver chip, whereby the frequency synthesizer chip generates the local oscillator signal, and the RF receiver chip performs RF signal reception and down-conversion processing. The RF transmitter module embeds a frequency synthesizer chip and an RF transmitter chip, whereby the RF transmitter chip performs baseband signal up-conversion and RF power amplification. Figure 3 Sub-figure a shows the top, top, and side views of the frequency synthesizer and RF transmitting module, while sub-figure b shows the corresponding views of the frequency synthesizer and RF receiving module. The fan-out module contains multiple redistribution layers (RDLs), which are metal wiring layers formed on the surface of the package through photolithography and electroplating processes. Figure 3 The RDL cross-section shown in sub-figure c illustrates how the multi-layer RDL is electrically connected to the pads of each chip, enabling the extraction and redistribution of chip signals. Simultaneously, high-density wiring meets the requirements for high-speed signal transmission between chips. Compared to traditional wire bonding packaging, fan-out packaging offers advantages such as shorter interconnect distances, lower parasitic parameters, and better signal integrity, making it suitable for high-frequency signal transmission applications.

[0055] HTCC ceramic substrates serve as the system-level carrier for the entire micromodule, enabling interconnection between functional modules and interfacing with external systems. HTCC, or High Temperature Co-fired Ceramic, is a technology that involves sintering green ceramic tapes and metallized patterns together at high temperatures to form a multilayer wiring substrate. For example... Figure 4 As shown, the HTCC ceramic substrate has a multilayer stacked structure, the number of which can be determined according to wiring requirements, preferably using more than 30 layers of green ceramic tape stacked together. The upper surface of the HTCC ceramic substrate has a TSV adapter board mounting area and a Fan-out module mounting area. The TSV silicon adapter board is connected to the TSV adapter board mounting area through a first solder ball array, and the Fan-out module is connected to the Fan-out module mounting area through a second solder ball array. The solder ball array is used to achieve mechanical fixation and electrical interconnection between the module and the substrate. An impedance matching network is integrated within the HTCC ceramic substrate. This impedance matching network includes microstrip lines, which are used for impedance matching between RF signals and digital signals, reducing signal reflection at different impedance interfaces and ensuring signal transmission integrity. The bottom of the HTCC ceramic substrate has external interconnect terminals for electrical connection between the micromodule and external circuit boards or systems. The HTCC ceramic substrate has advantages such as stable dielectric constant, high thermal conductivity, and good matching of thermal expansion coefficient with silicon material, making it suitable as a system-level carrier for RF micromodules.

[0056] The digital chip is mounted on the upper surface of the TSV silicon adapter board, achieving vertical signal transmission with the HTCC ceramic substrate via a coaxially shielded TSV structure. The digital chip may include at least one of an FPGA, a wideband programmable RF transceiver, or a direct RF sampling transceiver. An FPGA (Field-Programmable Gate Array) is used to implement digital signal processing and system control functions. A wideband programmable RF transceiver is used to digitize RF signals. A direct RF sampling transceiver uses a direct RF sampling architecture to directly convert RF signals into digital signals. The TSV silicon adapter board also includes DDR memory and an IPD passive network. The DDR memory is used for data buffering, and the IPD (Integrated Passive Device) integrates passive components such as resistors, capacitors, and inductors onto a silicon substrate for impedance matching and filtering. The DDR memory and IPD passive network are electrically connected to the digital chip via the coaxially shielded TSV structure, forming a complete digital signal processing subsystem.

[0057] This invention also provides a three-dimensional packaging method for the above-mentioned broadband intermediate frequency heterogeneous integrated communication transceiver micro-module. This method includes step S1: TSV silicon adapter board fabrication; step S2: Fan-out module processing; step S3: digital chip stacking; and step S4: system-level integration. The steps are described in detail below with reference to the accompanying drawings.

[0058] Step S1 involves the fabrication of the TSV silicon interposer. (Refer to...) Figure 2 The process flow diagram shown in sub-Figure a is as follows: In this step, a high-resistivity silicon substrate is selected, and a through-hole array is formed on the high-resistivity silicon substrate by deep reactive ion etching process. After depositing an insulating layer on the inner wall of the through-hole, conductive material is filled. After surface planarization treatment, traces and pads are formed on the surface of the high-resistivity silicon substrate, and a ground layer is formed around the signal through-hole to form a coaxial shielded TSV structure, thus obtaining the TSV silicon adapter board.

[0059] Step S11 is deep silicon etching. A high-resistivity silicon substrate is selected as the substrate material for the TSV silicon interposer. The resistivity of the high-resistivity silicon substrate is preferably greater than 1 kΩ·cm, and the thickness can be selected according to design requirements. A via array is formed on the high-resistivity silicon substrate using Deep Reactive Ion Etching (DRIE) technology. DRIE is an anisotropic dry etching technique that, through alternating etching and sidewall passivation steps, can form high aspect ratio vertical vias on the silicon substrate. Figure 2As shown in the first step of sub-figure a, the aspect ratio R = H / D needs to be controlled during etching; where R is the aspect ratio; H is the etching depth in μm; and D is the via diameter in μm. The value of the aspect ratio R needs to comprehensively consider process feasibility and electrical performance. If the R value is too small, the via density will decrease; if the R value is too large, it will increase the etching difficulty and copper filling difficulty. The preferred range for the aspect ratio R is 8 to 12. The via diameter D can be determined according to the interconnect density requirements, and the via spacing should ensure sufficient insulation distance between adjacent vias.

[0060] Step S12 is the deposition of an insulating layer. For example... Figure 2 As shown in the second step of sub-Figure a, a SiO2 insulating layer is deposited on the inner wall of the via using plasma-enhanced chemical vapor deposition (PECVD). PECVD is a technique that uses plasma to activate reactive gases to achieve thin film deposition at relatively low temperatures. The function of the SiO2 insulating layer is to provide electrical isolation between the conductive material inside the signal via and the silicon substrate, preventing signal leakage to the silicon substrate and causing losses. The thickness of the insulating layer should ensure sufficient insulation strength, but should not be too thick to avoid affecting subsequent copper filling processes; a thickness of approximately 1 μm is preferred. The advantages of PECVD are its low deposition temperature, good film uniformity, and ability to achieve uniform coverage on the sidewalls of vias with high aspect ratios.

[0061] Step S13 involves filling with conductive material. For example... Figure 2 As shown in the third step of sub-Figure a, copper is filled into the via using a pulse electroplating process. Pulse electroplating is an electroplating technique that controls the electrodeposition process by periodically changing the direction and magnitude of the current. Compared with direct current electroplating, it has the advantages of better filling uniformity and lower void ratio. During pulse electroplating, a forward current density Jf and a reverse current density Jr need to be set, and the current density ratio K = Jr / Jf needs to be controlled; where K is the current density ratio; Jr is the reverse current density, with units of A / dm³. 2 Jf represents the forward current density, measured in A / dm³. 2 During the forward pulse, copper ions are deposited within the via, while during the reverse pulse, some of the deposited copper is dissolved. This alternating process eliminates copper buildup at the via opening and promotes copper ion diffusion towards the bottom of the via, thus achieving void-free bottom-up filling. The current density ratio K affects the filling effect; too small a K value results in insufficient reverse dissolution, while too large a K value reduces deposition efficiency. The preferred current density ratio K range is 1.5 to 3. By optimizing the pulse plating parameters, complete copper filling within the via can be achieved, forming the conductive core of the signal via.

[0062] Step S14 is surface planarization. For example... Figure 2As shown in the fourth step of sub-Figure a, the surface of the filled silicon substrate undergoes chemical mechanical polishing (CMP). CMP, or Chemical Mechanical Polishing, is a process technology that combines chemical etching and mechanical abrasion to achieve surface planarization. After electroplating, the silicon substrate surface will have an excess copper layer, and the surface may be uneven. The CMP process uses the synergistic effect of the polishing pad and polishing fluid to remove the excess copper layer and achieve a highly flat surface. Surface planarization is the foundation for subsequent surface metallization processes; good surface flatness ensures the accuracy of subsequent photolithography and etching processes.

[0063] Step S15 is surface metallization. For example... Figure 2 As shown in steps five and six of sub-Figure a, a metal layer is deposited using a sputtering process, followed by photolithography and etching to form traces and pads. Sputtering is a physical vapor deposition technique that uses high-energy ions to bombard a target, causing target atoms to sputter and deposit on the substrate surface. The metal layer is preferably a composite layer of titanium and copper; the titanium layer acts as an adhesion layer to enhance the bonding between the copper layer and the substrate, while the copper layer acts as a conductive layer. The photolithography process forms a patterned mask through the exposure and development of photoresist, and the etching process removes unwanted metal according to the mask pattern, ultimately forming the designed traces and pads. Simultaneously with the formation of the traces and pads, a ground layer is formed around the signal vias, together with the signal vias to form a coaxial shielded TSV structure. The ground layer provides a surrounding electromagnetic shield for the signal vias, effectively suppressing crosstalk between signal vias and improving signal transmission isolation. After completing the above steps, a TSV silicon adapter board is obtained.

[0064] Step S2 involves processing the Fan-out module. (Refer to...) Figure 3 This step involves embedding the frequency synthesizer chip and the radio frequency chip in an organic dielectric, using laser drilling and electroplating processes to form a multilayer RDL wiring, encapsulating them and forming a solder ball array to obtain the Fan-out module.

[0065] Step S21 involves chip embedding. The RF receiver chip, RF transmitter chip, and frequency synthesizer chip are positioned and embedded in a low-loss organic dielectric. The organic dielectric is preferably modified ABF material or other low-dielectric-constant materials, as these reduce dielectric loss during high-frequency signal transmission. Precise control of the chip's position is crucial during embedding, ensuring adequate spacing between chips to meet subsequent RDL routing requirements. Preferably, one frequency synthesizer chip and one RF receiver chip are embedded within the RF receiver module, while two frequency synthesizer chips and one RF transmitter chip are embedded within the RF transmitter module. Compared to traditional chip-mount packaging, embedded chip packaging offers advantages such as thinner package thickness, lower thermal resistance, and better electrical performance.

[0066] Step S22 involves RDL routing. For example... Figure 3As shown in sub-Figure c, microvias are formed on an organic dielectric using laser drilling, followed by copper electroplating to form a multilayer RDL wiring. Laser drilling utilizes a high-energy laser beam to ablate the organic dielectric, creating vias that enable vertical interconnections between upper and lower RDL layers and between the RDL and chip pads. Copper electroplating forms a copper wiring layer on the organic dielectric surface, which is then patterned into the designed wiring pattern using photolithography and etching processes. The number of wiring layers, n, can be determined based on interconnection requirements, with a preferred range of 3 to 5 layers. Multilayer RDL wiring enables complex signal routing and impedance matching, while high-density wiring improves the chip's I / O expansion capabilities. The line width and spacing of the RDL wiring should be determined based on signal frequency and impedance requirements; high-frequency signal traces require impedance control to ensure signal integrity.

[0067] Step S23 involves molding and ball bonding. The chip and RDL wiring are molded using encapsulation plastic, forming a solder ball array at the bottom to obtain the Fan-out module. The molding process encapsulates the chip and wiring within the molding compound, providing mechanical protection and environmental isolation. The molding compound is preferably a low-stress, high-thermal-conductivity epoxy-based composite material. After molding, a solder ball array is formed at the bottom of the Fan-out module using a ball bonding process. The solder balls are preferably SAC series lead-free solder. The solder ball array is used to achieve mechanical connection and electrical interconnection between the Fan-out module and the HTCC ceramic substrate.

[0068] Step S3 involves digital chip stacking. In this step, digital chips are mounted on the upper surface of the TSV silicon adapter board, and electrical connection between the digital chips and the TSV silicon adapter board is achieved through flip-chip bonding.

[0069] Step S31 involves digital chip mounting. At least one digital chip from an FPGA, broadband programmable RF transceiver, or RF direct acquisition transceiver is mounted onto the upper surface of a TSV silicon adapter board using a flip-chip bonding process. Flip-chip bonding is a packaging technology where the active side of the chip faces down, and the chip's pads are directly connected to the substrate pads via bumps on the chip's pads. Compared to wire bonding, flip-chip bonding offers advantages such as shorter interconnect distances, lower parasitic inductance, and lower thermal resistance, making it suitable for packaging high-frequency digital chips. During mounting, precise alignment of the chip bumps with the pads on the TSV silicon adapter board is required, followed by reflow soldering to form a reliable electrical connection.

[0070] Step S32 involves interconnecting peripheral devices. The DDR memory and IPD passive network are mounted on a TSV silicon adapter board, and electrical connections to the digital chip are achieved through a coaxial shielded TSV structure, forming a chip stack structure. The DDR memory provides high-speed data caching for the digital chip, while the IPD passive network provides power filtering and impedance matching functions. Peripheral devices are interconnected to the digital chip through wiring on the TSV silicon adapter board, and vertical signal transmission is achieved with the HTCC ceramic substrate through the coaxial shielded TSV structure. This three-dimensional stack structure shortens the signal transmission path, reduces interconnect parasitic parameters, and improves the electrical performance of the system.

[0071] Step S4 is system-level integration. (Refer to...) Figure 4 This step involves preparing an HTCC ceramic substrate with a built-in impedance matching network, mounting the TSV silicon adapter board and the Fan-out module to the corresponding mounting areas of the HTCC ceramic substrate, achieving interconnection through reflow soldering, and forming external interconnection terminals on the bottom of the HTCC ceramic substrate to obtain a broadband intermediate frequency heterogeneous integrated communication transceiver micromodule.

[0072] Step S41 involves the fabrication of the HTCC ceramic substrate. The HTCC ceramic substrate is fabricated using a multilayer green ceramic tape stacking process, forming an impedance matching network composed of microstrip lines within the HTCC ceramic substrate. The HTCC process first mixes ceramic powder with an organic binder to create green ceramic tape. Then, through-holes and metallization patterns are formed on the green ceramic tape through drilling and screen printing. After stacking multiple layers of green ceramic tape, they are co-fired at high temperature to form a dense multilayer ceramic substrate. The number of green ceramic tape layers can be determined according to the wiring layer requirements; preferably, a stack of 30 or more layers is used to meet complex wiring needs. Figure 4 As shown, the upper surface of the HTCC ceramic substrate has a TSV adapter board mounting area and a Fan-out module mounting area for subsequent module mounting. The design of the impedance matching network is crucial for ensuring the quality of high-frequency signal transmission, and appropriate impedance matching rules must be adopted according to different signal types.

[0073] When forming the impedance matching network, a combination of differential and single-ended impedance matching routing rules is adopted. The RF ADC input traces use differential impedance Z1 matching, the RF DAC output traces use differential impedance Z2 matching, the remaining differential signal lines use differential impedance Z3 matching, and the single-ended signal lines use single-ended impedance Z0 matching. Where Z1 is the ADC input differential impedance (in Ω), Z2 is the DAC output differential impedance (in Ω), Z3 is the remaining differential signal impedance (in Ω), and Z0 is the single-ended signal impedance (in Ω). The preferred value for the ADC input differential impedance Z1 is 50Ω, the preferred value for the DAC output differential impedance Z2 is 100Ω, the preferred value for the remaining differential signal impedance Z3 is 100Ω with a certain tolerance range, and the preferred value for the single-ended signal impedance Z0 is 50Ω. During routing, at least one grounding via should be provided on each side of the differential via. The grounding vias provide a stable reference ground plane for the differential signals, reducing common-mode noise. GPIO signal lines, SPI signal lines, ADC / DAC input traces, reference clock signals, and SYSREF signals are arranged in a layered isolation configuration. Different types of signals are arranged in different routing layers and isolated by a ground plane, which can effectively reduce crosstalk between signals.

[0074] Step S42 is the mounting process. Place the first solder ball and mount the TSV silicon adapter board in the TSV adapter board mounting area of ​​the HTCC ceramic substrate. Place the second solder ball and mount the Fan-out module in the Fan-out module mounting area. The first solder ball preferably uses SnAgCu series solder, and the second solder ball can use SnAg series solder. Before mounting, flux needs to be applied to the mounting area. Then, place the solder ball in the preset position, and then place the TSV silicon adapter board and Fan-out module in their respective mounting areas. The mounting equipment must have high-precision alignment capabilities to ensure accurate alignment between the module pads and the substrate pads.

[0075] Step S43 is reflow soldering. Reflow soldering is performed in a vacuum environment, controlling the peak temperature Tp and peak holding time tp; where Tp is the peak soldering temperature in °C and tp is the peak holding time in seconds. Reflow soldering is a soldering process that melts the solder by heating and forms solder joints after cooling. The peak temperature Tp needs to be higher than the melting point of the solder to ensure complete melting, but it should not be too high to avoid damaging the chip and substrate. The preferred range for the peak temperature Tp is 255 to 265 °C. The peak holding time tp should ensure that the solder fully wets the pads and forms a good intermetallic compound interface. The preferred range for the peak holding time tp is 30 to 90 seconds. The vacuum environment can reduce oxidation and bubbles during the soldering process and improve the reliability of the solder joints. After reflow soldering, a reliable mechanical connection and electrical interconnection are formed between the TSV silicon adapter board and the Fan-out module and the HTCC ceramic substrate.

[0076] Step S44 involves the formation of external terminals. External interconnect terminals are formed on the bottom of the HTCC ceramic substrate to obtain a broadband intermediate frequency heterogeneous integrated communication transceiver micromodule. The external interconnect terminals are preferably formed using a post-mounting process, and the diameter of the post-mounting can be determined according to current carrying capacity and spacing requirements. The external interconnect terminals are used to achieve electrical connection and mechanical fixation between the micromodule and external systems.

[0077] Following step S44, step S45, heat dissipation encapsulation, can be performed. A cover plate is bonded to the HTCC ceramic substrate using thermally conductive adhesive. The thickness hg of the thermally conductive adhesive is determined based on heat dissipation requirements; where hg is the thermally conductive adhesive thickness in μm. The thermally conductive adhesive should be made of a material with high thermal conductivity to ensure that the heat generated by the chip can be effectively conducted to the cover plate. If the thermally conductive adhesive thickness hg is too thin, it may lead to uneven adhesive layer or insufficient bonding strength; if it is too thick, it will increase thermal resistance. The preferred range for the thermally conductive adhesive thickness hg is 100 to 300 μm. The cover plate can be made of a metal material such as copper or aluminum alloy. Metal cover plates have good thermal conductivity and can conduct the chip's heat to an external heat sink or the environment. After heat dissipation encapsulation is completed, a complete broadband intermediate frequency heterogeneous integrated communication transceiver micromodule is obtained.

[0078] Reference Figure 5 and Figure 6 The prepared micro-modules were subjected to performance testing and thermal reliability analysis. For example... Figure 5 Subgraph a shows the curve of insertion loss S21 as a function of frequency, which characterizes the signal loss during transmission from the input to the output. Figure 5 Sub-figure b shows the curve of return loss S11 as a function of frequency. This curve characterizes the impedance matching of the input port; a smaller return loss indicates better impedance matching. The micro-module fabricated using the three-dimensional packaging method of this invention exhibits low insertion loss and good impedance matching characteristics over a wide bandwidth, meeting the application requirements of broadband intermediate frequency communication systems. Figure 6 The figure shown is a thermal reliability analysis result diagram, displaying the temperature field distribution cloud map of the system under a given ambient temperature. Through reasonable heat dissipation design, the junction temperature rise of the micromodule under operating conditions can be controlled at a low level, ensuring the long-term reliable operation of the system.

[0079] This invention achieves high-density packaging of digital and radio frequency (RF) chips through three-dimensional heterogeneous integration of a TSV silicon interposer, a Fan-out module, and an HTCC ceramic substrate. The coaxial shielded TSV structure effectively reduces signal transmission loss and inter-channel crosstalk, while the high-density RDL wiring of the Fan-out package meets the high-speed interconnection requirements of the RF chip. The impedance matching network of the HTCC ceramic substrate ensures the integrity of signal transmission. The overall packaging method is mature, highly feasible, and suitable for broadband intermediate frequency (IF) communication systems.

[0080] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A broadband intermediate frequency heterogeneous integrated communication transceiver micromodule, characterized in that, include: The TSV silicon adapter board uses a high-resistivity silicon substrate. The high-resistivity silicon substrate has a coaxial shielded TSV structure. The coaxial shielded TSV structure includes an inner signal via and an outer ground layer surrounding the inner signal via. The inner signal via is filled with a conductive material, and an insulating layer is provided between the inner wall of the inner signal via and the conductive material. The Fan-out module includes an RF receiver module and an RF transmitter module. The RF receiver module contains a frequency synthesizer chip and an RF receiver chip. The RF transmitter module contains a frequency synthesizer chip and an RF transmitter chip. The Fan-out module has a multi-layer redistribution layer (RDL) that is electrically connected to each chip. The HTCC ceramic substrate has a multilayer stacked structure. Its upper surface is provided with a TSV adapter board mounting area and a Fan-out module mounting area. The TSV silicon adapter board is connected to the TSV adapter board mounting area through a first solder ball array. The Fan-out module is connected to the Fan-out module mounting area through a second solder ball array. The HTCC ceramic substrate integrates an impedance matching network. The bottom of the HTCC ceramic substrate is provided with external interconnect terminals. A digital chip is disposed on the upper surface of the TSV silicon adapter board, and vertical signal transmission is achieved with the HTCC ceramic substrate through the coaxial shielded TSV structure.

2. The broadband intermediate frequency heterogeneous integrated communication transceiver micro-module according to claim 1, characterized in that: The RF receiver module contains one frequency synthesizer chip and one RF receiver chip, and the RF transmitter module contains two frequency synthesizer chips and one RF transmitter chip. The bottom of the Fan-out module is provided with a third solder ball array, which is electrically connected to the multilayer RDL and is used to achieve signal interconnection with the HTCC ceramic substrate.

3. The broadband intermediate frequency heterogeneous integrated communication transceiver micro-module according to claim 1, characterized in that: The impedance matching network includes a microstrip line, which is used for impedance matching between radio frequency signals and digital signals; the TSV silicon adapter board is also provided with a DDR memory and an IPD passive network, which are electrically connected to the digital chip through the coaxial shielded TSV structure.

4. The three-dimensional packaging method for a broadband intermediate frequency heterogeneous integrated communication transceiver micromodule as described in any one of claims 1-3, characterized in that, Includes the following steps: S1. TSV silicon adapter board fabrication: A high-resistivity silicon substrate is selected, and a through-hole array is formed on the high-resistivity silicon substrate by deep reactive ion etching process. After depositing an insulating layer on the inner wall of the through-hole, conductive material is filled. After surface planarization treatment, traces and pads are formed on the surface of the high-resistivity silicon substrate, and a ground layer is formed around the signal through-hole to form a coaxial shielded TSV structure, thus obtaining the TSV silicon adapter board. S2, Fan-out module fabrication: The frequency synthesizer chip and the radio frequency chip are embedded in an organic dielectric, and multi-layer RDL wiring is formed by laser drilling and electroplating processes. After plastic encapsulation, a solder ball array is formed to obtain the Fan-out module. S3. Digital chip stacking: The digital chip is mounted on the upper surface of the TSV silicon adapter board, and the electrical connection between the digital chip and the TSV silicon adapter board is achieved by flip-chip bonding process. S4. System-level integration: Prepare an HTCC ceramic substrate with a built-in impedance matching network, mount the TSV silicon adapter board and the Fan-out module to the corresponding mounting areas of the HTCC ceramic substrate, and interconnect them by reflow soldering. Form external interconnection terminals on the bottom of the HTCC ceramic substrate to obtain a broadband intermediate frequency heterogeneous integrated communication transceiver micro-module.

5. The three-dimensional packaging method according to claim 4, characterized in that, Step S1 specifically includes: S11. Deep Silicon Etching: A high-resistivity silicon substrate is selected, and a via array is formed on the high-resistivity silicon substrate by deep reactive ion etching (DRIE) process. During etching, the aspect ratio R is controlled as R=H / D, where R is the aspect ratio; H is the etching depth (μm); and D is the via diameter (μm). The aspect ratio R ranges from 8 to 12. S12, Insulating layer deposition: A SiO2 insulating layer is deposited on the inner wall of the through hole using plasma-enhanced chemical vapor deposition (PECVD). S13. Conductive material filling: Copper is filled into the through-hole using a pulse electroplating process. During pulse electroplating, a forward current density Jf and a reverse current density Jr are set, and the current density ratio K = Jr / Jf is controlled, where K is the current density ratio; Jr is the reverse current density (A / dm³). 2 Jf represents the forward current density (A / dm). 2 The current density ratio K ranges from 1.5 to 3. S14. Surface planarization: Chemical mechanical polishing (CMP) is performed on the surface of the filled silicon substrate. S15. Surface metallization: A metal layer is deposited using a sputtering process, and traces and pads are formed by photolithography and etching. A ground layer is formed around the signal vias to form a coaxial shielded TSV structure, resulting in a TSV silicon adapter board.

6. The three-dimensional encapsulation method according to claim 4, characterized in that, Step S2 specifically includes: S21. Chip embedding: Positioning and embedding the RF receiver chip, RF transmitter chip and frequency synthesizer chip into a low-loss organic medium; S22, RDL wiring: Laser drilling is used to form micro-vias on the organic medium, and copper plating is used to form multi-layer RDL wiring. The number of wiring layers n ranges from 3 to 5 layers. S23, Molding and Ball Placement: The chip and RDL wiring are encapsulated using encapsulation plastic, and a solder ball array is formed on the bottom to obtain the Fan-out module.

7. The three-dimensional encapsulation method according to claim 4, characterized in that, Step S3 specifically includes: S31. Digital chip mounting: At least one digital chip from the FPGA, broadband programmable RF transceiver, or RF direct acquisition transceiver is mounted on the upper surface of the TSV silicon adapter board by flip-chip bonding process. S32. Interconnection of peripheral devices: The DDR memory and IPD passive network are mounted on the TSV silicon adapter board, and the electrical connection with the digital chip is achieved through the coaxial shielded TSV structure to form a chip stack structure.

8. The three-dimensional encapsulation method according to claim 4, characterized in that, Step S4 specifically includes: S41. HTCC ceramic substrate preparation: HTCC ceramic substrate is prepared by multilayer green ceramic tape stacking process, and an impedance matching network composed of microstrip lines is formed in the HTCC ceramic substrate. S42, Mounting: Place the first solder ball in the TSV adapter board mounting area of ​​the HTCC ceramic substrate and mount the TSV silicon adapter board; place the second solder ball in the Fan-out module mounting area and mount the Fan-out module. S43. Reflow Soldering: Reflow soldering is performed in a vacuum environment. During soldering, the peak temperature Tp and the peak holding time tp are controlled, where Tp is the peak soldering temperature (°C); tp is the peak holding time (s); the value of Tp ranges from 255 to 265°C, and the value of tp ranges from 30 to 90s. S44. External terminal formation: External interconnection terminals are formed on the bottom of the HTCC ceramic substrate to obtain a broadband intermediate frequency heterogeneous integrated communication transceiver micro-module.

9. The three-dimensional packaging method according to claim 8, characterized in that, When forming the impedance matching network in step S41, the following wiring rules are adopted: The RF ADC input traces are matched using differential impedance Z1, the RF DAC output traces are matched using differential impedance Z2, the remaining differential signal lines are matched using differential impedance Z3, and the single-ended signal lines are matched using single-ended impedance Z0. Here, Z1 is the ADC input differential impedance (Ω); Z2 is the DAC output differential impedance (Ω); Z3 is the impedance of the remaining differential signals (Ω); and Z0 is the single-ended signal impedance (Ω). Z1 is 50Ω, Z2 is 100Ω, Z3 is 100Ω ± 5%, and Z0 is 50Ω. During routing, at least one grounding hole is set on each side of the differential via. GPIO signal lines, SPI signal lines, ADC / DAC input traces, reference clock signals, and SYSREF signals are routed using layered isolation.

10. The three-dimensional packaging method according to claim 8, characterized in that, The step S44 is followed by: S45. Heat dissipation packaging: The cover plate is bonded to the HTCC ceramic substrate using thermally conductive adhesive. The coating thickness hg of the thermally conductive adhesive is determined according to the heat dissipation requirements, where hg is the thickness of the thermally conductive adhesive (μm). The value of hg ranges from 100 to 300 μm, thus completing the packaging of the broadband intermediate frequency heterogeneous integrated communication transceiver micro-module.

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