Bidirectional interface configuration for memory

Abstract

Devices and methods can be related to configuration of an interface protocol to a memory. The interface protocol can define commands received by a memory device with a transceiver, receiver, and / or transmitter of an interface of the memory device. The interface protocol used by the memory device can be implemented with a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by the memory device can be selected by setting a mode register of the memory device.

Description

Technical Field

[0001] This disclosure generally relates to memory, and more specifically, to devices and methods associated with configuring a bidirectional interface to memory. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory may require power to maintain its data and includes, in particular, random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and includes, in particular, NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), and resistive variable memory (e.g., phase-change random access memory (PCRAM)), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM).

[0003] Memory is also used as a volatile and non-volatile data storage device for a wide range of electronic applications, including (but not limited to) personal computers, portable memory sticks, digital cameras, cellular phones, portable music players (e.g., MP3 players), movie players, and other electronic devices. Memory cells can be arranged in arrays, wherein the arrays are used in memory devices.

[0004] Commands can be provided to the memory using an interface protocol. Commands provided to the memory can be predefined, and these commands can be used to control the functions of the memory. Attached Figure Description

[0005] Figure 1 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure.

[0006] Figure 2 This is a block diagram of a device in the form of a computing system including interfaces, according to several embodiments of the present disclosure.

[0007] Figure 3A This is a block diagram of a memory device including a transmitter, a receiver, and a transceiver according to several embodiments of the present disclosure.

[0008] Figure 3B This is a block diagram of a memory device including multiple transceivers according to several embodiments of the present disclosure.

[0009] Figure 4Example flowcharts illustrating methods for performing operations in a memory according to several embodiments of the present disclosure.

[0010] Figure 5 An example machine is described, within which a set of instructions can be executed to cause the machine to perform the various methodologies discussed herein. Detailed Implementation

[0011] This disclosure includes apparatus and methods relating to configuring a bidirectional interface to a memory. The memory device may include multiple transceivers, transmitters, and / or receivers. The memory device may receive multiple signals via multiple pins. For example, the memory device may receive commands, addresses, and / or data, as well as other signals, via multiple pins. As used herein, multiple pins physically couple the memory device to a computing system. The pins of the memory device are the physical interface that enables communication between the memory device and the computing system. Transceivers, transmitters, and / or receivers may be coupled to the physical interface (e.g., the pins of the memory device) so that the transceivers, transmitters, and / or receivers receive or transmit signals via the physical interface.

[0012] In various instances, the protocol defines the use of transceivers, transmitters, and / or receivers. This protocol is described herein as an interface protocol. An interface protocol defines how transceivers, transmitters, and / or receivers are used and / or what types of data are received through them. For example, an interface protocol may define a first transceiver for commands, a second transceiver for addresses, and / or a third transceiver for data, as well as other uses for the transceivers. The interface protocol may also define whether the transceiver is used for directional or bidirectional data transmission.

[0013] An interface protocol defines communication between a memory device and devices external to the memory device. If devices communicate as defined by the interface protocol, then they may conform to the interface protocol. An interface protocol can be defined to enable a memory device to receive and process signals from multiple devices external to the memory device, where these devices are manufactured by multiple different vendors. Examples of interface protocols are the Double Data Rate (DDR5) standard and other standards such as DDR4 or any other DDR standard. In various examples, the interface protocol may be developed by organizations such as JEDEC, which enables any device compatible with the interface protocol to communicate with each other without incurring the expense of defining new interface protocols for multiple devices.

[0014] An interface protocol's ability to define communication between devices may be limited by the number of pins a memory device can have and / or the hardware coupled to those pins (e.g., transceivers, transmitters, and / or receivers for the memory device). The hardware coupled to the pins (e.g., transceivers, transmitters, and / or receivers) may also define the pin's directionality. In various examples, some pins may be configured to receive signals without transmitting signals or to transmit signals without receiving signals. The hardware coupled to the pins may be configured to function as defined by the interface protocol. For example, a pin configured to receive signals may be coupled to a receiver but not to a transmitter and / or transceiver.

[0015] In several instances, the directionality of a memory device's interface can be overcome by implementing multiple interface protocols and by implementing hardware to enable those protocols. As used herein, an interface may include buses, pins, and transceivers, transmitters, and / or receivers that couple one device to different devices. For example, an interface may include a host's transceivers, transmitters, and / or receivers, a bus that couples the host to the memory device, pins of the memory device, and transceivers, transmitters, and / or receivers of the memory device. Multiple interface protocols can be implemented in a single device using the same decoder and multiple multiplexers to reroute signals to different parts of the memory device.

[0016] Figure 1 This is a block diagram of a device in the form of a computing system 100 including a memory device 103, according to several embodiments of the present disclosure. As used herein, for example, the memory device 103, the memory array 110, and / or the host 102 may also be considered as a "device" individually.

[0017] In this example, computing system 100 includes a host 102 coupled to memory device 103 via interface 104. Computing system 100 may be a personal laptop, desktop computer, digital camera, mobile phone, memory card reader, or Internet of Things (IoT) enabled device, and other types of systems. Host 102 may include several processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing memory 103. Computing system 100 may include a separate integrated circuit, or both host 102 and memory device 103 may be on the same integrated circuit. For example, host 102 may be a system controller for a memory system including multiple memory devices 103, wherein the system controller provides access to the respective memory devices 103 through another processing resource (e.g., a central processing unit (CPU)).

[0018] exist Figure 1In the example shown, host 102 is responsible for executing the operating system (OS) and / or various applications that can be loaded thereto (e.g., loaded thereto from memory device 103 via control circuitry system 105). The OS and / or the various applications can be loaded from memory device 103 by providing access commands from host 102 to memory device 103 for accessing data including the OS and / or the various applications. Host 102 can also access data used by the OS and / or the various applications by providing access commands to memory device 103 for retrieving the data used to execute the OS and / or the various applications.

[0019] For clarity, computing system 100 has been simplified to focus on features particularly relevant to this disclosure. Memory array 110 may be, for example, a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and / or NOR flash array. Array 110 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digital lines or data lines). Although in Figure 1 The illustration shows a single array 110, but the embodiments are not limited thereto. For example, the memory device 103 may include several arrays 110 (e.g., several banks of memory cells in a DRAM).

[0020] Memory device 103 includes an address circuitry 106 for latching address signals provided via interface 104. The interface may include, for example, a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). The data bus, address bus, and command bus are respectively located in… Figure 2 , 3AInterfaces 204 and 304 are shown in 3B. This protocol can be custom or proprietary, or interface 104 can employ a first interface protocol, which can be a standardized interface protocol, such as Peripheral Component Interconnect High Speed ​​(PCIe), Gen-Z Interconnect, Accelerator Cache Coherent Interconnect (CCIX), or the like. In various instances, a standardized interface protocol can refer to an interface protocol defined in a standard. A non-standardized interface protocol (e.g., a second interface protocol) can refer to an interface protocol defined by a different standard or not defined by a standard. Address signals are received and decoded by row decoder 108 and column decoder 112 to access memory array 110. Data can be read from memory array 110 by sensing voltage and / or current changes on a sensing line using sensing circuitry system 111. Sensing circuitry system 111 may include, for example, a sensing amplifier capable of reading and latching a page (e.g., a row) of data from memory array 110. I / O circuitry system 107 can be used for bidirectional data communication with host 102 via interface 104. The read / write circuitry 113 is used to write data to or read data from the memory array 110. As an example, the circuitry 113 may include various drivers, latching circuitry, etc.

[0021] Control circuitry system 105 decodes signals provided by host 102. These signals may be commands provided by host 102. These signals may include chip enable signals, write enable signals, and address latch signals, used to control operations performed on memory array 110, including data read operations, data write operations, and data erase operations. In various embodiments, control circuitry system 105 is responsible for executing instructions from host 102. Control circuitry system 105 may include a state machine, sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination of the three. In some instances, host 102 may be a controller external to memory device 103. For example, host 102 may be a memory controller coupled to the processing resources of a computing device. Data may be provided to and / or from memory array 110 via data line 116.

[0022] In various embodiments, the control circuitry system 105 may include a command circuitry system and / or an address circuitry system. The command circuitry system and / or address circuitry system may include one or more decoders configured to decode command signals and / or address signals. Command signals may include commands provided to the memory device 103. Address signals may include addresses of the memory array 110. The control circuitry system 105 may also include a response circuitry system, which may include an encoder for encoding response signals. In various embodiments, the control circuitry system 105 may further include… Figure 1The diagram shows an I / O circuit system 107 located outside the control circuit system 105. The I / O circuit system 107 may include encoders and decoders for encoding and decoding data signals provided to and / or provided by the memory device 103.

[0023] In various examples, the functionality of memory device 103 can be controlled by host 102. For example, host 102 can provide commands to memory device 103 via interface 104 for reading memory array 110 and / or writing to memory array 110 and other functionalities of memory array 110. However, the implemented interface protocol may not define commands for controlling the functionalities of sensing circuitry system 111.

[0024] Figure 2 This is a block diagram of a device in the form of a computing system 200 including interfaces, according to several embodiments of the present disclosure. Interfaces 204-1, 204-2, 204-3, 204-4, and 204-5, referred to as interface 204, may include hardware configured to facilitate the transfer of signals between means such as memory controller 224 and memory device 203. Memory controller 224 may be incorporated into a host, for example... Figure 1 Host 102.

[0025] Interface 204 may include a first portion 204-1, a second portion 204-2, a third portion 204-3, a fourth portion 204-4, and a fifth portion 204-5. The first portion 204-1 and the second portion 204-2 of interface 204 may include a first bus. The third portion 204-3 and the fourth portion 204-4 of interface 204 may include a second bus. The fifth portion 204-5 of interface 204 may include a third bus. The first bus may be configured to transmit signals, including command signals and / or address signals, to memory device 203. Therefore, the first bus may include a command bus and / or an address bus. The second bus may be configured to transmit error signals (e.g., response signals). The third bus may be configured to transmit data stored by or to be stored by memory device 203. Therefore, the third bus may include a data bus. Data transmitted via the third bus may be stored in the memory array of memory device 203. The bus may include a physical connection between a memory controller 224 incorporated in the host and memory device 203.

[0026] Interface protocol (its implementation scheme is in) Figure 2(Not shown) This can be used to configure the first and second buses as unidirectional. The first bus can provide signals from the memory controller 224 to the memory device 203. The second bus can provide signals from the memory device 203 to the memory controller 224. The third bus can be bidirectional. Bidirectionality can be achieved by implementing software / firmware and hardware capable of transmitting and receiving signals in the memory device 203 and the memory controller 224.

[0027] Different interface protocols (their implementation schemes are in) Figure 2 (As shown in the diagram) can be used to configure the first bus, second bus, and third bus. The first bus can be configured such that the first part of interface 204-1 is unidirectional and the second part of interface 204-2 is bidirectional. The second bus can be configured such that the third part of interface 204-3 is unidirectional and the fourth part of interface 204-4 is bidirectional. The fifth part of interface 204-5 can remain bidirectional, as configured by different interface protocols and as specified by the implementation scheme of the interface protocols.

[0028] The first portion of interface 204-1 can be used to transmit command signals and / or address signals to memory device 203. The second portion of interface 204-2 can be used to transmit command signals, address signals, and / or data signals to memory controller 224 and memory device 203, and to transmit command signals, address signals, and / or data signals from memory controller 224 and memory device 203. The third portion of interface 204-3 can be used to transmit response signals from memory controller 224 to memory device 203. The fourth portion of interface 204-4 can be used to transmit response signals and / or data signals to memory controller and memory device 203, and to transmit response signals and / or data signals from memory controller and memory device 203. As used herein, response signals may include signals responding to command and / or address signals provided by a first bus or data signals provided by a third bus. As used herein, response signals may include error signals describing errors encountered by memory device 203, and other types of response signals. Response signals may also include signals indicating the completion of an operation performed by memory device 203. For example, a response signal can signal the completion of a write operation that stores data in the memory array of memory device 203. The fifth part of interface 204-5 can transmit data signals to and from memory controller 224 and memory device 203.

[0029] Interface 204 may include multiple pins coupling memory device 203 to memory controller 224. The pins of interface 204 may be made of metal, such as copper, nickel, and / or gold, and other types of metal. The pins of interface 204 may include top pins and bottom pins. The top and bottom pins may include pins formed on either side of the circuit board, and it is not desired to restrict the orientation of the pins on memory device 203.

[0030] The pins of interface 204 may include power supply (PWR) pins, ground (GND) pins, signal pins, and other possible types of pins. The PWR pin provides power to memory device 203, the GND pin provides a ground connection to memory device 203, and the signal pins provide signals to and from memory device 203.

[0031] Command signals, address signals, response signals, and / or data signals can be referred to as commands, addresses, responses, and / or data. Memory device 203 can receive commands, addresses, responses, and / or data via interface 204. Although Figure 2 The examples provided describe two different implementations of two different interface protocols, but multiple interface protocols can be implemented by updating the software / firmware and hardware of memory controller 224 and / or memory device 203. For example, three different interface protocols can be implemented to configure interface 204.

[0032] Each of the interface protocols may be incompatible with any of the other interface protocols. For example, the first interface protocol may be incompatible with the second interface protocol. For instance, the first interface protocol may not be used to configure the memory controller 224 and memory device 203 to provide data signals through the second part of interface 204-2, while the second interface protocol may be used to configure the memory controller 224 and memory device 203 to provide data signals through the second part of interface 204-2. Although the memory device 203 can be configured with the second interface protocol, which is incompatible with the first interface protocol, the memory device 203 can operate in accordance with the first interface protocol by avoiding signal transmission via the second part of interface 204-2.

[0033] As used herein, if pins configured by either the first or second interface protocol have the same orientation, then the first and second interface protocols are compatible with each other. If pins configured by the first and second interface protocols have different orientations (e.g., directional versus bidirectional), then the first and second interface protocols are incompatible with each other. Pins are also compatible with each other if they are configured to convey the same type of signal. For example, if a pin conveys a control signal under the first interface protocol and conveys both control and data signals under the second interface protocol, then the first and second interface protocols are incompatible.

[0034] Figure 3A This is a block diagram of a memory device 303A including a transmitter 344, a receiver 345, and a transceiver 346 according to several embodiments of the present disclosure. Figure 3A The interface 304 includes a first part 304-1, a second part 304-2, a third part 304-3, a fourth part 304-4, and a fifth part 304-5. Interface 304 couples the memory device 303A to a host or memory controller 324A. The memory device 303A can be configured using a first interface protocol.

[0035] Portions 304-1 and 304-2 may be unidirectional, allowing them to receive signals but not transmit them. Portions 304-1 and 304-2 are coupled to a receiver 341 configured to receive command / address signals. Receiver 341 may provide the received signals to command / address circuitry 338 of control circuitry 305. Command / address circuitry 338 may be configured to decode signals (e.g., command signals and / or address signals). Control circuitry 305 may also include response circuitry 339, which may be configured to encode response signals. Figure 3A and 3B The command and / or address circuitry 338 and the response circuitry 339 are identified as being incorporated into the control circuitry 305. However, the command and / or address circuitry 338 and the response circuitry 339 may be implemented externally to the control circuitry 305.

[0036] The response signal can be transmitted by transmitter 342. Portions of interfaces 304-3 and 304-4 can be unidirectional. Portion 304-5 can be bidirectional, enabling transceiver 343 to transmit and receive data signals. Transceiver 343 can be coupled to I / O circuitry 307 and can receive signals from the data lines of memory device 303A. In various embodiments, command and / or address circuitry 338, response circuitry 228, and / or I / O circuitry 307 may include encoders and / or decoders for encoding and / or decoding signals provided by interface 304. In at least one embodiment, interface 304 may include command receiver 341, response transmitter 342, and data transceiver 343. For example, interface 304 may be described as including command receiver 341, response transmitter 342, and / or data transceiver 343. Interface 304 can also be described as including a command transmitter 344, a response receiver 345, and / or a data transceiver 346.

[0037] Interface 304 couples memory device 303A to memory controller 324A. For example, portions of interfaces 304-1 and 304-2 couple transmitter 344 of memory controller 324A to receiver 341 of memory device 303A. Portions 304-3 and 304-4 couple receiver 345 of memory controller 324A to transmitter 342 of memory device 303A. Portion 304-5 couples transceiver 346 of memory controller 324A to transceiver 343 of memory device 303A.

[0038] Figure 3B This is a block diagram of a memory device 303B including multiple transceivers 333, 334, 335, 347, 348 and 349 according to several embodiments of the present disclosure. Figure 3B It includes an interface 304 comprising Part 6 304-6, Part 7 304-7, Part 8 304-8, Part 9 304-9, and Part 10 304-10. Interface 304 can couple the memory device 303B to a host or memory controller 324B.

[0039] Memory device 303B and Figure 3A The memory device 303A differs from the memory device 303B in that the memory device 303B implements the second interface protocol, while the memory device 303A implements the first interface protocol. The memory device 303A and memory device 303B also differ in that the memory device 303B implements a command transceiver 333 and a response transceiver 334 to respectively replace... Figure 3A The command receiver 341 and response transmitter 342 are shown in the diagram. The memory devices 303A and 303B also differ in that: Figure 3AThe receiver 341 and transmitter 342 are used to communicate with Figure 3B The transceivers 333 and 334 are coupled to the command and address circuit system 338, the response circuit system 339, and the I / O circuit system 307 in different ways.

[0040] Configuring the memory device 303B using the second interface protocol can configure the portion of interface 304 that was configured as unidirectional using the first interface protocol as bidirectional. For example, portions of interfaces 304-7 and 304-9 are configured bidirectionally for the memory device 303B, which is consistent with... Figure 3A The interfaces 304-2 and 304-4 for memory device 303A are configured as unidirectional counterparts, with the latter two being opposite. To achieve a bidirectional configuration, memory device 303B may include transceivers 333 and 334 (instead of receiver 341 and transmitter 342 as shown for memory device 303A). Similarly, memory controller 324B may be enabled to achieve bidirectionality for portions of interfaces 304-7 and 304-9 by implementing transceivers 347 and 348 of memory controller 324B instead of transmitter 344 and receiver 345 of memory controller 324A.

[0041] Interface 304 corresponding to memory device 303B can be configured such that portions of interface 304 are unchanged compared to interface 304 corresponding to memory device 303A. For example, portions of interfaces 304-6 and 304-8 corresponding to the first portion of the command bus and the second portion of the response bus can remain unidirectional, corresponding to portions of interfaces 304-1 and 304-3. Thus, various embodiments can implement a combination of receiver and transceiver to couple memory device 303B to portions of interfaces 304-6 and 304-7 instead of transceiver 333, as shown in association with memory device 303B. Interface 304 can also be described as including command transceiver 347, response transceiver 348, data transceiver 349, command transceiver 333, response transceiver 334, and / or data transceiver 335.

[0042] Transceivers 333 and 334 can be coupled to MUX 336 and 337, respectively. MUX 336 can couple transceiver 333 to command / address circuit system 338 and I / O circuit system 307. MUX 337 can couple transceiver 334 to response circuit system 339 and I / O circuit system 307.

[0043] For example, a portion of interface 304-6 can be coupled to command / address circuitry 338 via MUX 336, as configured by an interface protocol. A portion of interface 304-7 can be coupled to command / address circuitry 338 and / or I / O circuitry 307 via MUX 336, as configured by an interface protocol. Although not shown, different interface protocols can be used to configure MUX 336 to couple a portion of interface 304-6 to command / address circuitry 338 and / or I / O circuitry 307, and to couple a portion of interface 304-7 to command / address circuitry 338.

[0044] Considering that the I / O circuit system 307 can provide data for transmission, coupling a portion of interface 304-7 to the I / O circuit system 307 provides the capability for bidirectional communication. Transmitting data using the pins corresponding to portions of interfaces 304-7, 304-9, and 304-10 allows for greater data processing capacity compared to transmitting data using the pins corresponding to portions of interface 304-10.

[0045] Specific configurations of MUX 336 and 337 can be controlled using mode register 331. Specific configurations of transceivers 333 and 334 can also be controlled by mode register 331, such that command transceiver 333, response transceiver 334, MUX 336, and MUX 337 are coupled to mode register 331. As used herein, mode register 331 may contain registers (e.g., memory) accessible externally to memory device 303B. Mode register 331 can be set or reset using commands provided via open pins of an interface protocol. For example, the interface protocol may define pins as open so that commands not defined by the interface protocol can be provided through said open pins. Read or write commands provided to memory device 303B can be used to set or reset mode register 331.

[0046] In some instances, setting mode register 331 may be associated with selecting a first interface protocol, while resetting mode register 331 may be associated with selecting a second interface protocol. Although mode register 331 is marked, a single mode register 331 may be implemented. Implementing multiple mode registers 331 provides the ability to implement more than two interface protocols. Mode register 331 can be configured to select the interface protocols that can be used to configure MUX 336 and 337 and transceivers 333 and 334. For example, in response to setting mode register 331, MUX 336 and 337 can couple specific transceivers 333, 334, and / or 335 of interface 304 to command / address circuitry 338, response circuitry 339, and / or I / O circuitry 307. In response to setting or resetting mode register 331, transceivers 333 and 334 can be configured to transmit or receive signals to accommodate multiple interface protocols.

[0047] Mode register 331 can be set by a host including memory controller 324B. For example, memory device 303B can receive command signals via a portion of interface 304-6 to set mode register 331 to configure memory device 303B using an interface protocol. Memory controller 324B may also include memory configured to select an interface protocol. For example, memory controller 324B may also include a separate mode register (e.g., not shown) for selecting an interface protocol. The interface protocol selected by memory controller 324B may conform to the interface protocol selected for memory device 303B. For example, in response to a command to set or reset mode register 331 to select an interface protocol, memory controller 324B can set or reset mode register 324B or memory within the host to select the corresponding interface protocol. Therefore, memory within memory controller 324B can also be used to control transceivers 347, 348, and 349.

[0048] Figure 4 Example flowcharts illustrate methods for performing operations in memory according to several embodiments of the present disclosure. At 460, a first signal for setting a mode register of a memory device to configure the transceiver as unidirectional using a first interface protocol can be received via a transceiver. The first signal can be received from a host. For example, the first signal can be received via a command bus. At 462, a second signal can be received at the memory device, wherein the transceiver is configured as bidirectional using a second interface protocol in response to a receive selection of the second signal, and wherein the first interface protocol is different from the second interface protocol. In various examples, for example, the second signal can be an access command. The access command can be processed by the memory device. The second signal can be processed using the second interface protocol in response to the mode register being set.

[0049] In 464, a third signal can be transmitted via the transceiver of the memory device in response to the setting mode register and the receipt of the second signal. The third signal can be a response signal indicating that the second signal has been processed using the second interface protocol. For example, the third signal can indicate the completion of a command recognized by the second signal.

[0050] The method may further include avoiding configuration of different transceivers in response to the reception of the first signal. That is, different transceivers may be used unidirectionally or bidirectionally using both the first and second interface protocols. Different transceivers may also be configured in response to the reception of the first signal, wherein the different transceivers are configured unidirectionally using both the second and first interface protocols. Regarding the configuration of the various transceivers, receivers, and transmitters, whether or not the first or second interface protocol is implemented, the transceivers, receivers, and transmitters can remain unchanged.

[0051] Different transceivers may be configured to receive and / or transmit signals, including commands, addresses, data, and / or error signals, in response to the implementation of the second interface protocol. Different transceivers may be limited to receiving or transmitting commands, addresses, data, or error signals in response to the implementation of the first interface protocol.

[0052] In each instance, transceiver configuration is performed independently of the configuration of different transceivers using the first interface protocol and the second interface protocol. For example, the memory device can avoid configuring different transceivers in response to the reception of the first signal, wherein different transceivers are configured as bidirectional regardless of whether they are configured as unidirectional or bidirectional.

[0053] In various examples, a mode register coupled to the memory device is configured to execute a setup command and, in response to executing a first setup command, cause the memory device to operate in a first mode according to a first interface protocol. The mode register can also be configured to, in response to executing a second setup command, cause the memory device to operate in a second mode according to a second interface protocol. A particular transceiver can operate unidirectionally according to the first interface protocol. A particular transceiver can operate bidirectionally according to the second interface protocol.

[0054] A specific transceiver can be coupled to a command bus and configured to receive signals according to a first interface protocol and to receive and transmit signals according to a second interface protocol. Signals can be received and transmitted via the command bus. A specific transceiver can be configured to receive and transmit data via a data bus. A specific transceiver can be configured to receive and transmit commands via the command bus. A specific transceiver can be configured to receive and transmit addresses via an address bus. A specific transceiver can be configured to receive and transmit error signals via pins of a memory device.

[0055] The memory device may also include a MUX coupled to a particular transceiver and configured to couple the particular transceiver to a particular decoder. For example, a multiplexer may be further configured to provide signals received from a first decoder to the particular transceiver in response to the implementation of a first setup command.

[0056] The multiplexer may also be coupled to a mode register. The multiplexer may also be configured, in response to the implementation of a first setting command, to provide signals received via a specific transceiver to a first decoder, wherein the signals are provided without needing to be provided to a second decoder. The multiplexer may also be configured, in response to the implementation of a second setting command, to provide signals received from a specific transceiver to a second decoder and signals received from the second decoder to a specific transceiver. The first setting command can be used to select a first interface protocol, and the second setting command can be used to select a second interface protocol.

[0057] The multiplexer, in response to the implementation of a second setting command, can provide signals received from a specific transceiver to a first decoder and signals received from a specific transceiver to a second decoder. The multiplexer can also, in response to the implementation of a second setting command, provide signals received from the second decoder to a specific transceiver. The first interface protocol may conform to a standard, and the second interface protocol may not conform to a standard. Therefore, the first interface protocol may be referred to as a compliant interface protocol, and the second interface protocol may be referred to as a non-compliant interface protocol.

[0058] In various embodiments, the host may include a first transceiver and means coupled to the first transceiver. The means may be configured to use a first signal to configure the mode register of the memory device to configure the second transceiver of the memory device using a second interface protocol, which is transmitted via the first transceiver. That is, the host can control which interface protocol is implemented in the memory device and the host. The same interface protocol can be selected in the host and the memory device to allow the host and the interface protocol to correctly decode and encode signals using either the first interface protocol or the second interface protocol.

[0059] The host can cause a first transceiver, configured using a first interface protocol, to be configured using a second interface protocol. The first transceiver may be unidirectional before configuration and bidirectional after configuration. The first interface protocol and the second interface protocol are incompatible. The host can also cause a second signal to be transmitted to a memory device using both the first and second transceivers. The host can also cause a third signal to be received via the first transceiver in response to the transmission of the second signal, the first signal, and in response to configuration of the first transceiver. The first and second transceivers can be coupled to the host's memory device.

[0060] Figure 5 An example machine illustrating computer system 540 is described, within which a set of instructions can be implemented to cause the machine to perform various methodologies discussed herein. In various embodiments, computer system 540 may correspond to a system (e.g., Figure 1 A computing system 100 that includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1 (a memory device 103) or a device that can be used to perform controller operations (e.g., Figure 1 (Control circuitry 105). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0061] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while a single machine is described, the term "machine" should also be considered as any collection of machines that individually or jointly execute one (or more) instructions to perform any or more of the methodologies discussed herein.

[0062] The example computer system 540 includes a processing device 502, a main memory 504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 506 (e.g., flash memory, static random access memory (SRAM)), and a data storage system 518, which communicate with each other via a bus 530.

[0063] Processing device 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 502 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein. Computer system 540 may further include a network interface device 508 for communication via network 520.

[0064] Data storage system 518 may include machine-readable storage medium 524 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 526 or software embodying any or more of the methodologies or functions described herein. Instructions 526 may also reside wholly or at least partially in main memory 504 and / or processing device 502 during their execution by computer system 540, which also constitute machine-readable storage medium.

[0065] In one embodiment, instruction 526 includes implementation corresponding to Figure 1The machine-readable storage medium 524 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0066] As used herein, "several things" can refer to one or more of such things. For example, "several memory devices" can refer to one or more memory devices. "Multiple things" would prefer to be two or more. Additionally, the designation "N" as used herein (especially with respect to reference element symbols in the figures) indicates that several specific features so indicated may be included in several embodiments of this disclosure.

[0067] The figures in this document follow a numbering convention, where the first digit or the first few digits correspond to the drawing number and the remaining digits identify elements or components in the figure. Similar elements or components between different figures can be identified by using similar digits. It should be understood that elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, the scale and relative size of the elements provided in the figures are intended to illustrate various embodiments of this disclosure and are not intended to be limiting.

[0068] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements that achieve the same computational results may be used instead of the specific embodiments shown. This disclosure is intended to cover adjustments or variations of the various embodiments of this disclosure. It should be understood that the foregoing description is illustrative and non-limiting. Those skilled in the art will understand, upon reviewing the foregoing description, combinations of the foregoing embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications in which the foregoing structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims and the full scope of the equivalents entitled to by such claims.

[0069] In the foregoing detailed embodiments, various features are grouped into a single embodiment for the purpose of simplifying this disclosure. This approach of the disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those expressly cited in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed embodiments, wherein each claim is an independent, separate embodiment.

Claims

1. A device for configuring a bidirectional interface to a memory, comprising: Memory devices (103, 203, 303A, 303B) comprising multiple transceivers (333, 334, 335, 343, 346, 347, 348, 349); and Mode register (331), coupled to the memory device, wherein the mode register is configured to: Execute the configuration command; In response to the implementation of the first setting command, the memory device is caused to operate in a first mode according to the first interface protocol; as well as In response to the implementation of the second setting command, the memory device is caused to operate in the second mode according to the second interface protocol; According to the first interface protocol, a specific transceiver (333, 334, 335, 343, 346, 347, 348, 349) operates unidirectionally; and According to the second interface protocol, a specific transceiver operates bidirectionally; and The first interface protocol is incompatible with the second interface protocol.

2. The device of claim 1, wherein the particular transceiver is coupled to a command bus (104, 204-1, 204-2, 204-3, 204-4, 204-5, 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7, 304-8, 304-9, 304-10) and configured to: Receive signals according to the first interface protocol; and Signals are received and transmitted according to the second interface protocol, wherein the signals are received and transmitted via the command bus.

3. The device of claim 2, wherein the particular transceiver is configured to receive and transmit data via a data bus (104, 204-1, 204-2, 204-3, 204-4, 204-5, 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7, 304-8, 304-9, 304-10).

4. The device of claim 2, wherein the particular transceiver is configured to receive and transmit commands via the command bus.

5. The device of claim 2, wherein the particular transceiver is configured to receive and transmit addresses via an address bus (104, 204-1, 204-2, 204-3, 204-4, 204-5, 304-1, 304-2, 304-3, 304-4, 304-5, 304-6, 304-7, 304-8, 304-9, 304-10).

6. The device of claim 2, wherein the particular transceiver is configured to receive and transmit signals indicating errors via pins of the memory device.

7. The device according to any one of claims 1 to 6, further comprising a multiplexer (MUX) (336, 337) coupled to the particular transceiver and configured to couple the particular transceiver to the particular decoder (307, 338, 339).

8. The device of claim 7, wherein the multiplexer is further configured to provide a signal received from the particular decoder to the particular transceiver in response to the implementation of the first setting command.

9. The device of claim 7, wherein the multiplexer is further coupled to the mode register and further configured to provide a signal received via the particular transceiver to the particular decoder in response to the implementation of the first setting command, wherein the signal is provided without having to provide the signal to different decoders (307, 338, 339).

10. The device of claim 9, wherein the multiplexer is further configured to provide signals received from the particular transceiver to the different decoders and to provide signals received from the different decoders to the particular transceiver in response to the implementation of the second setting command.

11. The apparatus of claim 9, wherein the multiplexer is further configured to: The signal received from the specific transceiver is provided to the specific decoder; In response to the implementation of the second setting command, the signal received from the specific transceiver is provided to the different decoders; and In response to the implementation of the second setting command, the signals received from the different decoders are provided to the specific transceiver.

12. The device according to any one of claims 1 to 6, wherein the first interface protocol conforms to a standard, and the second interface protocol does not conform to the standard.

13. A method for configuring a bidirectional interface to a memory, comprising: The transceiver (333, 334, 335, 343, 346, 347, 348, 349) receives a mode register (331) for setting the memory devices (103, 203, 303A, 303B) to configure the transceiver as a unidirectional first signal using the first interface protocol; A second signal is received at the memory device, wherein the transceiver is configured to be bidirectional using a second interface protocol in response to a receive selection of the second signal, and wherein the first interface protocol is incompatible with the second interface protocol; and A third signal is transmitted via the transceiver of the memory device in response to setting the mode register and receiving the second signal.

14. The method of claim 13, further comprising avoiding configuration of different transceivers (333, 334, 335, 343, 346, 347, 348, 349) in response to the reception of the first signal.

15. The method of claim 13, further comprising configuring different transceivers (333, 334, 335, 343, 346, 347, 348, 349) in response to the reception of the first signal, wherein the different transceivers use the second interface protocol and the first interface protocol is configured to be unidirectional.

16. The method of claim 15, further comprising configuring the different transceivers to receive signals including commands, addresses, or error signals in response to implementing the second interface protocol.

17. The method according to any one of claims 13 to 16, further comprising avoiding the configuration of different transceivers (333, 334, 335, 343, 346, 347, 348, 349) in response to the reception of the first signal, wherein the different transceivers are configured to be bidirectional regardless of whether the transceivers are configured to be unidirectional or bidirectional.

18. The method according to any one of claims 13 to 16, wherein the second signal is received via the transceiver, and wherein the third signal indicates the completion of a command identified by the second signal.

19. A device for configuring a bidirectional interface to a memory, comprising: First transceiver (333, 334, 335, 343, 346, 347, 348, 349); Devices (224, 324A, 324B), coupled to the first transceiver and configured to: A first signal is transmitted via the first transceiver to configure a second transceiver (333, 334, 335, 343, 346, 347, 348, 349) of a memory device (103, 203, 303A, 303B) using a second interface protocol to set the mode register (331) of the memory device. The first transceiver configured using the first interface protocol is configured using the second interface protocol such that the first transceiver is unidirectional before being configured and bidirectional after being configured, and wherein the first interface protocol is incompatible with the second interface protocol. This causes the second signal to be transmitted to the memory device using the first transceiver and the second transceiver; and In response to the transmission of the second signal, the first signal, and the configuration of the first transceiver, a third signal is received via the first transceiver.

20. The device of claim 19, wherein the first transceiver and the second transceiver couple the memory device to the device.

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