Power supply device

Abstract

To reduce switching loss while saturation of magnetic flux density of a transformer is suppressed.SOLUTION: A power supply unit includes: a first bridge circuit; a transformer; a second bridge circuit; and a control unit for outputting a plurality of primary-side drive pulses which switch-operate a switch element in the first bridge circuit and a plurality of secondary-side drive pulses which switch-operate a switch element in the second bridge circuit and controls a phase difference between the first bridge circuit and the second bridge circuit to control DC voltage outputted from the second bridge circuit. The control unit performs control for adding a pattern in which all switch elements of a high side becomes an on-state or off-state and all switch elements of a low side becomes a state opposite to the switch elements of the high side to at least one of the plurality of primary-side drive pulses and the plurality of secondary-side drive pulses. and reducing a switching frequency of the switch element to be lower than a reference value.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a power supply device. [Background technology]

[0002] Patent Document 1 describes a DC-DC converter of the DAB (Dual Active Bridge) type. The DAB converter is a converter that can transmit power in both directions by controlling the phase between a drive pulse that drives a bridge circuit on the primary side and a drive pulse that drives a bridge circuit on the secondary side. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 5,027,264 Summary of the Invention [Problem to be solved by the invention]

[0004] In the DAB method, there are regions where soft switching operation is not possible (for example, light load regions), and switching losses occur in these regions. One possible way to suppress switching losses is to lower the switching frequency. However, in a DAB DC-DC converter, simply lowering the switching frequency can cause the magnetic flux density of the transformer to saturate.

[0005] An object of the present disclosure is to provide a power supply device that can reduce switching loss while suppressing saturation of magnetic flux density in a transformer. [Means for solving the problem]

[0006] The power supply device of the present disclosure includes a first bridge circuit including a plurality of arms each having a high-side switch element and a low-side switch element, and converting a DC voltage into an AC voltage and outputting the AC voltage; a transformer including a first winding and a second winding, wherein the AC voltage output from the first bridge circuit is input to the first winding and an induced AC voltage is output from the second winding; a second bridge circuit including a plurality of arms each having a high-side switch element and a low-side switch element, and converting the AC voltage output from the second winding of the transformer into a DC voltage and outputting the DC voltage to a load; and a power supply circuit that outputs a plurality of primary-side drive pulses to the switch elements in the first bridge circuit, switching the switch elements in the first bridge circuit. and a control unit that performs a switching operation of the switch elements in the second bridge circuit, outputs a plurality of secondary-side drive pulses to the switch elements in the second bridge circuit, performs a switching operation of the switch elements in the second bridge circuit, and controls a phase difference between the first bridge circuit and the second bridge circuit, thereby controlling a DC voltage output from the second bridge circuit, wherein the control unit adds a pattern to at least one of the plurality of primary-side drive pulses and the plurality of secondary-side drive pulses, in which all of the high-side switch elements are in an on state or an off state and all of the low-side switch elements are in an opposite state to the high-side switch elements, and performs control to lower the switching frequency of the switch elements below a reference value.

[0007] In the power supply device of the present disclosure, the control unit controls the duty ratio of at least one of the primary side drive pulse and the secondary side drive pulse to be lower than a reference value, thereby lowering the switching frequency of the switch element below a reference value.

[0008] In the power supply device of the present disclosure, the control unit controls the duty ratio to be lower than the reference value based on a ratio between a DC voltage input to the first bridge circuit and a DC voltage output from the second bridge circuit, thereby lowering the switching frequency of the switch element below the reference value.

[0009] In the power supply device of the present disclosure, the control unit calculates the switching frequency based on the phase difference between the first bridge circuit and the second bridge circuit and the duty ratio.

[0010] In the power supply device of the present disclosure, the first bridge circuit and the second bridge circuit are three-phase bridge circuits, and the transformer is a three-phase transformer. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to reduce switching loss while suppressing saturation of magnetic flux density in a transformer. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a power supply device according to the first embodiment. [Figure 2] FIG. 2 is a diagram illustrating an example of the configuration of a transformer unit according to the first embodiment. [Figure 3] FIG. 3 is a diagram illustrating an example of the configuration of the control unit according to the first embodiment. [Figure 4] FIG. 4 is a diagram for explaining a control method of a power supply device according to a comparative example. [Figure 5] FIG. 5 is a diagram for explaining a control method for the power supply device according to the first embodiment. [Figure 6] FIG. 6 is a diagram for explaining the definition of duty according to the first embodiment. [Figure 7] FIG. 7 is a diagram illustrating an example of the configuration of a control unit according to the second embodiment. [Figure 8] FIG. 8 is a diagram for explaining a method for setting a switching frequency according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Note that the present disclosure is not limited to these embodiments, and in the following embodiments, the same components are designated by the same reference numerals, and redundant description will be omitted.

[0014] [First embodiment] An example of the configuration of the power supply device according to the first embodiment will be described using Fig. 1. Fig. 1 is a diagram showing an example of the configuration of the power supply device according to the first embodiment.

[0015] 1 is a DAB type power supply device according to the first embodiment. The power supply device 100 receives a primary voltage V1, which is a DC voltage output from a power supply 1 and smoothed by a smoothing capacitor 2. The DC voltage output from the power supply device 100 is smoothed by a smoothing capacitor 3, and a secondary voltage V2 is input to a load 4.

[0016] The power supply device 100 includes a first bridge circuit 10, a second bridge circuit 20, a reactor 31, a reactor 32, a reactor 33, a transformer unit 40, and a control unit 50.

[0017] The first bridge circuit 10 includes a first arm 10a, a second arm 10b, and a third arm 10c. The first bridge circuit 10 is a three-phase bridge circuit including three arms. The first arm 10a is a U-phase arm. The second arm 10b is a V-phase arm. The third arm 10c is a W-phase arm. The phase difference between the first arm 10a and the second arm 10b is 120 degrees. The phase difference between the second arm 10b and the third arm 10c is 120 degrees. The phase difference between the third arm 10c and the first arm 10a is 120 degrees.

[0018] First arm 10a includes switch element 11 and switch element 12. Second arm 10b includes switch element 13 and switch element 14. Third arm 10c includes switch element 15 and switch element 16.

[0019] The switch elements 11, 13, and 15 are high-side switch elements, while the switch elements 12, 14, and 16 are low-side switch elements.

[0020] The switch elements 11 to 16 are, for example, but not limited to, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). The switch elements 11 to 16 may also be silicon power devices, GaN power devices, SiC power devices, IGBTs (Insulated Gate Bipolar Transistors), etc.

[0021] Switch elements 11 to 16 have parasitic diodes (body diodes). A parasitic diode is a pn junction between the back gate and the source and drain of a MOSFET. The parasitic diode can be used as a freewheeling diode to release transient back electromotive force when the transistor is turned off. In addition to the parasitic diode, a diode element may be added between the drain and source of each transistor.

[0022] The source terminal of switch element 11 is electrically connected to the drain terminal of switch element 12. The drain terminal of switch element 11 is electrically connected to the drain terminal of switch element 13. The source terminal of switch element 12 is electrically connected to the source terminal of switch element 14.

[0023] The source terminal of switch element 13 is electrically connected to the drain terminal of switch element 14. The drain terminal of switch element 13 is electrically connected to the drain terminal of switch element 15. The source terminal of switch element 14 is electrically connected to the source terminal of switch element 16.

[0024] The source terminal of the switch element 15 is electrically connected to the drain terminal of the switch element 16 .

[0025] A connection point N1 between the drain terminal of switch element 11, the drain terminal of switch element 13, and the drain terminal of switch element 15 is one input terminal of power supply device 100. A connection point N2 between the source terminal of switch element 12, the source terminal of switch element 14, and the source terminal of switch element 16 is the other input terminal of power supply device 100.

[0026] The connection point N1 is electrically connected to the high potential side of the smoothing capacitor 2. The connection point N2 is electrically connected to the low potential side of the smoothing capacitor 2. A DC voltage smoothed by the smoothing capacitor 2 is input between the connection point N1 and the connection point N2.

[0027] A connection point N3 between the source terminal of switch element 11 and the drain terminal of switch element 12 is a first output terminal of the first bridge circuit 10. A connection point N4 between the source terminal of switch element 13 and the drain terminal of switch element 14 is a second output terminal of the first bridge circuit 10. A connection point N5 between the source terminal of switch element 15 and the drain terminal of switch element 16 is a third output terminal of the first bridge circuit 10.

[0028] The second bridge circuit 20 includes a first arm 20a, a second arm 20b, and a third arm 20c. The second bridge circuit 20 is a three-phase bridge circuit including three arms. The first arm 20a is a U-phase arm. The second arm 20b is a V-phase arm. The third arm 20c is a W-phase arm. The phase difference between the first arm 20a and the second arm 20b is 120 degrees. The phase difference between the second arm 20b and the third arm 20c is 120 degrees. The phase difference between the third arm 20c and the first arm 20a is 120 degrees.

[0029] First arm 20a includes switch element 21 and switch element 22. Second arm 20b includes switch element 23 and switch element 24. Third arm 20c includes switch element 25 and switch element 26.

[0030] The switch element 21, the switch element 23, and the switch element 25 are high-side switch elements, while the switch element 22, the switch element 24, and the switch element 26 are low-side switch elements.

[0031] The switch elements 21 to 26 are, for example, but not limited to, MOSFETs. The switch elements 21 to 26 may also be silicon power devices, GaN power devices, SiC power devices, IGBTs, etc.

[0032] Switch elements 21 to 26 have parasitic diodes (body diodes). A parasitic diode is a pn junction between the back gate and the source and drain of a MOSFET. The parasitic diode can be used as a freewheel diode to release transient back electromotive force when the transistor is turned off. In addition to the parasitic diode, a diode element may be added between the drain and source of each transistor.

[0033] The source terminal of switch element 21 is electrically connected to the drain terminal of switch element 22. The drain terminal of switch element 21 is electrically connected to the drain terminal of switch element 23. The source terminal of switch element 22 is electrically connected to the source terminal of switch element 24.

[0034] The source terminal of switch element 23 is electrically connected to the drain terminal of switch element 24. The drain terminal of switch element 23 is electrically connected to the drain terminal of switch element 25. The source terminal of switch element 24 is electrically connected to the source terminal of switch element 26.

[0035] The source terminal of the switch element 25 is electrically connected to the drain terminal of the switch element 26 .

[0036] A connection point N6 between the source terminal of switch element 21 and the drain terminal of switch element 22 is a first input terminal of the second bridge circuit 20. A connection point N7 between the source terminal of switch element 23 and the drain terminal of switch element 24 is a second input terminal of the second bridge circuit 20. A connection point N8 between the source terminal of switch element 25 and the drain terminal of switch element 26 is a third input terminal of the second bridge circuit 20.

[0037] A connection point N9 between the drain terminal of switch element 21, the drain terminal of switch element 23, and the drain terminal of switch element 25 is one output terminal of power supply device 100. A connection point N10 between the source terminal of switch element 22, the source terminal of switch element 24, and the source terminal of switch element 26 is the other output terminal of power supply device 100.

[0038] The connection point N9 is electrically connected to the high potential side of the smoothing capacitor 3. The connection point N10 is electrically connected to the low potential side of the smoothing capacitor 3. The secondary side voltage V2 of the smoothing capacitor 3 becomes the output voltage of the power supply device 100.

[0039] The high potential side of the smoothing capacitor 3 is electrically connected to the high potential side of the load 4. The low potential side of the smoothing capacitor 3 is electrically connected to the low potential side of the load 4.

[0040] One end of the reactor 31 is electrically connected to the connection point N3, and the other end of the reactor 31 is electrically connected to the transformer unit 40.

[0041] One end of the reactor 32 is electrically connected to the connection point N4, and the other end of the reactor 32 is electrically connected to the transformer unit 40.

[0042] One end of the reactor 33 is electrically connected to the connection point N5, and the other end of the reactor 33 is electrically connected to the transformer unit 40.

[0043] The transformer unit 40 includes a first winding, a second winding, and a core. The transformer unit 40 is a type of transformer.

[0044] FIG. 2 is a diagram illustrating an example of the configuration of a transformer unit according to the first embodiment. As illustrated in FIG. 2, the transformer unit 40 includes a transformer 40a, a transformer 40b, and a transformer 40c. In the first embodiment, the transformer unit 40 is a three-phase transformer. In the example illustrated in FIG. 2, the transformer unit 40 is a Y-connected three-phase transformer. Although FIG. 2 illustrates the transformer unit 40 as a Y-connected three-phase transformer, the present disclosure is not limited thereto. For example, the transformer unit 40 may be a delta-connected three-phase transformer.

[0045] The transformer 40a includes a first winding 41a, a second winding 42a, a core 43a, a first terminal 44a, and a second terminal 45a. The transformer 40a is a U-phase transformer.

[0046] The first winding 41a is a primary winding. The second winding 42a is a secondary winding. The first winding 41a and the second winding 42a are wound around a core 43a. One end of the first winding 41a is electrically connected to a first terminal 44a. The first terminal 44a is electrically connected to the other end of the reactor 31. One end of the second winding 42a is electrically connected to a second terminal 45a. The second terminal 45a is electrically connected to a connection point N6.

[0047] The transformer 40b includes a first winding 41b, a second winding 42b, a core 43b, a first terminal 44b, and a second terminal 45b. The transformer 40b is a V-phase transformer.

[0048] The first winding 41b is a primary winding. The second winding 42b is a secondary winding. The first winding 41b and the second winding 42b are wound around a core 43b. One end of the first winding 41b is electrically connected to a first terminal 44b. The first terminal 44b is electrically connected to the other end of the reactor 32. One end of the second winding 42b is electrically connected to a second terminal 45b. The second terminal 45b is electrically connected to a connection point N7.

[0049] The transformer 40c includes a first winding 41c, a second winding 42c, a core 43c, a first terminal 44c, and a second terminal 45c. The transformer 40c is a W-phase transformer.

[0050] The first winding 41c is a primary winding. The second winding 42c is a secondary winding. The first winding 41c and the second winding 42c are wound around a core 43c. One end of the first winding 41c is electrically connected to a first terminal 44c. The first terminal 44c is electrically connected to the other end of the reactor 33. One end of the second winding 42c is electrically connected to a second terminal 45c. The second terminal 45c is electrically connected to a connection point N8.

[0051] The other end of the first winding 41a, the other end of the first winding 41b, and the other end of the first winding 41c are electrically connected to each other. The other end of the second winding 42a, the other end of the second winding 42b, and the other end of the second winding 42c are electrically connected to each other.

[0052] The control unit 50 controls the first bridge circuit 10 and the second bridge circuit 20. The control unit 50 includes, for example, an information processing device such as a CPU (Central Processing Unit) or an MPU (Micro Processing Unit), and a storage device such as a RAM (Random Access Memory) or a ROM (Read Only Memory). The control unit 50 may be realized by, for example, an integrated circuit such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field Programmable Gate Array). The control unit 50 may also be realized by a combination of hardware and software.

[0053] The control unit 50 switches the switch elements 11 to 16 between the on state and the off state by outputting a primary side drive pulse to the first bridge circuit 10. Specifically, the control unit 50 switches the switch elements 11 to 16 to the on state by outputting a high level primary side drive pulse from the switch element 11 to the gate terminal of the switch element 16. The control unit 50 switches the switch elements 11 to 16 to the off state by outputting a low level primary side drive pulse from the switch element 11 to the gate terminal of the switch element 16.

[0054] The control unit 50 switches the switch elements 21 to 26 between the on state and the off state by outputting a secondary-side drive pulse to the second bridge circuit 20. Specifically, the control unit 50 switches the switch elements 21 to 26 to the on state by outputting a high-level secondary-side drive pulse from the switch element 21 to the gate terminal of the switch element 26. The control unit 50 switches the switch elements 21 to 26 to the off state by outputting a low-level secondary-side drive pulse from the switch element 21 to the gate terminal of the switch element 26.

[0055] [Controller configuration example] An example of the configuration of the control unit according to the first embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of the configuration of the control unit according to the first embodiment.

[0056] As shown in FIG. 3, the control unit 50 includes an error calculation unit 51, a phase difference calculation unit 52, a drive pulse generation unit 53, a duty ratio calculation unit 54, a primary side pulse pattern addition unit 55, a secondary side pulse pattern addition unit 56, a primary side pulse drive unit 57, and a secondary side pulse drive unit 58.

[0057] The following describes the process performed by the control unit 50 when controlling the output voltage from the second bridge circuit 20.

[0058] The error calculation unit 51 calculates the error e between the voltage command value Vcom and the secondary voltage V2 based on the voltage command value Vcom commanded to the second bridge circuit 20 and the secondary voltage V2 actually output by the second bridge circuit 20.

[0059] The phase difference calculation unit 52 calculates the phase difference φ between the first bridge circuit 10 and the second bridge circuit 20 based on the error e.

[0060] The drive pulse generation unit 53 generates a plurality of first drive pulses S1 and a plurality of second drive pulses S2 based on the phase difference φ. The drive pulse generation unit 53 outputs the first drive pulses S1 to the primary pulse pattern addition unit 55. The drive pulse generation unit 53 outputs the second drive pulses S2 to the secondary pulse pattern addition unit 56.

[0061] The duty ratio calculation unit 54 calculates the voltage ratio between the primary voltage V1 of the first bridge circuit 10 and the secondary voltage V2 of the second bridge circuit 20 based on the primary voltage V1 and the secondary voltage V2.

[0062] The duty ratio calculation unit 54 calculates the duty ratio of a pulse pattern that simultaneously turns on at least all of the high-side switch elements and all of the low-side switch elements of the first bridge circuit 10, based on the voltage ratio between the primary-side voltage V1 and the secondary-side voltage V2. In this embodiment, the duty ratio of such a pulse pattern is called a first duty ratio D1. The first duty ratio D1 takes a value ranging from 0 to 1.

[0063] The duty ratio calculation unit 54 calculates the duty ratio of a pulse pattern that simultaneously turns on at least all of the high-side switch elements and all of the low-side switch elements of the second bridge circuit 20, based on the voltage ratio between the primary-side voltage V1 and the secondary-side voltage V2. In this embodiment, the duty ratio of such a pulse pattern is called a second duty ratio D2. The second duty ratio D2 takes a value ranging from 0 to 1.

[0064] The primary-side pulse pattern adding unit 55 adds a pulse pattern of a first duty ratio D1 to the plurality of first drive pulses S1 to generate a first output pulse S5. The first output pulse S5 is a reference signal that forms the basis of the drive pulse output from the switch element 11 to the gate terminal of the switch element 16 of the first bridge circuit 10.

[0065] The secondary-side pulse pattern adding unit 56 adds a pulse pattern of a second duty ratio D2 to the plurality of second drive pulses S2 to generate second output pulses S6. The second output pulses S6 are a reference signal that forms the basis of the drive pulses output from the switch elements 21 of the second bridge circuit 20 to the gate terminals of the switch elements 26.

[0066] Based on the first output pulse S5, the primary side pulse driver 57 generates a plurality of primary side drive pulses S7 to which a pulse pattern of a first duty ratio D1 is added, for switching between the on state and the off state of the switch elements 11 to 16 of the first bridge circuit 10. The primary side pulse driver 57 outputs the plurality of primary side drive pulses S7 to the gate terminals of the switch elements 11 to 16 of the first bridge circuit 10.

[0067] The secondary-side pulse driver 58 outputs a plurality of secondary-side drive pulses S8 to which a pulse pattern of a second duty ratio D2 is added, in order to switch between the on state and the off state of the switch elements 21 to 26 of the second bridge circuit 20, based on the second output pulse S6. The secondary-side pulse driver 58 outputs the plurality of secondary-side drive pulses S8 to the gate terminals of the switch elements 21 to 26 of the second bridge circuit 20.

[0068] (Control method of comparative example) Before describing this embodiment, a control method for a power supply device according to a comparative example will be described. Fig. 4 is a diagram for explaining the control method for a power supply device according to the comparative example. The configuration of the power supply device according to the comparative example is the same as that of power supply device 100 shown in Fig. 1.

[0069] Figure 4 shows the pulse patterns of each part on the secondary side and the output voltage of each phase. The switching frequency of the secondary drive pulse input to each switch element is constant. The duty ratio of the secondary drive pulse input to each part is 0.5.

[0070] Waveform 111 represents a secondary drive pulse input to the gate terminal of switch element 21. Waveform 112 represents a secondary drive pulse input to the gate terminal of switch element 22. Waveform 113 represents a secondary drive pulse input to the gate terminal of switch element 23. Waveform 114 represents a secondary drive pulse input to the gate terminal of switch element 24. Waveform 115 represents a secondary drive pulse input to the gate terminal of switch element 25. Waveform 116 represents a secondary drive pulse input to the gate terminal of switch element 26. Waveform 117 represents the output voltage from first arm 20a. Waveform 118 represents the output voltage from second arm 20b. Waveform 119 represents the output voltage from third arm 20c. Time t0 to time t6 constitutes the control pattern for one cycle of power supply device 100.

[0071] Between time t0 and time t3, a low-level secondary-side drive pulse is input to the gate terminal of switch element 21. Switch element 21 is in the off state between time t0 and time t3. Between time t3 and time t6, a high-level secondary-side drive pulse is input to the gate terminal of switch element 21. Switch element 21 is in the on state between time t3 and time t6. Between time t6 and time t9, a low-level secondary-side drive pulse is input to the gate terminal of switch element 21. Switch element 21 is in the off state between time t6 and time t9.

[0072] From time t0 to time t3, a high-level secondary-side drive pulse is input to the gate terminal of switch element 22. Switch element 22 is in the ON state from time t0 to time t3. From time t3 to time t6, a low-level secondary-side drive pulse is input to the gate terminal of switch element 22. Switch element 22 is in the OFF state from time t3 to time t6. From time t6 to time t9, a high-level secondary-side drive pulse is input to the gate terminal of switch element 22. Switch element 22 is in the ON state from time t6 to time t9.

[0073] Between time t0 and time t1, a low-level secondary-side drive pulse is input to the gate terminal of the switch element 23. The switch element 23 is in the off state between time t0 and time t1. Between time t1 and time t4, a high-level secondary-side drive pulse is input to the gate terminal of the switch element 23. The switch element 23 is in the on state between time t1 and time t4. Between time t4 and time t7, a low-level secondary-side drive pulse is input to the gate terminal of the switch element 23. The switch element 23 is in the off state between time t4 and time t7. Between time t7 and time t9, a high-level secondary-side drive pulse is input to the gate terminal of the switch element 23. The switch element 23 is in the on state between time t7 and time t9.

[0074] Between time t0 and time t1, a high-level secondary-side drive pulse is input to the gate terminal of the switch element 24. The switch element 24 is in the ON state between time t0 and time t1. Between time t1 and time t4, a low-level secondary-side drive pulse is input to the gate terminal of the switch element 24. The switch element 24 is in the OFF state between time t1 and time t4. Between time t4 and time t7, a high-level secondary-side drive pulse is input to the gate terminal of the switch element 24. The switch element 24 is in the ON state between time t4 and time t7. Between time t7 and time t9, a low-level secondary-side drive pulse is input to the gate terminal of the switch element 24. The switch element 24 is in the OFF state between time t7 and time t9.

[0075] A high-level secondary-side drive pulse is input to the gate terminal of switch element 25 from time t0 to time t2. Switch element 25 is in the ON state from time t0 to time t2. A low-level secondary-side drive pulse is input to the gate terminal of switch element 25 from time t2 to time t5. Switch element 25 is in the OFF state from time t2 to time t5. A high-level secondary-side drive pulse is input to the gate terminal of switch element 25 from time t5 to time t8. Switch element 25 is in the ON state from time t5 to time t8. A low-level secondary-side drive pulse is input to the gate terminal of switch element 25 from time t8 to time t9. Switch element 25 is in the OFF state from time t8 to time t9.

[0076] A low-level secondary-side drive pulse is input to the gate terminal of the switch element 26 from time t0 to time t2. The switch element 26 is in the off state from time t0 to time t2. A high-level secondary-side drive pulse is input to the gate terminal of the switch element 26 from time t2 to time t5. The switch element 26 is in the on state from time t2 to time t5. A low-level secondary-side drive pulse is input to the gate terminal of the switch element 26 from time t5 to time t8. The switch element 26 is in the off state from time t5 to time t8. A high-level secondary-side drive pulse is input to the gate terminal of the switch element 26 from time t8 to time t9. The switch element 26 is in the on state from time t8 to time t9.

[0077] As shown by waveforms 111 to 116, in the control method according to the comparative example, there is no pattern in which all of the high-side switch elements, switch element 21, switch element 23, and switch element 25, are in the on state or the off state at the same time.

[0078] The shaded area R1 indicates the voltage-time product of the voltage applied to the transformer unit 40 by the first arm 20a from time t6 to time t9.

[0079] (Control method of the first embodiment) A control method for the power supply device according to the first embodiment will be described with reference to Fig. 5. Fig. 5 is a diagram for explaining a control method for the power supply device according to the first embodiment.

[0080] Waveform 121 represents a secondary drive pulse input to the gate terminal of switch element 21. Waveform 122 represents a secondary drive pulse input to the gate terminal of switch element 22. Waveform 123 represents a pulse input to the secondary drive gate terminal of switch element 23. Waveform 124 represents a secondary drive pulse input to the gate terminal of switch element 24. Waveform 125 represents a secondary drive pulse input to the gate terminal of switch element 25. Waveform 126 represents a secondary drive pulse input to the gate terminal of switch element 26. Waveform 127 represents the output voltage from first arm 20a. Waveform 128 represents the output voltage from second arm 20b. Waveform 129 represents the output voltage from third arm 20c.

[0081] As shown in FIG. 5, waveforms 121 to 126 have additional pulse patterns P1 to P9 added to waveforms 111 to 116 shown in FIG.

[0082] The additional pattern P1 is an additional pattern added between time t0 and time t1. The additional pattern P1 is a pulse pattern in which a low-level secondary-side drive pulse is input to each gate terminal of each switch element on the high side, and a high-level secondary-side drive pulse is input to each gate terminal of each switch element on the low side. That is, in the additional pattern P1, switch elements 21, 23, and 25 are all in the OFF state, and switch elements 22, 24, and 26 are all in the ON state. Although the additional pattern P1 is shown as being added in the center of the interval between time t0 and time t1, the present disclosure is not limited to this.

[0083] The additional pattern P2 is an additional pattern added between time t1 and time t2. The additional pattern P2 is a pulse pattern in which a high-level secondary-side drive pulse is input to each gate terminal of each switch element on the high side, and a low-level secondary-side drive pulse is input to each gate terminal of each switch element on the low side. That is, in the additional pattern P2, switch elements 21, 23, and 25 are all in the ON state, and switch elements 22, 24, and 26 are all in the OFF state. Although the additional pattern P2 is shown as being added in the middle between time t1 and time t2, the present disclosure is not limited to this.

[0084] Additional pattern P3 is an additional pattern that is added between time t2 and time t3. The pulse pattern of additional pattern P3 is the same as the pulse pattern of additional pattern P1, and therefore a description thereof will be omitted.

[0085] Additional pattern P4 is an additional pattern that is added between time t3 and time t4. The pulse pattern of additional pattern P4 is the same as the pulse pattern of additional pattern P2, and therefore a description thereof will be omitted.

[0086] Additional pattern P5 is an additional pattern that is added between time t4 and time t5. The pulse pattern of additional pattern P5 is the same as the pulse pattern of additional pattern P1, and therefore a description thereof will be omitted.

[0087] Additional pattern P6 is an additional pattern that is added between time t5 and time t6. The pulse pattern of additional pattern P6 is the same as the pulse pattern of additional pattern P2, and therefore a description thereof will be omitted.

[0088] Additional pattern P7 is an additional pattern that is added between time t6 and time t7. The pulse pattern of additional pattern P7 is the same as the pulse pattern of additional pattern P1, and therefore a description thereof will be omitted.

[0089] Additional pattern P8 is an additional pattern that is added between time t7 and time t8. The pulse pattern of additional pattern P8 is the same as the pulse pattern of additional pattern P2, and therefore a description thereof will be omitted.

[0090] Additional pattern P9 is an additional pattern that is added between time t8 and time t9. The pulse pattern of additional pattern P9 is the same as the pulse pattern of additional pattern P1, and therefore a description thereof will be omitted.

[0091] The waveforms 121 to 126 have smaller duty ratios than the waveforms 111 to 116 shown in FIG. 4, respectively.

[0092] FIG. 6 is a diagram for explaining the definition of the duty ratio according to the first embodiment. In FIG. 6, the horizontal axis represents time, and the vertical axis represents the signal level input to the gate terminal of the switch element. A period T is one control period. A duty ratio section Tduty is the period of an additional pattern section. In the first embodiment, the duty ratio D is defined as follows: D=(Period T / 2-Duty ratio interval Tduty) / (Period T / 2)...(1)

[0093] In the first embodiment, as shown in equation (1), the longer the duty ratio section Tduty, the smaller the duty ratio D becomes.

[0094] The shaded region R2 indicates the voltage-time product of the voltage applied by the first arm 20a to the transformer unit 40 from time t6 to time t9. Region R2 is smaller than region R1 shown in FIG. 4 because additional patterns P7, P8, and P9 are added to waveforms 121 to 126. That is, in the power supply device 100 according to the first embodiment, the voltage applied to the transformer unit 40 is smaller than that in the comparative example, and therefore the magnetic flux density of the transformer unit 40 is also reduced compared to that in the comparative example. Note that the voltage applied to the transformer unit 40 by the second arm 20b and the third arm 20c is the same as the voltage applied to the transformer unit 40 by the first arm 20a, and therefore a description thereof will be omitted.

[0095] As described above, in the first embodiment, a pulse pattern is added in which all of the high-side switch elements are turned on or off, and all of the low-side switch elements are turned in the opposite state to the high-side switch elements, thereby making it possible to reduce the magnetic flux density generated in the transformer unit 40.

[0096] [Second embodiment] Next, a power supply device according to a second embodiment of the present disclosure will be described. The power supply device according to the second embodiment has the same circuit configuration as the power supply device 100 shown in Fig. 1, but differs in the configuration of the control unit 50.

[0097] In the first embodiment, the switching frequency of the pulses input to each switch element is described as being constant. In the second embodiment, the switching frequency is lowered to suppress the switching loss of each switch element.

[0098] In the DAB power supply device according to the comparative example, if the switching frequency is lowered to suppress switching loss in a region where soft switching operation is not possible, the magnetic flux density of the transformer may normally become saturated.

[0099] In contrast to this, in the power supply device 100, as described above, the magnetic flux density of the transformer unit 40 can be made smaller than that of the comparative example. Therefore, in the second embodiment, the switching frequency can be lowered to reduce switching loss without saturating the magnetic flux density of the transformer unit 40.

[0100] [Controller configuration example] An example of the configuration of the control unit according to the second embodiment will be described with reference to Fig. 7. Fig. 7 is a diagram showing an example of the configuration of the control unit according to the second embodiment.

[0101] As shown in FIG. 7, the control unit 50A includes an error calculation unit 51, a phase difference calculation unit 52, a drive pulse generation unit 53A, a duty ratio calculation unit 54A, a primary side pulse drive unit 57A, a secondary side pulse drive unit 58A, a frequency calculation unit 59, and a pulse pattern addition unit 60.

[0102] The duty ratio calculation unit 54A calculates the duty ratio D based on the input / output voltages and the phase difference calculation result by the phase difference calculation unit 52. The duty ratio calculation unit 54A calculates the duty ratio D based on the voltage ratio between the primary side voltage V1 and the secondary side voltage V2, and the phase difference φ between the first bridge circuit 10 and the second bridge circuit 20.

[0103] The frequency calculation unit 59 calculates the switching frequency ω of the pulses to be input to the gate terminals of the switch elements based on the phase difference φ between the first bridge circuit 10 and the second bridge circuit 20 calculated by the phase difference calculation unit 52 and the duty ratio D calculated by the duty ratio calculation unit 54A.

[0104] FIG. 8 is a diagram for explaining a method for setting a switching frequency according to the second embodiment. In FIG. 8, the horizontal axis represents the duty ratio D, and the vertical axis represents the settable switching frequency (ratio). In the example shown in FIG. 8, the switching frequency is normalized to 1 when the duty ratio D is 1. In FIG. 8, the state in which the duty ratio D is 1 and the switching frequency is 1 indicates the lower limit value of the switching frequency of the DAB method according to the comparative example. In the second embodiment, the state in which the switching frequency is 1 is called the reference value of the switching frequency.

[0105] As described above, in the DAB power supply device according to the comparative example, when the switching frequency becomes lower than the reference value, the magnetic flux density of the transformer unit 40 may become saturated. In the second embodiment, the magnetic flux density of the transformer unit 40 can be suppressed, and therefore the switching frequency can be made lower than the reference value in accordance with the waveform 130.

[0106] In the second embodiment, for example, by setting the duty ratio D to 0.8 as shown in FIG. 8, the switching frequency ω can be reduced to 0.4. That is, by having the duty ratio calculation unit 54A calculate the duty ratio D to be lower than the reference value, the frequency calculation unit 59 can calculate a lower switching frequency ω. As a result, in the second embodiment, the switching frequency can be lowered below the design limit at which the magnetic flux density of the transformer becomes saturated in the comparative example. For example, in the second embodiment, the duty ratio D can be set between approximately 0.66 and 1.

[0107] The pulse pattern adding unit 60 generates a first output pulse S11 and a second output pulse S12 having the duty ratio D calculated by the duty ratio calculating unit 54A and the switching frequency ω calculated by the frequency calculating unit 59. The phase difference between the first output pulse S11 and the second output pulse S12 is φ. The first output pulse S11 is a reference signal that forms the basis of a drive pulse that is input from the switch element 11 of the first bridge circuit 10 to the gate terminal of the switch element 16. The second output pulse S12 is a reference signal that forms the basis of a drive pulse that is input from the switch element 21 of the second bridge circuit 20 to the gate terminal of the switch element 26.

[0108] Based on the first output pulse S11, the drive pulse generation unit 53A generates a plurality of first drive pulses S13 to be input to the gate terminals of the switch elements 11 to 16 of the first bridge circuit 10. Based on the second output pulse S12, the drive pulse generation unit 53A generates a plurality of second drive pulses S14 to be input to the gate terminals of the switch elements 21 to 26 of the second bridge circuit 20.

[0109] The primary-side pulse driver 57A generates a plurality of primary-side drive pulses S15 to which a pulse pattern of duty ratio D is added, for switching between the on state and the off state of switch elements 11 to 16 of the first bridge circuit 10, based on the first drive pulse S13. The primary-side pulse driver 57A outputs the plurality of primary-side drive pulses S15 to the gate terminals of switch elements 11 to 16 of the first bridge circuit 10. As a result, the second embodiment can reduce switching loss of switch elements 11 to 16 of the first bridge circuit 10 while suppressing saturation of the magnetic flux density of the transformer unit 40.

[0110] The secondary-side pulse driver 58A outputs a plurality of secondary-side drive pulses S16 to which a pulse pattern of duty ratio D is added, for switching the on state and off state of the switch elements 21 to 26 of the second bridge circuit 20, based on the second drive pulse S14. The secondary-side pulse driver 58A outputs the plurality of secondary-side drive pulses S16 to the gate terminals of the switch elements 21 to 26 of the second bridge circuit 20. As a result, the second embodiment can reduce switching loss of the switch elements 21 to 26 of the second bridge circuit 20 while suppressing saturation of the magnetic flux density of the transformer unit 40.

[0111] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the contents of these embodiments. Furthermore, the above-described components include those that can be easily imagined by a person skilled in the art, those that are substantially the same, and those that are within the so-called equivalent range. Furthermore, the above-described components can be combined as appropriate. Furthermore, various omissions, substitutions, or modifications of the components can be made without departing from the spirit of the above-described embodiments. [Explanation of symbols]

[0112] 1 power supply 2,3 Smoothing capacitor 4. Load 10 First bridge circuit 20 Second bridge circuit 10a, 20a First arm 10b, 20b Second arm 10c,20c 3rd arm 11, 12, 13, 14, 15, 16, 21, 22, 23, 24, 25, 26 Switch elements 31, 32, 33 Reactor 40 Transformer section 40a, 40b, 40c transformers 41a, 41b, 41c First winding 42a, 42b, 42c Second winding 43a, 43b, 43c Core 44a, 44b, 44c First terminal 45a, 45b, 45c 2nd terminal 50 control section 51 Error calculation section 52 Phase difference calculation section 53 Drive pulse generation unit 54,54A Duty ratio calculation section 55 Primary side pulse pattern adding section 56 Secondary side pulse pattern adding section 57,57A Primary side pulse driver 58,58A Secondary side pulse driver 59 Frequency calculation section 60 Pulse pattern adding section

Claims

1. a first bridge circuit including a plurality of arms each having a high-side switch element and a low-side switch element, and converting a DC voltage into an AC voltage and outputting the AC voltage; a transformer including a first winding and a second winding, the AC voltage output from the first bridge circuit being input to the first winding and the AC voltage induced in the transformer being output from the second winding; a second bridge circuit including a plurality of arms each having a high-side switch element and a low-side switch element, converting the AC voltage output from the second winding of the transformer into a DC voltage and outputting the DC voltage to a load; a control unit that outputs a plurality of primary side drive pulses to the switch elements in the first bridge circuit to cause the switch elements in the first bridge circuit to perform a switching operation, outputs a plurality of secondary side drive pulses to the switch elements in the second bridge circuit to cause the switch elements in the second bridge circuit to perform a switching operation, and controls a phase difference between the first bridge circuit and the second bridge circuit, thereby controlling a DC voltage output from the second bridge circuit; Equipped with The control unit an additional pattern is added to at least one of the plurality of primary-side drive pulses and the plurality of secondary-side drive pulses, in which all of the high-side switch elements are in an on state or an off state and all of the low-side switch elements are in an opposite state to the high-side switch elements; and by performing control to make the duty ratio of at least one of the primary-side drive pulses and the secondary-side drive pulses lower than when the additional pattern is not added, the switching frequency of the switch elements is made lower than when the additional pattern is not added; power supply.

2. the control unit performs control to make the duty ratio lower than when the additional pattern is not added, based on a ratio between a DC voltage input to the first bridge circuit and a DC voltage output from the second bridge circuit, thereby making the switching frequency of the switch element lower than when the additional pattern is not added. The power supply device of claim 1 .

3. the control unit calculates the switching frequency based on a phase difference between the first bridge circuit and the second bridge circuit and the duty ratio.

3. The power supply device according to claim 1 or 2.

4. the first bridge circuit and the second bridge circuit are three-phase bridge circuits, The transformer is a three-phase transformer. The power supply device according to any one of claims 1 to 3.

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