GaN HEMT discrete multi-stage active gate driver and driving method

Abstract

The invention discloses a GaN HEMT discrete multi-stage active gate driver and a driving method, and relates to the technical field of gate drivers, and the driver comprises a PWM generation module which outputs a PWM high-frequency signal; the driving signal generation module is used for generating a driving signal through a logic gate combination PWM signal and adjusting a driving stage; the gate driving module comprises two independent dual-channel gate drivers, each driver is provided with two independent driving units, each driving unit comprises a driving stage, and the driving stages are controlled through driving signals to enable the GaN HEMT to have discrete gate resistance values; and the device service life condition prediction module is used for optimizing an active grid driving strategy by collecting dynamic electrical parameters and thermodynamic parameters of the device in real time. According to the invention, switching oscillation and voltage and current overshoot generated by the GaN HEMT at an ultrahigh switching speed are effectively suppressed, real-time service life prediction and active protection of the GaN HEMT are realized, and the system reliability is improved.

Description

Technical Field

[0001] This application relates to the field of gate driver technology, and in particular to a GaN HEMT discrete multi-stage active gate driver and driving method. Background Technology

[0002] With the rapid development of power electronics technology toward high frequency, high efficiency, and high power density, gallium nitride (GaN), a third-generation semiconductor material, has shown great potential in high power density switching power supplies, server power supplies, electric vehicle on-board chargers, and renewable energy inverters due to its excellent material properties (such as wide bandgap, high breakdown field strength, and high electron saturation drift velocity).

[0003] Compared to traditional silicon-based MOSFETs and IGBTs, GaN HEMT devices offer significant advantages such as lower on-resistance, faster switching speeds (switching times down to the nanosecond level), significantly reduced switching losses, and no reverse recovery charge, making it possible to achieve higher efficiency and smaller size power conversion systems. However, while the ultra-high switching speed (dV / dt, di / dt) of GaN HEMTs brings efficiency advantages, it also introduces serious challenges. It can increase voltage and current overshoot, generate significant electromagnetic interference (EMI), threaten system electromagnetic compatibility (EMC), and may even cause the device to be subjected to excessive voltage stress, which can reduce device reliability or even lead to failure under long-term operation.

[0004] Since GaN HEMTs have no body diode and reverse conduction depends on the channel, and considering the ultra-high-speed switching characteristics of GaN HEMTs, the traditional approach for GaN drivers is not to actively shape the switching curve like silicon-based drivers, but to minimize reverse conduction losses.

[0005] Traditional drivers focus only on real-time switching control, lacking the ability to monitor key device parameters (such as drain-source voltage Vds, drain current Id, and junction temperature T), adaptive adjustment mechanisms for drive parameters based on degradation states, and lifetime prediction models for cumulative damage. Fixed-parameter drive strategies may lead to increased oscillations, overshoot runaway, or unexpected failures after device aging.

[0006] In summary, how to effectively suppress switching oscillations and voltage / current overshoots in GaN HEMTs at ultra-high switching speeds, while reducing switching losses and ensuring the long-term reliability of the system, is an urgent problem to be solved. Summary of the Invention Based on this, the objective of this invention is to address the aforementioned technical problems by providing a GaN HEMT discrete multi-stage active gate driver and driving method that can effectively suppress switching oscillations and voltage / current overshoots generated by GaN HEMTs at ultra-high switching speeds, while reducing switching losses and ensuring the long-term operational reliability of the system.

[0007] To achieve the above-mentioned objectives, the first aspect of this application provides a GaN HEMT discrete multi-level active gate driver, comprising: a GaN HEMT type first transistor, a gate driving module, a driving signal generation module, a PWM generation module, and a device lifetime condition prediction module. The gate drive module includes first and second independent dual-channel gate drivers. The output A and output B terminals of the two independent dual-channel gate drivers are connected to independent first to fourth drive units, and each drive unit is connected to a drive voltage V. g The gate of the first transistor is connected to the first to fourth gate resistors R. g_1 R g_2 R g_3 R g_4 The first to fourth gate resistors R g_1 R g_2 R g_3 R g_4 The other end is connected to the first to fourth drive units, forming the first to fourth drive stages; The drive signal generation module includes a second FPGA, the PWM generation module includes an AI chip and a first FPGA, and the device lifetime condition prediction module includes a sensor and shares the AI ​​chip and the first FPGA with the PWM generation module. The first acquisition terminal of the sensor is connected to the gate of the first transistor, the second acquisition terminal of the sensor is connected to the source of the first transistor, the output terminal of the sensor is connected to port one of the AI ​​chip, port two of the AI ​​chip is connected to port one of the first FPGA, port two of the first FPGA is connected to port one of the second FPGA, and ports two to five of the second FPGA are connected to input ports A and B of two dual-channel gate drivers respectively.

[0008] Preferably, each of the driving units has the same structure, including a first resistor, a second resistor, a diode, a capacitor, a MOSFET-type second transistor, and a gate resistor. One end of the first resistor and the second resistor are both connected to the output port A or output port B of the first independent dual-channel gate driver or the second independent dual-channel gate driver. The other end of the first resistor is connected to one end of the capacitor, and the other end of the capacitor is grounded. The other end of the second resistor is connected to the cathode of the diode. The anode of the diode is connected to the gate of the second transistor. The drain of the second transistor is connected to the driving voltage. The source of the second transistor is connected to one end of the gate resistor, and the other end of the gate resistor is connected to the gate of the first transistor.

[0009] To achieve the objective of this invention, a second aspect of this application provides a driving method for a GaN HEMT discrete multi-stage active gate driver, applied to the GaN HEMT discrete multi-stage active gate driver described in the first aspect of the above technical solution. The method includes the following steps: S1: Connect the AI ​​chip to the first FPGA via the PCIe interface; S2: Develop firmware and AI chip for the first FPGA, and deploy the Transformer model in the AI ​​chip; S3: Control the first FPGA to output 4 high-frequency PWM signals and input them to the second FPGA; S4: The second FPGA is used to perform logic combination processing on the four high-frequency PWM signals. By parallel processing of multiple digital logic channels, high-resolution drive signals are generated in real time. S5: The generated drive signal is fed into two capacitor-isolated independent dual-channel gate drivers. The two drive stages at the output ports A and B of each gate driver are independent of each other, and each drive stage is connected to a drive voltage. By controlling the conduction of the second transistor of the MOSFET type in different drive stages through the drive signal, the resistance value of the gate resistor is controlled, so that the first transistor of GaN HEMT type has discrete gate resistance values. S6: Then, the switching transient behavior of the discrete multi-stage active gate driver of GaN HEMT is optimized by using discrete gate resistance values. S7: Using a sensor, the surface temperature of the first GaN HEMT transistor is acquired in real time to calculate its junction temperature, and the drain-source voltage V is also acquired. ds and drain current I d Feedback is sent back to the AI ​​chip, where a Transformer model deployed within the chip identifies junction temperature drift and V. ds The subtle increase in hidden correlation enables real-time lifetime prediction and proactive protection of the first transistor in GaN HEMT type.

[0010] Preferably, the specific steps for firmware development of the first FPGA in step S2 are as follows: S21: Create a Vivado project, initialize settings and configure the IP library; S22: Develop the PCIe communication core, configure the XDMA IP core, and connect the AXI-Lite interface; S23: Design a 4-channel PWM generator using Verilog code, including designing the core counter module and instantiating the 4 channels; S24: Then, implement the double buffering mechanism and top-level module integration using Verilog code; S25: Finally, configure the constraint file and perform timing verification, then burn all code files into the first FPGA.

[0011] Preferably, step S4 includes the following specific steps: S41: Design Verilog logic operation code and burn it into the second FPGA; S42: The Verilog logic operation code performs logical combination processing on the input 4-channel PWM signals to generate high-resolution drive signals in real time.

[0012] Preferably, the logical operation type in the logical operation code includes at least one of AND, OR, XOR, and XNOR, and the PWM signals participating in the logical operation type during logical combination processing include 2, 3, or 4 signals.

[0013] Preferably, the method for optimizing switching transient behavior using discrete gate resistance values ​​in step S6 includes the following specific steps: S61: Generate four drive signals A, B, C, and D that can control the gate connection of the GaN HEMT with different resistance values; S62: When the gate-source voltage V of the GaN HEMT gs Reaching Miller plateau voltage V miller When signal A is input to the first driver stage, the GaN HEMT gate connection can shorten the Miller plateau time and accelerate V. ds The decreasing gate resistance; S63: If it is necessary to quickly charge the gate capacitor at the start of conduction to reduce turn-on losses, and to reduce the drain current change rate di / dt after initial conduction to prevent the stray inductance of the main circuit from inducing a large reverse voltage that causes a sharp rise in drain current, the gate resistance needs to be increased from a low value to a high value. Therefore, an improvement is made to step S62: input the C signal to the first driver stage, input the A signal to the second, third, and fourth driver stages, then disconnect the first driver stage, while the other driver stages are still connected to the GaN HEMT gate, so as to increase the gate resistance of the GaN HEMT gate from a low value to a high value. S64: When the GaN HEMT reaches the late Miller plateau, input signal A to the fourth driver stage and signal D to the first driver stage, so that the gate connection of the GaN HEMT can suppress V. ds Downstroke and I d Gate resistor with overshoot resistance.

[0014] Preferably, the specific steps for real-time lifetime prediction and active protection of GaN HEMTs in step S7 are as follows: S71: Collects junction temperature data and V via sensors. ds Data and I d data; S72: Process the junction temperature data using a high sampling rate and high resolution ADC, V ds Data and I d The data is then synchronized with the time of the three data points and input into the first FPGA. S73: The first FPGA is used to remove measurement noise from the time-synchronized data and perform normalization preprocessing and feature extraction to reduce data dimensionality and latency. The feature vector containing the timestamp is calculated and sent to the AI ​​chip. S74: Utilizes the Transformer model deployed in the AI ​​chip to analyze the degradation feature sequence that evolves over time, and outputs lifetime prediction and failure mode identification; S75: The prediction and recognition results output by the Transformer model are used for monitoring and early warning. The protection action decision output by the model is converted into a specific gate resistance control signal. The gate resistance control signal is sent to the first FPGA through the AI ​​chip, and then the generated PWM signal is adjusted to control the drive signal generated by the second FPGA to indirectly control the gate drive module. The gate drive module dynamically switches the state of the four drive stages according to the received drive signal, changing the gate resistance R of the GaN HEMT gate connection. g_i The resistance value; S76: If a high failure risk is predicted, dynamically increase the gate resistance R connected to the circuit. g_iThe resistance value can be adjusted to sacrifice some efficiency for reliability and extended lifespan, or the drive signal output by the second FPGA can be directly adjusted to send the drive signal with the highest gate resistance value to all drive stages.

[0015] Preferably, the normalization preprocessing operation in step S73 includes the following steps: S731: The collected junction temperature data are set as T={ , … },in This represents the value of the i-th parameter, with T used as the input data for the normalization method; S732: Using the Min-Max linear normalization method, for each feature of the input data:

[0016] in, This represents the theoretical minimum junction temperature. Indicates the maximum allowable junction temperature of the device. To obtain the normalized value of the i-th parameter, normalize the set T, resulting in the output of the normalization preprocessing operation. , … .

[0017] Preferably, the processing steps of the Transformer model include: The AI ​​chip receives a normalized, pre-processed data stream from the first FPGA; it then inputs time-series samples into the Transformer model. [ ] Where n is the size of the time window for the Transformer model design; A dedicated buffer is set up to continuously store the latest n+1 time steps of data. When new data arrives, the oldest data is discarded, forming a new input sequence: X t =[ ] in, ; The original data vector at each time step It is mapped to a higher-dimensional vector space through a linear embedding layer. The mathematical expression is as follows:

[0018] in, Represents the weight matrix. Representing the bias vector, we obtain a sequence:

[0019] in, ; Then, the position encoding vector containing absolute time information is... Add to the embedding vector The above can be expressed mathematically as follows:

[0020] in, Dimensions and Same; PE can be obtained using the following formula:

[0021]

[0022] Where pos is the position of the data in the sequence, d is the dimension of PE, 2i is the even dimension, and 2i+1 is the odd dimension, thus obtaining the sequence:

[0023] Next, a self-attention mechanism is used to process the sequence. In and , , Matrix multiplication yields a matrix with unchanged dimensions. , , vector, , , It is a set of weights learned through the training process, which are then used to associate other vectors with it. , , Multiply them to get the corresponding products. , , Vectors, then let and dot product, and dot product, and dot product, and dot product... , , ...and then separately , , ...multiply and then add to get ,this This indicates whether the junction temperature is related to the voltage and current at previous times from the first time perspective. Similarly, other vectors of sequence Z are calculated in the same way to obtain a new sequence containing global context information. each They all incorporate sequences A Information on all time steps; if With multiple groups , , The weight matrix yields multiple sets This becomes the multi-head self-attention mechanism, expressed by the following formula:

[0024] The output of each sublayer is residually concatenated with the input of that sublayer, and then layer normalization is performed. The calculation formula is as follows:

[0025] Where X represents the input to the self-attention mechanism Attention. The output, after processing, is the final feature sequence:

[0026] in, Each of them ; Then The input is sent to a multitasking output header, which outputs the predicted remaining lifetime and gate resistance R. g_i Discrete control levels, each corresponding to a different switching speed and stress level. Compared with the prior art, the beneficial effects of this invention are: This invention generates PWM signals using an AI chip and an FPGA. The FPGA then processes multiple digital logic channels in parallel to generate high-resolution drive signals in real time, thereby controlling the gate drive. It optimizes the switching transient behavior of GaN HEMTs using fully discrete, low-cost segmented control of active resistors. Compared to traditional gate drives, active discrete resistor driving achieves finer dynamic control, suppressing switching oscillations and voltage / current overshoot issues at ultra-high switching speeds in GaN HEMTs, reducing switching losses, and improving electromagnetic interference. Furthermore, it uses a Transformer model to analyze the junction temperature and voltage characteristics of the GaN HEMT. ds I d The data is processed to identify junction temperature drift and V. ds The subtle increase in hidden correlation enables real-time prediction and proactive protection of the first transistor in GaN HEMT type, which can improve switching speed and efficiency and enhance system reliability. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the overall structure of a GaN HEMT discrete multi-stage active gate driver in one embodiment. Figure 2 This is a flowchart illustrating the steps of a driving method for a GaN HEMT discrete multi-level active gate driver in one embodiment. Figure 3 This is a schematic diagram of how PWM signals are logically combined to generate drive signals in one embodiment. Attached image description: 1- First GaN HEMT transistor; 2- Device lifetime condition prediction module, 201- Sensor; 3- Drive signal generation module, 301- Second FPGA; 4- Gate drive module, 401- First independent dual-channel gate driver, 402- Second independent dual-channel gate driver, 403- First drive unit, 404- Second drive unit, 405- Third drive unit, 406- Fourth drive unit; 5- PWM generation module, 521- AI chip, 522- First FPGA; 6- Second MOSFET transistor Detailed Implementation To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention. The following embodiments are used to illustrate the invention but are not intended to limit its scope.

[0029] In the description of this invention, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0030] Example 1 Embodiment 1 of this application provides a GaN HEMT discrete multi-stage active gate driver, such as... Figure 1 As shown, it includes: a GaN HEMT (gallium nitride high electron mobility transistor) type first transistor 1, a device lifetime condition prediction module 2, a drive signal generation module 3, a gate drive module 4, and a PWM generation module 5; Gate driving module 4 includes a first independent dual-channel gate driver 401 and a second independent dual-channel gate driver 402. The output A and output B terminals of the two independent dual-channel gate drivers are sequentially connected to independent first driving unit 403, second driving unit 404, third driving unit 405, and fourth driving unit 406. Each driving unit is connected to a driving voltage Vg. The gate of the first transistor 1 is connected to a gate resistor R. g_1 R g_2 R g_3 R g_4 Gate resistance R g_1 R g_2 R g_3 R g_4 The other end is connected sequentially to the first to fourth drive units, forming the first to fourth drive stages; The drive signal generation module 3 includes a second FPGA 301, the PWM generation module 5 includes an AI chip 521 and a first FPGA 522, and the device lifetime condition prediction module 2 includes a sensor 201 and shares the AI ​​chip 521 and the first FPGA 522 with the PWM generation module 5. The first acquisition terminal of sensor 201 is connected to the gate of the first transistor 1, the second acquisition terminal of sensor 6 is connected to the source of the first transistor 1, the output terminal of sensor 6 is connected to port one of AI chip 521, port two of AI chip 521 is connected to port one of the first FPGA 522, port two of the first FPGA 522 is connected to port one of the second FPGA 301, and ports two to five of the second FPGA 301 are respectively connected to input ports A and B of the first independent dual-channel gate driver 401 and input ports A and B of the second independent dual-channel gate driver 402.

[0031] Each of the aforementioned driving units has the same structure, including a first resistor R1, a second resistor R2, a diode, a capacitor, a MOSFET-type second transistor 6, and a gate resistor R. g_i One end of R1 and R2 is connected to output port A or output port B of the first independent dual-channel gate driver 401 or the second independent dual-channel gate driver 402. The other end of R1 is connected to one end of a capacitor, and the other end of the capacitor is grounded. The other end of R2 is connected to the cathode of a diode. The anode of the diode is connected to the gate of the second transistor 6, and the drain of the second transistor 6 is connected to the driving voltage V. g The source and gate resistors R of the second transistor 6 g_i One end is connected to the gate resistor R. g_i The other end is connected to the gate of the first transistor 1.

[0032] In this embodiment, the independent dual-channel gate drivers 401 and 402 are capacitively isolated independent dual-channel gate drivers with a delay of less than or equal to 10 nanoseconds, which can meet the transmission requirements of level signals composed of high-frequency PWM logic combinations. Capacitive isolation has the lowest transmission delay compared to optocoupler isolation and magnetic coupling isolation, and the transmission rate is very high. Compared to optocoupler isolation, there is no physical loss.

[0033] It should be noted that the sensor 201 in this embodiment includes a thermocouple, a differential probe, and a Rogowski coil, used to collect junction temperature data (calculated by collecting surface temperature) and drain-source voltage V. ds and drain current data I d， Other types of sensors capable of collecting the above data can also be used.

[0034] Example 2 Embodiment 2 of this application, based on Embodiment 1, provides a driving method for a GaN HEMT discrete multi-level active gate driver, such as... Figure 2 As shown, the method for use in a GaN HEMT discrete multi-stage active gate driver described in Example 1 includes the following steps: S1: Connect the AI ​​chip to the first FPGA via the PCIe interface; S2: Develop firmware and AI chip for the first FPGA, and deploy the Transformer model in the AI ​​chip; S3: Control the first FPGA to output 4 high-frequency PWM signals and input them to the second FPGA; S4: The second FPGA is used to perform logic combination processing on the four high-frequency PWM signals. By processing multiple digital logics in parallel, high-resolution drive signals are generated in real time. It should be noted that the lookup table (LUT) and register resources in the configurable logic block (CLB) of the FPGA are used to process multiple digital logics in parallel. S5: The generated drive signal is fed into two capacitor-isolated independent dual-channel gate drivers. The two drive stages at the output ports A and B of each gate driver are independent of each other, and each drive stage is connected to a drive voltage. By controlling the conduction of the second transistor of the MOSFET type in different drive stages through the drive signal, the resistance value of the gate resistor is controlled, so that the first transistor of GaN HEMT type has discrete gate resistance values. S6: Optimize the switching transient behavior of discrete multi-stage active gate drivers in GaN HEMTs using discrete gate resistance values. S7: Using a sensor, the surface temperature of the first GaN HEMT transistor is acquired in real time to calculate its junction temperature, and the drain-source voltage V is also acquired. ds and drain current Id Feedback is sent back to the AI ​​chip, where a Transformer model deployed within the chip identifies junction temperature drift and V. ds The subtle increase in hidden correlation enables real-time lifetime prediction and proactive protection of the first transistor in GaN HEMT type.

[0035] In this embodiment, step S1 uses an AI chip combined with an FPGA to generate four high-frequency PWM signals.

[0036] The specific steps for firmware development of the first FPGA in step S2 are as follows: S21: Create a Vivado project, initialize settings and configure the IP library; S22: Develop the PCIe communication core, configure the XDMA IP core, and connect the AXI-Lite interface; S23: Design a 4-channel PWM generator using Verilog code, including designing the core counter module and instantiating the 4 channels; S24: Then, implement the double buffering mechanism and top-level module integration using Verilog code; S25: Finally, configure the constraint file and perform timing verification, then burn all code files into the first FPGA.

[0037] In this embodiment, step S4 includes the following specific steps: S41: Design Verilog logic operation code and burn it into the second FPGA; S42: The Verilog logic operation code performs logical combination processing on the four input PWM signals to generate high-resolution drive signals in real time. It should be noted that the logic operation type in the logic operation code includes at least one of AND, OR, XOR, and XNOR, and can also be other meaningful logic operations. When performing logical combination processing, the PWM signals participating in the logic operation type include 2, 3, or 4 signals.

[0038] like Figure 3 As shown, in this embodiment, the PWM generation module uses an AI chip combined with an FPGA to generate four high-frequency PWM waveforms, thus outputting four PWM signals PWM1-PWM4. Applying a XNOR logic combination to PWM1 and PWM2 generates signal A; applying an XOR combination to PWM2 and PWM3 generates signal B; applying an AND combination to PWM3 and PWM4 generates signal C; XORing PWM1 and PWM4 generates signal D; ANDing PWM1 and PWM4 generates signal E; and XNORing PWM2 and PWM3 generates signal F. Through different logic combinations, the PWM driver stage exhibits very high flexibility.

[0039] In this embodiment, step S5 uses the aforementioned drive signal to control the gate resistance values ​​of the first to fourth drive stages as follows: =1Ω, =6Ω, =12Ω, =25Ω.

[0040] Step S6, which optimizes switching transient behavior using discrete gate resistance values, includes the following specific steps: (Only a few cases are described below): S61: Generate four drive signals A, B, C, and D (in this embodiment, they correspond to gate resistors of different values ​​connected to the gate of the GaN HEMT) that can control the gate connection of the GaN HEMT. =1Ω, =6Ω, =12Ω, =25Ω); Four drive signals are input to INA and INB of two capacitor-isolated independent dual-channel gate drivers respectively to control OUTA and OUTB; S62: When the gate-source voltage V of the GaN HEMT gs Reaching Miller plateau voltage V miller When signal A is input to the first driver stage, the GaN HEMT gate connection can shorten the Miller plateau time and accelerate V. ds The decreasing gate resistance (in this embodiment, the gate resistance of the access is...) =1Ω); S63: If it is necessary to quickly charge the gate capacitor at the start of conduction to reduce turn-on losses, and to reduce the drain current change rate di / dt after initial conduction to prevent the stray inductance of the main circuit from inducing a large reverse voltage that causes a sharp rise in drain current, the gate resistance needs to be increased from a low value to a high value. Therefore, an improvement is made to step S62: Input the C signal into the first driver stage, and input the A signal into the second, third, and fourth driver stages (equivalent to connecting 1Ω first, and then connecting other resistors). Then disconnect the first driver stage, while the other driver stages are still connected to the GaN HEMT gate, so that the gate resistance of the GaN HEMT gate is increased from a low value to a high value. S64: When the GaN HEMT reaches the late Miller plateau, input signal A to the fourth driver stage and signal D to the first driver stage, so that the gate connection of the GaN HEMT can suppress V. ds Downstroke and I d The gate resistor for overshoot (25Ω in this embodiment; a 25Ω resistor is connected to the GaN HEMT gate to suppress Vds undershoot and Id overshoot).

[0041] The specific steps for real-time lifetime prediction and active protection of GaN HEMTs in step S7 are as follows: S71: Collects junction temperature data and V via sensors. ds Data and I d data; S72: Process the junction temperature data using a high sampling rate and high resolution ADC, V ds Data and I d The data is then synchronized with the time of the three data points and input into the first FPGA. S73: The first FPGA is used to remove measurement noise from the time-synchronized data and perform normalization preprocessing and feature extraction to reduce data dimensionality and latency. The feature vector containing the timestamp is calculated and sent to the AI ​​chip. S74: Utilizes the Transformer model deployed in the AI ​​chip to analyze the degradation feature sequence that evolves over time, and outputs lifetime prediction and failure mode identification; S75: The prediction and recognition results output by the Transformer model are used for monitoring and early warning. The protection action decision output by the model is converted into a specific gate resistance control signal. The gate resistance control signal is sent to the first FPGA through the AI ​​chip, and then the generated PWM signal is adjusted to control the drive signal generated by the second FPGA to indirectly control the gate drive module. The gate drive module dynamically switches the state of the four drive stages according to the received drive signal, changing the gate resistance R of the GaN HEMT gate connection. g_i The resistance value; S76: If a high failure risk is predicted, dynamically increase the gate resistance R connected to the circuit. g_i The resistance value can be adjusted to sacrifice some efficiency in exchange for reliability and extended lifespan, or the drive signal output by the second FPGA can be directly adjusted to send the drive signal with the highest gate resistance value (D signal with a resistance value of 25Ω in this embodiment) to all drive stages.

[0042] In this embodiment, the normalization preprocessing operation in step S73 includes the following steps: S731: Assuming the collected junction temperature data is T, treat the collected junction temperature data as a set T = { , … },in This represents the value of the i-th parameter, with T used as the input data for the normalization method; S732: Using the Min-Max linear normalization method, for each feature of the input data:

[0043] in, This represents the theoretical minimum junction temperature. Indicates the maximum allowable junction temperature of the device. To obtain the normalized value of the i-th parameter, normalize the set T, resulting in the output of the normalization preprocessing operation. , … .

[0044] Example 3 This embodiment 3, based on embodiments 1 and 2, further explains the processing steps of the Transformer model deployed in the AI ​​chip, as follows: The AI ​​chip receives a normalized, pre-processed data stream from the first FPGA; it then inputs time-series samples into the Transformer model. [ ] Where n is the size of the time window for the Transformer model design; A dedicated buffer is set up to continuously store the latest n+1 time steps of data. When new data arrives, the oldest data is discarded, forming a new input sequence: X t =[ ] in, ; The original data vector at each time step It is mapped to a higher-dimensional vector space through a linear embedding layer. The mathematical expression is as follows:

[0045] in, Represents the weight matrix. Representing the bias vector, we obtain a sequence:

[0046] in, ; Then, the position encoding vector containing absolute time information is... Add to the embedding vector The above can be expressed mathematically as follows:

[0047] in, Dimensions and Same; PE can be obtained using the following formula:

[0048]

[0049] Where pos is the position of the data in the sequence, d is the dimension of PE, 2i is the even dimension, and 2i+1 is the odd dimension, thus obtaining the sequence:

[0050] Next, a self-attention mechanism is used to process the sequence. In and , , Matrix multiplication yields a matrix with unchanged dimensions. , , vector, , , It is a set of weights learned through the training process, which are then used to associate other vectors with it. , , Multiply them to get the corresponding products. , , Vectors, then let and dot product, and dot product, and dot product, and dot product... , , ...and then separately , , ...multiply and then add to get ,this This indicates whether the junction temperature is related to the voltage and current at previous times from the first time perspective. Similarly, other vectors of sequence Z are calculated in the same way to obtain a new sequence containing global context information. each They all incorporate sequences A Information on all time steps; if With multiple groups , , The weight matrix yields multiple sets This becomes the multi-head self-attention mechanism, expressed by the following formula:

[0051] The output of each sublayer is residually concatenated with the input of that sublayer, and then layer normalization is performed. The calculation formula is as follows:

[0052] Where X represents the input to the self-attention mechanism Attention. The output, after processing, is the final feature sequence:

[0053] in, Each of them ; Then The input is given to a multitasking output header, which outputs the predicted remaining lifetime (y_life) and the discrete adjustment level of the gate resistance Rg (e.g., […]). , , Each level corresponds to a different switching speed and stress level.

[0054] In summary, this invention provides a GaN HEMT discrete multi-level active gate driver and driving method, proposing to utilize the lookup table (LUT) and register resources in the configurable logic block (CLB) of an FPGA to generate high-resolution drive control signals in real time through parallel processing of multiple digital logic channels, thereby controlling the gate drive.

[0055] Since GaN HEMTs lack a body diode and their reverse conduction relies on the channel, and considering the ultra-high-speed switching characteristics of GaN HEMTs, traditional GaN drivers do not actively shape the switching curve like silicon-based drivers, but rather minimize reverse conduction losses. This proposed approach optimizes the switching transient behavior of GaN HEMTs.

[0056] The proposed method uses a capacitor-isolated driver chip to dominate the gate drive circuit. The gate drive circuit is divided into four separate drive stages, each with its own drive voltage. and its own gate resistance This allows for high flexibility in gate signals. Capacitive isolation offers the lowest propagation delay and a very high transmission rate compared to optocoupler and magnetic isolation, and it suffers no physical loss compared to optocoupler isolation.

[0057] This paper proposes a fully discrete, low-cost active resistor segmented control method. Compared with traditional gate drives (voltage source drive, current source drive, and resonant drive), active discrete resistor drive can achieve more precise dynamic control, reduce switching losses, improve EMI and overshoot, and enhance switching speed, efficiency, and system reliability. Compared with active current drive and active voltage drive, active discrete resistor drive is cheaper and easier to implement. By adjusting the gate resistance at different stages of the switching transient, the dv / dt and di / dt of the drain and source terminals of the GaN HEMT are changed.

[0058] This paper proposes using an AI chip (such as the Ascend 310B) to deploy a Transformer model to process junction temperature, Vds, and Id data of GaN HEMTs. Transformer is a deep learning architecture whose core uses a "self-attention mechanism" to dynamically calculate the importance weights of each part of the input data, achieving efficient modeling of long-range dependencies. Unlike the serial processing of traditional recurrent neural networks (RNNs), Transformer processes all input elements (such as temperature, voltage, and current points in a time series) in parallel, significantly improving computational efficiency. It automatically mines the inherent correlations in the data through an "encoder-decoder" structure. Transformer has extremely strong long-range dependencies and supports ultra-long sequences, while the core limitation of LSTM in processing long sequences lies in gradient decay and memory bottlenecks. In GaN HEMT lifetime prediction and operating condition prediction applications, Transformer's self-attention mechanism can directly capture the degradation correlations of thousands of switching cycles and identify the hidden correlation between junction temperature drift and slight increases in Vds. This enables real-time lifetime prediction and proactive protection of GaN HEMTs, and is particularly useful for judging the long-cycle degradation process of devices, improving switching speed and efficiency and enhancing system reliability.

Claims

1. A GaN HEMT discrete multi-stage active gate driver, characterized in that, include: The GaN HEMT type includes a first transistor (1), a device lifetime condition prediction module (2), a drive signal generation module (3), a gate drive module (4), and a PWM generation module (5). The gate driving module (4) includes a first independent dual-channel gate driver (401) and a second independent dual-channel gate driver (402). The output A and output B terminals of the two independent dual-channel gate drivers are sequentially connected to an independent first driving unit (403), a second driving unit (404), a third driving unit (405), and a fourth driving unit (406). Each driving unit is connected to a driving voltage V. g The gate of the first transistor (1) is connected to a gate resistor R. g_1 R g_2 R g_3 R g_4 Gate resistance R g_1 R g_2 R g_3 R g_4 The other end is connected sequentially to the first to fourth drive units, forming the first to fourth drive stages; The drive signal generation module (3) includes a second FPGA (301), the PWM generation module (5) includes an AI chip (521) and a first FPGA (522), and the device life condition prediction module (2) includes a sensor (201) and shares the AI ​​chip (521) and the first FPGA (522) with the PWM generation module (5). The first acquisition terminal of the sensor (201) is connected to the gate of the first transistor (1), the second acquisition terminal of the sensor (6) is connected to the source of the first transistor (1), the output terminal of the sensor (6) is connected to port one of the AI ​​chip (521), port two of the AI ​​chip (521) is connected to port one of the first FPGA (522), port two of the first FPGA (522) is connected to port one of the second FPGA (301), and ports two to five of the second FPGA (301) are connected to input ports A and B of the first independent dual-channel gate driver (401) and input ports A and B of the second independent dual-channel gate driver (402) respectively.

2. The GaN HEMT discrete multi-stage active gate driver according to claim 1, characterized in that, Each of the aforementioned driving units has the same structure, including a first resistor R1, a second resistor R2, a diode, a capacitor, a MOSFET-type second transistor (6), and a gate resistor R. g_i One end of R1 and R2 is connected to output port A or output port B of the first independent dual-channel gate driver (401) or the second independent dual-channel gate driver (402). The other end of R1 is connected to one end of a capacitor, and the other end of the capacitor is grounded. The other end of R2 is connected to the cathode of a diode. The anode of the diode is connected to the gate of the second transistor (6). The drain of the second transistor (6) is connected to the driving voltage V. g The source and gate resistors R of the second transistor (6) g_i One end is connected to the gate resistor R. g_i The other end is connected to the gate of the first transistor (1).

3. A driving method for a GaN HEMT discrete multi-stage active gate driver, used in any one of claims 1-2, characterized in that, The method includes the following steps: S1: Connect the AI ​​chip to the first FPGA via the PCIe interface; S2: Develop firmware and AI chip for the first FPGA, and deploy the Transformer model in the AI ​​chip; S3: Control the first FPGA to output 4 high-frequency PWM signals and input them to the second FPGA; S4: The second FPGA is used to perform logic combination processing on the four high-frequency PWM signals. By parallel processing of multiple digital logic channels, high-resolution drive signals are generated in real time. S5: The generated drive signal is fed into two capacitor-isolated independent dual-channel gate drivers. The two drive stages at the output ports A and B of each gate driver are independent of each other, and each drive stage is connected to a drive voltage. By controlling the conduction of the second transistor of the MOSFET type in different drive stages through the drive signal, the resistance value of the gate resistor is controlled, so that the first transistor of GaN HEMT type has discrete gate resistance values. S6: Optimize the switching transient behavior of discrete multi-stage active gate drivers in GaN HEMTs using discrete gate resistance values. S7: Using a sensor, the surface temperature of the first GaN HEMT transistor is acquired in real time to calculate its junction temperature, and the drain-source voltage V is also acquired. ds and drain current I d Feedback is sent back to the AI ​​chip, where a Transformer model deployed within the chip identifies junction temperature drift and V. ds The subtle increase in hidden correlation enables real-time lifetime prediction and proactive protection of the first transistor in GaN HEMT type.

4. The driving method of a GaN HEMT discrete multi-stage active gate driver according to claim 3, characterized in that, The specific steps for firmware development of the first FPGA in step S2 are as follows: S21: Create a Vivado project, initialize settings and configure the IP library; S22: Develop the PCIe communication core, configure the XDMA IP core, and connect the AXI-Lite interface; S23: Design a 4-channel PWM generator using Verilog code, including designing the core counter module and instantiating the 4 channels; S24: Then, implement the double buffering mechanism and top-level module integration using Verilog code; S25: Finally, configure the constraint file and perform timing verification, then burn all code files into the first FPGA.

5. The driving method of a GaN HEMT discrete multi-stage active gate driver according to claim 3, characterized in that, The S4 step includes the following specific steps: S41: Design Verilog logic operation code and burn it into the second FPGA; S42: The Verilog logic operation code performs logical combination processing on the input 4-channel PWM signals to generate high-resolution drive signals in real time.

6. The driving method of a GaN HEMT discrete multi-stage active gate driver according to claim 5, characterized in that, The logical operation types in the logical operation code include at least one of AND, OR, XOR, and XNOR, and the PWM signals participating in the logical operation types during logical combination processing include 2, 3, or 4 signals.

7. The driving method of a GaN HEMT discrete multi-stage active gate driver according to claim 3, characterized in that, The method for optimizing switching transient behavior using discrete gate resistance values ​​in step S6 includes the following specific steps: S61: Generate four drive signals A, B, C, and D that can control the gate connection of the GaN HEMT with different resistance values; S62: When the gate-source voltage V of the GaN HEMT gs Reaching Miller plateau voltage V miller When signal A is input to the first driver stage, the GaN HEMT gate connection can shorten the Miller plateau time and accelerate V. ds The decreasing gate resistance; S63: If it is necessary to quickly charge the gate capacitor at the start of conduction to reduce turn-on losses, and to reduce the drain current change rate di / dt after initial conduction to prevent the stray inductance of the main circuit from inducing a large reverse voltage that causes a sharp rise in drain current, the gate resistance needs to be increased from a low value to a high value. Therefore, an improvement is made to step S62: input the C signal to the first driver stage, input the A signal to the second, third, and fourth driver stages, then disconnect the first driver stage, while the other driver stages are still connected to the GaN HEMT gate, so as to increase the gate resistance of the GaN HEMT gate from a low value to a high value. S64: When the GaN HEMT reaches the late Miller plateau, input signal A to the fourth driver stage and signal D to the first driver stage, so that the gate connection of the GaN HEMT can suppress V. ds Downstroke and I d Gate resistor with overshoot resistance.

8. The driving method of a GaN HEMT discrete multi-stage active gate driver according to claim 3, characterized in that, The specific steps for real-time lifetime prediction and active protection of GaN HEMTs in step S7 are as follows: S71: Collects junction temperature data and V via sensors. ds Data and I d data; S72: Process the junction temperature data using a high sampling rate and high resolution ADC, V ds Data and I d The data is then synchronized with the time of the three data points and input into the first FPGA. S73: The first FPGA is used to remove measurement noise from the time-synchronized data and perform normalization preprocessing and feature extraction to reduce data dimensionality and latency. The feature vector containing the timestamp is calculated and sent to the AI ​​chip. S74: Utilizes the Transformer model deployed in the AI ​​chip to analyze the degradation feature sequence that evolves over time, and outputs lifetime prediction and failure mode identification; S75: The prediction and recognition results output by the Transformer model are used for monitoring and early warning. The protection action decision output by the model is converted into a specific gate resistance control signal. The gate resistance control signal is sent to the first FPGA through the AI ​​chip, and then the generated PWM signal is adjusted to control the drive signal generated by the second FPGA to indirectly control the gate drive module. The gate drive module dynamically switches the state of the four drive stages according to the received drive signal, changing the gate resistance R of the GaN HEMT gate connection. g_i The resistance value; S76: If a high failure risk is predicted, dynamically increase the gate resistance R connected to the circuit. g_i The resistance value can be adjusted to sacrifice some efficiency in exchange for reliability and extended lifespan, or the drive signal output by the second FPGA can be directly adjusted to send the drive signal with the highest gate resistance value to all drive stages.

9. The driving method of a GaN HEMT discrete multi-stage active gate driver according to claim 8, characterized in that, The normalization preprocessing operation in step S73 includes the following steps: S731: The collected junction temperature data are set as T={ , … },in This represents the value of the i-th parameter, with T used as the input data for the normalization method; S732: Using the Min-Max linear normalization method, for each feature of the input data: in, This represents the theoretical minimum junction temperature. Indicates the maximum allowable junction temperature of the device. To obtain the normalized value of the i-th parameter, normalize the set T, resulting in the output of the normalization preprocessing operation. , … .

10. A driving method for a GaN HEMT discrete multi-stage active gate driver according to any one of claims 3-9, characterized in that, The processing steps of the Transformer model include: The AI ​​chip receives a normalized, pre-processed data stream from the first FPGA; it then inputs time-series samples into the Transformer model. [ ] Where n is the size of the time window for the Transformer model design; A dedicated buffer is set up to continuously store the latest n+1 time steps of data. When new data arrives, the oldest data is discarded, forming a new input sequence: X t =[ ] in, ; The original data vector at each time step It is mapped to a higher-dimensional vector space through a linear embedding layer. The mathematical expression is as follows: in, Represents the weight matrix. Representing the bias vector, we obtain a sequence: in, ; Then, the position encoding vector containing absolute time information is... Add to the embedding vector The above can be expressed mathematically as follows: in, Dimensions and Same; PE can be obtained using the following formula: Where pos is the position of the data in the sequence, d is the dimension of PE, 2i is the even dimension, and 2i+1 is the odd dimension, thus obtaining the sequence: Next, a self-attention mechanism is used to process the sequence. In and , , Matrix multiplication yields a matrix with unchanged dimensions. , , vector, , , It is a set of weights learned through the training process, which are then used to associate other vectors with it. , , Multiply them to get the corresponding products. , , Vectors, then let and dot product, and dot product, and dot product, and dot product... , , ...and then separately , , ...multiply and then add to get ,this This indicates whether the junction temperature is related to the voltage and current at previous times from the first time perspective. Similarly, other vectors of sequence Z are calculated in the same way to obtain a new sequence containing global context information. Each They all incorporate sequences A Information on all time steps; if With multiple groups , , The weight matrix yields multiple sets This becomes the multi-head self-attention mechanism, expressed by the following formula: The output of each sublayer is residually concatenated with the input of that sublayer, and then layer normalization is performed. The calculation formula is as follows: Where X represents the input to the self-attention mechanism Attention. The output, after processing, is the final feature sequence: in, Each of them ; Then The input is sent to a multitasking output header, which outputs the predicted remaining lifetime and gate resistance R. g_i The discrete adjustment levels correspond to different switching speeds and stress levels.

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