Methods, integrated circuits, and integrated circuit packages for implementing power management

Abstract

A power management and a method for implementing power management, integrated circuit, and integrated circuit package are disclosed. One exemplary embodiment is a method of operating a portable audio device, the method comprising: reading, by a power supply controller, a logic speed measurement from a logic gate delay line, the power supply controller and the logic gate delay line implemented on a semiconductor substrate; calculating, by the power supply controller, a speed margin based on the logic speed measurement; generating, by the power supply controller, a value indicative of a modified voltage level, the generating based on the speed margin; and modifying, by a main voltage converter on the semiconductor substrate, an output voltage in response to the value indicative of the modified voltage level.

Description

Technical Field

[0001] This patent application relates to the field of power management technology for integrated circuit devices. Background Technology

[0002] Low power consumption plays a crucial role in battery-powered portable audio devices, such as hearing aids. Reducing the size of hearing aids allows for a proper physical fit between the device and the ear (e.g., the ear canal). Size reduction can be achieved by reducing the power consumed by the device. However, size reduction can be challenging because hearing aids typically run complex algorithms that use integrated circuits to perform a great deal of digital processing. The power requirements of digital logic in such devices can be substantial and often account for the largest portion of total power consumption. Summary of the Invention

[0003] At least one example is a method of operating an integrated circuit on a semiconductor substrate, the method comprising: reading a logic speed measurement from a logic gate delay line by a power controller, the power controller and the logic gate delay line being implemented on the semiconductor substrate; calculating a speed margin by the power controller based on the logic speed measurement; generating a value indicating a modified voltage by the power controller, the generation being based on the speed margin; and modifying an output voltage by a main voltage converter on the semiconductor substrate in response to the value indicating the modified voltage.

[0004] In the exemplary method: calculating the speed margin may further include determining the difference between a logic speed measurement and a target speed value. Modifying the output voltage may further include at least one of the following: increasing the output voltage in response to a value indicating the voltage to be modified; and decreasing the output voltage in response to a value indicating the voltage to be modified. Determining the difference between the logic speed measurement and the target speed value also includes determining the amount by which the logic speed measurement is faster or slower than the target speed value.

[0005] In an exemplary method, reading the logic speed measurement may further include determining the distance the active state propagates along the logic gate delay line over a predetermined time period.

[0006] In an exemplary method, the main voltage converter may further include at least one of the following: a charge pump; a switch-mode power converter; and a linear regulator.

[0007] An exemplary method may further include: measuring a signal indicating power consumption of a device on a semiconductor substrate by a host voltage controller, the host voltage controller being implemented on the semiconductor substrate; generating a value indicating a modified host voltage by the host voltage controller, the generation being based on the signal indicating power consumption; and modifying the host voltage of a plurality of transistors applied to the semiconductor substrate by a host voltage converter on the semiconductor substrate, the modification being in response to the value indicating the modified voltage. Generating the value indicating the modified host voltage may further include generating the value indicating the modified host voltage such that the host voltage is reduced by at least one of the following: power consumption of the plurality of transistors; and leakage current of the plurality of transistors. The host voltage converter may further include a charge pump, and wherein measuring the signal indicating power consumption further includes counting the number of pumping actions performed by the charge pump. The host voltage converter may further include a switch-mode power converter, and wherein measuring the signal indicating power consumption further includes counting the number of times the main switch of the switch-mode power converter is activated. The main voltage converter may also include a charge pump, and the method further includes: reading a value indicating the voltage supplied to the charge pump by a pump controller, the pump controller being implemented on a semiconductor substrate; reading a value indicating the output voltage of the charge pump by the pump controller; dividing the value indicating the supplied voltage by the value indicating the output voltage to generate a result; determining a charge pump ratio based on the result, a threshold ratio value, and a hysteresis value; and changing the operating characteristics of the charge pump based on the charge pump ratio.

[0008] In an exemplary method, the main voltage converter may be a charge pump, and the method may further include: reading a value indicating the voltage supplied to the charge pump by a pump controller, the pump controller being implemented on a semiconductor substrate; reading a value indicating the output voltage of the charge pump by the pump controller; dividing the value indicating the supplied voltage by the value indicating the output voltage to generate a result; determining a charge pump ratio based on the result, a threshold ratio value, and a hysteresis value; and changing the operating characteristics of the charge pump based on the charge pump ratio.

[0009] Another example is an integrated circuit on a semiconductor substrate, comprising: a processing core; a system memory coupled to the processing core; a main voltage converter defining a main control input, a main power input, and a main voltage output, the main voltage converter being configured to change a voltage driven to the main voltage output in response to the main control input; a logic gate delay line embedded within the processing core, the logic gate delay line defining a plurality of gate outputs; and a power controller defining a plurality of gate inputs coupled to the plurality of gate outputs of the logic gate delay line and a main control output coupled to the main control input of the main voltage converter. The power controller may be configured to: read the plurality of gate outputs from the logic gate delay line; generate a logic speed measurement based on the read plurality of gate outputs; calculate a speed margin based on the logic speed measurement; and drive a value indicating a modified voltage level to the main control output in response to the speed margin.

[0010] In an exemplary integrated circuit, the logic gate delay line may also include a plurality of serially aligned buffers disposed alongside the logic path within the processing core.

[0011] In an exemplary integrated circuit, the power controller may further include a target speed register coupled to a communication bus; wherein, when the power controller calculates a speed margin, the power controller is further configured to determine a difference between a logic speed measurement value and a target speed value stored in the target speed register. When the power controller determines the difference between the logic speed measurement value and the target speed value, the power controller may be configured to determine an amount by which the logic speed measurement value is faster or slower than the target speed value.

[0012] In an exemplary integrated circuit, when a power controller reads multiple gate outputs from a logic gate delay line, the power controller can be configured to determine the distance that an active state propagates along the logic gate delay line over a predetermined time period.

[0013] In an exemplary integrated circuit, the main voltage converter may further include at least one of the following: a charge pump; a switch-mode power supply; a linear regulator; and a charge pump and a linear regulator.

[0014] An exemplary integrated circuit may further include: a drive output defined by a main voltage converter; a main voltage converter defining a main control input, a main power input, and a main voltage output, the main power input being coupled to the main voltage output and the main voltage output being coupled to a main connector of a transistor within a processing core, the main voltage converter being configured to change the voltage driven to the main connector of the transistor within the processing core in response to the main control input; and a main voltage controller defining a drive input coupled to the drive output of the main voltage converter and a main control output coupled to the main control input of the main voltage converter. The main voltage controller may be configured to: measure a signal indicating power consumption via the drive output of the main voltage converter; generate a value indicating a modified main voltage in response to the signal indicating power consumption; and drive the value indicating the modified main voltage to the main control output. When the main voltage controller generates a value indicating a modified main voltage, the main voltage controller can be configured to generate the value indicating the modified voltage for use in at least one of the following: reducing power consumption of transistors; and reducing leakage current of transistors in the processing core. The main voltage converter may be a charge pump; and when the main voltage controller measures a signal indicating power consumption, the main voltage controller may be further configured to count the number of pump actions performed by the charge pump within a predetermined time period. The main voltage converter may be a switch-mode power converter; and when the main voltage controller measures a signal indicating power consumption, the main voltage controller is further configured to count the number of main switching actions of the switch-mode power converter within a predetermined time period. An exemplary integrated circuit may also include: a main voltage converter, which may be a charge pump and defines a pump ratio input, the charge pump being configured to operate according to operating characteristics in response to the pump ratio input; and a pump controller defining a first input coupled to a main power input of the charge pump, a second input coupled to a main voltage output of the charge pump, and a pump ratio output coupled to the pump ratio input of the charge pump. The pump controller can be configured to: read the value of the voltage indicated by the first input to the charge pump; read the value of the voltage indicated by the second input to the main voltage output; divide the value of the voltage indicated by the charge pump by the value of the voltage indicated by the main voltage output, the division generating a result; determine the charge pump ratio based on the result, a threshold ratio value, and a hysteresis value; and drive the charge pump ratio to the pump ratio input of the charge pump.

[0015] The exemplary integrated circuit may further include: a main voltage converter, which may be a charge pump and defines a pump ratio input, the charge pump being configured to operate according to operating characteristics in response to the pump ratio input; and a pump controller defining a first input coupled to a main power input of the charge pump, a second input coupled to a main voltage output of the charge pump, and a pump ratio output coupled to the pump ratio input of the charge pump. The pump controller may be configured to: read a value indicating a voltage supplied to the charge pump via the first input; read a value indicating a voltage driven to the main voltage output via the second input; divide the value indicating the voltage supplied to the charge pump by the value indicating the voltage driven to the main voltage output, the division generating a result; determine a charge pump ratio based on the result, a threshold ratio value, and a hysteresis value; and drive the charge pump ratio to the pump ratio input of the charge pump.

[0016] Another example is an integrated circuit package comprising: a first semiconductor die; a second semiconductor die; and the first semiconductor die and the second semiconductor die being co-packaged within the integrated circuit package. The first semiconductor die may include: a processing core; system memory coupled to the processing core; a bidirectional communication bus coupled to the processing core; a main voltage converter defining a main control input, a main power input, and a main voltage output, the main voltage converter being configured to change the voltage driven to the main voltage output in response to the main control input; a logic gate delay line embedded within the processing core, the logic gate delay line defining a plurality of gate outputs; and a power controller defining a plurality of gate inputs coupled to the plurality of gate outputs of the logic gate delay line and a main control output coupled to the main control input of the main voltage converter. The power controller can be configured to: read multiple gate outputs from the logic gate delay line; generate a logic speed measurement based on the read multiple gate outputs; calculate a speed margin based on the logic speed measurement; and drive a value indicating a modified voltage level to the main control output in response to the speed margin. The second semiconductor die may include wireless communication circuitry coupled to the bidirectional communication bus, the wireless chip being configured to communicate wirelessly with devices outside the integrated circuit package.

[0017] In an exemplary integrated circuit package, the first semiconductor die may further include: a drive output defined by a main voltage converter; a body voltage converter defining a body control input, a body power input, and a body voltage output, the body power input being coupled to the main voltage output and the body voltage output being coupled to a body connector of a transistor within a processing core, the body voltage converter being configured to change the voltage driven to the body connector of the transistor within the processing core in response to the body control input; and a body voltage controller defining a drive input coupled to the drive output of the main voltage converter and a body control output coupled to the body control input of the body voltage converter. The body voltage controller may be configured to: measure a signal indicating power consumption via the drive output of the main voltage converter; generate a value indicating a modified body voltage in response to the signal indicating power consumption; and drive the value indicating the modified body voltage to the body control output. When the main voltage controller generates a value indicating a modified main voltage, the main voltage controller can be configured to generate the value indicating the modified voltage for use in at least one of the following: reducing power consumption of transistors; and reducing leakage current of a plurality of transistors. The first semiconductor die may also include a neural network accelerator coupled to a weight memory. The neural network accelerator can be configured to: retrieve a plurality of weights of a neural network from the weight memory; and perform neural network processing, wherein the neural network processing includes a plurality of multiply-accumulate (MAC) operations that operate in parallel to multiply an input value with weights selected from the plurality of weights to accumulate the results of the multiplications to a sum of products representing values ​​corresponding to neurons in the neural network. In some cases, the main voltage converter may be a charge pump; and when the main voltage controller measures a signal indicating power consumption, the main voltage controller may be further configured to count the number of pumping actions performed by the charge pump within a predetermined time period. In some cases, the main voltage converter may be a switch-mode power converter; and when the main voltage controller measures a signal indicating power consumption, the main voltage controller may be further configured to count the number of times the main switch of the switch-mode power converter is activated within a predetermined time period. In some cases, the main voltage converter may be a charge pump that defines a pump ratio input, the charge pump being configured to operate according to operating characteristics in response to the pump ratio input, and the first semiconductor die may further include: a pump controller that defines a first input coupled to a main power input of the charge pump, a second input coupled to a main power output of the charge pump, and a pump ratio output coupled to the pump ratio input of the charge pump.The pump controller can be configured to: read the value of the voltage indicated by the first input to the charge pump; read the value of the voltage indicated by the second input to the main voltage output; divide the value of the voltage indicated by the charge pump by the value of the voltage indicated by the main voltage output, the division generating a result; determine the charge pump ratio based on the result, a threshold ratio value, and a hysteresis value; and drive the charge pump ratio to the pump ratio input of the charge pump.

[0018] In an exemplary integrated circuit package, the main voltage converter may be a charge pump defining a pump ratio input configured to operate according to operating characteristics in response to the pump ratio input. The first semiconductor die may also include a pump controller defining a first input coupled to a main power input of the charge pump, a second input coupled to a main voltage output of the charge pump, and a pump ratio output coupled to the pump ratio input of the charge pump. The pump controller may be configured to: read a value indicating a voltage supplied to the charge pump via the first input; read a value indicating a voltage driven to the main voltage output via the second input; divide the value indicating the voltage supplied to the charge pump by the value indicating the voltage driven to the main voltage output, the division generating a result; determine a charge pump ratio based on the result, a threshold ratio value, and a hysteresis value; and drive the charge pump ratio to the pump ratio input of the charge pump. Attached Figure Description

[0019] To describe the exemplary embodiments in detail, reference will now be made to the accompanying drawings, in which:

[0020] Figure 1 A hearing aid integrated circuit according to at least some embodiments is shown in block diagram form;

[0021] Figure 2 A block diagram of a power management system and a processing kernel according to at least some embodiments is shown;

[0022] Figure 3 A block diagram illustrating the main voltage management according to at least some implementation schemes is shown;

[0023] Figure 4 It is a block diagram of the main voltage management according to at least some implementation schemes;

[0024] Figure 5a A block diagram of a power management system according to at least some embodiments is shown;

[0025] Figure 5b A block diagram of a power management system according to at least some embodiments is shown; and

[0026] Figure 6 A flowchart of a method according to at least some implementation schemes is shown.

[0027] definition

[0028] Various terms are used to refer to specific system components. Different companies may use different names to refer to a component – ​​this document is not intended to distinguish between components with different names but the same function. In the following discussion and in the claims, the terms “comprising” and “including” are used in an open form, and therefore, these terms should be interpreted as meaning “including, but not limited to…”. Additionally, the terms “coupled” or “coupled” are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, the connection can be made either directly or indirectly via other devices and connections.

[0029] With respect to electrical equipment (whether standalone or as part of an integrated circuit), the terms "input" and "output" refer to the electrical connection to the electrical equipment and should not be considered as verbs indicating the need for operation. For example, a voltage converter (such as a switching power converter) may have a power input, and this "input" defines the electrical connection to the voltage converter and should not be understood as requiring power to be input to an operational amplifier. Similarly, a voltage converter may have a voltage output, and the "output" defines the electrical connection to the voltage converter and should not be understood as requiring the output of voltage and / or power from the voltage converter. Detailed Implementation

[0030] The following discussion relates to various embodiments of the invention. While one or more of these embodiments may be preferred, the disclosed embodiments should not be construed as or otherwise used to limit the scope of this disclosure, including the claims. Furthermore, those skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is intended only as an example of that embodiment and is not intended to imply that the scope of this disclosure, including the claims, is limited to that embodiment.

[0031] Various exemplary embodiments relate to methods and systems for power management systems for integrated circuits. More specifically, exemplary embodiments relate to power management systems for controlling the output voltage of a voltage converter to reduce the power consumption of an integrated circuit. More specifically, exemplary embodiments relate to reading results from a logic gate delay line and modifying the output voltage of the voltage converter based on those results. Other exemplary embodiments relate to power management systems for controlling the body voltage of a body connection driven to a plurality of transistors to reduce power consumption associated with leakage current. Further exemplary embodiments relate to power management systems for controlling the pump ratio of a charge pump to reduce power consumption. Further exemplary embodiments relate to power management systems for controlling the body voltage by controlling the pump ratio of the charge pump. The specification first turns to the overall system to guide the reader.

[0032] Figure 1 A hearing aid integrated circuit (IC) 100, which can be integrated into a hearing aid according to at least some embodiments, is illustrated in block diagram form. An exemplary hearing aid including the hearing aid IC 100 has an associated battery 103, a microphone 102, and a speaker 104 electrically coupled to the hearing aid IC 100. During operation, the hearing aid receives sound through the microphone 102, converts the sound waves into electrical signals, and forwards the electrical signals to be processed by the hearing aid IC 100. The processed signals are converted into sound waves by the speaker 104 and sent to the ear. The exemplary hearing aid is powered by the battery 103. As will be discussed in more detail below, the hearing aid IC 100 includes a mechanism for regulating power consumption by adaptively scaling the voltage supplied to various logic circuits of the hearing aid IC 100. For example, the voltage supplied to the logic circuits may be reduced to a level that allows the logic circuits to operate at a specified operating frequency, taking into account variations in silicon process technology and temperature.

[0033] An exemplary hearing aid IC 100 includes: a power management 110, a processing core 120 with embedded logic gate delay lines 130, a communication bus 140, multiple system memories 150, and multiple system interfaces 160 (labeled "I / F160" in the figure). The power management 110 is coupled to all circuitry on the hearing aid IC 100 and provides operable power. Although Figure 1Although not shown, the processing core 120, system memory 150, and system interface 160 are coupled to the communication bus 140. In the exemplary system, the communication bus 140 may be part of the system interface 160. The system interface 160 is configured to be coupled to additional external devices, such as electrically erasable programmable read-only memory (EEPROM), volume control circuitry, mating connectors, push-buttons, and sensors. The exemplary wireless chip 142 and external non-volatile memory 144 are electrically coupled to the hearing aid IC 100 via the communication bus 140 or via a separate communication bus (not specifically shown).

[0034] System interface 160 (e.g., communication bus 140) may take any suitable form, such as a Serial Peripheral Interface (SPI), Dual SPI (DSPI), Quad SPI (QSPI), I2C, I3C, Pulse Code Modulation (PCM) signal interface, Universal Asynchronous Receiver / Transmitter (UART) circuitry, General Purpose Input / Output (GPIO) pins, an embedded multimedia card (eMMC), and a low-speed A / D (LSAD) converter. SPI, DSPI, and QSPI are synchronous, full-duplex, serial primary-secondary based communication interfaces and may be 3-wire or 4-wire based. I2C and I3C, on the other hand, are serial protocols based on two-wire interfaces and are configured to support multi-master features. An exemplary PCM interface may be used to stream audio signal data to and from hearing aid 100. An exemplary UART may include logic circuitry to transmit and receive asynchronous serial communication, which includes data with a configurable format and configurable speed. Exemplary GPIOs are digital signal pins whose function (specifically, input or output) is determined during runtime. In the exemplary system, GPIO pins can be connected to external digital inputs (such as push buttons) or digital outputs (such as controllers or triggers of external companion chips). An exemplary eMMC may include an interface, flash memory, and a flash memory controller to provide an embedded non-volatile memory system. An exemplary LSAD can provide analog-to-digital conversion of electrical signals for data processing purposes and may include internal power inputs and ground inputs.

[0035] Processing core 120 performs signal processing functions, including various digital signal processing (DSP) algorithms and multiple types for wireless communication protocols. In one example, processing core 120 includes at least one low-power DSP core and a reduced instruction set computer (RISC). Exemplary processing core 120 may also include a filter engine and multiple configurable hardware accelerators. In another exemplary system, processing core 120 may include a neural network hardware accelerator to implement neural network functions, including fetching multiple weights from a weight memory and performing multiple multiply-accumulate (MAC) operations in parallel. The MAC operation repeatedly multiplies the input value with weights selected from the multiple weights to accumulate the result of the multiplication into a sum representing the product of values ​​corresponding to neurons in the neural network.

[0036] Power management 110 includes circuitry configured to implement adaptive voltage scaling to modify the voltage supplied to the logic circuitry, thereby reducing the power consumed by the hearing aid. In some cases, a single battery is sufficient, but in others, multiple batteries (e.g., in series or parallel) may be used. Depending on the type of hearing aid, various types of batteries may be used. In the exemplary system, the battery provides a supply voltage of less than 2V. In some cases, the battery is rechargeable; in others, it is disposable.

[0037] Power management 110 is communicatively coupled to logic gate delay lines 130 within processing core 120 and can read the measurement results generated by logic gate delay lines 130. Logic gate delay lines 130 and the measurement results derived therefrom are discussed in more detail below. However, once read, the measurement results are further processed by power management 110 and used to control one or more power converters (e.g., switch-mode power converters or charge pumps) within power management 110.

[0038] See still Figure 1 The hearing aid IC 100 communicates with an exemplary external wireless chip 142 via a communication bus 140. In the exemplary system, the wireless chip 142 includes a multi-protocol system-on-a-chip (SoC) to implement various wireless communication-related schemes. For example, the wireless chip 142 may include an SoC to implement Bluetooth Low Energy (BLE) and / or multiple 2.4 GHz ultra-low power wireless applications. Furthermore, in the exemplary system, a non-volatile memory 144 is coupled to the hearing aid IC 100 via the communication bus 140. The non-volatile memory 144 may include any suitable non-volatile component, such as EEPROM, flash memory, mass storage devices, or a combination thereof. The specification now turns to a more detailed description of power management 110.

[0039] Figure 2A block diagram of a power management system and processing core according to at least some embodiments is shown. Specifically, exemplary power management 110 includes a power controller 210 and a main voltage converter 220. The main voltage converter 220 defines a main control input 222, a main power input 226, and a main voltage output 224. The main power input 226 is coupled to a battery 103, and the main voltage output 224 is coupled to and provides operating power to all logic circuitry of a hearing aid IC 100. Exemplary power controller 210 defines a plurality of gate inputs 214A-214C and a main control output 212. The main control output 212 is coupled to the main control input 222 of the main voltage converter 220. The main voltage converter 220 is configured to change the voltage driven to the main voltage output 224 in response to a signal change at the main control input 222.

[0040] Logic gate delay line 130 is embedded within processing core 120. Exemplary logic gate delay line 130 defines a plurality of gate outputs 134A-134C coupled to gate inputs 214A-214C of power controller 210. Although only three gate outputs 134A-134C are shown (and therefore only three gate inputs 214A-214C are shown), logic gate delay line 130 may define any suitable number of gate outputs 134. In embodiments, the number of output gates 134 depends on the number of bits specified for the result. For example, the number of gate outputs 134 suitable for a 3-bit result could be 7. In another example, the number of gate outputs 134 suitable for a 4-bit result could be 15. Exemplary logic gate delay line 130 includes a plurality of delay elements 132A-132C coupled to the plurality of gate outputs 134A-134C. Although in Figure 2 Only three delay elements 132A-132C are shown, but the logic gate delay line 130 can define any suitable number of delay elements 132. Multiple delay elements 132 can include multiple series-aligned buffers. Logic gate outputs 134 can each include the logic output of a flip-flop. In another exemplary system, each logic gate output 134 may include a flip-flop further associated with a recapture logic component (not shown). For example, the recapture logic component may include a multiplexer configured to reduce metastability by first feeding the captured signal into the multiplexer and then into the logic gate output 134. In one example, in the next clock cycle, the signal may be fed back into the multiplexer input and then back into the logic gate output 134 to achieve resynchronization. The delay line of the logic gate delay line 130 may be placed along and run alongside the longest physical digital logic processing path within the processing core 120. The hearing aid IC 100 may include more than one logic gate delay line. In an exemplary case, the hearing aid IC 100 may include multiple logic gate delay lines configured to reduce the impact of on-chip process variations.

[0041] Logic gate delay line 130 is configured to generate a logic speed measurement or result read by power management 110. Specifically, when logic gate delay line 130 is in operation, transitions are driven onto logic gate delay line 130. For example, a transition may include a failure state transitioning to an active state, or an active state transitioning to a failure state. The transition propagates along logic gate delay line 130 through various delay elements. For example, at the transition of the next clock cycle, logic gate output 134 captures the result at a predetermined measurement point (e.g., a predetermined time period after driving the transition onto logic gate delay line 130). If a signal indicating a transition has propagated along the logic gate delay line to logic gate output 134, that particular logic gate output 134, which stores an initial '0' value, captures a '1' value. Thus, which logic gate output 134 captures a '1' value in response to a transition indicates the propagation distance along the delay line within the predetermined period, and power controller 210 determines the measured logic speed based on that propagation distance.

[0042] The exemplary logic gate delay line 130 may include a synthesized logic block having multiple standard cells (e.g., buffers, AND gates). A verification scheme for the exemplary logic gate delay line 130 may include static timing analysis (STA) based on multiple standard cells under operating conditions, which may include process-voltage-temperature (PVT) and / or clock frequency. Since the logic gate delay line 130 is located adjacent to a path (e.g., the longest path) through the processing core 120, the delay line 130 may include a comparison result with a calculated path through the hearing aid IC 100. Therefore, the result of the logic gate delay line 130 (e.g., how far an active or inactive state propagates along the logic gate delay line 130 over a predetermined time period) may indicate the setup timing margin of the processing core 120.

[0043] According to an exemplary embodiment, power controller 210 is configured to read multiple logic gate outputs 134A-134C from logic gate delay line 130. Exemplary power controller 210 generates a logic speed measurement based on the read logic gate outputs 134A-134C and calculates a speed margin using this measurement. Based on this speed margin, exemplary power controller 210 drives a value indicating a modified voltage level to main control output 212 to regulate the output voltage generated by main voltage converter 220.

[0044] More specifically, power controller 210 reads gate output 134, which indicates the distance a transition (e.g., active state) propagates along logic gate delay line 130 over a predetermined time period. Based on the logic speed measurement, power controller 210 can calculate a speed margin. This speed margin can be determined during the characterization of hearing aid IC 100. In an exemplary system, the speed margin can be specified based on a settling time, which includes the shortest time before the logic component stabilizes before a subsequent clock edge arrives. The speed margin can be specific to operating conditions that may include process-voltage-temperature (PVT) and clock frequency. In an exemplary system, the larger the overall number corresponding to the value captured by logic gate output 134 (i.e., the farther the transition propagates along the delay line), the higher the speed margin associated with hearing aid IC 100. Conversely, the smaller the overall number corresponding to the value captured by logic gate output 134, the lower the speed margin associated with hearing aid IC 100. The speed margin can be used to drive a value indicating a modified voltage level to the main control input 222 of main voltage converter 220.

[0045] For example, assume that logic gate delay line 130 comprises ten logic gates, and therefore ten logic gate outputs 134. Also assume that the logic gates are reset or disabled before the test begins. In an exemplary case, an active state is applied to the first logic gate on the first edge of a clock signal, and then the state of each logic gate output 134 is read on the next edge of that clock signal. If the active state propagates halfway along logic gate delay line 130, the reading may be in the form of 1111100000 for a specific combination of clock speed and applied voltage. If the clock speed increases (all other conditions remain equal), the next logic speed measurement may be 1100000000 (i.e., the active state has less time to propagate). Conversely, if the clock speed decreases (all other conditions remain equal), another logic speed measurement may be 1111111100 (i.e., the active state has more time to propagate).

[0046] In the exemplary system, the power controller 210 may include a target speed register 216. During the initialization of the hearing aid IC 100, a target speed value for a particular hearing aid IC 100 can be written to the target speed register 216. The target speed value can be determined using STA and / or during the characterization of the hearing aid IC 100 after manufacturing, and therefore differences caused by manufacturing variations (e.g., variations in light emission doping, linewidth variations, oxide thickness variations, etc.) and clock jitter can be taken into account. However, the exemplary power controller 210 determines a speed margin based on the difference between a logic speed measurement and the target speed value stored in the target speed register 216. More specifically, the power controller 210 can determine the speed margin based on the amount by which the logic speed measurement is faster or slower than the target speed value, and use the speed margin to determine a modified voltage level. Specifically, if the logic speed measurement is faster than the target speed value, the power controller 210 can set the modified voltage value to be lower than the current output voltage. Similarly, if the measured logic speed is slower than the target speed value, the power controller 210 can set the modified voltage value to be higher than the current output voltage. In response to setting the modified voltage value, the power controller 210 can then drive a signal indicating the modified voltage level to the main control input 222 of the main voltage converter 220.

[0047] For example, suppose the target speed register 216 holds a target speed value that directly or indirectly indicates, in a system with ten gates in the logic gate delay line 130, the target speed is reached when the active state propagates through five of those ten gates (e.g., the target reading could be 1111100000). If the logic speed measurement produces a reading of, for example, 1111111100, the target speed measurement results in a speed margin of incremental distance three logic gates after the target point. In this case, the system can speed up the clock or change the voltage (or both) to improve processor performance. On the other hand, if the logic speed measurement produces a reading of, for example, 1100000000, the target speed measurement results in a speed margin of incremental distance three logic gates before the target point. In this case, the system can slow down the clock or change the voltage (or both) to reduce internal logic errors. It should be understood that the power controller 210 does not need to directly utilize the exemplary results of the position encoding shown above to operate. For example, the system can encode the distance result as a quantity with fewer bits (e.g., a 3-bit result for a logic gate delay line for 7 gates, or a 4-bit result for a logic gate delay line for 15 gates). This specification now turns to describe the exemplary main voltage converter 220 in more detail.

[0048] In response to a signal driven to the main control input 222 by the power controller 210, the main voltage converter 220 can generate a desired output voltage. In use, in response to a value or signal driven to the main control input 222 (e.g., a value indicating a modified voltage level), the main voltage converter 220 can modify the output voltage level to drive the modified output voltage to the main voltage output 224. In an exemplary system, the main voltage converter 220 may not increase the output voltage level above a predetermined higher level, and / or may not decrease the output voltage level below a predetermined lower level.

[0049] The main voltage converter 220 may include any suitable device configured to provide an output voltage based on a supply voltage. In an exemplary system, the main voltage converter 220 may include a charge pump configured to generate an output voltage that may be a predetermined ratio of the supply voltage. This ratio may be programmed to any suitable value. In an exemplary system, suitable values ​​may include ratios such as '1 / 1' (LDO mode, charge pump disabled), '4 / 5', '3 / 4', '2 / 3', '1 / 2', and '1 / 3'. Thus, by changing the ratio and / or operating frequency, the output voltage can be selectively controlled. In another exemplary system, the main voltage converter 220 may include a switch-mode power converter configured to generate a modified output voltage by changing the duty cycle of a switching device. In another exemplary system, the main voltage converter 220 may include a linear regulator having a buck converter configured to modify the output voltage. In other cases, the linear regulator may be combined with another device (e.g., a charge pump, a switch-mode power converter) to supply and regulate the output voltage.

[0050] Figure 3 A block diagram of an exemplary power management 110 according to an alternative embodiment is shown. The exemplary power management 110 includes the previously introduced power controller 210, main voltage converter 320, and main voltage management 310. Similarly, the power controller 210 defines a main control output 212. The main voltage converter 320 defines a main power input 226, a main voltage output 224, and a main drive output 324. As previously described, the main power input 226 is coupled to the battery 103, and the main voltage output 224 is coupled to and provides operating power to all logic circuitry of the hearing aid IC 100. The main voltage output 224 is also coupled to the main voltage management 310. The main voltage management 310 defines a drive input 312 and a main voltage output 314. The drive input 312 is coupled to the main drive output 324. The main voltage output 314 is coupled to a plurality of main connectors (not specifically shown) of transistors within the processing core 120.

[0051] During operation, exemplary power management 110 can reduce the combined power consumption associated with hearing aid IC 100. Combined power may include dynamic power and power associated with leakage current. Exemplary power management 110 can adjust dynamic power consumption (e.g., by adjusting the voltage provided by main voltage converter 320) and leakage current (e.g., by adjusting the voltage provided by main voltage management 310). For example, during operation, when hearing aid IC 100 is processing a signal, exemplary power management 110 can adjust dynamic power consumption and leakage current individually or in combination based on the intensity of audio processing, which may be classified depending on the audio environment.

[0052] Figure 3 The exemplary power management 110 can be configured to modify the output voltage of the main voltage converter 320, such as Figure 1 and 2 The exemplary power management 110 can also be configured to measure a value indicating dynamic power consumption and, in response to that measurement, change the body bias voltage or body voltage driven to a plurality of transistors to modify leakage current and threshold voltage. Changing the body voltage allows the transistor speed to be changed, thereby changing the leakage current. More specifically, increasing the transistor speed increases the leakage current, while decreasing the transistor speed decreases the leakage current.

[0053] In addition to providing an output voltage on the main voltage output 224, the exemplary main voltage converter 320 also provides a signal indicating power consumption to the main driver output 324, as will be shown below. Figure 4 As described in more detail below. Similar to the exemplary main voltage converter 220, the main voltage converter 320 may include any suitable device configured to provide an output voltage based on the supply voltage. For example, the main voltage converter 320 may include a charge pump, a switch-mode power supply, a linear regulator, and / or a charge pump and a linear regulator.

[0054] Figure 4 This is a block diagram of an exemplary host voltage management 310 according to at least some embodiments. The host voltage management 310 includes a host voltage controller 410 and a host voltage converter 420. The host voltage controller 410 defines a drive input 412 and a host control output 414. The drive input 412 is coupled to a main drive output 324 of the host voltage converter 320. Figure 3The main voltage converter 420 defines a main control input 422, a main power supply input 416, and a main voltage output 314 to provide one or more main bias voltages. For example, the main voltage output 314 may be configured to provide a main bias voltage for an N-type metal-oxide-semiconductor (NMOS) transistor and a main bias voltage for a P-type metal-oxide-semiconductor (PMOS) transistor. The main power supply input 416 is coupled to a main voltage output 224 (not shown). The main control output 414 is coupled to the main control input 422 of the main voltage converter 420. Figure 4 As shown, the main voltage output 314 is coupled to the main connector of the multiple transistors 430A-430C of the processing core 120. Although Figure 4 Only three transistors 430A-430C are shown in the diagram to avoid overcomplicating it, but the main voltage converter 420 can be coupled to any suitable number of transistors 430A-430C, including all the transistors in the processing core 120.

[0055] The body voltage management 310 can be configured to modify the body voltage associated with or applied to transistors 430A-430C. For example, modifying the body voltage can change the threshold voltage associated with transistors 430A-430C to modify the transistor speed, thereby modifying the associated leakage current. For example, the body voltage management 310 can be configured to apply a body bias voltage to change the threshold voltage, thereby changing the transistor speed. Further details regarding the operation of the body voltage management 310 are provided below.

[0056] Still referencing Figure 4An exemplary host voltage controller 410 measures a signal indicating the power supplied to the main drive output 324 of the host voltage converter 320. In the exemplary system, the host voltage converter 320 can be configured to perform an action associated with voltage conversion as long as the value driven to the host voltage output 314 is within a specified voltage level range, and can be configured not to perform an action if the value is outside the specified voltage level range. Therefore, the signal indicating power consumption can be measured based on counting the number of actions associated with the host voltage converter 320. Specifically, the host voltage controller 410 can count the number of actions performed by the host voltage converter 320 within a predetermined time period and associate the number of actions with the power consumption of the hearing aid IC within the predetermined time period. In the exemplary system, the host voltage converter 320 includes an asynchronous charge pump, and the host voltage controller 410 can be configured to count the number of pump actions of the charge pump within the predetermined time period, multiply the number of pump actions by a coefficient to determine the amount of energy per pump action depending on the charge pump ratio configuration, to determine a value indicating power consumption. In another exemplary system, the main voltage converter 320 includes an asynchronous switch-mode power converter, and the main voltage controller 410 can be configured to count the number of times the main switch of the switch-mode power converter is activated within a predetermined time period to determine a value indicating power consumption.

[0057] In response to a signal indicating power consumption, the host voltage controller 410 can generate a value associated with the host voltage and drive that value to the host control output 414. This value can indicate a modification to the host voltage such that it reduces the power consumption associated with transistors 430A-430C and / or the leakage current associated with multiple transistors 430A-430C. In one example, the host voltage can reduce the sum of the power consumption associated with transistors 430A-430C and the power consumption associated with the leakage current. In an exemplary system, the value driven to the host control output 414 can be associated with adjusting the host bias voltage of the NMOS transistors in one direction and adjusting the host bias voltage of the PMOS transistors in the opposite direction.

[0058] In the exemplary system, the main voltage controller 410 can determine whether power consumption increases or decreases within a predetermined time period. Based on whether power consumption increases or decreases, the main voltage controller 410 (and thus the main voltage management 310) in the exemplary system can increase or decrease the main bias voltage applied to transistors 430A-430C by, for example, modifying the value to the main control output 414 via a configured step size. In some exemplary systems, the main voltage controller 410 can be configured to change the value to the main control output 414 to maintain it within a predetermined range.

[0059] The main voltage converter 420 can take any suitable form, such as a charge pump; a switch-mode power supply; a linear regulator; and / or a charge pump and a linear regulator. When used, in response to the main control input 422, the main voltage converter 420 is configured to change the voltage driven on the main voltage output 314. In some exemplary cases, the main voltage converters 220 / 320 can be charge pumps. When the main voltage converters 220 / 320 are charge pumps, in addition to changing the output voltage driven to the main voltage output 224 to reduce power consumption, further power reduction can be achieved by selectively controlling the charge pump ratio.

[0060] Figure 5a A block diagram of an exemplary power management 110 including a charge pump management 500 according to at least some embodiments is shown. The charge pump management 500 is configured to implement a system for controlling the charge pump ratio. The exemplary charge pump management 500 includes a previously introduced power controller 210, a main voltage converter 220 in the form of a charge pump 520, and a pump controller 510. As previously described, the power controller defines a main control output 212. The pump controller 510 defines a first input 514 coupled to a main power input 226, a second input 516 coupled to a main voltage output 224, and a pump ratio output 512. As previously described, the main voltage converter 220 defines a main power input 226, a main voltage output 224, and a main control input 222. The exemplary charge pump 520 defines a pump ratio input 522 and a main voltage output 224. The main control output 212 of the power controller 210 is coupled to the main control input 222 of the main voltage converter 220. The pump ratio input 522 is coupled to the pump ratio output 512.

[0061] Pump controller 510 is configured to read the value of the voltage indicated to be supplied to charge pump 520 (e.g., reading the voltage of battery 103) via a first input 514. Additionally, exemplary pump controller 510 is configured to read the value of the voltage indicated to be driven to main voltage output 224 via a second input 516. Based on the values ​​read at the first input 514 and the second input 516, pump controller 510 is configured to drive a signal to pump ratio output 512 to select the pump ratio of charge pump 520. In an exemplary case, pump controller 510 may divide the value of the voltage indicated to be supplied to charge pump 520 by the value of the voltage indicated to be driven to main voltage output 224 to generate a result. Based on this result, pump controller 510 may determine the charge pump ratio, threshold ratio value, and hysteresis value. Pump controller 510 may drive the charge pump ratio to pump ratio input 522 of charge pump 520. In response to pump ratio input 522, charge pump 520 may operate according to operating characteristics. For example, the charge pump may generate an output voltage based on operating characteristics.

[0062] Pump controller 510 can also be configured to reduce the number of switches between two different charge pump ratios. In various exemplary systems, pump controller 510 may be coupled to a configuration register (not shown) to store a programmable threshold ratio value and a configurable hysteresis value. In exemplary systems, the threshold ratio value may be programmed to a preferred switching ratio. In use, pump controller 510 may compare a calculated charge pump ratio obtained based on division with the threshold ratio. Pump controller 510 may then make a decision, based on the division and the hysteresis value, whether to switch from the current charge pump ratio to the calculated charge pump ratio.

[0063] Figure 5b This is a block diagram of an exemplary power management system 110 configured to implement control of the host voltage and further automatically control of the charge pump ratio. The exemplary power management system 110 includes a charge pump management system 500 and a host voltage management system 310. The charge pump management system 500 is coupled to the host voltage management system 310. In the exemplary system, the charge pump management system 500 may be coupled to the host voltage management system 310 via a drive input 412. Various components of the exemplary power management system 110 are described in detail in the accompanying drawings above.

[0064] Figure 6 A method according to at least some embodiments is illustrated. Specifically, the method begins (box 600) and includes: reading a logic speed measurement from a logic gate delay line by a power supply controller (box 602); calculating a speed margin by the power supply controller based on the logic speed measurement (box 604); generating a value indicating a modified voltage level by the power supply controller, the generation being based on the speed margin (box 606); and modifying an output voltage by a main voltage converter on a semiconductor substrate in response to the value indicating the modified voltage level (box 608). The method may then end (box 610).

[0065] Many electrical connections in the accompanying drawings are shown as direct couplings without intermediate devices, but this is not explicitly stated in the description above. However, for electrical connections shown in the drawings without intermediate devices, this paragraph should serve as a preliminary basis for the claims to refer to any electrical connection as a “direct coupling.”

[0066] The foregoing discussion is intended to illustrate the principles and various embodiments of the invention. Once the foregoing disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are intended to encompass all such variations and modifications.

Claims

1. A method for operating an integrated circuit on a semiconductor substrate, the method comprising: The power controller reads logic speed measurements from multiple gate outputs defined by logic gate delay lines, the power controller and the logic gate delay lines being implemented on the semiconductor substrate, wherein the logic gate delay lines are embedded within the processing core of the integrated circuit and are placed along and run alongside the longest physical digital logic processing path within the processing core; The power controller calculates the speed margin based on the logic speed measurement value; The power controller generates a value indicating the voltage to be modified, the generation being based on the speed margin; as well as The output voltage is modified by the main voltage converter on the semiconductor substrate in response to the value indicating the modified voltage.

2. The method according to claim 1: The calculation of the speed margin also includes determining the difference between the logical speed measurement value and the target speed value; The modification of the output voltage further includes at least one of the following: increasing the output voltage in response to the value indicating the modified voltage; and decreasing the output voltage in response to the value indicating the modified voltage.

3. The method according to claim 1, further comprising: A signal indicating the power consumption of a device on the semiconductor substrate is measured by a main voltage controller, which is implemented on the semiconductor substrate. The main voltage controller generates a value indicating the modification of the main voltage, the generation being based on a signal indicating power consumption; as well as The host voltage applied to a plurality of transistors on the semiconductor substrate is modified by a host voltage converter on the semiconductor substrate, the modification being performed in response to the value indicating the modified voltage.

4. The method of claim 3, wherein the main voltage converter is a charge pump, and the method further comprises: The value of the voltage supplied to the charge pump is read by the pump controller, which is implemented on the semiconductor substrate; The value of the output voltage indicating the charge pump is read by the pump controller; The pump controller divides the value of the indicated supplied voltage by the value of the indicated output voltage to generate a result; The charge pump ratio is determined based on the results, the threshold ratio value, and the hysteresis value. as well as The operating characteristics of the charge pump are changed based on the charge pump ratio.

5. The method of claim 1, wherein the main voltage converter is a charge pump, and the method further comprises: The value of the voltage supplied to the charge pump is read by the pump controller, which is implemented on the semiconductor substrate; The value of the output voltage indicating the charge pump is read by the pump controller; The pump controller divides the value of the indicated supplied voltage by the value of the indicated output voltage to generate a result; The charge pump ratio is determined based on the results, the threshold ratio value, and the hysteresis value. as well as The operating characteristics of the charge pump are changed based on the charge pump ratio.

6. An integrated circuit on a semiconductor substrate, the integrated circuit comprising: Process the kernel; System memory, which is coupled to the processing kernel; A main voltage converter, defining a main control input, a main power input, and a main voltage output, the main voltage converter being configured to change the voltage driven to the main voltage output in response to the main control input; A logic gate delay line is embedded within the processing core and placed along and runs alongside the longest physical digital logic processing path within the processing core, the logic gate delay line defining multiple gate outputs; and A power controller that defines a plurality of gate inputs coupled to the plurality of gate outputs of the logic gate delay lines and a main control output coupled to the main control input of the main voltage converter, and the power controller is configured to: Read the outputs of the plurality of gates from the logic gate delay lines; Logical speed measurement values ​​are generated based on reading the outputs of the multiple gates; The speed margin is calculated based on the logical speed measurement value; as well as In response to the speed margin, a value indicating a modified voltage level is driven to the main control output.

7. The integrated circuit of claim 6, wherein the logic gate delay line further comprises a plurality of serially aligned buffers disposed adjacent to the logic path within the processing core.

8. The integrated circuit of claim 6, wherein the power controller further comprises: A target speed register, which is coupled to a communication bus; When the power controller calculates the speed margin, the power controller is further configured to determine the difference between the logical speed measurement value and the target speed value stored in the target speed register.

9. The integrated circuit according to claim 6, further comprising: A drive output, which is defined by the main voltage converter; A main voltage converter defines a main control input, a main power input, and a main voltage output, the main power input being coupled to the main voltage output and the main voltage output being coupled to a main connector of a transistor within the processing core, the main voltage converter being configured to change the voltage of the main connector of the transistor within the processing core in response to the main control input; and A main voltage controller, defining a drive input coupled to the drive output of the main voltage converter and a main control output coupled to the main control input of the main voltage converter, the main voltage controller being configured to: The power consumption signal is measured by the drive output of the main voltage converter; as well as A value indicating a modified body voltage is generated in response to the signal indicating power consumption; as well as The value indicating the modified main body voltage will be driven to the main body control output.

10. The integrated circuit according to claim 9, further comprising: The main voltage converter further includes a charge pump and defines a pump ratio input, the charge pump being configured to operate according to operating characteristics in response to the pump ratio input; A pump controller, defining a first input coupled to the main power input of the charge pump, a second input coupled to the main voltage output of the charge pump, and a pump ratio output coupled to the pump ratio input of the charge pump, the pump controller being configured to: The value of the voltage provided to the charge pump via the first input is read. The value of the voltage driven to the main voltage output is read through the second input; The value of the voltage indicated to be supplied to the charge pump is divided by the value of the voltage indicated to be driven to the main voltage output to generate the result; The charge pump ratio is determined based on the results, the threshold ratio value, and the hysteresis value. as well as The charge pump ratio is driven to the pump ratio input of the charge pump.

11. The integrated circuit according to claim 6, further comprising: The main voltage converter further includes a charge pump and defines a pump ratio input, the charge pump being configured to operate according to operating characteristics in response to the pump ratio input; A pump controller, defining a first input coupled to the main power input of the charge pump, a second input coupled to the main voltage output of the charge pump, and a pump ratio output coupled to the pump ratio input of the charge pump, the pump controller being configured to: The value of the voltage provided to the charge pump via the first input is read. The value of the voltage driven to the main voltage output is read through the second input; The value of the voltage indicated to be supplied to the charge pump is divided by the value of the voltage indicated to be driven to the main voltage output to generate the result; The charge pump ratio is determined based on the results, the threshold ratio value, and the hysteresis value. as well as The charge pump ratio is driven to the pump ratio input of the charge pump.

12. An integrated circuit package, the integrated circuit package comprising: A first semiconductor die, the first semiconductor die comprising: Process the kernel; System memory, which is coupled to the processing kernel; A bidirectional communication bus, which is coupled to the processing kernel; A main voltage converter, defining a main control input, a main power input, and a main voltage output, the main voltage converter being configured to change the voltage driven to the main voltage output in response to the main control input; A logic gate delay line, embedded within the processing core and placed along and running alongside the longest physical digital logic processing path within the processing core, the logic gate delay line defining a plurality of gate outputs; and A power controller that defines a plurality of gate inputs coupled to the plurality of gate outputs of the logic gate delay lines and a main control output coupled to the main control input of the main voltage converter, and the power controller is configured to: Read the outputs of the plurality of gates from the logic gate delay lines; Logical speed measurement values ​​are generated based on reading the outputs of the multiple gates; The speed margin is calculated based on the aforementioned logical speed measurement; and In response to the speed margin, a value indicating a modified voltage level is driven to the main control output; A second semiconductor die, the second semiconductor die including a wireless communication circuit coupled to the bidirectional communication bus, the wireless communication circuit being configured to communicate wirelessly with devices outside the integrated circuit package; The first semiconductor die and the second semiconductor die are jointly packaged into the integrated circuit package.

13. The integrated circuit package of claim 12, wherein the first semiconductor die further comprises: A drive output, which is defined by the main voltage converter; A main voltage converter defines a main control input, a main power input, and a main voltage output, the main power input being coupled to the main voltage output and the main voltage output being coupled to a main connector of a transistor within the processing core, the main voltage converter being configured to change the voltage of the main connector of the transistor within the processing core in response to the main control input; and A main voltage controller, defining a drive input coupled to the drive output of the main voltage converter and a main control output coupled to the main control input of the main voltage converter, the main voltage controller being configured to: The power consumption signal is measured by the drive output of the main voltage converter; as well as A value indicating a modified body voltage is generated in response to the signal indicating power consumption; as well as The value indicating the modified main body voltage will be driven to the main body control output.

14. The integrated circuit package of claim 13, wherein the main voltage converter further includes a charge pump and defines a pump ratio input, the charge pump being configured to operate according to an operating characteristic in response to the pump ratio input, and wherein the first semiconductor die further includes: A pump controller, defining a first input coupled to the main power input of the charge pump, a second input coupled to the main power output of the charge pump, and a pump ratio output coupled to the pump ratio input of the charge pump, the pump controller being configured to: The value of the voltage provided to the charge pump via the first input is read. The value of the voltage driven to the main voltage output is read through the second input; The value of the voltage indicated to be supplied to the charge pump is divided by the value of the voltage indicated to be driven to the main voltage output to generate the result; The charge pump ratio is determined based on the results, the threshold ratio value, and the hysteresis value. as well as The charge pump ratio is driven to the pump ratio input of the charge pump.

15. The integrated circuit package of claim 12, wherein the main voltage converter further includes a charge pump and defines a pump ratio input, the charge pump being configured to operate according to an operating characteristic in response to the pump ratio input, and wherein the first semiconductor die further includes: A pump controller, defining a first input coupled to the main power input of the charge pump, a second input coupled to the main voltage output of the charge pump, and a pump ratio output coupled to the pump ratio input of the charge pump, the pump controller being configured to: The value of the voltage provided to the charge pump via the first input is read. The value of the voltage driven to the main voltage output is read through the second input; The value of the voltage indicated to be supplied to the charge pump is divided by the value of the voltage indicated to be driven to the main voltage output to generate the result; The charge pump ratio is determined based on the results, the threshold ratio value, and the hysteresis value. as well as The charge pump ratio is driven to the pump ratio input of the charge pump.

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