Integrated Passive Components

Abstract

This integrated passive component has an upper surface and a lower surface that are facing in mutually opposite directions. The integrated passive component comprises: an insulating film having a first surface facing in the same direction as the upper surface and a second surface facing in the same direction as the lower surface; a capacitor disposed within the insulating film; and a multilayer wiring structure disposed on the first surface of the insulating film. The multilayer wiring structure includes a plurality of resin layers and a plurality of wiring layers, which are alternately laminated. Each of the plurality of wiring layers includes a plurality of wires, and at least some of the plurality of wires constitute an inductor. The insulating film contains an inorganic material layer comprising an inorganic insulating material, and the thickness of the inorganic material layer is thinner than the sum of the individual thicknesses of the plurality of resin layers of the multilayer wiring structure. The second surface of the insulating film constitutes the lower surface of the integrated passive component.

Description

[Technical Field]

[0001] The present invention relates to an integrated passive component and a method for manufacturing an integrated passive component. [Background technology]

[0002] An integrated passive component is known in which a smoothing layer is disposed on a substrate, and a capacitor and an inductor are disposed on the smoothing layer (Patent Document 1). The inductor is composed of multiple wires in a multilayer wiring structure in which multiple resin layers and multiple wires are alternately stacked. For the substrate, for example, silicon single crystal, alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO3 single crystal, surface-oxidized silicon, glass, quartz, ferrite, etc. are used. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2021 / 193132 Summary of the Invention [Problem to be solved by the invention]

[0004] In integrated passive components, thicker and more multi-layered wiring and resin layers that make up the inductor are required to improve their electrical characteristics. When wiring and resin layers become thicker, cracks tend to occur in the resin layer due to thermal stress caused by the difference in linear expansion coefficient between the resin layer and the substrate. Also, peeling tends to occur at the interface between the resin layer and the smoothing layer. When cracks or peeling occur, moisture resistance decreases. To prevent cracks and peeling, the thickness of the resin layer and the number of layers must be limited, which restricts the improvement of the electrical characteristics of integrated passive components.

[0005] An object of the present invention is to provide an integrated passive component that is less susceptible to cracks and peeling due to thermal stress, and a method for manufacturing the same. [Means for solving the problem]

[0006] According to one aspect of the present invention, 1. An integrated passive component having oppositely facing top and bottom surfaces, It has a first surface facing the same direction as the upper surface and a second surface facing the same direction as the lower surface. and a lower insulating film and an upper insulating film disposed on the lower insulating film. An insulating film; Between the lower insulating film and the upper insulating film a capacitor disposed thereon; a multilayer wiring structure disposed on the first surface of the insulating film; Including, the multilayer wiring structure includes a plurality of resin layers and a plurality of wiring layers that are alternately stacked, each of the plurality of wiring layers includes a plurality of wirings, and at least a portion of the plurality of wirings constitutes an inductor; the insulating film includes an inorganic material layer made of an inorganic insulating material, and the thickness of the inorganic material layer is thinner than the sum of the thicknesses of the plurality of resin layers of the multilayer wiring structure; At least the lower insulating film of the insulating films is included in the inorganic material layer, The second surface of the insulating film is provided with integrated passive components forming the lower surface.

[0007] From the matters described in the section of the preferred embodiment of the present invention, 1. An integrated passive component having oppositely facing top and bottom surfaces, an insulating film having a first surface facing the same direction as the upper surface and a second surface facing the same direction as the lower surface; a capacitor disposed within the insulating film; a multilayer wiring structure disposed on the first surface of the insulating film; a support member made of an insulating resin attached to the second surface of the insulating film; Including, the multilayer wiring structure includes a plurality of resin layers and a plurality of wiring layers that are alternately stacked, each of the plurality of wiring layers includes a plurality of wirings, and at least a portion of the plurality of wirings constitutes an inductor; The insulating film includes an inorganic material layer made of an inorganic insulating material, and the thickness of the inorganic material layer is thinner than the sum of the thicknesses of the plurality of resin layers of the multilayer wiring structure. The invention is derived.

[0008] In addition to the matters described in the section of the preferred embodiment of the present invention, forming a lower insulating film on one surface of a temporary substrate made of a semiconductor; forming a capacitor on a partial region of the lower insulating film; forming an upper insulating film on the lower insulating film so as to cover the capacitor; forming a multilayer wiring structure in which a plurality of resin layers and a plurality of wirings constituting an inductor are alternately stacked on the upper insulating film; The temporary substrate is removed to expose the lower insulating film. The invention is derived . [Effects of the Invention]

[0009] Because the thickness of the inorganic material layer is thinner than the sum of the thicknesses of the multiple resin layers in the multilayer wiring structure, the occurrence of thermal stress can be suppressed. Furthermore, because a resin is used for the support member, the difference in the linear expansion coefficient between the support member and each of the multiple resin layers in the multilayer wiring structure is small. This allows the occurrence of thermal stress to be suppressed. As a result, the occurrence of cracks and peeling due to thermal stress can be suppressed. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1A is a diagram showing the shapes and positional relationships of the components of an integrated passive component according to a first embodiment in a plan view, and FIG. 1B is an equivalent circuit diagram of the integrated passive component according to the first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along dashed line 2-2 in FIG. 1A. [Figure 3] 3A to 3C are cross-sectional views of an integrated passive component according to a first embodiment at intermediate stages in its manufacture. [Figure 4] 4A to 4C are cross-sectional views of an integrated passive component according to the first embodiment at intermediate stages in its manufacture. [Figure 5]5A and 5B are cross-sectional views of the integrated passive component according to the first embodiment at intermediate stages in its manufacture. [Figure 6] 6A and 6B are cross-sectional views of the integrated passive component according to the first embodiment at intermediate stages in its manufacture. [Figure 7] FIG. 7 is a cross-sectional view of the integrated passive component according to the first embodiment at an intermediate stage in its manufacture. [Figure 8] FIG. 8 is a cross-sectional view of an integrated passive component according to a second embodiment. [Figure 9] FIG. 9 is a cross-sectional view of an integrated passive component according to a third embodiment. [Figure 10] FIG. 10A is a diagram showing the shapes and positional relationships of the components of the integrated passive component according to the fourth embodiment in a plan view, and FIG. 10B is an equivalent circuit diagram of the integrated passive component according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] [First Example] An integrated passive component and a method for manufacturing the same according to a first embodiment will be described with reference to FIGS. 1A to 7. FIG.

[0012] 1A is a diagram showing the shapes and positional relationships of the respective components of an integrated passive component 10 according to a first embodiment in a plan view, and Fig. 1B is an equivalent circuit diagram of the integrated passive component 10 according to the first embodiment. The integrated passive component 10 according to the first embodiment has a capacitor 20, an inductor 40, an input terminal In, an output terminal Out, a ground terminal GND, and a dummy terminal DMY, which are provided on a common insulating film.

[0013] 1B, an inductor 40 is connected between an input terminal In and an output terminal Out, and a capacitor 20 is connected between the input terminal In and a ground terminal GND. The integrated passive component 10 according to the first embodiment functions as a low-pass filter.

[0014] As shown in Fig. 1A, the integrated passive component 10 according to the first embodiment includes three wiring layers, from the first to third layers. A plurality of external connection terminals, such as an input terminal In, an output terminal Out, and a ground terminal GND, are arranged on the third wiring layer. In Fig. 1A, the wires in the first wiring layer are indicated by relatively dark, upward-sloping hatching, and the wires in the second wiring layer are indicated by relatively light, downward-sloping hatching. The outlines of the external connection terminals are indicated by the thickest solid lines, and the outlines of the wires in the third wiring layer are indicated by the second thickest solid lines.

[0015] The first layer of wiring constituting inductor 40 makes approximately one turn along the periphery of the square, the second layer of wiring has a spiral shape with approximately 2 turns, and the third layer of wiring has a spiral shape with approximately 1+3 / 4 turns. By connecting the first to third layer of wiring in series, inductor 40 with approximately 4+3 / 4 turns is formed. One end of the first layer of wiring is connected to input terminal In via the second and third layer of wiring, and one end of the third layer of wiring is connected to output terminal Out.

[0016] Furthermore, one end of the wiring in the first layer is connected to one electrode of the capacitor 20. The other electrode of the capacitor 20 is connected to the ground terminal GND via the wiring in the first to third layers.

[0017] FIG. 2 is a cross-sectional view taken along dashed line 2-2 in FIG. 1A. The integrated passive component 10 according to the first embodiment has an upper surface 10U and a lower surface 10L facing in opposite directions. The integrated passive component 10 includes an insulating film 11 and a multilayer wiring structure 30. The insulating film 11 has a first surface 11U facing in the same direction as the upper surface 10U of the integrated passive component 10, and a second surface 11L facing in the same direction as the lower surface 10L. The multilayer wiring structure 30 is disposed on the first surface 11U of the insulating film 11. The lower surface 10L of the integrated passive component 10 and the second surface 11L of the insulating film 11 are the same plane, and the second surface 11L of the insulating film 11 forms the lower surface 10L of the integrated passive component 10.

[0018] A capacitor 20 is disposed in the insulating film 11. Next, the configurations of the insulating film 11 and the capacitor 20 will be described. The insulating film 11 includes a lower insulating film 11A having a second surface 11L, and an upper insulating film 11B disposed thereon and having a first surface 11U. The capacitor 20 is disposed between the lower insulating film 11A and the upper insulating film 11B. For example, the capacitor 20 is disposed in a partial region of the upper surface of the lower insulating film 11A, and the upper insulating film 11B covers the capacitor 20. The lower insulating film 11A and the upper insulating film 11B are each formed of an inorganic insulating material, such as silicon oxide or silicon nitride.

[0019] The capacitor 20 includes a lower electrode layer 20L, a capacitor dielectric film 20D, and an upper electrode layer 20U, which are stacked in this order on the lower insulating film 11A. An opening is provided in a part of the capacitor dielectric film 20D, and a contact electrode 20C disposed on the capacitor dielectric film 20D is connected to the lower electrode layer 20L through this opening. Note that the capacitor dielectric film 20D does not necessarily have to have an opening. In this case, two conductor patterns disposed on the capacitor dielectric film 20D constitute a pair of electrodes of the capacitor 20.

[0020] The multilayer wiring structure 30 includes multiple resin layers and multiple wiring layers that are alternately stacked. The integrated passive component 10 according to the first embodiment includes three resin layers 31, 32, and 33 and three wiring layers. Multiple wirings 35 are arranged in the first wiring layer, multiple wirings 36 are arranged in the second wiring layer, and multiple wirings 37 are arranged in the third wiring layer. Note that a multilayer structure of two or four or more layers may be used as needed.

[0021] The two resin layers 31 and 32 are respectively present between two adjacent layers of wiring 35, 36, and 37 in the multiple wiring layers, and the resin layers 31 and 32 are in contact with each other in the region where the wiring 36 is not arranged. The resin layer 33 is present between the wiring 37 in the uppermost wiring layer and the external connection terminal 38, and the resin layers 32 and 33 are in contact with each other in the region where the wiring 37 is not arranged. In the region where two adjacent resin layers are in contact with each other, the interface between them may not be clearly observed. The multilayer wiring structure 30 may include at least one of a resin layer placed between the wiring 35 in the lowermost wiring layer and the insulating film 11 that forms its underlying layer and a resin layer that covers the external connection terminal 38 and the surface of the resin layer 33 that forms its underlying layer.

[0022] A plurality of external connection terminals 38 are arranged on the uppermost resin layer 33. Solder 39 is placed on the external connection terminals 38. The external connection terminals 38 are connected to underlying wiring 37 through via holes provided in the resin layer 33. Some of the multiple wirings in the multilayer wiring structure 30 form an inductor 40. The wirings 35, 36, and 37 that form the inductor 40 are arranged across three wiring layers, from the first to third layers.

[0023] One of the first layer wirings 35 is connected to the upper electrode layer 20U of the capacitor 20 through an opening provided in the upper insulating film 11B, and the other of the first layer wirings 35 is connected to the contact electrode 20C through an opening provided in the upper insulating film 11B, and is connected to the lower electrode layer 20L of the capacitor 20 via the contact electrode 20C.

[0024] An input terminal In, which is one of the plurality of external connection terminals 38, is connected to the lower electrode layer 20L of the capacitor 20 via the wirings 37, 36, and 35 of the respective wiring layers and the contact electrode 20C. Although not shown in the cross-sectional view of FIG. 2, external connection terminals such as the output terminal Out, the ground terminal GND, and the dummy terminal DMY are arranged on the resin layer 33 as shown in FIG. 1A.

[0025] Next, a method for manufacturing the integrated passive component 10 according to the first embodiment will be described with reference to Figures 3A to 7. Each of Figures 3A to 7 is a cross-sectional view of the integrated passive component 10 according to the first embodiment at an intermediate stage in the manufacturing process.

[0026] As shown in FIG. 3A, a lower insulating film 11A is formed on one surface (hereinafter sometimes referred to as the upper surface) of a temporary substrate 55 made of a semiconductor. A silicon substrate, for example, is used as the temporary substrate 55. The lower insulating film 11A is formed of an inorganic insulating material. For example, the lower insulating film 11A is formed of a material containing silicon and oxygen as constituent elements (e.g., silicon oxide) or a material containing silicon and nitrogen as constituent elements (e.g., silicon nitride). The lower insulating film 11A is formed by, for example, sputtering, plasma-enhanced chemical vapor deposition (plasma CVD), metal-organic chemical vapor deposition (MOCVD), or the like. Note that the silicon oxide or silicon nitride constituting the lower insulating film 11A may contain impurities.

[0027] 3B, a photoresist film 60 is formed on the lower insulating film 11A, and an opening 60H is formed in a region where the lower electrode layer 20L (FIG. 2) of the capacitor 20 is to be formed. A conductor film 61 is formed on the lower insulating film 11A exposed at the bottom of the opening and on the photoresist film 60. The conductor film 61 is made of, for example, Cu or an alloy containing Cu as a main component, and is formed by, for example, vacuum deposition.

[0028] As shown in Fig. 3C, the photoresist film 60 and the conductive film 61 (Fig. 3B) deposited thereon are removed, thereby leaving the lower electrode layer 20L of the capacitor 20 on the lower insulating film 11A.

[0029] 4A, a dielectric film 62 is formed so as to cover the exposed surfaces of the lower electrode layer 20L and the lower insulating film 11A. The dielectric film 62 is made of a dielectric material such as silicon oxide or silicon nitride. The dielectric film 62 is formed by, for example, sputtering, plasma CVD, MOCVD, or the like.

[0030] As shown in FIG. 4B, when the upper surface of temporary substrate 55 is viewed from above (hereinafter, sometimes simply referred to as "viewed from above"), openings 20H are formed through dielectric film 62 at locations overlapping with portions of lower insulating film 11A. At this time, unnecessary portions of dielectric film 62 (FIG. 4A) (portions deposited on lower insulating film 11A) may be removed. A capacitor dielectric film 20D formed from a portion of dielectric film 62 (FIG. 4A) remains on lower electrode layer 20L.

[0031] 4C, an upper electrode layer 20U and a contact electrode 20C are formed on the capacitor dielectric film 20D. The contact electrode 20C is connected to the lower electrode layer 20L through an opening 20H provided in the capacitor dielectric film 20D. The method for forming the upper electrode layer 20U and the contact electrode 20C is the same as the method for forming the lower electrode layer 20L.

[0032] An upper insulating film 11B is formed on the lower insulating film 11A so as to cover the upper electrode layer 20U and the contact electrode 20C. The upper insulating film 11B is made of an inorganic insulating material, such as silicon oxide or silicon nitride, and is formed by the same method as the lower insulating film 11A. Note that the silicon oxide or silicon nitride constituting the upper insulating film 11B may contain impurities. An opening 11H is formed in the upper insulating film 11B to expose a portion of each of the upper electrode layer 20U and the contact electrode 20C.

[0033] As shown in FIG. 5A, a metal film 63 is formed to cover the upper insulating film 11B. The metal film 63 also covers the bottom and side surfaces of the opening 11H formed in the upper insulating film 11B. The metal film 63 is made up of two layers: a Ti layer and a Cu layer disposed thereon. The metal film 63 is formed by, for example, sputtering.

[0034] A photoresist film 64 is formed on the metal film 63, and an opening 64H is formed in the region where the first layer of wiring 35 is to be formed. Using the metal film 63 as a seed layer, Cu is deposited by electrolytic plating, thereby forming the first layer of wiring 35 in the opening 64H.

[0035] As shown in FIG. 5B, the photoresist film 64 (FIG. 5A) is removed, thereby exposing a portion of the metal film 63 (FIG. 5A). The exposed metal film 63 is removed by wet etching. The metal film 63 used as a seed layer remains between the first-layer wiring 35 and the upper insulating film 11B. This method of forming the wiring 35 is called a semi-additive method.

[0036] As shown in FIG. 6A, a first-layer resin layer 31 is formed on the first-layer wiring 35 and the upper insulating film 11B. The resin layer 31 can be formed by adhering a semi-cured resin film containing a photosensitive material using a vacuum lamination method. For example, an epoxy resin film or a polyimide resin film is used as the resin film. Although the underlying surface of the resin layer 31 has irregularities, the upper surface of the resin layer 31 is substantially flat.

[0037] Predetermined regions of the resin layer 31 are exposed to light and then developed to form multiple via holes. Each via hole 31H exposes, for example, a portion of the wiring 35 connected to the lower electrode layer 20L of the capacitor 20 via the contact electrode 20C. After the via holes are formed, the resin layer 31 in a semi-cured state is cured by performing a heat treatment.

[0038] 6B, a second layer of wiring 36 is formed on the first layer of resin layer 31. The second layer of wiring 36 can be formed by the same semi-additive method as used to form the first layer of wiring 35.

[0039] 7, a second resin layer 32, a third wiring layer 37, a third resin layer 33, and external connection terminals 38 are formed. A vacuum lamination method is used to form the resin layers 32 and 33, and a semi-additive method can be used to form the wiring 37 and external connection terminals 38. Solder 39 is placed on the upper surface of the external connection terminals 38.

[0040] Thereafter, the temporary substrate 55 is removed while the top surface of the third resin layer 33 and the external connection terminals 38 are protected with adhesive tape or the like. In FIG. 7, the removed temporary substrate 55 is indicated by a dashed line. After removing the temporary substrate 55, the integrated passive component 10 is separated into individual pieces, and the adhesive tape used for protection is peeled off, thereby completing the integrated passive component 10 shown in FIG. 2. The temporary substrate 55 can be removed by wet etching using tetramethylammonium hydroxide (TMAH) or the like. Alternatively, a portion of the temporary substrate 55 may be ground or polished, and then the remaining portion may be wet etched. For example, if the thickness of the temporary substrate 55 is 700 μm, a 500 μm portion may be ground or polished first, and the remaining 200 μm portion may be wet etched.

[0041] Next, the excellent effects of the first embodiment will be described. In a configuration in which the temporary substrate 55 (FIG. 7) is not removed, thermal stress occurs due to the difference in the linear expansion coefficient between the resin layers 31, 32, and 33 and the temporary substrate 55. For example, the linear expansion coefficient of resins such as polyimide and epoxy is approximately 20 ppm / °C or more and 65 ppm / °C or less. In contrast, the linear expansion coefficient of single-crystal silicon used in the temporary substrate 55 is approximately 3 ppm / °C. Thermal stress makes it easy for cracks to occur in the resin layers 31, 32, and 33, and also makes it easy for peeling to occur at the interface between the insulating film 11 and the resin layer 31. The occurrence of cracks or peeling reduces moisture resistance and the quality of the integrated passive component 10.

[0042] In particular, if the wiring 35, 36, 37 and resin layers 31, 32, 33 are thickened and the number of layers in the multilayer wiring structure 30 is increased in order to improve the electrical characteristics of the integrated passive component 10, cracks and peeling tend to occur. In the first embodiment, the temporary substrate 55 is removed, so thermal stress is less likely to occur. As a result, cracks and peeling are less likely to occur, and deterioration in the quality of the integrated passive component 10 can be suppressed.

[0043] In particular, the effect of removing the temporary substrate 55 is significant when the resin layers 31, 32, and 33 and the wires 35, 36, and 37 of the multilayer wiring structure 30 are thick. For example, significant effects are achieved when the resin layers 31, 32, and 33 are each 10 μm or thicker and the wires 35, 36, and 37 are each 5 μm or thicker. Furthermore, to improve the electrical characteristics of the integrated passive component 10, it is more preferable to set the thickness of each of the resin layers 31, 32, and 33 to 20 μm or thicker and the thickness of the wires 35, 36, and 37 to 10 μm or thicker. However, increasing the thickness of the resin layers 31, 32, and 33 and the wires 35, 36, and 37 beyond what is necessary results in little improvement in electrical characteristics and, instead, increases manufacturing difficulties. Therefore, it is preferable to set the thickness of each of the resin layers 31, 32, and 33 to 30 μm or less, and the thickness of each of the wires 35, 36, and 37 to 15 μm or less.

[0044] If the lower insulating film 11A and the upper insulating film 11B made of an inorganic insulating material are made thick, thermal stress becomes apparent due to the difference in the linear expansion coefficient of the insulating film 11 and the linear expansion coefficient of the resin layers 31, 32, and 33. To prevent the influence of thermal stress caused by the difference in the linear expansion coefficient of the insulating film 11 and the linear expansion coefficient of the resin layers 31, 32, and 33 from becoming apparent, it is preferable to make the thickness of the inorganic material layer included in the insulating film 11, i.e., the total thickness of the lower insulating film 11A and the upper insulating film 11B, thinner than the sum of the thicknesses of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30, and more preferably to make it equal to or less than half the sum of the thicknesses of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30.

[0045] Using silicon nitride for the lower insulating film 11A can improve the moisture resistance of the integrated passive component 10. Using silicon oxide for the upper insulating film 11B can apply a general semiconductor microfabrication process to the step of forming the opening 11H (FIG. 4C) in the upper insulating film 11B.

[0046] If the capacitor 20 is made too thick, the processing accuracy of the lower electrode layer 20L, the capacitor dielectric film 20D, and the upper electrode layer 20U will decrease, resulting in a decrease in capacitance accuracy. To prevent a decrease in the capacitance accuracy of the capacitor 20, the total thickness of the lower electrode layer 20L, the capacitor dielectric film 20D, and the upper electrode layer 20U is preferably set to 2 μm or less. To prevent a decrease in the capacitance accuracy of the capacitor 20 and a decrease in the characteristics of the inductor 40, the minimum thickness of each of the multiple wirings 35, 36, and 37 constituting the inductor 40 is preferably set to be greater than the thickness of the thicker of the lower electrode layer 20L and the upper electrode layer 20U of the capacitor 20, more preferably at least five times that thickness. By thickening the multiple wirings 35, 36, and 37 constituting the inductor 40, the electrical resistance of the wiring can be reduced.

[0047] Furthermore, as the number of layers in the multilayer wiring structure 30 increases, the adoption of a configuration in which the temporary substrate 55 is removed provides significant benefits. This is particularly true when the number of layers in the multilayer wiring structure 30 is three or more. In a configuration in which the number of layers in the multilayer wiring structure 30 is three or more, the electrical characteristics of the inductor can be improved by arranging the multiple wirings 35, 36, and 37 that make up the inductor 40 across three or more wiring layers. Furthermore, the design inductance value per unit area can be increased compared to a configuration in which the multiple wirings 35, 36, and 37 that make up the inductor 40 are arranged across two or fewer wiring layers.

[0048] If the distance in the stacking direction between two adjacent wires 35, 36 and two adjacent wires 36, 37 in the stacking direction of the multilayer wiring structure 30 becomes short, the influence of parasitic capacitance between the wires will degrade the characteristics of the inductor 40. In order to suppress the degradation of the characteristics of the inductor 40, it is preferable to set the minimum value of the distance in the stacking direction between adjacent wires in the stacking direction of the multilayer wiring structure 30 (i.e., the distance in the stacking direction between the wires 35 and 36, and the distance in the stacking direction between the wires 36 and 37) to be equal to or greater than the maximum value of each thickness of the multiple wires 35, 36, 37 that make up the inductor 40.

[0049] Note that the distance between adjacent wires in the stacking direction of the multilayer wiring structure 30 may be equal to or greater than the maximum thickness of each of the wires 35, 36, and 37 that make up the inductor 40. In this case, it is also possible to suppress to some extent the degradation of the characteristics of the inductor 40 due to the influence of the parasitic capacitance between the wires.

[0050] [Second Example] Next, an integrated passive component according to a second embodiment will be described with reference to Fig. 8. Below, a description of the configuration common to the integrated passive component according to the first embodiment described with reference to Figs. 1A to 7 will be omitted.

[0051] FIG. 8 is a cross-sectional view of an integrated passive component 10 according to a second embodiment. In the first embodiment (FIG. 2), the upper insulating film 11B is made of an inorganic insulating material. In contrast, in the second embodiment, the upper insulating film 11B is made of an organic insulating material, such as an insulating resin material containing epoxy or polyimide as a main component. The resin that makes up the upper insulating film 11B may contain impurities. The upper insulating film 11B made of an organic insulating material can be formed by, for example, a coating method. In this case, the upper surface of the upper insulating film 11B is substantially flat.

[0052] Next, we will explain the excellent effects of Example 2. As with Example 1, Example 2 can also suppress the occurrence of cracks and peeling due to thermal stress, and can also suppress the deterioration of electrical characteristics.

[0053] Furthermore, in the second embodiment, since the upper insulating film 11B is formed of an organic insulating material, it is easier to make the upper insulating film 11B thicker than in the first embodiment. When the upper insulating film 11B is thicker, the distance between the capacitor 20 and the inductor 40 in the stacking direction increases. As a result, excellent electrical isolation between the passive elements is achieved, and the eddy current loss of the inductor 40 can be reduced.

[0054] In the first embodiment (FIG. 2), the thickness of the inorganic material layer of the insulating film 11 is equal to the total thickness of the lower insulating film 11A and the upper insulating film 11B. In the first embodiment, it is preferable that the thickness of this inorganic material layer, i.e., the total thickness of the lower insulating film 11A and the upper insulating film 11B, is thinner than the sum of the thicknesses of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30.

[0055] In contrast, in the second embodiment, the thickness of the inorganic material layer of the insulating film 11 is equal to the thickness of the lower insulating film 11A. Because the upper insulating film 11B is made of an organic insulating material, the linear expansion coefficient of the upper insulating film 11B is close to the linear expansion coefficients of the resin layers 31, 32, and 33. In order to reduce the effects of thermal stress, it is preferable to make the thickness of the lower insulating film 11A, which is an inorganic material layer, thinner than the sum of the thicknesses of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30.

[0056] [Third Example] Next, an integrated passive component according to a third embodiment will be described with reference to Fig. 9. Below, a description of the configuration common to the integrated passive component according to the first embodiment described with reference to Figs. 1A to 7 will be omitted.

[0057] 9 is a cross-sectional view of an integrated passive component 10 according to a third embodiment. In the first embodiment (FIG. 2), the second surface 11L of the insulating film 11 forms the lower surface 10L of the integrated passive component 10. In contrast, in the third embodiment, a support member 50 made of an insulating material is adhered to the second surface 11L of the insulating film 11, and the lower surface 10L of the integrated passive component 10 is formed by the surface of the support member 50 facing in the direction opposite to the surface adhered to the insulating film 11.

[0058] An insulating resin film is used as the support member 50. The support member 50 is adhered to the second surface 11L of the insulating film 11, for example, by the adhesiveness of the resin. Alternatively, the support member 50 may be adhered to the second surface 11L of the insulating film 11 using an adhesive. The difference between the linear expansion coefficient of the support member 50 and the linear expansion coefficient of each of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30 is smaller than the difference between the linear expansion coefficient of the temporary substrate 55 (FIG. 7) and the linear expansion coefficient of each of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30. Generally, a single-crystal silicon substrate is used as the temporary substrate 55. In this case, the difference between the linear expansion coefficient of the support member 50 and the linear expansion coefficient of each of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30 is smaller than the difference between the linear expansion coefficient of single-crystal silicon and the linear expansion coefficient of each of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30.

[0059] Next, the advantageous effects of the third embodiment will be described. In the third embodiment, a support member 50 is bonded to the second surface 11L of the insulating film 11, and the difference between the linear expansion coefficient of the support member 50 and the linear expansion coefficient of each of the resin layers 31, 32, and 33 of the multilayer wiring structure 30 is smaller than the difference between the linear expansion coefficient of the temporary substrate 55 (FIG. 7) and the linear expansion coefficient of each of the resin layers 31, 32, and 33 of the multilayer wiring structure 30. Therefore, compared to a configuration in which the temporary substrate 55 remains, the occurrence of cracks and peeling due to thermal stress can be suppressed.

[0060] Furthermore, since the support member 50 is bonded to the insulating film 11, the mechanical strength of the integrated passive component 10 can be increased compared to the first embodiment. To obtain sufficient mechanical strength, it is preferable that the thickness of the support member 50 be greater than the thickness of the lower insulating film 11A.

[0061] In order to ensure sufficient heat dissipation through the support member 50, it is preferable to use a material for the support member 50 that has a thermal conductivity lower than that of the lower insulating film 11A. For example, it is preferable to use a material called a high thermal conductivity resin for the support member 50.

[0062] Next, a modification of the third embodiment will be described. In the third embodiment, an insulating resin is used for the support member 50, but an inorganic insulating material may also be used. For example, ceramics, glass, etc. may also be used. In this case, too, it is preferable to make the difference between the linear expansion coefficient of the support member 50 and the linear expansion coefficient of each of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30 smaller than the difference between the linear expansion coefficient of the temporary substrate 55 (FIG. 7) and the linear expansion coefficient of each of the multiple resin layers 31, 32, and 33 of the multilayer wiring structure 30.

[0063] [Fourth Example] Next, an integrated passive component according to a fourth embodiment will be described with reference to Figures 10A and 10B. Below, a description of the configuration common to the integrated passive component according to the first embodiment described with reference to Figures 1A to 7 will be omitted.

[0064] Fig. 10A is a diagram showing the shapes and positional relationships of the components of an integrated passive component 10 according to the fourth embodiment in a plan view, and Fig. 10B is an equivalent circuit diagram of the integrated passive component 10 according to the fourth embodiment. Similar to the integrated passive component 10 according to the first embodiment (Fig. 1A), the integrated passive component 10 according to the fourth embodiment also has a capacitor, an inductor, an input terminal In, an output terminal Out, a ground terminal GND, and a dummy terminal DMY provided on a common insulating film. However, the integrated passive component 10 according to the fourth embodiment also includes multiple capacitors C1, C2, C3, C4, C5, and C6 and multiple inductors L1, L2, L3, L4, and L5, forming a bandpass filter.

[0065] 10B, a capacitor C1, an inductor L1, and a capacitor C2 are connected in series between the input terminal In and the output terminal Out, in that order from the input terminal In side. A series circuit of a capacitor C3 and an inductor L2 and a series circuit of a capacitor C4 and an inductor L3 are connected in parallel between the input terminal In and the ground terminal GND. A series circuit of a capacitor C5 and an inductor L4 and a series circuit of a capacitor C6 and an inductor L5 are connected in parallel between the output terminal Out and the ground terminal GND.

[0066] Each of the plurality of capacitors C1, C2, C3, C4, C5, and C6 is composed of a lower electrode layer, a capacitor dielectric film, and an upper electrode layer, similar to capacitor 20 (FIG. 2) of integrated passive component 10 according to the first embodiment. The upper electrode layer may be composed of two conductor patterns separated from each other, and these two conductor patterns may be used as a pair of electrode terminals of the capacitor. Each of the plurality of inductors L1, L2, L3, L4, and L5 is composed of multiple wires in multilayer wiring structure 30, similar to inductor 40 (FIG. 2) of integrated passive component 10 according to the first embodiment.

[0067] 10A, the wires in the first wiring layer are hatched with relatively darker diagonal lines, and the wires in the second wiring layer are hatched with relatively lighter diagonal lines, and the outlines of the external connection terminals are indicated by the thickest solid lines, and the outlines of the wires in the third wiring layer are indicated by the second thickest solid lines.

[0068] Five inductors L1, L2, L3, L4, and L5 and six capacitors C1, C2, C3, C4, C5, and C6 are arranged so as not to overlap one another in a plan view. The wiring that constitutes each of the inductors L1, L2, and L4 is arranged across three wiring layers. The wiring that constitutes each of the inductors L3 and L5 is arranged across two wiring layers.

[0069] Next, the excellent effects of the fourth embodiment will be described. As with the first embodiment, the fourth embodiment can also suppress the occurrence of cracks and peeling due to thermal stress, and can also suppress the deterioration of electrical characteristics. Furthermore, as in the fourth embodiment, by arranging multiple capacitors and multiple inductors on a common insulating film 11, various passive circuits can be realized.

[0070] The above-described embodiments are merely examples, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. Similar effects resulting from similar configurations of multiple embodiments will not be mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above-described embodiments. For example, it will be obvious to those skilled in the art that various modifications, improvements, combinations, etc. are possible. [Explanation of symbols]

[0071] 10 Integrated Passive Components 10L Bottom side of integrated passive components 10U Integrated Passives Top Side 11. Insulating film 11A Lower insulating film 11B Upper insulating film 11H opening 11L Second surface of insulating film 11U First surface of insulating film 20 Capacitor 20C Contact electrode 20D capacitor dielectric film 20H opening 20L Capacitor lower electrode layer Upper electrode layer of 20U capacitor 30 Multilayer wiring structure 31, 32, 33 Resin layer 31H Beer Hall 35, 36, 37 Wiring 38 External connection terminal 39 Solder 40 Inductor 50 Support member 55 Temporary board 60 Photoresist film 60H opening 61 Conductor layer 62 Dielectric film 63 Metallic Film 64 Photoresist film 64H opening

Claims

1. 1. An integrated passive component having oppositely facing top and bottom surfaces, an insulating film having a first surface facing the same direction as the upper surface and a second surface facing the same direction as the lower surface, the insulating film including a lower insulating film and an upper insulating film disposed on the lower insulating film; a capacitor disposed between the lower insulating film and the upper insulating film; a multilayer wiring structure disposed on the first surface of the insulating film; Including, the multilayer wiring structure includes a plurality of resin layers and a plurality of wiring layers that are alternately stacked, each of the plurality of wiring layers includes a plurality of wirings, and at least a portion of the plurality of wirings constitutes an inductor; the insulating film includes an inorganic material layer made of an inorganic insulating material, and the thickness of the inorganic material layer is thinner than the sum of the thicknesses of the plurality of resin layers of the multilayer wiring structure; At least the lower insulating film of the insulating films is included in the inorganic material layer, The second surface of the insulating film constitutes the lower surface of the integrated passive component.

2. 2. The integrated passive component according to claim 1, wherein the plurality of wirings constituting the inductor are arranged across three or more wiring layers among the plurality of wiring layers.

3. 3. An integrated passive component according to claim 2, wherein the distance in the stacking direction between adjacent wires in the multilayer wiring structure is equal to or greater than the maximum value of the thickness of each of the plurality of wires constituting the inductor.

4. the capacitor includes a lower electrode layer, an upper electrode layer disposed closer to the upper surface than the lower electrode layer, and a capacitor dielectric film disposed between the lower electrode layer and the upper electrode layer, 4. An integrated passive component according to claim 1, wherein the minimum thickness of each of the plurality of wirings constituting the inductor is greater than the thickness of the thicker of the lower electrode layer and the upper electrode layer of the capacitor.

5. 4. The integrated passive component according to claim 1, wherein the plurality of wirings are made of Cu or an alloy containing Cu as a main component.

6. the lower insulating film has the second surface, the upper insulating film has the first surface, 4. An integrated passive component according to claim 1, wherein said upper insulating film is made of silicon oxide.

7. The lower insulating film has the second surface, and the upper insulating film has the first surface, 4. An integrated passive component according to claim 1, wherein said upper insulating film is made of a resin.

8. 7. An integrated passive component according to claim 6, wherein said lower insulating film is made of silicon nitride.

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