Filter circuit configuration calculation device, calculation method, and information processing program

Abstract

To provide a technique capable of determining a filter circuit configuration by calculation.SOLUTION: A calculation device determines element positions of circuit elements, terminal positions of input and output terminals, and wiring topology of wiring. The calculation device generates a two-dimensional lattice. The calculation device determines an element lattice, a terminal lattice, and a wiring lattice array that is a continuous lattice. The calculation device calculates evaluation values representing the performance of a filter circuit formed by the element lattice, the terminal lattice, and the wiring lattice array. The calculation device generates an acquisition function that uses, as arguments, the element lattice, the terminal lattice, and the wiring lattice array. The calculation device calculates an optimal solution of the acquisition function. The calculation device repeatedly executes determination of the element lattice, the terminal lattice, and the wiring lattice array, calculation of the evaluation values, generation of the acquisition function, and calculation of the optimal solution. The calculation device determines, based on the optimal solution, the next element lattice, terminal lattice, and wiring lattice array.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a calculation device and a calculation method that can determine a filter circuit configuration. [Background technology]

[0002] As devices become increasingly miniaturized, noise signals can adversely affect other devices within the device, potentially causing malfunctions. Therefore, there is a demand for creating optimal filter circuits that reduce target noise. Related technologies are disclosed in Patent Documents 1 and 2. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-166620 [Patent Document 2] Japanese Patent Application Laid-Open No. 2000-13167 Summary of the Invention [Problem to be solved by the invention]

[0004] In noise filter design, filter performance changes depending on the placement of elements and the wiring topology (wiring pattern shape) between elements. However, there are an infinite number of combinations of element placement and wiring patterns, making optimization difficult. [Means for solving the problem]

[0005] One embodiment of a computing device disclosed herein is a computing device that determines the configuration of a filter circuit including circuit elements, input terminals, output terminals, and wiring. The computing device determines element positions of circuit elements, terminal positions of input terminals and output terminals, a wiring topology of wiring connecting the element positions and the terminal positions, and a wiring topology of wiring connecting the element positions. The computing device includes a two-dimensional lattice generation unit that generates a two-dimensional lattice. Each of a plurality of lattices included in the two-dimensional lattice is configured to be able to represent the element positions, terminal positions, and wiring topology. The computing device includes a determination unit that determines an element lattice that is a lattice corresponding to the element positions, a terminal lattice that is a lattice corresponding to the terminal positions, and a wiring lattice array that is a series of lattices corresponding to the wiring topology. The computing device includes an evaluation value calculation unit that calculates the performance of a filter circuit formed by the element lattice, the terminal lattice, and the wiring lattice array as an evaluation value. The computing device includes an acquisition function generation unit that generates an acquisition function that takes the element lattice, the terminal lattice, and the wiring lattice array as arguments, and that represents the possibility of obtaining a better evaluation value. The computing device includes a calculation unit that calculates an optimal solution of the acquisition function generated by the acquisition function generation unit. The calculation device repeatedly executes the following steps: determination of element lattices, terminal lattices, and wiring lattice arrays by a determination unit; calculation of evaluation values ​​by an evaluation value calculation unit; generation of acquisition functions by an acquisition function generation unit; and calculation of an optimal solution by a calculation unit. The determination unit determines the next element lattice, terminal lattice, and wiring lattice array based on the optimal solution calculated by the calculation unit.

[0006] With the above configuration, an optimization problem can be defined using an acquisition function, with element positions, terminal positions, and wiring topology as variables and the performance of the filter circuit as the evaluation value. Then, by finding the optimal solution on the acquisition function, it is possible to predict the performance of the filter circuit for a combination of element positions, terminal positions, and wiring topology using all past evaluation value results. Furthermore, by repeatedly calculating the evaluation value, the acquisition function can be learned, thereby improving the accuracy of predicting the performance of the filter circuit. As a result, it is possible to design a filter circuit with high noise performance with fewer calculations than when predictions using the acquisition function are not performed. This enables optimization of the filter circuit.

[0007] The determination unit may generate a plurality of element lattice candidates, a plurality of terminal lattice candidates, and a plurality of wiring lattice array candidates. The determination unit may determine an element lattice selected from the plurality of element lattice candidates as an element lattice corresponding to the element position. The determination unit may determine a terminal lattice selected from the plurality of terminal lattice candidates as a terminal lattice corresponding to the terminal position. The determining unit may determine a wiring grid array selected from a plurality of candidates for the wiring grid array as the wiring grid array corresponding to the wiring topology. Details of the effects will be described in the embodiments.

[0008] The two-dimensional grid may have a first axis and a second axis that are orthogonal to each other. When generating multiple candidates for a wiring grid array connecting the first grid and the second grid, the determination unit may generate a first candidate and a second candidate. The first candidate may correspond to a wiring topology in which only the coordinate of the second axis is changed to minimize the distance between the first grid and the second grid, and then only the coordinate of the first axis is changed to connect with the second grid. The second candidate may correspond to a wiring topology in which only the coordinate of the first axis is changed to minimize the distance between the first grid and the second grid, and then only the coordinate of the second axis is changed to connect with the second grid. Details of the effects will be described in the examples.

[0009] The two-dimensional grid may have a first axis and a second axis that are orthogonal to each other. When generating multiple candidates for a wiring grid row connecting the first grid and the second grid, the determination unit may generate a special candidate. The special candidate may be a wiring grid row connecting all of the multiple candidates in the first grid and all of the multiple candidates in the second grid. Details of the effects will be described in the examples.

[0010] The acquisition function may be a QUBO-style function that can be solved by an Ising solver. Details of the effects will be explained in the examples.

[0011] A penalty term that one element position is provided for one circuit element may be provided. Details of the effect will be described in the examples.

[0012] The element grid, terminal grid, and wiring grid array may be binary variables expressed by one-hot expressions. The effects will be described in detail in the examples.

[0013] The calculation device may further include a network interface capable of communicating with the first server. The calculation unit may transmit acquisition information to the first server via the network interface to cause the first server to acquire the acquisition function generated by the acquisition function generation unit. The calculation unit may receive an optimal solution of the acquisition function calculated by the first server from the first server via the network interface. Details of the effects will be described in the examples.

[0014] The network interface may be configured to further communicate with the second server. The two-dimensional lattice generation unit may transmit two-dimensional lattice information to the second server via the network interface, causing the second server to generate a two-dimensional lattice. The determination unit may transmit determination information to the second server via the network interface, causing the second server to determine an element lattice, a terminal lattice, and a wiring lattice array. The evaluation value calculation unit may transmit evaluation value calculation information to the second server via the network interface, causing the second server to calculate an evaluation value. The acquisition function generation unit may transmit acquisition function information to the second server via the network interface, causing the second server to generate an acquisition function. The calculation unit may transmit acquisition information to the first server via the network interface, causing the first server to acquire the acquisition function generated by the second server. Details of the effects will be described in the examples.

[0015] The filter circuit may be a π-type filter circuit. The circuit elements may include an inductor and a capacitor. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic configuration diagram of a communication system 1. FIG. [Figure 2]FIG. 2 is a diagram showing an example of a two-dimensional lattice 30. [Figure 3] FIG. 2 is a circuit configuration diagram of a noise filter circuit 40. [Figure 4] FIG. 10 is a diagram illustrating a method for creating four candidates for the first wiring. [Figure 5] FIG. 10 is a diagram illustrating a method for creating four candidates for the first wiring. [Figure 6] FIG. 10 is a diagram showing an example of a completed model of the noise filter circuit 40 using a two-dimensional lattice 30. [Figure 7] 10 is a table showing one-hot representations of each candidate. [Figure 8] FIG. 7 is a diagram showing an example of a bit string when the completed model of FIG. 6 is expressed in one-hot form. [Figure 9] 2 is a flow diagram showing the processing contents of the arithmetic device 10, the first server 100, and the second server 200. FIG. [Figure 10] FIG. 1 is a schematic diagram of an acquisition function. [Figure 11] 1 is a table showing one-hot representations of candidate standards. DETAILED DESCRIPTION OF THE INVENTION [Example]

[0017] (Configuration of communication system 1) 1, the communication system 1 includes a computing device 10, a first server 100, and a second server 200. The computing device 10 is connected to the Internet 6 via a LAN 4. The first server 100 and the second server 200 are connected to the Internet 6. The computing device 10, the first server 100, and the second server 200 may be located in different countries, or may all be located in the same country.

[0018] The arithmetic device 10 is a device used to determine the configuration of a noise filter circuit. The arithmetic device 10 may be, for example, a PC. The arithmetic device 10 includes an operation unit 12, a display unit 14, a network interface 16, and a control unit 20. The operation unit 12 may include a keyboard, a mouse, etc. The display unit 14 is a display for displaying various information. The network interface 16 is connected to a LAN 4. The arithmetic device 10 is capable of communicating with a first server 100, a second server 200, etc. via the network interface 16. The control unit 20 includes a CPU 22 and a memory 24.

[0019] The memory 24 includes a program 25 and a device information storage area 26. The CPU 22 executes various processes in accordance with the program 25 stored in the memory 24. That is, when the CPU 22 executes the program 25, the control unit 20 functions as a two-dimensional grid generation unit 31, a determination unit 32, an evaluation value calculation unit 33, an acquisition function generation unit 34, an arithmetic unit 35, and the like. The specific functions of these units will be described later. The memory 24 may be a computer-readable storage medium. The computer-readable storage medium is a non-transitory medium such as a ROM, RAM, flash memory, or hard disk.

[0020] The first server 100 is an Ising machine that uses an Ising model to solve combinatorial optimization problems. The first server 100 is a server that can provide cloud services. In other words, the first server 100 can calculate an optimal solution to a combinatorial optimization problem uploaded to the first server 100 by a user.

[0021] The first server 100 includes a network interface 110 and a control unit 120. The first server 100 is capable of communicating with the arithmetic device 10, the second server 200, and the like via the network interface 110. The control unit 120 includes a CPU 121 and a memory 122. A program 123 is stored in the memory 122. The CPU 121 executes various processes in accordance with the program 123.

[0022] The second server 200 is a server configured separately from the first server 100. The second server 200 is a server that determines the configuration of a noise filter circuit. The second server 200 includes a network interface 210 and a control unit 220. The second server 200 is capable of communicating with the arithmetic device 10, the first server 100, and the like via the network interface 210. The control unit 220 includes a CPU 221 and a memory 222. A program 223 is stored in the memory 222. The CPU 221 executes various processes in accordance with the program 223.

[0023] A user can calculate the optimal structure of a desired noise filter circuit by operating the calculation device 10 to access the first server 100 and the second server 200. That is, the calculation of the noise filter circuit described below can be performed using a cloud service.

[0024] (Explanation of the 2D lattice model) A two-dimensional lattice 30 used in the technology of this specification will be described with reference to FIG. 2. The two-dimensional lattice 30 is a model used to represent the element positions, terminal positions, and wiring topology of a noise filter circuit. Each of the multiple lattices included in the two-dimensional lattice 30 is configured to be able to represent the element positions, terminal positions, and wiring topology. FIG. 2 shows an example of the two-dimensional lattice 30. The two-dimensional lattice 30 has an x-axis and a y-axis that are orthogonal to each other. The example of the two-dimensional lattice 30 in FIG. 2 has 15 lattices in the x-axis direction and 10 lattices in the y-axis direction, for a total of 150 lattices. The back surface is grounded.

[0025] In this embodiment, a case will be described in which a π-type noise filter circuit 40 shown in Fig. 3 is modeled using a two-dimensional lattice 30. The noise filter circuit 40 in Fig. 3 includes an input terminal IT, an input-side capacitor IC, an inductor L, an output-side capacitor OC, and an output terminal OT. The inductor L is disposed on the connection path between the input terminal IT and the output terminal OT. The input terminal IT is also connected to ground via the input-side capacitor IC. The output terminal OT is also connected to ground via the output-side capacitor OC.

[0026] As shown in FIG. 2, the input terminal IT, input capacitor IC, inductor L, output capacitor OC, and output terminal OT each have two candidate locations. In FIG. 2, each candidate location for a terminal and a circuit element is indicated by a single hatched grid. That is, for the location of the input terminal IT, there is a first candidate IT1 and a second candidate IT2. For the location of the input capacitor IC, there is a first candidate IC1 and a second candidate IC2. For the location of the inductor L, there is a first candidate L1 and a second candidate L2. For the location of the output capacitor OC, there is a first candidate OC1 and a second candidate OC2. For the location of the output terminal OT, there is a first candidate OT1 and a second candidate OT2. These candidates may be automatically generated by the program 223 of the second server 200, as described below, or may be determined by the user.

[0027] The noise filter circuit 40 also includes first to fourth wirings. The wiring topology (the shape of the wiring) of each of the first to fourth wirings can be expressed as a continuous grid array. The first wiring is a wiring that connects either the first candidate IT1 or the second candidate IT2 with either the first candidate IC1 or the second candidate IC2. The second wiring is a wiring that connects either the first candidate IC1 or the second candidate IC2 with either the first candidate L1 or the second candidate L2. The third wiring is a wiring that connects either the first candidate L1 or the second candidate L2 with either the first candidate OC1 or the second candidate OC2. The fourth wiring is a wiring that connects either the first candidate OC1 or the second candidate OC2 with either the first candidate OT1 or the second candidate OT2.

[0028] There are four patterns for the first wiring: a pattern from the first candidate IT1 to the first candidate IC1, a pattern from the first candidate IT1 to the second candidate IC2, a pattern from the second candidate IT2 to the first candidate IC1, and a pattern from the second candidate IT2 to the second candidate IC2. Similarly, there are four patterns for each of the second, third, and fourth wirings.

[0029] For the first wiring, there are four candidates (first candidate W11, second candidate W12, third candidate W13, and special candidate W1e) for each of the four patterns. For the second wiring, there are four candidates (first candidate W21, second candidate W22, third candidate W23, and special candidate W2e) for each of the four patterns. For the third wiring, there are four candidates (first candidate W31, second candidate W32, third candidate W33, and special candidate W3e) for each of the four patterns. For the fourth wiring, there are four candidates (first candidate W41, second candidate W42, third candidate W43, and special candidate W4e) for each of the four patterns. These wiring candidates may be generated by the program 223 of the second server 200.

[0030] A method for creating four candidates for the first wiring in a pattern in which the first wiring runs from the first candidate IT1 to the first candidate IC1 will be described below (FIGS. 4 and 5). Note that in FIG. 4 and FIG. 5, the grid forming the wiring is shown filled in gray.

[0031] The method for creating the wiring topology of the first candidate W11 will be explained (Figure 4). Starting from the first candidate IT1, only the y-axis coordinate is changed in the -y direction so that the distance to the first candidate IC1 is minimized. This generates a wiring topology from the first candidate IT1 to the relay point P1. After that, starting from the relay point P1, only the x-axis coordinate is changed in the +x direction so that it connects to the first candidate IC1. This generates a wiring topology from the relay point P1 to the first candidate IC1. With the above steps, the first candidate W11 for the first wiring is completed.

[0032] The method for creating the wiring topology of the second candidate W12 will be explained (Figure 4). Starting from the first candidate IT1, only the x-axis coordinate is changed in the +x direction so that the distance to the first candidate IC1 is minimized. This generates a wiring topology from the first candidate IT1 to the relay point P2. After that, starting from the relay point P2, only the y-axis coordinate is changed in the -y direction so that it connects to the first candidate IC1. This generates a wiring topology from the relay point P2 to the first candidate IC1. With the above steps, the second candidate W12 for the first wiring is completed.

[0033] The method for creating the wiring topology of the third candidate W13 will be explained (Figure 4). Starting from the first candidate IT1, only the y-axis coordinate is shifted in the -y direction until the y-direction distance between the first candidate IT1 and the first candidate IC1 is halved. This generates a wiring topology from the first candidate IT1 to the relay point P3a. Then, starting from the relay point P3a, only the x-axis coordinate is shifted in the +x direction until the x-direction distance between the first candidate IT1 and the first candidate IC1 is zero. This generates a wiring topology from the relay point P3a to the relay point P3b. Then, starting from the relay point P3b, only the y-axis coordinate is shifted in the -y direction so as to connect to the first candidate IC1. This generates a wiring topology from the relay point P3b to the first candidate IC1. This completes the third candidate W13 for the first wiring.

[0034] The effects of the above-described wiring topology generation method will now be described. Because the magnitude of the induced current and parasitic capacitance generated during operation are determined by the wiring topology, changes in the wiring topology significantly affect filter performance. Therefore, when generating wiring topology candidates, it is preferable to carefully select candidates with significantly different topologies. A conventional method for enumerating wiring topology candidates is graph theory (k-shortest path), which enumerates paths between nodes beginning with the shortest path. However, this theory generates a large number of paths with similar topologies, making it difficult to carefully select and generate candidates with significantly different topologies. On the other hand, with the wiring topology generation method of this embodiment, the first candidate W11 can be a wiring topology with a large route that protrudes most in the -x and -y directions. The second candidate W12 can be a wiring topology with a large route that protrudes most in the +x and +y directions. The third candidate W13 can be a wiring topology intermediate between the first candidate W11 and the second candidate W12. In other words, the difference in wiring topology between the first candidate W11, the second candidate W12, and the third candidate W13 can be maximized. This makes it possible to carefully select and create three candidates with significantly different topologies.

[0035] Using Figure 5, we will explain how to create the wiring topology of the special candidate W1e. All of the grids between the wirings are selected as wirings so as to connect all of the candidates for the input terminal IT (i.e., the first candidate IT1 and the second candidate) and all of the candidates for the input capacitor IC (i.e., the first candidate IC1 and the second candidate IC2). This completes the special candidate W1e with a solid wiring shape.

[0036] It should be noted that four candidates can be generated for each of the four patterns of the second wiring. Also, four candidates can be generated for each of the four patterns of the third wiring. Also, four candidates can be generated for each of the four patterns of the fourth wiring. The method for generating the four candidates for the second to fourth wirings is the same as the method for generating the four candidates for the first wiring, so a description thereof will be omitted.

[0037] Fig. 6 shows an example of a completed model of a noise filter circuit 40 using a two-dimensional lattice 30. Fig. 6 shows a case where the second candidate IT2, the second candidate IC2, the second candidate L2, the first candidate OC1, and the first candidate OT1 are selected as the terminal and element locations. Fig. 6 also shows a case where the second candidate W12, the first candidate W21, the first candidate W31, and the third candidate W43 are selected as the wiring topology.

[0038] (Digitization of candidates into binary variables using one-hot representation) The candidates for the input terminal IT, input-side capacitor IC, inductor L, output-side capacitor OC, output terminal OT, and first to fourth wirings described in FIG. 2 can be expressed as binary variables. In this embodiment, a case where each candidate is expressed as a binary variable using one-hot expression will be described. FIG. 7(A) shows one-hot expressions of position candidates for the input terminal IT. The first candidate IT1 is expressed as "10," and the second candidate IT2 is expressed as "01." Similarly, FIG. 7(B) shows one-hot expressions of position candidates for the input-side capacitor IC. FIG. 7(C) shows one-hot expressions of position candidates for the inductor L. FIG. 7(D) shows one-hot expressions of position candidates for the output-side capacitor OC. FIG. 7(E) shows one-hot expressions of position candidates for the output terminal OT. The contents of FIGS. 7(B) to 7(E) are similar to those of FIG. 7(A), and therefore will not be described again.

[0039] FIG. 7(F) shows the one-hot representation of the first wiring. The first candidate W11 for the first wiring is represented by "100", the second candidate W12 is represented by "010", and the third candidate W13 is represented by "001". The special candidate W1e is represented by "000". Similarly, FIG. 7(G) shows the one-hot representation of the second wiring. FIG. 7(H) shows the one-hot representation of the third wiring. FIG. 7(I) shows the one-hot representation of the fourth wiring. The contents of FIG. 7(G) to FIG. 7(I) are the same as those of FIG. 7(F), so explanations will be omitted.

[0040] FIG. 8 shows an example of a bit string when the completed model of FIG. 6 is one-hot expressed. The bit example of FIG. 8 includes a position bit string and a wiring bit string. The position bit string is an example of bits indicating candidates for the input terminal IT, the input capacitor IC, the inductor L, the output capacitor OC, and the output terminal OT. That is, the position bit string includes a total of 10 bits, which are an arrangement of the bits from FIG. 7(A) to FIG. 7(E). The wiring bit string is an example of bits indicating candidates for the first to fourth wirings. That is, the wiring bit string includes a total of 12 bits, which are an arrangement of the bits from FIG. 7(F) to FIG. 7(I).

[0041] (arithmetic processing) Specific details of the processing performed by the arithmetic device 10, the first server 100, and the second server 200 will be described using the flow of FIG. 9. In step S10, conditions for the filter circuit are set. Specifically, in product design, the type of noise and noise frequency that need to be attenuated are determined. Then, a filter circuit configuration (e.g., a π filter, a band-pass filter, etc.) suitable for attenuating the determined noise is determined. By determining the filter circuit configuration, the type and number of required elements can be obtained. The conditions for step S10 may be set by the user or by a device that performs automatic design for EMC optimization. In this embodiment, a case where the filter circuit configuration is a π filter, as shown in FIG. 3, will be described.

[0042] In step S20, the two-dimensional lattice generation unit 31 transmits two-dimensional lattice information to the second server 200. The two-dimensional lattice information is information for causing the second server 200 to generate the two-dimensional lattice 30. The two-dimensional lattice information may include the filter circuit configuration determined in step S10, the type and number of required elements, etc. The second server 200 determines the required size of the two-dimensional lattice 30 based on the two-dimensional lattice information. Then, the second server 200 generates the two-dimensional lattice 30. In this embodiment, as shown in FIG. 2, a two-dimensional lattice 30 with 15 lattices in the x-axis direction and 10 lattices in the y-axis direction is generated.

[0043] In step S30, the determination unit 32 transmits determination information to the second server 200. The determination information is information for causing the second server 200 to determine the element lattice, terminal lattice, and wiring lattice array. The determination information may include, for example, information specifying the number of candidates for each of the terminal position, element position, and wiring topology. In this embodiment, as shown in FIG. 2, two candidates for each of the terminal position and element position are determined. Furthermore, as shown in FIGS. 4 and 5, four candidates for each of the wiring topologies are determined.

[0044] In step S40, the second server 200 determines the initial circuit configuration. Specifically, one candidate is selected from each of the terminal position, element position, and wiring topology candidates. The selection of the initial circuit configuration may be performed randomly. In this embodiment, a case where the initial circuit configuration shown in FIG. 6 is determined will be described.

[0045] In step S50, the evaluation value calculation unit 33 transmits evaluation value calculation information to the second server 200. The evaluation value calculation information is information for causing the second server 200 to calculate an evaluation value of the filter circuit modeled by the two-dimensional lattice 30. An example of the evaluation value is S 21 The parameters are: 21 The smaller the parameter, the better. Various methods can be used to calculate the evaluation value. For example, calculation using FEM may be used.

[0046] In step S60, it is determined whether the number of loops of the process is equal to or less than a predetermined upper limit. If the upper limit is exceeded (S60: NO), the flow ends. On the other hand, if the upper limit is not exceeded (S60: YES), the flow proceeds to step S70, where the process continues.

[0047] In step S70, the acquisition function generation unit 34 transmits acquisition function information to the second server 200. The acquisition function information is information for causing the second server 200 to generate an acquisition function. The acquisition function will now be described. FIG. 10 shows a schematic diagram of the acquisition function. The acquisition function is a function that defines an optimization problem in which the terminal positions, element positions, and wiring topology are "binary variables" and the performance of the filter circuit is the "evaluation value." The binary variables are 22 bit strings expressed in one-hot format, as shown in the example of FIG. 8. The evaluation value is calculated as the S 21 The parameters are the acquisition function. In other words, the acquisition function is a function that takes the element lattice, terminal lattice, and wiring lattice array as arguments and represents the possibility of obtaining a better evaluation value. The acquisition function is a QUBO-format function. Therefore, it can be solved by the Ising solver provided by the first server 100.

[0048] The technology described herein is characterized by applying the optimization problem to an electromagnetic filter circuit. Therefore, the acquisition function used in this embodiment includes a penalty term specific to electromagnetics. This penalty means that only one of multiple candidates for circuit element locations can be selected (complete exclusion). Selecting two or more candidates results in two or more identical circuit elements being connected, making it impossible to form the desired filter circuit. For example, of the first candidate IC1 and the second candidate IC2 in Figure 2, only one must be selected. Therefore, the one-hot expressions (see Figure 7(B)) representing the first candidate IC1 and the second candidate IC2 must be either "10" or "01," and "11" and "00" are not permitted.

[0049] On the other hand, multiple wiring topologies can be selected (overlap allowed). This is because a conduction path can be ensured even if multiple wirings exist. Therefore, in the one-hot representation of the first wiring (see Figure 7(F)), values ​​such as "110," "101," "111," and "011" can be used in addition to "100," "010," and "0001." Also, if none of the wiring topology candidates is selected, a special candidate may be selected. For example, if the one-hot representation of the first wiring (see Figure 7(F)) results in "000," the special candidate W1e (Figure 5) wiring topology is selected. This makes it possible to ensure conduction between elements even when no penalty is set for the wiring topology.

[0050] The contents of the acquisition function and the penalty terms are conventional techniques, so a detailed explanation will be omitted.

[0051] In step S80, the calculation unit 35 transmits the acquisition information to the second server 200. The acquisition information is information for causing the first server 100 to acquire the acquisition function generated by the second server 200. The acquisition information may be, for example, address information of the first server 100. The second server 200 may transmit the generated acquisition function to the first server 100 based on the acquisition information.

[0052] In step S90, the first server 100 receives the acquisition function. Then, an optimal solution of the acquisition function is calculated using an Ising machine. Specifically, as shown in FIG. 10, the acquisition function is minimized using Bayesian optimization. This allows the optimal solution of the acquisition function to be used in the next filter circuit search.

[0053] In step S100, the first server 100 transmits the calculated optimal solution to the second server 200. The second server 200 receives the optimal solution.

[0054] In step S110, the determination unit 32 transmits determination information to the second server 200. The determination information is information that instructs the second server 200 to determine the next filter circuit to be searched for. Having received the determination information, the second server 200 determines the next element lattice, terminal lattice, and wiring lattice array based on the optimal solution received in step S100. Then, the process returns to step S50.

[0055] As described above, the calculation of the evaluation value by the evaluation value calculation unit 33 (step S50), the generation of the acquisition function by the acquisition function generation unit 34 (step S70), the calculation of the optimal solution by the calculation unit 35 (step S90), and the determination of the element lattice, terminal lattice, and wiring lattice array by the determination unit 32 (step S110) are repeatedly executed until the upper limit number of times is reached. This makes it possible to update the acquisition function every time an evaluation value is calculated. By repeatedly calculating the evaluation value, the acquisition function can be learned, thereby improving the prediction accuracy of the filter circuit performance.

[0056] (effect) The technology described herein allows an optimization problem to be defined using an acquisition function, with element positions, terminal positions, and wiring topology as variables and filter circuit performance as an evaluation value. Then, by finding an optimal solution to the acquisition function (step S90), all past evaluation values ​​can be used to predict the filter circuit performance for a given combination of element positions, terminal positions, and wiring topology. Furthermore, repeated calculation of evaluation values ​​allows the acquisition function to be learned, thereby improving the accuracy of filter circuit performance predictions. As a result, it becomes possible to design a filter circuit with high noise performance with fewer calculations than when predictions using an acquisition function are not performed. It is possible to automatically generate an optimal filter circuit that reduces target noise without relying on experience. This facilitates the reduction of electromagnetic shielding materials and miniaturization.

[0057] Although the embodiments of the technology disclosed in this specification have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples exemplified above.

[0058] (Variation) In this embodiment, multiple candidates are provided for each of the element position, terminal position, and wiring topology. However, this is not limiting and multiple candidates can be set for various targets. For example, multiple candidates may be set for the specifications of circuit elements. FIG. 11(A) shows the one-hot representation of the specification candidates for the input capacitor IC. The first specification candidate IC1s (10 μF) is represented by "100," the second specification candidate IC2s (100 μF) is represented by "010," and the third specification candidate IC3s (500 μF) is represented by "001." Similarly, FIG. 11(B) shows the one-hot representation of the specification candidate for the inductor L. FIG. 11(C) shows the one-hot representation of the specification candidate for the output capacitor OC. A specification bit string can be constructed by arranging the bits shown in FIGS. 11(A) to 11(C), for a total of nine bits. The specification bit string can be combined with the position bit string and the wiring bit string (FIG. 8). This makes it possible to optimize the filter circuit, including the specifications of the circuit elements.

[0059] The technology of this specification is not limited to π-type filter circuits but can be applied to various filter circuits (e.g., band-pass filter circuits). Furthermore, the technology of this specification is not limited to passive filters but can also be applied to active filters. Circuit elements that can be used with the technology of this specification are not limited to capacitors and inductors but can also be resistors, transformers, operational amplifiers, etc.

[0060] The method of obtaining the evaluation value in step S50 is not limited to calculation, but may also be to actually configure a filter circuit and obtain the evaluation value experimentally.

[0061] The method of expressing candidate element positions as binary variables is not limited to one-hot representation, and various other representations can be used, such as simple binary representation.

[0062] The first server 100 and the second server 200 may be an integrated server. Alternatively, the computing device 10 may have the functions of the first server 100 and the second server 200 and operate as a standalone server.

[0063] The technical elements described in this specification or drawings exhibit technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings simultaneously achieve multiple objectives, and achieving one of those objectives is itself technically useful.

[0064] The x-axis is an example of the first axis, and the y-axis is an example of the second axis. [Explanation of symbols]

[0065] 1: Communication system 10: Arithmetic unit 22: CPU 24: Memory 25: Program 30: Two-dimensional grid 31: Two-dimensional grid generation unit 32: Determination unit 33: Evaluation value calculation unit 34: Generation unit 35: Arithmetic unit 40: Noise filter circuit 100: First server 200: Second server IT: Input terminal IC: Input capacitor L: Inductor OC: Output capacitor OT: Output terminal

Claims

1. A computing device for determining a configuration of a filter circuit having circuit elements, input terminals, output terminals, and wiring, a computing device that determines an element position of the circuit element, terminal positions of the input terminal and the output terminal, a wiring topology of the wiring that connects the element position and the terminal position, and a wiring topology of the wiring that connects between the element positions, The computing device a two-dimensional lattice generation unit that generates a two-dimensional lattice, wherein each of a plurality of lattices included in the two-dimensional lattice is configured to be able to represent the element positions, the terminal positions, and the wiring topology; a determination unit that determines an element lattice that is a lattice corresponding to the element position, a terminal lattice that is a lattice corresponding to the terminal position, and a wiring lattice array that is a series of lattices that corresponds to the wiring topology; an evaluation value calculation unit that calculates, as an evaluation value, the performance of a filter circuit formed by the element grid, the terminal grid, and the wiring grid array; an acquisition function generation unit that generates an acquisition function that takes the element lattice, the terminal lattice, and the wiring lattice array as arguments and indicates the possibility of obtaining a better evaluation value; a calculation unit that calculates an optimal solution of the acquisition function generated by the acquisition function generation unit; Equipped with determining the element lattice, the terminal lattice, and the wiring lattice array by the determination unit, calculating the evaluation value by the evaluation value calculation unit, generating the acquisition function by the acquisition function generation unit, and calculating the optimal solution by the calculation unit; the determination unit determines the next element grid, the terminal grid, and the wiring grid array based on the optimal solution calculated by the calculation unit. Computing device.

2. The determination unit generating a plurality of candidates for the element grid, a plurality of candidates for the terminal grid, and a plurality of candidates for the wiring grid array; determining an element lattice selected from a plurality of element lattice candidates as an element lattice corresponding to the element position; determining a terminal lattice selected from the plurality of terminal lattice candidates as a terminal lattice corresponding to the terminal position; 2. The computing device according to claim 1, wherein a wiring grid row selected from a plurality of candidates for the wiring grid row is determined as the wiring grid row corresponding to the wiring topology.

3. the two-dimensional grating has orthogonal first and second axes; the determining unit generates a first candidate and a second candidate when generating a plurality of candidates for the wiring grid array connecting a first grid and a second grid; the first candidate corresponds to a wiring topology obtained by changing only the coordinate of the second axis so as to minimize the distance between the first grid and the second grid, and then changing only the coordinate of the first axis so as to connect to the second grid; 3. The computing device according to claim 2, wherein the second candidate corresponds to a wiring topology in which only the coordinate of the first axis is changed so that the distance between the first grid and the second grid is minimized, and then only the coordinate of the second axis is changed so that the second candidate is connected to the second grid.

4. the two-dimensional grating has orthogonal first and second axes; the determining unit generates a special candidate when generating a plurality of candidates for the wiring grid array connecting a first grid and a second grid; The computing device according to claim 2 , wherein the special candidate is a wiring grid row connecting all of the plurality of candidates in the first grid and all of the plurality of candidates in the second grid.

5. The arithmetic device according to claim 1 , wherein the acquisition function is a QUBO-type function that can be solved by an Ising solver.

6. The arithmetic device according to claim 5 , further comprising a penalty term that the number of said element positions is one for one said circuit element.

7. 7. The arithmetic device according to claim 1, wherein the element lattice, the terminal lattice, and the wiring lattice array are binary variables in one-hot representation.

8. further comprising a network interface capable of communicating with the first server; The calculation unit transmitting acquisition information for causing the first server to acquire the acquisition function generated by the acquisition function generation unit to the first server via the network interface; The computing device according to claim 1 , wherein the optimal solution of the acquisition function computed in the first server is received from the first server via the network interface.

9. the network interface is further configured to be able to communicate with a second server; the two-dimensional lattice generation unit transmits two-dimensional lattice information for causing the second server to generate the two-dimensional lattice to the second server via the network interface; the determination unit transmits, to the second server via the network interface, determination information for causing the second server to determine the element lattice, the terminal lattice, and the wiring lattice array; the evaluation value calculation unit transmits evaluation value calculation information for causing the second server to calculate the evaluation value to the second server via the network interface; the acquisition function generation unit transmits acquisition function information for causing the second server to generate the acquisition function to the second server via the network interface; the calculation unit transmits the acquisition information for causing the first server to acquire the acquisition function generated by the second server to the first server via the network interface; The computing device according to claim 8 .

10. the filter circuit is a π-type filter circuit, The computing device of claim 1 , wherein the circuit elements include an inductor and a capacitor.

11. A calculation method for determining a configuration of a filter circuit having circuit elements, input terminals, output terminals, and wiring, comprising: A calculation method for determining an element position of the circuit element, terminal positions of the input terminal and the output terminal, a wiring topology of the wiring connecting the element position and the terminal position, and a wiring topology of the wiring connecting between the element positions, comprising: The calculation method includes: a two-dimensional lattice generation step of generating a two-dimensional lattice, wherein each of a plurality of lattices included in the two-dimensional lattice is configured to be able to represent the element positions, the terminal positions, and the wiring topology; a determining step of determining an element grid, which is a grid corresponding to the element positions, a terminal grid, which is a grid corresponding to the terminal positions, and a wiring grid array, which is a series of grids corresponding to the wiring topology; an evaluation value calculation step of calculating, as an evaluation value, the performance of a filter circuit formed by the element grid, the terminal grid, and the wiring grid array; an acquisition function generation step of generating an acquisition function that takes the element lattice, the terminal lattice, and the wiring lattice array as arguments and represents the possibility of obtaining a better evaluation value; a calculation step of calculating an optimal solution of the acquisition function generated in the acquisition function generation step; Equipped with repeatedly executing the determination of the element lattice, the terminal lattice, and the wiring lattice array in the determination step, the calculation of the evaluation value in the evaluation value calculation step, the generation of the acquisition function in the acquisition function generation step, and the calculation of the optimal solution in the calculation step; the determining step determines the next element grid, the terminal grid, and the wiring grid array based on the optimal solution calculated in the calculating step; Calculation method.

12. An information processing program that is read into a computer of a computing device and determines a configuration of a filter circuit having circuit elements, input terminals, output terminals, and wiring, an information processing program for determining an element position of the circuit element, terminal positions of the input terminal and the output terminal, a wiring topology of the wiring connecting the element position and the terminal position, and a wiring topology of the wiring connecting between the element positions, The computing device a two-dimensional lattice generation unit that generates a two-dimensional lattice, wherein each of a plurality of lattices included in the two-dimensional lattice is configured to be able to represent the element positions, the terminal positions, and the wiring topology; a determination unit that determines an element lattice that is a lattice corresponding to the element position, a terminal lattice that is a lattice corresponding to the terminal position, and a wiring lattice array that is a series of lattices that corresponds to the wiring topology; an evaluation value calculation unit that calculates, as an evaluation value, the performance of a filter circuit formed by the element grid, the terminal grid, and the wiring grid array; an acquisition function generation unit that generates an acquisition function that takes the element lattice, the terminal lattice, and the wiring lattice array as arguments and indicates the possibility of obtaining a better evaluation value; a calculation unit that calculates an optimal solution of the acquisition function generated by the acquisition function generation unit; and make it work, determining the element lattice, the terminal lattice, and the wiring lattice array by the determination unit, calculating the evaluation value by the evaluation value calculation unit, generating the acquisition function by the acquisition function generation unit, and calculating the optimal solution by the calculation unit; the determination unit determines the next element grid, the terminal grid, and the wiring grid array based on the optimal solution calculated by the calculation unit. Information processing program.

Images