Quantum field programmable photonic gate arrays, integrated photonic and quantum devices, and programmable circuits

Abstract

The present invention relates to an integrated photonic and quantum system implemented by the combination and interconnection of programmable photonic processing blocks implemented on a photonic chip, which is capable of implementing one or more simultaneous quantum and classical circuits with optical feedback paths and / or linear multi-port conversion by appropriate programming of its resources and selection of its input / output ports. The present invention also relates to a quantum field programmable photonic gate array (Q-FPGA) comprising at least one programmable circuit based on a tunable beam splitter with independent coupling and phase shift configurations and surrounding high performance building blocks enabling classical and quantum operation.

Description

[Technical Field]

[0001] The present invention relates to an integrated photonic and quantum system implemented by the combination and interconnection of programmable photonic processing blocks implemented on an optical circuit, which can implement one or more quantum and classical circuits with optical feedback paths and / or linear multi-port conversion by programming its resources and selecting its input and output ports.

[0002] The present invention also relates to a quantum field programmable photonic gate array (Q-FPPGA) comprising at least one programmable circuit based on a tunable beam splitter with independent phase tuning and peripheral high performance building blocks enabling classical and quantum operation. [Background technology]

[0003] Programmable multifunction photonics (PMP) aims to design integrated optical hardware architectures that can implement a wide variety of applications and functions by means of suitable programming of its components. Various authors have conducted theoretical studies proposing different architectures and design principles for programmable circuits based on cascaded beam splitters or Mach-Zehnder interferometers (MZIs). While these proposals offer versatile hardware solutions for realizing programmable circuits, they do not define a complete architectural solution for photonic devices that can be programmed to realize simple, complex, or arbitrary circuits, either singly or simultaneously. Only very recent patents (US16 / 235,056, JP2018-247546, P201930410, P201831118), proposed in light of the aforementioned details, have led to the definition of field-programmable photonic arrays (FPGAs).

[0004] Furthermore, we demonstrate that the combination of basic optical processing units with the ability to program / tune / select beam splitting ratios between their output ports and phase tuning leads to waveguide mesh elements with different mesh topologies and unprecedented versatility in terms of their functionality. In particular, some of the proposed architectures enable feedback loops of optical signals inside the mesh, enabling the creation of optical cavities, Sagnac loops, and more complex circuits. Furthermore, a very recent patent application (P201930410) also describes a technological improvement of waveguide meshes based on the combination of tunable basic units (TBUs) with the same spatial / angular orientation, meaning that the longitudinal axes of the TBUs are parallel to each other. This technological advantage results in reduced manufacturing defects and improves the performance and scalability of the fabricated circuits.

[0005] In parallel, various authors have presented integrated circuits that perform linear transformations of guided wave modes at the input of a waveguide mesh. The proposed architectures require a combination of beam splitters and phase actuators with fixed interconnections. Some publications use these circuits to perform a limited set of operations used in quantum signal processing, particularly in the creation of transformation arrays, where they describe the operation between input and output modes. Summary of the Invention [Problem to be solved by the invention]

[0006] The object of the present invention is to solve the above-mentioned problems and enable the design of programmable quantum and classical signal processing systems, in which all the above-mentioned components are connected to a reconfigurable optical core that allows the implementation of reconfigurable linear transformations, signal conditioning and dynamic interconnections of classical high-performance processing blocks, quantum high-performance processing blocks, chip-to-chip couplers and chip-to-fiber couplers.

[0007] The objective of the present invention is based on the repetition, replication, and interconnection of programmable photonic analog units, preferably reconfigurable interconnects implemented within a photonic chip. These components provide basic building blocks for implementing basic optical analog signal operations (reconfigurable optical power and energy division and independent phase configuration) and, by extension, the implementation of reconfigurable 2x2 rotating arrays or gates. In a very broad sense, the processing performed can be considered reconfigurable in the same way that programmable logic blocks (PLBs) perform digital operations in configurable analog blocks (CBAs) perform analog operations in electronic field programmable gate arrays or field programmable analog arrays (FPAAs). Thus, in light of what is proposed below, the objective of the present invention is that by means of specific programming of resources and integrated components, namely, programmable photonic analog blocks, classical high-performance building blocks (HPBs), and quantum high-performance building blocks (QHPBs), as well as the selection of ports to be used, one or a variety of simultaneous photonic circuits and / or linear multiport transformations can be obtained. Thus, the essential contribution of the present invention is the architecture, workflow, technology stacking, and technology description that enables a general-purpose interconnected program to perform quantum signal processing in parallel with quantum and classical signal processing. [Means for solving the problem]

[0008] The object of the present invention is to provide an architecture consisting of a core connected to optical ports, a high-performance processing block, and a high-performance quantum processing block, comprising at least three layers that describe the architecture physically and from a software perspective. The core of the device has different types of internal interconnections of programmable photonic analog blocks or tunable basic units that are uniformly oriented and can be implemented to form patterns, including, but not limited to, a) a uniform distribution of conventional hexagons, b) a proposed layout of uniformly oriented units, c) a uniform distribution of conventional triangles, d) a proposed layout of uniformly oriented units, e) a proposed layout of uniformly oriented units, and by means of forming non-uniform patterns.

[0009] Full quantum operation requires that the circuit be optically input with a signal coming from a quantum source and detected at a quantum signal detection element. Overall, these systems or circuits are capable of performing the reconfigurable linear transformations required for quantum operations, but do not offer the flexibility required for the dynamic interconnection between different subsystems or processing blocks required for a processor.

[0010] The quantum field programmable photonic gate array photonic and quantum system of the present invention offers a set of advantages inherent in field or real-time programming, enhanced by the circuit topology introduced by the present invention.

[0011] Benefits include: · Reduced production time and time to market. Reduced prototype development time and non-recurring costs. · Reduced financial risk in developing an idea and translating it into an ASPIC. Multi-function simultaneous or parallel operation circuits. Circuit optimization. · Reduced manufacturing footprint, improved single and common architecture. Increased productivity and repeatability of programmable photonic analog blocks. · A larger number of alternative topologies, not constrained by geometric factors and fixed layouts.

[0012] The proposed Q-FPPGA of the present invention is suitable for the following applications: Classic Applications: Aerospace and Defense (Aviation, Communications, Security, Space) Automotive (high-definition video, image processing, vehicle networks, connectivity) Data centers (servers, routers, switches, gateways) High-performance computing (servers, supercomputers, SIGINT systems, high-end radar, high-end beamforming systems, quantum computing, high-speed neural networks) Integrated circuit design (ASPIC prototyping, hardware emulation) Wired and wireless communications (optical transport networks, 5G connectivity interfaces, mobile backhaul) Hardware accelerator Artificial intelligence, machine learning, and deep learning applications Educational Kit [Brief explanation of the drawings]

[0013] The accompanying set of drawings shows, in an illustrative and non-limiting sense, in accordance with a preferred practical embodiment of the invention, in order to complement the description given in the specification and to aid in a better understanding of the nature of the invention. [Figure 1] This figure shows the general scheme of the Q-FPPGA architecture and details the three layers that describe the architecture from a physical and software perspective. [Figure 2a] 1A-1C show non-limiting examples of schematic diagrams for embodiments of a Q-FPGA core: (a1) a conventional hexagonal uniform arrangement; (a2) a proposed uniformly oriented unit arrangement. [Figure 2b]1A-1B show non-limiting examples of schematic diagrams for embodiments of a Q-FPGA core: (b1) a conventional square uniform arrangement; (b2) a proposed uniformly oriented unit arrangement. [Figure 2c] 1A-1C show non-limiting examples of schematic diagrams for embodiments of a Q-FPGA core: (c1) a conventional uniform distribution of triangles; (c2) a proposed uniformly oriented unit arrangement. [Figure 2d] 1A and 1B show schematic diagrams for embodiments of a Q-FPGA core with uniformly oriented tunable elementary units and following a non-uniform pattern; and FIG. 1C shows some non-limiting examples. [Figure 2e] 1A and 1B show schematic diagrams for embodiments of a Q-FPGA core with uniformly oriented tunable elementary units and following a non-uniform pattern; and FIG. 1C shows some non-limiting examples. [Figure 3] FIG. 1 illustrates a non-limiting classification of different classical and quantum devices present in a Q-FPPGA architecture. [Figure 4] The diagram (left) shows the main steps involved in the design / construction flow of the integrated photonic and quantum system of the present invention, and (right) shows the expanded layout including the soft and hard layers of the photonic circuitry and surrounding high performance elements. [Figure 5] FIG. 1 illustrates the simultaneous implementation of a classical ring cavity circuit, a Mach-Zehnder interferometer, and a 3×3 multi-port device using the reconfigurable Q-FPGA core of our chip. [Figure 6] On the left, a non-limiting example of an implementation of a quantum circuit with a verification path (in this case a CNOT gate) is shown. [Figure 7] FIG. 1 illustrates a non-limiting example of an implementation of a switched or simultaneous resource-sharing set of programmable quantum circuits. [Figure 8] 1 illustrates a non-limiting example of the concurrent execution of an independent set of quantum circuits, each using its own resources. [Figure 9]FIG. 1 illustrates a non-limiting example of a programmable quantum circuit that supports the quantum Fourier transform. [Figure 10] (Left) is an example of simultaneously constructing a quantum circuit and a classical circuit, and (right) is the layout of the implemented circuit. DETAILED DESCRIPTION OF THE INVENTION

[0014] Exemplary embodiments of the invention are described below according to the illustrated drawings.

[0015] In FIG. 1, a Q-FPGA is shown that includes at least one, and preferably many, programmable photonic analog blocks (PPABs), realized by a series of waveguide elements integrated into a photonic circuit.

[0016] These blocks have programmable characteristics and can propagate optical signals in both directions.

[0017] The design of FIG. 1 does not consider any particular interconnection topology for the Q-FPPGA core, and the resulting design shown therein is for illustrative purposes only.

[0018] FIG. 2 shows various alternatives and interconnect geometries designed for the implementation of a Q-FPPGA core.

[0019] While various configurations for implementing PPAB can be considered, we will describe a very basic four-port design as described in the references US 16 / 235,056, JP2018-247546, P201930410, and P201831118.

[0020] The function of the PPAB is to provide an independently tunable power coupling relationship and an adjustable phase response configuration, as described below.

[0021] Collectively, the waveguide mesh performs dynamic routing or switching between different Q-FPGA ports and regions, and between classical and quantum high performance building blocks.

[0022] Like modern FPGA families, Q-FPGAs can include classical and quantum high-performance processing blocks (HPB, QHPB) to extend their capabilities and include higher-level functions connected to the chip core, as shown schematically on the right side of Figure 1.

[0023] Having these functions and higher level blocks embedded in the chip reduces the area required for these functions compared to their implementation via the basic blocks of the core.

[0024] Furthermore, by using the core exclusively, it is not possible to divide and program a part of the function.

[0025] Examples of these processing blocks include highly dispersive elements, helical delay lines, general modulation and photodetection subsystems, optical amplifier and light source subsystems, and high performance filtering structures, to name a few.

[0026] A special case of HPB includes elements interconnected in an optical core, which may be either spectrally periodic or aperiodic, including multiplexing and demultiplexing subsystems, allowing processing on different spatial channels / modes as well as different spectral channels / modes.

[0027] However, the major technological advancement comes from the interconnection of quantum HPBs. These HPBs provide quantum functionality that can be efficiently partitioned, distributed, and programmed within Q-FPGA cores, in addition to combining them with HPBs and QHPBs as quantum sources, detectors, processing signals, and collateral detectors, to cite a few.

[0028] FIG. 3 provides a non-limiting example of the components present in a Q-FPGA.

[0029] PPAB is a 2x2 photonic block or component with a common phase shift

[0030]

number

[0031] and the optical power split ratio K=sin□ (0<=K<=1) between the waveguide input and output access fields can be configured independently.

[0032] By means of specific programs and the connection of processing blocks, the Q-FPPQA divides conventional optical processing circuits into reconfigurable photonic interconnect (RPI) and PPAB units, and by using high-performance processing blocks, it can perform complex autonomous and / or parallel circuits, signal processing transformations, and quantum processing operations.

[0033] In particular, the concept of programming a Q-FPPGA core is illustrated by three general design approaches, each of which is shown in Figure 5 .

[0034] Figure 5(a) shows how the configuration of each processing block leads to the programming of two optical filters based on a ring resonator and a Mach-Zehnder interferometer.

[0035] Figure 5(b) shows the program of the Q-FPPGA core to obtain a multiport interferometer.

[0036] A quantum field programmable photonic gate array (Q-FPPA) according to the present invention is an array of unspecified elements that can be interconnected according to user specifications configured for a wide variety of classical and quantum applications. Q-FPPGAs combine the programmable nature of the most basic reconfigurable photonic integrated circuits with quantum processing components in a scalable interconnect structure, enabling dynamically programmable circuits with much higher processing density. Thus, the programming of complex circuits comes from the interconnectivity. Our proposed invention solves some of the problems associated with quantum circuits: quantum and classical circuits are programmed using shared resources integrated within the chip, resulting in the advantages inherent in direct (or field) programmable hardware approaches, namely, shorter time to manufacture, develop, and take solutions to market, shorter prototype development time, and non-recurring engineering costs, reduced financial risk in developing ideas and translating them into ASPIC, multi-function and multi-task operation, circuit optimization, better yield and reproducibility of PPABs.

[0037] Compared with FPPA and reconfigurable photonic circuits, this invention incorporates dynamic quantum signal processing through the aggregation of high-performance processing blocks and the design of workflow and architecture.

[0038] The left side of Figure 4 shows the main steps in the design flow process described here.

[0039] Similar to photonic FPPAs, the starting point of the design flow is the entry of the applications to be performed, which in this case can be both classical and / or quantum applications.

[0040] The specification is then processed through an optimization procedure to enhance the area used and the performance of the final circuit.The specification is then transformed into a circuit compatible with the elements included in the Q-FPPGA (technology mapping process), optimizing attributes such as delay, performance, and number of elements used.

[0041] The technology mapping phase converts the optimized network into a circuit consisting of a limited set of Q-FPGA elements.

[0042] This is done by selecting components and parts of the network that can each be implemented by the elements available in the Q-FPPGA, and then specifying how these elements are to be interconnected.

[0043] This determines the total number of processing components required for the intended implementation.

[0044] Next, decisions regarding the placement of different parts of the circuit follow, assigning each to a specific location on the Q-FPGA, at which point global routing is responsible for selecting which processing elements will act as access paths.

[0045] In contrast to electronic FPGAs, this structure does not make a physical distinction between processing elements and interconnect elements. Subsequently, the processing elements are correspondingly configured, the performance is calculated, and the design is verified. This process can be done physically by providing all the necessary configuration data to a programming unit to configure the final chip, or by using an accurate model of the Q-FPGA. At each step, an optimization process can be performed that determines how to reconfigure any previous steps. From the above description, it can be understood that a Q-FPGA includes not only physical photonic and electronic control hardware, but also a software layer (see the top right portion of Figures 1 and 4). The steps involved in the design flow can be performed automatically by the software layer, by the user, or by a mixture of the two, depending on the autonomy and capabilities of the Q-FPPGA. Furthermore, failure in any of the preceding steps requires an iterative process until the specifications are successfully met. The parallel optimization process tolerates defects and manufacturing imperfections, providing robust operation in addition to the ability to increase the processing power of the physical device. Furthermore, Q-FPPGAs can incorporate multiple independent cores that can be interconnected to each other and to high performance processing blocks to increase processing capacity. These waveguide cores can be integrated within the same substrate or in different chips. [Example of operation] 6-10 provide some examples in which different types of Q-FPGAs are simultaneously programmed to emulate and implement different quantum photonic circuits.

[0046] The examples are illustrative of capabilities and are not intended to be exhaustive; rather, they show simple configurations that can be extended to more complex circuits.

[0047] In such layouts, only relevant components such as I / O ports, HPB, and QHPB are shown. In each case, the figure includes a Q-FPPGA layout with the operating PPAB highlighted within the waveguide core, as well as layouts of the different implemented circuits.

[0048] Figure 6 represents the operational case when the Q-FPPGA is programmed to implement a quantum gate.

[0049] The case shown here corresponds to a C-NOT gate with the configuration shown on the right side of the figure, where the input state and herald photon are generated by a QHPB that generates photon pairs via nonlinear effects such as spontaneous four-wave mixing (SFWM), and the output state and herald photon are detected by means of a specific QHPB block that implements a photon counter. The programmable mesh waveguide performs two tasks: filtering one of the two photons generated by the SWFM and a linear unitary transformation that implements the CNOT gate. The QHPB should ideally be on the same chip, but can be placed externally within the Q-FPPGA through hybrid or heterogeneous integration (note that the unused HPB blocks and I / O ports of the Q-FPPGA are not shown for simplicity). Furthermore, more complex circuits can be implemented by extending the concepts shown and using a higher proportion of resources, components and mesh parts, as well as extra QHPBs implementing additional sources and detectors. FIG. 7 shows operation in the switching mode. Here, two or more circuits are programmed across available sources, specifically independent photon sources, in a Q-FPPGA that in this case share a common QHPB. Examples are shown of a triangular boson sampler and a Hadamard gate, the implementations of which are shown in the upper right and lower right corners, respectively.

[0050] Both circuits share a common core formed by a QHPB that generates photon pairs via SFWM, as well as a waveguide mesh to perform their corresponding linear transformations. Switching is performed by tuning a programmable photonic analog block (PPAB) inside the waveguide mesh to select operation of one circuit or another. Photon detection is performed in this example by a non-shared QBPB.

[0051] FIG. 8 illustrates operation in a shared mode, where two or more circuits are simultaneously configured on a physical device defined by a waveguide mesh and a perimeter block. In this particular case, a QHPB is employed for preparation and detection of the input and output signals, respectively, and different sections of the waveguide mesh are used to perform the required photon filtering and linear unitary transformation. The two circuits are, in this case, a Hadamard gate and a cascade of gates corresponding to the X, Y, and Z rotation transformations. The QHPB implementing the Hadamard gate initial state is a photon pair source that requires post-filtering, while the QHPB implementing the rotation cascade matrix initial state is a single-photon source.

[0052] Figure 9 illustrates the case where an (N-dimensional) state or quantum mode is input to the QFPGA via one of the I / O ports. Here, the QFPGA is programmed to perform a simple linear transformation, and no additional QHPB is used unless the final state needs to be measured. For example, the example in Figure 9 illustrates the performance of a quantum Fourier transform operation. Finally, Fig. 10 shows an example of mixed operation of classical and quantum signals, where part of the core formed by the waveguide mesh implements a quantum gate (rotating array cascade), and the other part implements a classical coupled-cavity filter (CROW) to process the classical signal generated by using two HPBs consisting of integrated DBF lasers and external modulators. [Physical Implementation] The physical implementation of Q-FPGA devices requires integrated optics approaches based on silicon photonics technology or other materials from group 4, or hybrid / heterogeneous combinations with other materials such as materials from groups 3-5. Regarding PPAB elements, currently available integrated photonics technology options allow the integration of phase-adjusting elements such as MEMS, thermo-optical, opto-mechanical, electro-capacitive, phase-change materials, or non-volatile actuators. These phase actuators can be integrated into any interferometric or non-interferometric, resonant or non-resonant structure with two or more ports. Finally, as mentioned above, more complex Q-FPPGA layouts can be designed by configuring different block interconnect schemes. Some examples are shown in Figure 2.

[0053] As shown in Figure 1, the physical device (hardware) corresponding to the integrated optical circuit requires system integration with control electronics to perform the programming tasks of the optoelectronic actuators and to perform the tasks and overall optimization of the circuit.

Claims

1. A reconfigurable quantum field programmable photonic gate array core, and comprising at least a quantum high performance building block (QHPB); at least a quantum high performance building block (QHPB) is connected to said reconfigurable quantum field programmable photonic gate array core; the quantum high performance building block (QHPB) and the reconfigurable quantum field programmable photonic gate array core are connected by a dynamic interconnect; Quantum Field Programmable Photonic Gate Array (Q-FPGA).

2. at least one quantum field programmable photonic gate array (Q-FPGA) further comprising at least one optical port connected to the reconfigurable quantum field programmable photonic gate array core and / or at least one high performance building block (HPB); 10. The quantum field programmable photonic gate array (Q-FPGA) of claim 1.

3. The reconfigurable quantum field programmable photonic gate array core comprises at least one programmable photonic analog block (PPAB) implemented by a series of photonic waveguide elements integrated on a photonic chip.

3. A quantum field programmable photonic gate array (Q-FPGA) according to claim 1 or 2.

4. The reconfigurable quantum field programmable photonic gate array core includes at least two interconnected programmable photonic analog blocks (PPABs) that are uniformly oriented and arranged following a uniform pattern.

4. The quantum field programmable photonic gate array (Q-FPGA) of claim 3.

5. The uniform arrangement pattern is one selected from a hexagonal uniform waveguide mesh arrangement, a square uniform waveguide mesh arrangement, and a triangular uniform waveguide mesh arrangement.

5. The quantum field programmable photonic gate array (Q-FPGA) of claim 4.

6. The reconfigurable quantum field programmable photonic gate array core comprises at least two interconnected programmable photonic analog blocks (PPABs) arranged in a uniformly oriented and non-uniform pattern.

4. The quantum field programmable photonic gate array (Q-FPGA) of claim 3.

7. At least the quantum high performance building block (QHPB) is one selected from a quantum source, a detector, a processing unit, and a detector; The quantum field programmable photonic gate array (Q-FPGA) of claim 2.

8. and a plurality of independent cores interconnected to each other and to the at least one of the at least one optical port and the at least one high performance building block (HPB). The quantum field programmable photonic gate array (Q-FPGA) of claim 2.

9. A physical layer including at least the quantum field programmable photonic gate array (Q-FPGA) according to any one of claims 1 to 8; an electronic control layer; A software layer; Including, Integrated photonic and quantum devices realized via photonic circuits integrated on chip substrates.

10. A programmable quantum circuit comprising the integrated photonic and quantum device of claim 9.

11. 11. The programmable quantum circuit of claim 10, wherein the circuit is based on a ring resonator or a Mach-Zehnder interferometer (MZI).

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