Multilayer electronic components

Abstract

To provide a laminated electronic component that can be easily inspected.SOLUTION: A laminated electronic component includes a laminate 10 in which a plurality of dielectric layers 11a to 11i are laminated in the lamination direction, the laminate 10 having a first surface and a second surface provided on both sides in the lamination direction, a first side surface electrode 14c provided on a side surface of the laminate 10, inductors L1 and L2 provided in the laminate, a capacitor C provided between the inductors L1 and L2 and the first surface, via wirings 15a and 15b which penetrate from the first dielectric layer 11b in contact with the inductors L1 and L2 through the dielectric layers to the second dielectric layer 11h located closer to the first surface side than at least a part of the capacitor C, and electrically conduct one ends of the inductors L1 and L2 to the first side surface electrode 14c, and a second side surface electrode 14c which is electrically conducted to the first side surface electrode 14c through the inductors L1 and L2 and the via wirings 15a and 15b, and is provided on the side surface of the laminate 10.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a laminated electronic component, for example, a laminated electronic component having a laminate in which a plurality of dielectric layers are stacked. [Background technology]

[0002] Wireless communication terminals such as smartphones and mobile phones use filters that remove unwanted interference waves and multiplexers such as diplexers. It is known to use a laminate in which dielectric layers are stacked as a filter or multiplexer. It is also known to provide a side electrode on the side of the laminate for electrical connection to the outside (e.g., Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 142667 [Patent Document 2] Japanese Patent Application Publication No. 2017-212717 Summary of the Invention [Problem to be solved by the invention]

[0004] In a laminated electronic component having side electrodes, the inductor can be electrically connected to the side electrodes by connecting the inductor to the side electrodes on the surface of the dielectric layer on which the inductor is formed. The inductor can be inspected by checking the continuity between the side electrodes to which the inductor is connected. However, it is difficult to inspect a dielectric layer on which no inductor is provided.

[0005] The present invention has been made in consideration of the above-mentioned problems, and has an object to make it possible to easily perform an inspection. [Means for solving the problem]

[0006] The present invention provides a laminate in which a plurality of dielectric layers are stacked in a stacking direction, the laminate having a first surface and a second surface provided on both sides in the stacking direction, a first side electrode provided on a side of the laminate, an inductor provided within the laminate, a capacitor provided between the inductor and the first surface, and a first dielectric layer in contact with the inductor. All The capacitance Tayo and penetrates the dielectric layer to the second dielectric layer located on the first surface side. By doing so, the dielectric layer of the entire capacitor formation region in which all the capacitors are provided is penetrated, a via wiring that electrically connects one end of the inductor and the first side electrode; and a via wiring that electrically connects the inductor and the first side electrode through the via wiring and is provided on a side of the laminate. and a resistance defect can be inspected by conducting the electrical connection between the first side electrode and the second side electrode. and a second side surface electrode.

[0007] In the above configuration, the inductor may be configured not to be electrically connected to the first side electrode on the second surface side of the capacitor.

[0008] In the above configuration, another via wiring may be provided that penetrates the dielectric layers from the first dielectric layer to the second dielectric layer and connects the other end of the inductor to the second side electrode.

[0009] In the above configuration, Located closest to the first surface The capacitance Ta and The structure may include a conductor pattern provided between the first surface and adjacent dielectric layers, the conductor pattern electrically connecting the via wiring and the first side electrode.

[0010] In the above configuration, a bottom electrode is provided on the first surface and connected to the first side electrode, and the via wiring is connected to the bottom electrode. directly It can be configured to be connected.

[0011] In the above configuration, the planar area of ​​the via wiring that penetrates at least one of the dielectric layers of the plurality of dielectric layers other than the via wiring electrically connected between the first side electrode and the second side electrode can be configured to be larger than the planar area of ​​the via wiring electrically connected between the first side electrode and the second side electrode.

[0012] In the above configuration, the capacitor may have one end connected to a path between the first side electrode and the second side electrode, and the other end connected to a ground electrode provided on the surface of the laminate.

[0013] In the above configuration, at least a part of the via wiring may not overlap the first side surface electrode in the thickness direction of the first side surface electrode.

[0014] In the above configuration, the distance between the via wiring and the first side surface electrode may be 50 μm or more.

[0015] The above configuration may further include a low-pass filter including the inductor and the capacitor.

[0016] The above configuration may further include a multiplexer including the low-pass filter. [Effects of the Invention]

[0017] According to the present invention, the inspection can be easily carried out. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a circuit diagram of an LPF according to the first embodiment. [Figure 2] 2(a) and 2(b) are a perspective view and a cross-sectional view of the laminated electronic component according to the first embodiment. [Figure 3] 3(a) to 3(f) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the first embodiment. [Figure 4] 4(a) to 4(d) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the first embodiment. [Figure 5] 5(a) and 5(b) are cross-sectional schematic views of a laminated electronic component according to Comparative Example 1. FIG. [Figure 6] 6(a) and 6(b) are cross-sectional schematic views of the laminated electronic component according to the first embodiment. [Figure 7] 7(a) to 7(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the first modified example of the first embodiment. [Figure 8] 8(a) to 8(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the second modification of the first embodiment. [Figure 9] 9(a) to 9(f) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the third modification of the first embodiment. [Figure 10] 10(a) to 10(d) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the third modification of the first embodiment. [Figure 11] 11(a) to 11(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the fourth modification of the first embodiment. [Figure 12] FIG. 12 is a perspective view of the simulated structure. [Figure 13] FIG. 13(a) is a side view of the vicinity of the via wiring 15b, and FIG. 13(b) is a plan view of the vicinity of the via wiring 15b. [Figure 14] 14(a) to 14(c) are diagrams showing the Q values ​​of the inductors for D1 to D3, respectively, in the simulation. [Figure 15] 15(a) to 15(f) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the fifth modified example of the first embodiment. [Figure 16] 16(a) to 16(d) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the fifth modified example of the first embodiment. [Figure 17]17(a) to 17(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the sixth modification of the first embodiment. [Figure 18] 18(a) to 18(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to the seventh modified example of the first embodiment. [Figure 19] FIG. 19 is a circuit diagram of a front-end circuit in which the communication module according to the second embodiment is used. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. [Example]

[0020] As a first embodiment, a laminated electronic component having a low-pass filter (LPF) will be described as an example. Fig. 1 is a circuit diagram of the LPF in the first embodiment. As shown in Fig. 1, an LPF 20 is connected between an input terminal Tin and an output terminal Tout. The LPF 20 passes, to the output terminal Tout, signals in a pass band lower than the cutoff frequency of high-frequency signals input to the input terminal Tin, and suppresses signals in a frequency band higher than the cutoff frequency. The LPF 20 includes inductors L1 and L2 and capacitors C1 to C5.

[0021] Inductors L1 and L2 are connected in series between the input terminal Tin and the output terminal Tout. Nodes N1 to N3 are provided on the path between the input terminal Tin and the output terminal Tout. A capacitor C1 is shunt-connected to the node N1 between the input terminal Tin and the inductor L1. A capacitor C3 is shunt-connected to the node N2 between the inductors L1 and L2. A capacitor C5 is shunt-connected to the node N3 between the inductor L2 and the output terminal Tout. One end of the capacitors C1, C3, and C5 is connected to the nodes N1 to N3, respectively, and the other end is connected to the ground terminal Tg. The capacitor C2 is connected in parallel to the inductor L1 between the nodes N1 and N2. The capacitor C4 is connected in parallel to the inductor L2 between the nodes N2 and N3. In the LPF 20, the input terminal Tin and the output terminal Tout are electrically connected (i.e., connected in a DC manner).

[0022] Table 1 shows examples of the inductances of the inductors L1 and L2 and the capacitances of the capacitors C1 to C5. [Table 1] The number of inductors and capacitors and their element values ​​(ie, inductance and capacitance) can be set appropriately.

[0023] 2(a) and 2(b) are a perspective view and a cross-sectional view of a laminated electronic component according to Example 1. The stacking direction of the laminate 10 is the Z direction, the longitudinal direction is the X direction, and the transverse direction is the Y direction. As shown in FIG. 2(a), the surfaces on both sides of the laminate 10 in the Z direction are the top surface 10a (the surface on the +Z side) and the bottom surface 10b (the surface on the -Z side). In the laminated electronic component 100, the surfaces on both sides of the laminate 10 in the Y direction are the side surface 10c (the surface on the +Y side) and the side surface 10d (the surface on the -Y side). External electrodes 14 are provided on the side surfaces 10c and 10d. The external electrodes 14 are electrodes for electrically connecting to an external circuit or external device. The external electrodes 14 are joined to external electrodes by a conductive bonding material such as solder. The external electrodes 14 function as an input terminal Tin, an output terminal Tout, and a ground terminal Tg. The external electrodes 14 include upper electrodes 14a provided on the upper surface 10a, lower electrodes 14b provided on the lower surface 10b, and side electrodes 14c provided on the side surfaces 10c and 10d. The external electrodes 14 may include only the side electrodes 14c, without including the upper and lower electrodes 14a and 14b. By providing the side electrodes 14c, when the laminated electronic component 100 is mounted on a mounting substrate, the state of bonding between the external electrodes 14 and the mounting substrate using a bonding material such as solder can be observed from above.

[0024] As shown in FIG. 2(b), the laminate 10 includes a plurality of dielectric layers 11a-11i stacked in the Z direction. Conductor patterns 12a-12i are provided on the top surfaces of the dielectric layers 11a-11i, respectively. Note that FIG. 2(b) also illustrates conductor patterns 12b, 12g, and 12h. Via wirings 13b-13h are provided penetrating the dielectric layers 11b-11h. The via wirings 15a and 15b each include via wirings 13b-13h that connect in the Z direction. The region of the dielectric layers 11a-11d is an inductor-forming region 18a where inductors L1 and L2 are formed. The region of the dielectric layers 11e-11i is a capacitor-forming region 18b where capacitors C1-C5 are formed. When the laminated electronic component 100 is mounted on a mounting board, if the inductors L1 and L2 are close to the mounting board, eddy current loss occurs in the inductors L1 and L2 due to the conductor patterns in the mounting board, resulting in a decrease in the Q value. Therefore, the inductor-forming region 18a is provided on the upper surface 10a side of the laminate 10, and the capacitor-forming region 18b is provided between the inductor-forming region 18a and the lower surface 10b of the laminate 10. This increases the distance between the inductors L1 and L2 and the mounting substrate, making it possible to suppress a decrease in the Q value of the inductors L1 and L2.

[0025] 3(a) to 4(d) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to Example 1. FIGS. 3(a) to 4(c) are plan views of the dielectric layers 11a to 11i, respectively. FIG. 4(d) is a plan view of the lower surface of the dielectric layer 11i seen through from above. In FIG. 4(c), the via wiring 13h is shown by a dashed line. FIG. 2(b) corresponds to the AA cross section of FIGS. 3(a) to 4(d).

[0026] As shown in Fig. 3(a), a conductor pattern 12a including a direction identification mark and a top surface electrode 14a are provided on the top surface 10a of the dielectric layer 11a. As shown in Fig. 3(b), a conductor pattern 12b including patterns L1a and L2a is provided on the top surface of the dielectric layer 11b. One end of the pattern L1a and one end of the pattern L2a are connected to via wiring 13b, which is part of via wirings 15a and 15b.

[0027] As shown in Fig. 3(c), a conductor pattern 12c including patterns L1b and L2b is provided on the upper surface of the dielectric layer 11c. As shown in Fig. 3(d), a conductor pattern 12d including patterns L1c and L2c is provided on the upper surface of the dielectric layer 11d. The patterns L1a to L1c are electrically connected by via wirings 13b and 13c to form inductor L1. The patterns L2a to L2c are electrically connected by via wirings 13b and 13c to form inductor L2.

[0028] As shown in Fig. 3(e), a conductor pattern 12e including patterns C2a and C4a is provided on the upper surface of the dielectric layer 11e. As shown in Fig. 3(f), a conductor pattern 12f including patterns C2b and C4b is provided on the upper surface of the dielectric layer 11f. The patterns C2a and C2b sandwiching the dielectric layer 11e form a capacitor C2. The patterns C4a and C4b sandwiching the dielectric layer 11e form a capacitor C4.

[0029] As shown in FIG. 4(a), a conductor pattern 12g including patterns C1a, C3a, and C5a is provided on the upper surface of the dielectric layer 11g. As shown in FIG. 4(b), a conductor pattern 12h including a pattern G is provided on the upper surface of the dielectric layer 11h. On the upper surface of the dielectric layer 11h, the pattern G is connected to the side electrode 14c that forms the ground terminal Tg. The pattern G includes patterns C1b, C3b, and C5b. The patterns C1a and C1b sandwiching the dielectric layer 11g form a capacitor C1. The patterns C3a and C3b sandwiching the dielectric layer 11g form a capacitor C3. The patterns C5a and C5b sandwiching the dielectric layer 11g form a capacitor C5.

[0030] As shown in Fig. 4(c), a conductor pattern 12i including patterns 16a and 16b is provided on the upper surface of the dielectric layer 11i. On the upper surface of the dielectric layer 11i, the pattern 16a is connected to the side electrode 14c that forms the input terminal Tin. As a result, the pattern 16a electrically connects the via wiring 15a and the input terminal Tin.11i On the upper surface of the dielectric layer 11i, the pattern 16b is connected to the side electrode 14c that forms the output terminal Tout. As a result, the pattern 16b electrically connects the via wiring 15b and the output terminal Tout. As shown in FIG. 4(d), a lower surface electrode 14b is provided on the lower surface 10b of the dielectric layer 11i. As described above, one end of the pattern L1a provided on the upper surface of the dielectric layer 11b is electrically connected to the input terminal Tin via the via wiring 15a and the pattern 16a. One end of the pattern L2a provided on the upper surface of the dielectric layer 11b is electrically connected to the output terminal Tout via the via wiring 15b and the pattern 16b.

[0031] The dielectric layers 11a-11i are made of a ceramic material and contain, for example, an oxide of Si, Ca, and Mg (e.g., diopside crystal CaMgSiO) as a main component. The main component of the dielectric layers 11a-11i may be an oxide other than Si, Ca, and / or Mg. Furthermore, the dielectric layers 11a-11i may contain, as an insulating material, an oxide of at least one of Ti, Zr, and Al.

[0032] The conductive patterns 12a-12i, via wirings 13b-13i, and external electrodes 14 are non-magnetic metal layers mainly composed of, for example, Ag, Pd, Pt, Cu, Ni, Au, an Au-Pd alloy, or an Ag-Pt alloy. In addition to the above metal materials, external electrodes 14 may also contain non-conductive materials such as TiO2, ZrO2, or Al2O3.

[0033] The laminate 10 is manufactured, for example, as follows: The dielectric layers 11a to 11i are produced, for example, using a doctor blade method. Via wiring 13b to 13i is formed penetrating the dielectric layers 11b to 11i. For example, via holes penetrating the dielectric layers 11a to 11i are formed by laser light irradiation. The via wiring 13b to 13i is formed in the via holes using a squeegee method or the like. Conductor patterns 12a to 12i are formed on the surfaces of the dielectric layers 11a to 11i. The conductor patterns 12a to 12i are formed, for example, by screen printing or transfer printing. The dielectric layers 11a to 11i are stacked to form the laminate 10. For example, heat pressing or an adhesive is used to stack the dielectric layers 11a to 11i. The laminate 10 is fired, for example, at 700°C or higher. As a result, the dielectric layers 11a to 11i become a sintered body. Side electrodes 14c are formed on the side surfaces of the laminate 10.

[0034] 5(a) and 5(b) are cross-sectional schematic diagrams of a laminated electronic component according to Comparative Example 1. As shown in FIG. 5(a), in Comparative Example 1, inductors L1 and L2 are formed by conductor patterns 12b in an inductor-forming region 18a. One end of inductor L1 is connected to the input terminal Tin in the inductor-forming region 18a, and one end of inductor L2 is connected to the output terminal Tout in the inductor-forming region 18a. Capacitor C is formed by patterns Ca and Cb sandwiching a dielectric layer 11e in the capacitor-forming region 18b. Pattern Ca is electrically connected to the other end of inductor L1 and the other end of inductor L2 via via wirings 13b to 13d. Pattern Cb is electrically connected to ground pattern G via via wirings 13f to 13g. As a result, inductors L1 and L2 are connected in series between the input terminal Tin and the output terminal Tout, and capacitor C is shunt-connected.

[0035] As shown in FIG. 5(b), when forming the laminate 10, the dielectric layers 11a to 11i may become misaligned. For example, the dielectric layer 11g is misaligned in the +X direction. This causes the via wirings 13f and 13g to become misaligned, as indicated by the dashed line 50, resulting in a disconnection between the via wirings 13f and 13g. Alternatively, the contact resistance between the via wirings 13f and 13g may increase. However, even if the continuity between the input terminal Tin and the output terminal Tout is inspected, it is not possible to inspect the misalignment of the dielectric layers 11c to 11i below the inductor-forming region 18a. Furthermore, a continuity inspection between the input terminal Tin or the output terminal Tout and the ground terminal Tg cannot be performed due to the presence of the capacitor C.

[0036] 6(a) and 6(b) are cross-sectional schematic diagrams of a laminated electronic component according to Example 1. As shown in FIG. 6(a), in Example 1, one end of inductor L1 is electrically connected to the input terminal Tin via via wiring 15a and pattern 16a, and one end of inductor L2 is electrically connected to the output terminal Tout via via wiring 15b and pattern 16b. In this manner, inductors L1 and L2 are not connected to the input terminal Tin and the output terminal Tout in inductor-forming region 18a. Inductors L1 and L2 are electrically connected to the input terminal Tin and the output terminal Tout via patterns 16a and 16b below capacitor-forming region 18b.

[0037] As shown in FIG. 6(b), when the dielectric layer 11g is displaced in the +X direction, the via wiring 13g forming the via wirings 15a and 15b is displaced in the +X direction, as indicated by dashed lines 50a and 50b. When the continuity between the input terminal Tin and the output terminal Tout is inspected, a disconnection or high resistance occurs between the input terminal Tin and the output terminal Tout. This allows inspection of misalignment of the dielectric layers 11b to 11h in the inductor-forming region 18a and the capacitor-forming region 18b. Furthermore, defects in the via wirings 13b to 13h can be inspected. The continuity inspection may be performed using either a direct current or an alternating current to inspect the continuity between the input terminal Tin and the output terminal Tout.

[0038] [Modification 1 of Example 1] 7(a) to 7(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to Modification 1 of Example 1. Dielectric layers 11a to 11g are the same as those in FIGS. 3(a) to 4(a) of Example 1. FIGS. 7(a) and 7(b) are plan views of dielectric layers 11h and 11i, respectively. FIG. 7(c) is a plan view of the lower surface of dielectric layer 11i seen from above. In FIG. 7(c), via wiring 13i is indicated by a dashed line.

[0039] As shown in Fig. 7(a), the configuration of the conductor pattern 12h and via wiring 13h on the dielectric layer 11h is the same as that in Fig. 4(b). As shown in Fig. 7(b), the conductor pattern 12i is not provided on the dielectric layer 11i. Via wiring 13i is provided to penetrate the dielectric layer 11i. Via wiring 15a and 15b are formed by connecting the via wirings 13b to 13i, respectively.

[0040] As shown in FIG. 7(c), the lower surface electrode 14b provided on the lower surface 10b of the dielectric layer 11i includes patterns 17a and 17b. The via wiring 15a is electrically connected to the input terminal Tin through the pattern 17a. The via wiring 15b is electrically connected to the output terminal Tout through the pattern 17b. The other configurations are the same as those in the first embodiment, and therefore a description thereof will be omitted. In the first modification of the first embodiment, a continuity test can be performed on the dielectric layer 11i in addition to the dielectric layers 11b to 11h.

[0041] [Modification 2 of Example 1] 8(a) to 8(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to Modification 2 of Example 1. Dielectric layers 11a to 11g are the same as those in FIGS. 3(a) to 4(a) of Example 1. FIGS. 8(a) and 8(b) are plan views illustrating dielectric layers 11h and 11i, respectively. FIG. 8(c) is a plan view of the lower surface of dielectric layer 11i seen through from above. In FIG. 8(c), via wiring 13i is illustrated by a dashed line.

[0042] As shown in Fig. 8(a), the configuration of the conductor pattern 12h and via wiring 13h on the dielectric layer 11h is the same as that shown in Fig. 4(b). As shown in Fig. 8(b), a conductor pattern 12i including patterns 16a and 16b is provided on the dielectric layer 11i. The via wiring 15a and 15b are connected to the patterns 16a and 16b, respectively. The patterns 16a and 16b are connected to the input terminal Tin and the output terminal Tout, respectively.

[0043] As shown in FIG. 8(c), via wirings 15a and 15b are connected to patterns 17a and 17b, respectively. Patterns 17a and 17b are connected to the input terminal Tin and the output terminal Tout, respectively. The other configurations are the same as those in Example 1, and therefore description thereof will be omitted. In Modification 2 of Example 1, patterns 16a and 17a are connected in parallel between the via wiring 15a and the input terminal Tin, and patterns 16b and 17b are connected in parallel between the via wiring 15b and the output terminal Tout. This reduces the parasitic inductance between the via wiring 15a and the input terminal Tin, and reduces the parasitic inductance between the via wiring 15b and the output terminal Tout.

[0044] [Modification 3 of Example 1] 9(a) to 10(d) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to Modification 3 of Example 1. 9(a) to 10(d) are plan views of the dielectric layers 11a to 11i, respectively. 10(d) is a plan view of the lower surface of the dielectric layer 11i seen through from above. In FIG. 10(d), the via wiring 13i is indicated by a dashed line.

[0045] As shown in FIG. 9(a), the dielectric layer 11a is the same as FIG. 3(a) of Example 1. As shown in FIG. 9(b), the via wiring 15a is not provided, and one end of the pattern L1a is connected to the input terminal Tin. As shown in FIGS. 9(c) to 9(e), the dielectric layer 11a is the same as FIG. 3(c) and FIG. 3(e) of Example 1, except that the via wiring 15a is not provided. As shown in FIG. 9(f), the via wiring 15a is not provided, and the pattern C2b is connected to the input terminal Tin on the upper surface of the dielectric layer 11f. As shown in FIG. 10(a), the via wiring 15a is not provided, and the pattern C1a is connected to the input terminal Tin on the upper surface of the dielectric layer 11g. As shown in FIGS. 10(b) and 10(c), the dielectric layer 11a is the same as FIG. 7(b) and FIG. 7(c) of Variation 1 of Example 1, except that the via wiring 15a is not provided. As shown in FIG. 10(d), the via wiring 15b is connected to the pattern 17b, and the pattern 17b is connected to the output terminal Tout. The other configurations are the same as those of the first modification of the first embodiment, and therefore description thereof will be omitted. As in the third modification of the first embodiment, either one of the via wirings 15a and 15b may not be provided.

[0046] [Modification 4 of Example 1] 11(a) to 11(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to Modification 4 of Example 1. Figures 11(a) to 11(c) are plan views of dielectric layers 11d to 11f, respectively. Dielectric layers 11a to 11c and 11g to 11i are the same as those in Example 1 or Modification 1 of Example 1.

[0047] As shown in Fig. 11(a), the width W3a of the via wiring 13d1 electrically connected between patterns L1c and L2c is larger than the width W3 of the via wiring 13d in the via wirings 15a and 15b. As shown in Fig. 11(b), the width W3a of the via wiring 13e1 provided between patterns C2a and C4a is larger than the width W3 of the via wiring 13e in the via wirings 15a and 15b. As shown in Fig. 11(c), the width W3a of the via wiring 13f1 connected to the via wiring 13e1 is larger than the width W3 of the via wiring 13f in the via wirings 15a and 15b. The other configurations are the same as those of Example 1 or Modification 1 of Example 1, and therefore description thereof will be omitted.

[0048] By inspecting the continuity between the input terminal Tin and the output terminal Tout, misalignment of the dielectric layers 11b to 11i can be detected. Furthermore, it is possible to inspect the via wirings 15a and 15b for continuity defects due to causes other than misalignment. However, it is difficult to inspect the via wirings 13d1 to 13f1 other than the via wirings 15a and 15b for continuity defects due to causes other than misalignment. Therefore, the width W3a of the via wirings 13d1 to 13f1 other than the via wirings 15a and 15b is made larger than the width W3 of the via wirings 15a and 15b. This makes the via wirings 13d1 to 13f1 less likely to break or become highly resistant. Therefore, even if it is not possible to inspect the via wirings 13d1 to 13f1 for continuity defects due to causes other than misalignment, it is possible to prevent the via wirings 13d1 to 13f1 from becoming defective.

[0049] According to Example 1 and its Modifications 1 to 4, a side electrode 14c (second side electrode) corresponding to the input terminal Tin and a side electrode 14c (first side electrode) corresponding to the output terminal Tout are provided on the side surface 10c of the laminate 10. Inductors L1 and L2 are provided within the laminate 10. Capacitors C1 to C5 are provided between the inductors L1 and L2 and the bottom surface 10b (first surface). A via wiring 15b penetrates the dielectric layers 11b to 11h (or 11i) between the dielectric layers 11b to 11h (or 11i) and electrically connects one end of the inductor L2 to the output terminal Tout. Here, the dielectric layer 11b (first dielectric layer) is in contact with the inductors L1 and L2. The dielectric layer 11h (or 11i) (second dielectric layer) is located closer to the bottom surface 10b than at least a portion of the capacitors C1 to C5. The input terminal Tin and the output terminal Tout are electrically connected via the inductor L2 and the via wiring 15b. This allows inspection of defects in the dielectric layers 11b to 11h by inspecting the continuity between the input terminal Tin and the output terminal Tout, as shown in FIG. 6(b).

[0050] The inductor L2 is not electrically connected to the output terminal Tout on the upper surface 10a (second surface) side of the capacitors C1 to C5, so that defects in the dielectric layers 11b to 11h can be inspected by inspecting the continuity between the input terminal Tin and the output terminal Tout.

[0051] As in the first embodiment and its first modification, another via wiring 15a passes through the dielectric layers 11b to 11h (or 11b to 11i) and electrically connects the other end of the inductor L1 to the input terminal Tin. This allows inspection of electrical continuity in the multiple via wirings 15a and 15b, compared to when the via wiring 15a is not provided as in the second modification of the first embodiment, and therefore allows inspection of defects in the dielectric layers 11b to 11h with high accuracy.

[0052] 11(a) to 11(c) of Modification 4 of Example 1, the planar area of ​​via wirings 13d1 to 13f1 that penetrate at least one dielectric layer 11d to 11f other than via wirings 15a and 15b electrically connected between the input terminal Tin and the output terminal Tout is larger than the planar area of ​​via wirings 15a and 15b. This makes it possible to suppress defects in via wirings 13d1 to 13f1 that cannot be inspected for conduction defects other than misalignment of dielectric layers 11b to 11h. The planar area of ​​via wirings 13d1 to 13f1 is preferably 1.5 times or more, more preferably 2 times or more, the planar area of ​​via wirings 15a and 15b.

[0053] As shown in Fig. 4(c) of the first embodiment, a pattern 16b is provided between the adjacent dielectric layers 11h and 11i between at least a portion of the capacitors C1 to C5 and the lower surface 10b, and electrically connects the via wiring 15b and the output terminal Tout. This allows the via wiring 15b to be electrically connected to the output terminal Tout. As in the first modification of the first embodiment, the lower surface electrode 14b does not need to be provided.

[0054] 7(c) of the first modification of the first embodiment, the lower surface electrode 14b is provided on the lower surface 10b and connected to the side surface electrode 14c. The via wiring 15b is connected to the pattern 17b of the lower surface electrode 14b. This allows the via wiring 15b to be electrically connected to the output terminal Tout.

[0055] One end of each of the capacitors C1, C3, and C5 is connected to a path between the input terminal Tin and the output terminal Tout, and the other end is connected to a ground terminal Tg (ground electrode) provided on the surface of the laminate 10. By shunt-connecting the capacitors C1, C3, and C5, an LPF 20 including the inductors L1 and L2 and the capacitors C1 to C5 can be formed.

[0056] In the first embodiment and its modified examples, the first and second side electrodes are the output terminal Tout and the input terminal Tin, respectively, but the side electrodes may be terminals other than the output terminal Tout and the input terminal Tin. Although the first and second side electrodes are provided on the same side surface 10c, the first side surface electrode may be provided on the side surface 10c, and the second side surface electrode may be provided on the side surface 10d. The cutoff frequency of the LPF 20 is, for example, 0.5 GHz to 5 GHz. Although the laminated electronic component includes the LPF 20, the laminated electronic component may be a filter other than a low-pass filter. Furthermore, the laminated electronic component may include a filter other than a low-pass filter.

[0057] [simulation] The Q value of the inductor was simulated using electromagnetic field analysis. FIG. 12 is a perspective view of the simulated structure. FIG. 13(a) is a side view of the vicinity of the via wiring 15b, and FIG. 13(b) is a plan view of the vicinity of the via wiring 15b. As shown in FIGS. 12 to 13(b), an inductor L consisting of patterns La and Lb is provided within the laminate 10. An external electrode 14 is provided from the upper surface 10a of the laminate 10, passing through the side surface 10c and extending to the lower surface 10b. The external electrode 14 includes an upper surface electrode 14a provided on the upper surface 10a, a lower surface electrode 14b provided on the lower surface 10b, and a side surface electrode 14c provided on the side surface 10c. One end of the inductor L is electrically connected to the lower surface electrode 14b via the via wiring 15b. The other end of the inductor L is connected to the via wiring 15a.

[0058] The simulation conditions are as follows: Laminate 10 Width Wx1:2.5mm Width Wy1: 2.0 mm Thickness T1: 0.6 mm Dielectric constant: 10 Inductor L Inner diameter Wx2: 700 μm Inner diameter Wy2: 600 μm Width W2: 60 μm Thickness T2: 10 μm Q value simulated frequency: 3.3GHz Width W1 of external electrode 14: 400 μm Width of via wiring 15b: 50 μm The center of the side electrode 14c in the X direction and the center of the via wiring 15b in the X direction are substantially aligned. 15b The distance between the upper surface 10a and the inductor L is D1, the width of the upper surface electrode 14a in the Y direction is D2, and the distance between the upper surface 10a and the inductor L is D3.

[0059] 14(a) to 14(c) show the Q values ​​of the inductor for D1 to D3, respectively, in a simulation. The dots represent simulated values. The straight line in FIG. 14(a) is an approximation of the dots. In FIG. 14(a), D2 is fixed at 0 mm (i.e., no top electrode 14a is provided), D3 is fixed at 0.035 mm, and D1 is varied to simulate the Q value of the inductor L. Sample A is a sample with a side electrode 14c provided on the side surface 10c, while Sample B is a sample with a bottom electrode 14b only on the bottom surface 10b, without a side electrode 14c provided on the side surface 10c. In Sample B, the Q value improves as D1 decreases. This is because shortening D1 increases the distance between the via wiring 15b and the winding portion of the inductor L. In Sample A, when D1 is 0.05 mm or greater, the Q value improves as D1 decreases. This is similar to Sample B. When D1 is 0.05 mm or less, the Q value decreases as D1 becomes shorter. This is thought to be because the via wiring 15b approaches the side electrode 14c. Thus, the distance D1 between the via wiring 15b and the side electrode 14c is preferably 50 μm or more. Considering manufacturing errors, D1 is more preferably 75 μm or more, and even more preferably 100 μm or more.

[0060] In FIG. 14(b), D1 is fixed at 0.1 mm, D3 is fixed at 0.035 mm, and D2 is varied to simulate the Q value of inductor L. When D2 is 0.1 mm or less, the Q value is almost constant. When D2 is 0.1 mm or more, the Q value decreases and the variation in the Q value increases. When D2 is 0.1 mm or more, the top surface electrode 14a overlaps with the inductor L and via wiring 15b in a planar view. This is thought to be the reason for the decrease in the Q value. It is preferable that the top surface electrode 14a does not overlap with the inductor L and via wiring 15b in a planar view.

[0061] In Figure 14(c), D1 is fixed at 0.1 mm, D2 is fixed at 0.2 mm, and D3 is changed to simulate the Q value of inductor L. When D3 is 0.05 mm or more, the Q value is almost constant. When D3 is 0.05 mm or less, the Q value decreases as D3 becomes shorter. This is because inductor L approaches top electrode 14a.

[0062] As described above, it is preferable that the top surface electrode 14a does not overlap with the inductor L and the via wiring 15b in a plan view. If the top surface electrode 14a overlaps with the inductor L and the via wiring 15b, it is preferable that the distance D3 between the inductor L and the top surface electrode 14a be 50 μm or more. Considering manufacturing errors, D3 is more preferably 75 μm or more, and even more preferably 100 μm or more.

[0063] [Modification 5 of Example 1] 15(a) to 16(d) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to Variation 5 of Example 1. FIGS. 15(a) to 16(c) are plan views of the dielectric layers 11a to 11i, respectively. FIG. 16(d) is a plan view of the lower surface of the dielectric layer 11i seen through from above. In FIG. 16(d), the via wiring 13i is shown by a dashed line.

[0064] As shown in FIG. 15(a), the dielectric layer 11a is the same as that shown in FIG. 3(a) of the first embodiment. As shown in FIG. 15(b), the via wiring 15a is provided between the input terminal Tin and the ground terminal Tg in the X direction, and the via wiring 15b is provided between the output terminal Tout and the ground terminal Tg in the X direction. The rest of the configuration is the same as that shown in FIG. 3(b). In FIGS. 15(c) to 16(b), the shapes of the conductor patterns 12c to 12h differ from those shown in FIGS. 3(c) to 4(b) due to the positions of the via wirings 15a and 15b. As shown in FIG. 16(c), the positions of the via wirings 15a and 15b differ from those shown in FIG. 7(b). As shown in FIG. 16(d), the pattern 17a extends from the input terminal Tin to the +X side and is connected to the via wiring 15a. The pattern 17b extends from the output terminal Tout to the -X side and is connected to the via wiring 15b. The other configurations are the same as those of the first modification of the first embodiment, and therefore a description thereof will be omitted.

[0065] As shown in the simulation, the Q value of the inductor increases as the distance D3 between the via wirings 15a and 15b and the input terminal Tin and the output terminal Tout increases. However, increasing D3 increases the size of the laminated electronic component. Therefore, in Modification 5 of Example 1, the via wirings 15a and 15b are designed not to overlap with the input terminal Tin and the output terminal Tout when viewed from the Y direction (thickness direction of the side electrode). As a result, as shown in FIG. 16(c), even if the distance D3 between the via wirings 15a and 15b and the side surface 10c is shortened, the distance D4 between the via wirings 15a and 15b and the input terminal Tin and the output terminal Tout can be increased to, for example, 50 μm or more. This allows the laminated electronic component to be miniaturized and the Q values ​​of the inductors L1 and L2 to be improved. When the via wirings 15a and 15b approach the ground terminal Tg, the Q value decreases due to eddy current loss. The decrease in the Q value due to the via wirings 15a and 15b being closer to the ground terminal Tg is greater than the decrease in the Q value due to the via wirings 15a and 15b being closer to the input terminal Tin and the output terminal Tout. Therefore, it is preferable that the distance D4 be shorter than the distance D5 between the via wirings 15a and 15b and the ground terminal Tg. It is preferable that the distance D4 be equal to or smaller than half the distance D5.

[0066] [Modification 6 of Example 1] 17(a) to 17(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to Variation 6 of Example 1. Dielectric layers 11a to 11g are the same as those in FIGS. 15(a) to 16(a) of Variation 5 of Example 1. FIGS. 17(a) and 17(b) are plan views of dielectric layers 11h and 11i, respectively. FIG. 17(c) is a plan view of the lower surface of dielectric layer 11i seen from above. In FIG. 17(b), via wiring 13h is indicated by a dashed line.

[0067] As shown in FIG. 17(a), the configuration of the conductor pattern 12h and via wiring 13h on the dielectric layer 11h is the same as that shown in FIG. 16(b). As shown in FIG. 17(b), a conductor pattern 12i including patterns 16a and 16b is provided on the dielectric layer 11i. The pattern 16a extends from the input terminal Tin to the +X side and is connected to the via wiring 15a. The pattern 16b extends from the output terminal Tout to the −X side and is connected to the via wiring 15b. As shown in FIG. 17(c), no via wiring 13i penetrating the dielectric layer 11i is provided. The other configurations are the same as those of the fifth modification of the first embodiment, and therefore a description thereof will be omitted. As in the sixth modification of the first embodiment, the via wirings 15a and 15b do not have to be provided in the dielectric layer 11i.

[0068] [Seventh Modification of the First Embodiment] 18(a) to 18(c) are plan views showing the dielectric layers in the laminate of the laminated electronic component according to Variation 7 of Example 1. Dielectric layers 11a to 11g are the same as those in FIGS. 15(a) to 16(a) of Variation 5 of Example 1. FIGS. 18(a) and 18(b) are plan views of dielectric layers 11h and 11i, respectively. FIG. 18(c) is a plan view of the lower surface of dielectric layer 11i seen through from above. In FIGS. 18(b) and 18(c), via wirings 13h and 13i are shown by dashed lines, respectively.

[0069] As shown in FIG. 18(a), the configuration of the conductor pattern 12h and the via wiring 13h on the dielectric layer 11h is the same as that shown in FIG. 16(b). As shown in FIG. 18(b), the via wiring 13h is arranged so as not to overlap the input terminal Tin and the output terminal Tout when viewed from the Y direction, and the via wiring 13i is arranged so as to overlap the input terminal Tin and the output terminal Tout. The patterns 16a and 16b are not connected to the input terminal Tin and the output terminal Tout, but electrically connect the via wirings 13h and 13i. As shown in FIG. 18(c), the configuration of the lower surface electrode 14b and the via wiring 13i is the same as that shown in FIG. 7(c) of the first modification of the first embodiment. The other configurations are the same as those of the sixth modification of the first embodiment, and therefore a description thereof will be omitted. As in the seventh modification of the first embodiment, the planar positions of the via wirings 13h and 13i among the via wirings 15a (and 15b) may be different, and the pattern 16a (and 16b) may electrically connect the via wirings 13h and 13i. As in the seventh modification of the first embodiment, it is sufficient that at least a portion of the via wirings 15a and 15b does not overlap with the input terminal Tin and the output terminal Tout when viewed in the Y direction. This allows the laminated electronic component to be miniaturized and the Q values ​​of the inductors L1 and L2 to be improved. [Example]

[0070] Example 2 is an example of a multiplexer and a communication module in which Example 1 and its modified examples are used. Fig. 19 is a circuit diagram of a front-end circuit in which the communication module according to Example 2 is used. As shown in Fig. 19, the front-end circuit includes a triplexer 30, a switch 34, a duplexer 37, a power amplifier (PA) 38, and a low-noise amplifier (LNA) 39. The triplexer 30 includes a high-pass filter (HPF) 31, a band-pass filter (BPF) 32, and a low-pass filter (LPF) 33.

[0071] An antenna 40 is connected to a common terminal Ta. One ends of the HPF 31, BPF 32, and LPF 33 are commonly connected to the common terminal Ta. A switch 34 is connected to the other ends of the HPF 31, BPF 32, and LPF 33. The HPF 31 passes high-frequency signals in the high band and suppresses signals of other frequencies. The BPF 32 passes high-frequency signals in the middle band, which have frequencies lower than the high band, and suppresses signals of other frequencies. The LPF 33 passes high-frequency signals in the low band, which have frequencies lower than the middle band, and suppresses signals of other frequencies.

[0072] A common node Na of the multiple duplexers 37 is connected to the switch 34. The switch 34 selects one of the multiple duplexers 37 and connects it to the other ends of the HPF 31, BPF 32, and LPF 33. The duplexer 37 has a transmit filter 35 which is a BPF and a receive filter 36 which is also a BPF. The transmit filter 35 and the receive filter 36 are connected to a PA 38 and an LNA 39, respectively.

[0073] A transmission signal input to a transmission terminal Tx is amplified by a PA 38. A transmission filter 35 outputs high-frequency signals in the transmission band among the amplified signals to a common node Na and suppresses signals of other frequencies. The filtered transmission signal passes through a switch 34 and the HPF 31, BPF 32, or LPF 33, and is output from an antenna 40.

[0074] A received signal input to the antenna 40 passes through the HPF 31, BPF 32 or LPF 33, and switch 34. The receive filter 36 passes signals in the receive band among the high-frequency signals input to the common node Na and suppresses signals of other frequencies. The filtered received signal is amplified by the LNA 39 and output to the receive terminal Rx.

[0075] The filters of the first embodiment and its modifications can be used for the LPF 33 of the triplexer 30. The laminated electronic component may include at least one of the BPF 32 and the HPF 31 in addition to the LPF 33. Although the triplexer 30 has been described as an example of a multiplexer, the multiplexer may also be a diplexer, a duplexer, or a quadplexer.

[0076] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0077] 10 Laminate 10a top surface 10b Bottom side 10c, 10d side 11a-11i Dielectric layer 12a-12i Conductor pattern 13a-13i, 15a, 15b Via wiring 14 External electrode 14a Top electrode 14b Bottom electrode 14c side electrode 16a, 16b, 17a, 17b patterns 20 LPF

Claims

1. a laminate in which a plurality of dielectric layers are laminated in a lamination direction, the laminate having a first surface and a second surface provided on both sides in the lamination direction; a first side electrode provided on a side surface of the laminate; an inductor provided within the laminate; a capacitor disposed between the inductor and the first surface; a via wiring that penetrates through the dielectric layers from a first dielectric layer in contact with the inductor to a second dielectric layer located closer to the first surface than all of the capacitors, thereby penetrating the dielectric layers of the entire capacitor formation region in which all of the capacitors are provided, and electrically connects one end of the inductor and the first side electrode; a second side electrode that is electrically connected to the first side electrode through the inductor and the via wiring, that is provided on a side surface of the laminate, and that can test for resistance defects based on the electrical connection between the second side electrode and the first side electrode; A laminated electronic component comprising:

2. 2. The laminated electronic component according to claim 1, wherein the inductor is not electrically connected to the first side electrode on the second surface side of the capacitor.

3. 3. The laminated electronic component according to claim 1, further comprising another via wiring that penetrates the dielectric layers from the first dielectric layer to the second dielectric layer and electrically connects the other end of the inductor to the second side electrode.

4. A laminated electronic component described in any one of claims 1 to 3, comprising a conductive pattern provided between adjacent dielectric layers between the capacitor located closest to the first surface and the first surface, electrically connecting the via wiring and the first side electrode.

5. a bottom electrode provided on the first surface and connected to the first side electrode; The laminated electronic component according to claim 1 , wherein the via wiring is directly connected to the lower surface electrode.

6. A laminated electronic component described in any one of claims 1 to 5, wherein the planar area of ​​a via wiring that penetrates at least one of the plurality of dielectric layers other than the via wiring electrically connected between the first side electrode and the second side electrode is larger than the planar area of ​​the via wiring electrically connected between the first side electrode and the second side electrode.

7. 7. The laminated electronic component according to claim 1, wherein one end of the capacitor is connected to a path between the first side electrode and the second side electrode, and the other end is connected to a ground electrode provided on the surface of the laminate.

8. The laminated electronic component according to claim 1 , wherein at least a portion of the via wiring does not overlap with the first side surface electrode in the thickness direction of the first side surface electrode.

9. The laminated electronic component according to claim 1 , wherein the distance between the via wiring and the first side electrode is 50 μm or more.

10. The laminated electronic component according to claim 1 , further comprising a low-pass filter including the inductor and the capacitor.

11. The laminated electronic component according to claim 10 , further comprising a multiplexer including the low-pass filter.

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