Class d amplifier circuit

Abstract

To provide a class D amplifier circuit that outputs an output signal with desired characteristics even if a voltage of a signal input to a capacitor of a low-pass filter changes.SOLUTION: A class D amplifier circuit includes: a PWM modulation circuit; a first driving circuit connected to the PWM modulation circuit; a second driving circuit connected to the PWM modulation circuit; and a differential signal filter circuit 38 connected to the first driving circuit and the second driving circuit. The differential signal filter circuit includes a first inductor 40a, a second inductor 40b, a first capacitor 1a, a second capacitor 1b, a first input terminal 50a, a second input terminal 50b, a first output terminal 56a, a second output terminal 56b, and a reference potential terminal. The first capacitor and the second capacitor each include dielectric and electrodes sandwiching the dielectric. The first input terminal is connected to the first driving circuit, the second input terminal is connected to the second driving circuit, the reference potential terminal is connected to a reference potential, and the first output terminal and the second output terminal are connected to a load circuit 62.SELECTED DRAWING: Figure 15

Description

[Technical Field]

[0001] The present invention relates to a class D amplifier circuit. [Background technology]

[0002] Class D amplifier circuits are known that amplify audio signals and output them to a load such as a speaker. For example, Patent Document 1 describes a class D amplifier circuit that uses PWM modulation. The class D amplifier circuit includes a PWM modulation circuit, a drive circuit, and a low-pass filter. The PWM modulation circuit outputs a PWM modulated signal. The drive circuit amplifies the PWM modulated signal and outputs the amplified PWM modulated signal. The low-pass filter circuit outputs an analog audio signal by removing high-frequency components from the amplified PWM modulated signal. The low-pass filter circuit is composed of an inductor and a capacitor. The output analog audio signal is supplied to a load. If the analog signal represents audio and the load is a speaker, the load generates the audio represented by the analog signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-180695 Summary of the Invention [Problem to be solved by the invention]

[0004] The capacitance of the capacitor that constitutes the low-pass filter circuit of a class-D amplifier circuit varies depending on the voltage applied to the capacitor. If the capacitance of the capacitor varies depending on the applied voltage, the cutoff frequency of the low-pass filter will vary depending on the pulse. If the cutoff frequency of the low-pass filter varies, the audio signal output to the output terminal may no longer have the desired characteristics. Therefore, an object of the present invention is to provide a class D amplifier circuit that can output an output signal with desired characteristics even if the voltage of the signal input to the capacitor of the low-pass filter changes. [Means for solving the problem]

[0005] A class D amplifier circuit of the present invention is a class D amplifier circuit comprising a PWM modulation circuit, a drive circuit connected to the PWM modulation circuit, and a low-pass filter circuit connected to the drive circuit, wherein the low-pass filter circuit comprises an inductor, a first capacitor, and a second capacitor, and the first capacitor and the second capacitor each comprise a dielectric and electrodes sandwiching the dielectric, the low-pass filter circuit comprises an input terminal, a first potential terminal, a second potential terminal, and an output terminal, wherein the input terminal is connected to the drive circuit, the first potential terminal is connected to a first potential, the second potential terminal is connected to a second potential lower than the first potential, the output terminal is connected to a load circuit, one external electrode of the first capacitor is connected to the first potential terminal, one external electrode of the second capacitor is connected to the second potential terminal, the other external electrode of the first capacitor and the other external electrode of the second capacitor are connected to the output terminal, one external electrode of the inductor is connected to the input terminal, and the other external electrode of the inductor is connected to the output terminal. [Effects of the Invention]

[0006] According to the present invention, it is possible to provide a class D amplifier circuit that can output an output signal with desired characteristics even if the voltage of the signal input to the capacitor of the low-pass filter changes. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating a class D amplifier circuit of the present invention. [Figure 2] 1A and 1B are diagrams showing the terminals of the inductor and capacitor of the present invention; [Figure 3] FIG. 10 is a diagram showing the relationship between the voltage applied to a capacitor and the capacitance of the capacitor. [Figure 4] 10A and 10B are diagrams illustrating a potential difference and the like when a signal is input to the low-pass filter circuit of the present invention. [Figure 5] FIG. 1 is a diagram illustrating a conventional class D amplifier circuit. [Figure 6] FIG. 1 is a diagram illustrating a case where a signal is input to a conventional low-pass filter circuit. [Figure 7] 1 is a perspective view showing a four-terminal multilayer ceramic capacitor according to the present invention; [Figure 8] 1 is a diagram showing at least a portion of an internal electrode of the present invention; [Figure 9] FIG. 1 is a diagram showing a circuit configuration of a low-pass filter circuit according to the present invention. [Figure 10] FIG. 8 is a cross-sectional view taken along line II in FIG. 7. [Figure 11] FIG. 8 is a cross-sectional view taken along line II-II in FIG. 7. [Figure 12] 8 is a cross-sectional view taken along line III-III in FIG. 7, showing the planar structure of a first internal electrode 10a. [Figure 13] 8 is a cross-sectional view taken along line III-III in FIG. 7, showing the planar structure of a second internal electrode 10b. [Figure 14] 8 is a cross-sectional view taken along line III-III in FIG. 7, showing the planar structure of a third internal electrode 10c. [Figure 15] FIG. 10 is a diagram illustrating a class D amplifier circuit according to another embodiment of the present invention. [Figure 16] 10 is a diagram showing a potential difference and the like when a signal is input to a differential signal filter circuit according to another embodiment of the present invention. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0008] (Embodiment 1) DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a diagram showing an overview of a class D amplifier circuit 30 of the present invention.

[0009] (Overview of Class D amplifier circuit) The class-D amplifier circuit 30 of this embodiment includes a PWM modulation circuit 32, a drive circuit 34 connected to the PWM modulation circuit 32, and a low-pass filter circuit 36 ​​connected to the drive circuit 34. As described above, the PWM modulation circuit 32 outputs a PWM modulated signal. The drive circuit 34 amplifies the PWM modulated signal and outputs the amplified PWM modulated signal. The low-pass filter circuit 36 ​​removes high-frequency components from the amplified PWM modulated signal.

[0010] (Outline of low-pass filter circuit) The low-pass filter circuit 36 ​​includes an inductor 40 and a capacitor 1. A load circuit 62 is connected to the low-pass filter circuit 36. The signal output from the low-pass filter circuit 36 ​​is input to the load circuit 62.

[0011] More specifically, the low-pass filter circuit 36 ​​includes an inductor 40 and at least two capacitors 1. The two capacitors 1 are designated as a first capacitor 1a and a second capacitor 1b. In FIG. 1, the first capacitor 1a is designated as C1, and the second capacitor 1b is designated as C2.

[0012] Each capacitor 1 includes a dielectric and electrodes sandwiching the dielectric, that is, the capacitor 1 can be a capacitor that forms a lumped constant circuit, such as a multilayer ceramic capacitor or a film capacitor.

[0013] (Low-pass filter circuit terminal) The low-pass filter circuit 36 ​​has four external terminals: an input terminal 50, a first potential terminal 52a, a second potential terminal 52b, and an output terminal 56. The input terminal 50 is connected to the drive circuit 34. The first potential terminal 52a is connected to a first potential. The second potential terminal is connected to a second potential. The output terminal 56 is connected to a load circuit 62. Here, the first potential may be, for example, a power supply voltage potential, and the second potential may be, for example, a GND (ground) potential.

[0014] (Connection in a low-pass filter circuit) The connection of terminals inside the low-pass filter circuit 36 ​​will be described with reference to FIG. 2. FIG. 2 is a diagram showing the terminals of the inductor 40 and the capacitor 1. The inductor 40 has two inductor external electrodes 42. One of the inductor external electrodes 42 is referred to as a first inductor external electrode 42a, and the other is referred to as a second inductor external electrode 42b. The first inductor external electrode 42a is connected to an input terminal 50. The second inductor external electrode 42b is connected to an output terminal 56.

[0015] The connections of the capacitor 1 will now be described. The first capacitor 1a and the second capacitor 1b each have two external electrodes 20. One of the external electrodes 20 of the first capacitor 1a is referred to as external electrode (A) 20a, and the other is referred to as external electrode (B) 20b. The external electrode (A) 20a is connected to the first potential terminal 52a, and the external electrode (B) 20b is connected to the output terminal 56.

[0016] Next, the second capacitor 1b will be described. One of the external electrodes 20 of the second capacitor 1b is referred to as external electrode (D) 20d, and the other is referred to as external electrode (C) 20c. The external electrode (D) 20d is connected to the second potential terminal 52b, and the external electrode (C) 20c is connected to the output terminal 56.

[0017] (Voltage and capacity) The class D amplifier circuit 30 of this embodiment has the above-described configuration, and is therefore capable of outputting an output signal with desired characteristics even when the voltage of the signal input to the capacitor 1 included in the low-pass filter circuit 36 ​​changes. The following describes each of these points in order. FIG. 3 is a diagram showing the relationship between the voltage applied to a capacitor and the capacitance of the capacitor. The X-axis of FIG. 3 represents the voltage applied to the capacitor. The Y-axis of FIG. 3 represents the capacitance of the capacitor. A capacitor consisting of a dielectric and electrodes sandwiching the dielectric changes its capacitance depending on the applied voltage. As indicated by point P2 in FIG. 3, when the voltage applied to the capacitor is relatively large, the capacitance of the capacitor decreases. In contrast, as indicated by point P1 in FIG. 3, when the voltage applied to the capacitor is relatively small, the capacitance of the capacitor increases. In this way, the capacitance of a capacitor changes depending on the voltage applied to the capacitor.

[0018] In a class-D amplifier circuit in which a capacitor serving as a lumped constant circuit is provided in a low-pass filter circuit, if the capacitance of the capacitor fluctuates according to the input pulse voltage, it becomes difficult to obtain an output signal with the desired characteristics, because the cutoff frequency of the low-pass filter circuit fluctuates according to the input pulse voltage.

[0019] In this regard, the class D amplifier circuit 30 of this embodiment is capable of outputting an output signal with desired characteristics even if the voltage of the signal input to the capacitor 1 of the low-pass filter circuit 36 ​​changes. This will be explained below. Figure 4 is a diagram showing the voltages applied to each capacitor 1 when a pulse is input to the class D amplifier circuit 30 of this embodiment. The X axis of Figure 4 represents time. The Y axis of Figure 4 represents potential.

[0020] When the pulse input to the low-pass filter circuit 36 ​​is Hi, the voltage applied to C2, the second capacitor 1b, increases (d2 in FIG. 4). Conversely, the voltage applied to C1, the first capacitor 1a, decreases (d1 in FIG. 4). Therefore, the capacitance reduction of C2 is greater than the capacitance reduction of C1. Conversely, when the pulse input to capacitor 1 is L, the voltage applied to C1, the first capacitor 1a, increases (d3 in Figure 4). Conversely, the voltage applied to C2, the second capacitor 1b, decreases (d4 in Figure 4). Therefore, the capacitance decrease of C1 is greater than the capacitance decrease of C2.

[0021] Thus, in the low-pass filter circuit 36 ​​of this embodiment, when the capacitance of one of the capacitors C1 and C2 decreases significantly, the capacitance of the other capacitor decreases less. As a result, the total capacitance that fluctuates with pulses is suppressed for the entire low-pass filter circuit 36. This suppresses fluctuations in the cutoff frequency of the low-pass filter circuit 36. This makes it easier to obtain desired characteristics for the output signal output to the output terminal 56.

[0022] This can be more clearly understood by comparing it with a conventional class D amplifier circuit. Figure 5 is a diagram showing a conventional class D amplifier circuit 301. The conventional class-D amplifier circuit 301 includes a PWM modulation circuit 321, a drive circuit 341, a low-pass filter circuit 361, and a load circuit 621. The low-pass filter circuit 361 includes an inductor 401 and a capacitor 101. The capacitor 101 is indicated by C in FIG. 5 . One external electrode of the inductor 401 is connected to an input terminal 501 of the low-pass filter circuit 361. The other external electrode of the inductor 401 is connected to an output terminal 561 of the low-pass filter circuit 361. Conventional low-pass filter circuit 361 includes only one capacitor 101. One external electrode of capacitor 101 is connected to second potential terminal 521b. The potential of second potential terminal 521b can be set to GND (ground) potential. The other external electrode of capacitor 101 is connected to output terminal 561. Furthermore, a load circuit 621 such as a speaker is connected to the output terminal 561 .

[0023] Consider a case where a pulse is input to input terminal 501 of low-pass filter circuit 361 in conventional class-D amplifier circuit 301 shown in Fig. 5. Fig. 6 is a diagram showing the voltage applied to capacitor 101 and the like when a pulse is input to conventional class-D amplifier circuit 301. When the pulse input to low-pass filter circuit 36 ​​is Hi, the voltage applied to capacitor 101 (C) increases (d5 in FIG. 6). On the other hand, when the input pulse is L, the voltage applied to C decreases (d6 in FIG. 6). Therefore, when the pulse is Hi, the capacitance of C decreases, and when the pulse is L, the capacitance of C decreases. In this way, in conventional class-D amplifier circuit 301, the capacitance of capacitor 101 changes in response to fluctuations in the pulse voltage. If the capacitance of capacitor 101, i.e., C, fluctuates in response to the pulse, the cutoff frequency of low-pass filter circuit 361 will fluctuate in response to the pulse. If the cutoff frequency of low-pass filter circuit 361 fluctuates, there is a risk that the audio signal, for example, output to output terminal 561 will not have the desired characteristics.

[0024] In contrast, in the class D amplifier circuit 30 of this embodiment, the low-pass filter circuit 36 ​​is provided with two capacitors 1. Therefore, even if the voltage of the pulse input to the low-pass filter circuit 36 ​​fluctuates significantly, the effect on the signal output from the output terminal 56 can be suppressed. Furthermore, for example, if the load circuit 62 connected to the output terminal 56 is a speaker and the signal to be output is an audio signal, a desired and preferable audio output can be obtained.

[0025] Various setting values ​​in the class-D amplifier circuit 30 of this embodiment can be determined as appropriate. Examples of setting values ​​include a cutoff frequency of 50 kHz to 100 kHz, a capacitance of C1 (first capacitor 1a) of 7 uF, a capacitance of C2 (second capacitor) of 7 uF, and an inductance of inductor 40 of 500 nH. The capacitance ratio between capacitors C1 and C2 can be set within ±50%, preferably ±10%.

[0026] (Capacitor configuration) Next, we will explain the configuration of the capacitor 1. The two capacitors 1, namely, the first capacitor 1a and the second capacitor 1b, provided in the low-pass filter circuit 36 ​​are each composed of one four-terminal multilayer ceramic capacitor 1c. First, the overall structure of the four-terminal multilayer ceramic capacitor 1c will be explained with reference to FIG.

[0027] (Outline of a four-terminal multilayer ceramic capacitor) As shown in FIG. 7, the four-terminal multilayer ceramic capacitor 1c includes a laminate 2 and external electrodes 20.

[0028] (Direction definition) The drawings appropriately show the L direction, W direction, and T direction. The L direction is the length direction of the four-terminal multilayer ceramic capacitor 1c. The W direction is the width direction of the four-terminal multilayer ceramic capacitor 1c. The T direction is the height direction of the four-terminal multilayer ceramic capacitor 1c. Therefore, the cross section shown in FIG. 10 is called an LT cross section, and the cross section shown in FIG. 11 is called a WT cross section. Furthermore, FIGS. 12, 13, and 14 are called LW cross sections. The length direction L, width direction W, and height direction T do not necessarily have to be perpendicular to each other. The length direction L, width direction W, and height direction T may intersect each other.

[0029] (Outer shape of laminate) The laminate 2 has a substantially rectangular parallelepiped shape. The laminate 2 has two main surfaces 3, two end surfaces 4, and two side surfaces 5. The main surfaces 3 are surfaces facing the height direction T. The end surfaces 4 are surfaces facing the length direction L. The side surfaces 5 are surfaces facing the width direction W. One of the two main surfaces 3 is the first main surface 3a, and the other is the second main surface 3b. One of the two end surfaces 4 is the first end surface 4a, and the other is the second end surface 4b. One of the two side surfaces 5 is the first side surface 5a, and the other is the second side surface 5b. Figure 7 shows the second main surface 3b and the first side surface 5a.

[0030] It is preferable that the ridges and corners of the laminate 2 are rounded. A ridge is a portion where two surfaces of the laminate 2 intersect. A corner is a portion where three surfaces of the laminate 2 intersect. The size of the laminate 2 is not particularly limited.

[0031] (external electrode) The external electrodes 20 formed on the laminate 2 include a first external electrode 20e, a second external electrode 20f, a third external electrode 20g, and a fourth external electrode 20h. The first external electrode 20e is formed mainly on the first end surface 4a of the laminate 2, the second external electrode 20f is formed mainly on the first side surface 5a of the laminate 2, the third external electrode 20g is formed mainly on the second side surface 5b of the laminate 2, and the fourth external electrode 20h is formed mainly on the second end surface 4b of the laminate 2.

[0032] Specifically, the first external electrode 20e is formed continuously over the entire first end surface 4a of the laminate 2, as well as over parts of the two main surfaces 3 and parts of the two side surfaces. The second external electrode 20f is formed continuously over part of the first side surface 5a and parts of the two main surfaces 3 of the laminate 2. Similar to the second external electrode 20f, the third external electrode 20g is formed continuously over part of the second side surface 5b and parts of the two main surfaces 3 of the laminate 2. Similar to the first external electrode 20e, the fourth external electrode 20h is formed continuously over the entire second end surface 4b of the laminate 2, as well as over parts of the two main surfaces 3 and parts of the two side surfaces.

[0033] (Outline of the internal electrode) The laminate 2 includes a plurality of dielectrics 7 and a plurality of internal electrodes 10. The internal electrodes 10 included in the four-terminal multilayer ceramic capacitor 1c will be described with reference to Fig. 8. Fig. 8 is a diagram showing at least a portion of the internal electrodes 10 provided in the four-terminal multilayer ceramic capacitor 1c. The internal electrodes 10 include at least one layer of first internal electrodes 10a, at least one layer of second internal electrodes 10b, and at least one layer of third internal electrodes 10c.

[0034] The first internal electrode 10a, the second internal electrode 10b, and the third internal electrode 10c are arranged in this order in the height direction T. Fig. 8 shows one layer of each internal electrode 10. This is an example, and the configuration shown in Fig. 8 may be repeatedly stacked multiple times.

[0035] (Internal electrode lead-out part) The internal electrode 10 has a facing portion 11 and an extended portion 12. The facing portion 11 is a portion where one internal electrode 10 overlaps another internal electrode 10 when viewed from the height direction T. The extended portion 12 is a portion extended from the facing portion 11 in order to connect the internal electrode 10 to the external electrode 20. In other words, the facing portion 11 is connected to the external electrode 20 via the extended portion 12.

[0036] Specifically, the first internal electrode 10a has a first lead portion 12a extending in the longitudinal direction L. The first opposing portion 11a of the first internal electrode 10a is connected to the first external electrode 20e via the first lead portion 12a.

[0037] Similarly, the second internal electrode 10b has a second lead portion 12b and a third lead portion 12c extending in the width direction W. The second opposing portion 11b of the second internal electrode 10b is connected to the second external electrode 20f via the second lead portion 12b. The second opposing portion 11b of the second internal electrode 10b is connected to the third external electrode 20g via the third lead portion 12c. In this way, the second internal electrode 10b is connected to two external electrodes 20 in the width direction W.

[0038] The third internal electrode 10c has a fourth lead portion 12d extending in the length direction L. The third opposing portion 11c of the third internal electrode 10c is connected to the fourth external electrode 20h via the fourth lead portion 12d.

[0039] As described above, the internal electrodes 10 are connected to four corresponding external electrodes 20. The four external electrodes 20 correspond to the four terminals of the four-terminal multilayer ceramic capacitor 1c.

[0040] The correspondence between the two capacitors 1 provided in the low-pass filter circuit 36 ​​and the four-terminal multilayer ceramic capacitor 1c will be described. Fig. 9 is a diagram showing the circuit configuration of the low-pass filter circuit 36. As described above, the first capacitor 1a and the second capacitor 1b included in the low-pass filter circuit 36 ​​are configured as one four-terminal multilayer ceramic capacitor 1c.

[0041] The first capacitor 1a corresponds to the portion where the first internal electrode 10a and the second internal electrode 10b of the four-terminal multilayer ceramic capacitor 1c face each other, and the second capacitor 1b corresponds to the portion where the second internal electrode 10b and the third internal electrode 10c of the four-terminal multilayer ceramic capacitor 1c face each other.

[0042] Therefore, the external electrode (A) 20a of the first capacitor 1a corresponds to the first external electrode 20e of the four-terminal multilayer ceramic capacitor 1c.

[0043] Furthermore, the external electrode (B) 20b of the first capacitor 1a corresponds to the second external electrode 20f and the third external electrode 20g of the four-terminal multilayer ceramic capacitor 1c. Similarly, the external electrode (C) 20c of the second capacitor 1b corresponds to the second external electrode 20f and the third external electrode 20g of the four-terminal multilayer ceramic capacitor 1c. This is because the first capacitor 1a and the second capacitor 1b share the second internal electrode 10b.

[0044] Furthermore, the external electrode (D) 20d of the second capacitor 1b corresponds to the fourth external electrode 20h of the four-terminal multilayer ceramic capacitor 1c.

[0045] In summary, the four-terminal multilayer ceramic capacitor 1c includes multiple internal electrodes 10 and first to fourth external electrodes. The first external electrode 20e corresponds to one external electrode 20 of the first capacitor 1a connected to the first potential terminal 52a, i.e., the external electrode (A) 20a. The fourth external electrode 20h corresponds to one external electrode 20 of the second capacitor 1b connected to the second potential terminal 52b, i.e., the external electrode (D) 20d. The second external electrode 20f and the third external electrode 20g correspond to the other external electrode 20 of the first capacitor 1a, i.e., the external electrode (B) 20b. The second external electrode 20f and the third external electrode 20g also correspond to the other external electrode 20 of the second capacitor 1b, i.e., the external electrode (C) 20c.

[0046] The multiple internal electrodes 10 include a first internal electrode 10a connected to a first external electrode 20e. The multiple internal electrodes 10 also include a second internal electrode 10b facing the first internal electrode 10a via a dielectric 7 and connected to a second external electrode 20f and a third external electrode 20g. The multiple internal electrodes 10 also include a third internal electrode 10c facing the second internal electrode 10b via a dielectric 7 and connected to a fourth external electrode 20h.

[0047] The cross-sectional structure of the laminate 2 will be described below with reference to a cross-sectional view of the laminate 2. (Internal structure of laminate (LT cross section)) The internal structure of the laminate 2 will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view of the four-terminal multilayer ceramic capacitor 1c shown in Fig. 7 taken along line II. Fig. 10 shows a cross-section of the four-terminal multilayer ceramic capacitor 1c taken along line LT. The laminate 2 includes a plurality of dielectrics 7 and a plurality of internal electrodes 10. The plurality of dielectrics 7 and the plurality of internal electrodes 10 are stacked on top of each other in the height direction T.

[0048] (Internal electrode) As described above, the internal electrodes 10 include the first internal electrode 10a, the second internal electrode 10b, and the third internal electrode 10c. In the LT cross section, the first opposing portion 11a of the first internal electrode 10a is connected to the first external electrode 20e formed on the first end face 4a via the first lead portion 12a. Also, the third opposing portion 11c of the third internal electrode 10c is connected to the fourth external electrode 20h formed on the second end face 4b via the fourth lead portion 12d. On the other hand, the second internal electrode 10b is not connected to the external electrode 20 in the LT cross section. This is because the second internal electrode 10b is connected to the external electrode 20 at the side surface 5.

[0049] (Internal structure of laminate (WT cross section)) The internal structure of the laminate 2 will be described with reference to Fig. 11. Fig. 11 is a cross-sectional view of the four-terminal multilayer ceramic capacitor 1c taken along line II-II of Fig. 7. Fig. 11 shows a WT cross section of the four-terminal multilayer ceramic capacitor 1c.

[0050] In the WT cross section, the second opposing portion 11b of the second internal electrode 10b is connected to the second external electrode 20f formed on the first side surface 5a via the second lead portion 12b. Also, the second opposing portion 11b of the second internal electrode 10b is connected to the third external electrode 20g formed on the second side surface 5b via the third lead portion 12c. In this way, the second internal electrode 10b is connected to the external electrode 20 on both side surfaces 5. On the other hand, the first internal electrode 10a and the third internal electrode 10c are not connected to the external electrode 20 in the WT cross section. This is because the first internal electrode 10a and the third internal electrode 10c are connected to the external electrode 20 at the end face 4.

[0051] (Planar structure of internal electrode (LW cross section)) The planar structure of the internal electrode 10 will be described with reference to Fig. 12 to Fig. 14. The planar structure refers to the structure of the internal electrode 10 when viewed from the height direction T of the four-terminal multilayer ceramic capacitor 1c. Fig. 12 to Fig. 14 are cross-sectional views taken along line III-III in Fig. 7. Fig. 12 to Fig. 14 show the LW cross section of the four-terminal multilayer ceramic capacitor 1c.

[0052] (1st internal electrode) FIG. 12 shows the planar structure of the first internal electrode 10a. The first opposing portion 11a of the first internal electrode 10a is connected to the first external electrode 20e formed on the first end surface 4a via the first lead portion 12a. The length of the first lead portion 12a in the width direction W is shorter than the length of the first opposing portion 11a in the width direction W. In addition, the first internal electrode 10a is not connected to any external electrodes 20 other than the first external electrode 20e.

[0053] (2nd internal electrode) FIG. 13 shows the planar structure of the second internal electrode 10b. The second opposing portion 11b of the second internal electrode 10b is connected to the second external electrode 20f formed on the first side surface 5a via the second lead portion 12b. The second opposing portion 11b of the second internal electrode 10b is connected to the third external electrode 20g formed on the second side surface 5b via the third lead portion 12c. The length in the longitudinal direction L of the second lead portion 12b and the length in the longitudinal direction L of the third lead portion 12c are shorter than the length in the longitudinal direction L of the second opposing portion 11b. The second internal electrode 10b is not connected to any external electrodes 20 other than the second external electrode 20f and the third external electrode 20g.

[0054] (3rd internal electrode) FIG. 14 shows the planar structure of the third internal electrode 10c. The third opposing portion 11c of the third internal electrode 10c is connected to a fourth external electrode 20h formed on the second end surface 4b via a fourth lead portion 12d. The length of the fourth lead portion 12d in the width direction W is shorter than the length of the third opposing portion 11c in the width direction W. In addition, the third internal electrode 10c is not connected to any external electrodes 20 other than the fourth external electrode 20h.

[0055] (number of dielectric layers) The number of dielectric layers 7 stacked on the laminate 2 can be, for example, 5 to 2000.

[0056] (dielectric thickness) The thickness of the dielectric 7 can be set to, for example, 0.3 μm or more and 0.6 μm or less.

[0057] (Dielectric material) The dielectric 7 may be made of a dielectric ceramic mainly composed of BaTiO3, CaTiO3, SrTiO3, CaZrO3, etc. Alternatively, a material containing a subcomponent such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound may be added to the main component.

[0058] (Number of internal electrode layers) The number of layers of the internal electrodes 10 can be, for example, 10 to 2000. The number of layers of the internal electrodes 10 includes the number of layers of the first internal electrodes 10a and the number of layers of the second internal electrodes 10b.

[0059] (internal electrode thickness) The thickness of the internal electrode 10 can be set to, for example, 0.1 μm or more and 5.0 μm or less, and preferably 0.2 μm or more and 2.0 μm or less.

[0060] (internal electrode material) The material of the internal electrode 10 can be, for example, a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy of Ni and Cu, an alloy of Ag and Pd, etc. In addition, the material of the internal electrode 10 may contain dielectric particles having the same composition as the ceramic contained in the dielectric 7.

[0061] (size of multilayer ceramic capacitor) The size of the four-terminal multilayer ceramic capacitor 1c is not particularly limited. The size of the four-terminal multilayer ceramic capacitor 1c can be, for example, as follows: The length direction L dimension of the four-terminal multilayer ceramic capacitor 1c, including the laminate 2 and the external electrodes 20, is defined as L dimension. The L dimension is preferably 0.25 mm or more and 1.0 mm or less. The height direction T dimension of the four-terminal multilayer ceramic capacitor 1c, including the laminate 2 and the external electrodes 20, is defined as T dimension. The T dimension is preferably 0.125 mm or more and 0.5 mm or less. The width direction W dimension of the four-terminal multilayer ceramic capacitor 1c, including the laminate 2 and the external electrodes 20, is defined as W dimension. The W dimension is preferably 0.125 mm or more and 0.5 mm or less.

[0062] (Layer structure of external electrodes) The external electrode 20 may have a multi-layer structure. For example, a three-layer structure may have three layers: an underlayer, an inner plating layer, and a surface plating layer. The underlayer may be, for example, a baked layer of a material containing a glass component and a metal. The inner plating layer may be a Ni plating layer. The surface plating layer may be a Sn plating layer.

[0063] (Manufacturing method of multilayer ceramic capacitors) A method for manufacturing the four-terminal multilayer ceramic capacitor 1c will now be described. (Making stacked blocks) Ceramic green sheets and electrode paste for the internal electrodes 10 are prepared.

[0064] (Paste application) The electrode paste is applied to the ceramic green sheets in a desired pattern. The application of the electrode paste to the ceramic green sheets can be performed by, for example, screen printing or gravure printing. This results in ceramic green sheets for the inner layer portion on which the paste is printed.

[0065] (Laminated) A predetermined number of ceramic green sheets without the pattern of the internal electrode 10 printed thereon are stacked. This creates the portion corresponding to the outer layer portion. Ceramic green sheets for the inner layer portion, coated with paste, are stacked on top of this in sequence. This creates the portion corresponding to the inner layer portion. A predetermined number of ceramic green sheets for the other outer layer portion are then stacked on top of this. This creates a laminated sheet. The laminated sheet is pressed in the height direction using a means such as an isostatic press to create a laminated block.

[0066] (Fabrication of stacked chips) The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0067] (Firing) Next, the laminated chip is fired to produce the laminate 2. The firing temperature depends on the materials of the dielectric 7 and the internal electrodes 10, but is preferably 900°C or higher and 1400°C or lower.

[0068] (external electrode) Next, the external electrodes 20 are formed. First, a conductive paste that will become the base layer is applied to the desired position of the laminate 2 and baked to form the base layer. After that, a Ni plating layer is formed on the base layer, and then a Sn plating layer is formed on the Ni plating layer. The Ni plating layer becomes the inner plating layer, and the Sn plating layer becomes the surface plating layer. In this manner, the four-terminal multilayer ceramic capacitor 1c to be provided in the class-D amplifier circuit 30 can be fabricated.

[0069] (Embodiment 2) A second embodiment of the present invention will be described below with reference to FIGS. 15 and 16. FIG. 15 is a diagram showing a class-D amplifier circuit of the second embodiment. FIG. 16 is a diagram showing a potential difference when a signal is input to the differential signal filter circuit of the second embodiment. The following explanation will mainly focus on differences from the first embodiment. In the second embodiment, a filter circuit including two capacitors 1 is used as a differential signal filter. The configuration of the class-D amplifier circuit 30 of the second embodiment will be described below in order.

[0070] (Drive circuit) The class-D amplifier circuit 30 of the second embodiment includes a PWM modulation circuit (not shown), a first drive circuit 34a connected to the PWM modulation circuit, a second drive circuit 34b connected to the PWM modulation circuit, and a differential signal filter circuit 38 connected to the first drive circuit 34a and the second drive circuit 34b. In this way, the class-D amplifier circuit 30 includes two drive circuits 34. The first drive circuit 34a is OUTP, and the second drive circuit 34b is OUTN.

[0071] (Differential signal filter circuit) The differential signal filter circuit 38 includes two inductors 40 and two capacitors 1. The two inductors 40 are a first inductor 40a and a second inductor 40b. The two capacitors 1 are a first capacitor 1a and a second capacitor 1b. The first capacitor 1a and the second capacitor 1b each include a dielectric 7 and internal electrodes 10 that sandwich the dielectric 7.

[0072] (Terminal connection) The differential signal filter circuit 38 has two input terminals 50 and two output terminals 56. Specifically, the differential signal filter circuit 38 has a first input terminal 50a, a second input terminal 50b, a first output terminal 56a, a second output terminal 56b, and a reference potential terminal 54. The first input terminal 50a is connected to the first drive circuit 34a, and the second input terminal 50b is connected to the second drive circuit 34b. The reference potential terminal 54 is connected to a reference potential such as ground. The first output terminal 56a and the second output terminal 56b are connected to a load circuit 62.

[0073] (Capacitor) The following describes the connections of the capacitors 1. One external electrode 20i of the first capacitor 1a is connected to the first input terminal 50a, and one external electrode 20j of the second capacitor 1b is connected to the second input terminal 50b. The other external electrode 20k of the first capacitor 1a and the other external electrode 20l of the second capacitor 1b are connected to the reference potential terminal 54.

[0074] (inductor) The connections of the inductors 40 will now be described. One external electrode 42d of the first inductor 40a, which is one of the two inductors 40, is connected to the first input terminal 50a, and the other external electrode 42c of the first inductor 40a is connected to the first drive circuit 34a. Also, one external electrode 42f of the second inductor 40b is connected to the second input terminal 50b, and the other external electrode 42e of the second inductor 40b is connected to the second drive circuit 34b.

[0075] (four-terminal multilayer ceramic capacitor) Similarly to the low-pass filter circuit 36 ​​of the first embodiment, the first capacitor 1a and the second capacitor 1b provided in the differential signal filter circuit 38 are each formed of a single four-terminal multilayer ceramic capacitor 1c.

[0076] In the class D amplifier circuit 30 of the second embodiment, it is possible to output an output signal with desired characteristics even if the voltage of the signal input to the capacitor 1 of the differential signal filter circuit 38 changes. This will be explained below. Fig. 5 is a diagram showing the voltages applied to each capacitor 1 when a pulse is input to the class D amplifier circuit 30 of this embodiment. The X axis of Fig. 5 represents time. The Y axis of Fig. 5 represents potential.

[0077] When the pulse input to the first capacitor 1a of the differential signal filter circuit 38 is Hi, the voltage applied to C1, which is the first capacitor 1a, increases (d7 in FIG. 16). Conversely, the voltage applied to C2, which is the second capacitor 1b, decreases (d8 in FIG. 16). Therefore, the capacitance reduction of C1 is greater than the capacitance reduction of C2. Conversely, when the pulse input to the first capacitor 1a of the differential signal filter circuit 38 is L, the voltage applied to C1, which is the first capacitor 1a, decreases (d9 in FIG. 16). Conversely, the voltage applied to C2, which is the second capacitor 1b, increases (d10 in FIG. 16). Therefore, the capacitance reduction amount of C2 is greater than the capacitance reduction amount of C1.

[0078] Thus, in the differential signal filter circuit 38 of this embodiment, when the capacitance of one of the capacitors C1 and C2 decreases significantly, the capacitance of the other capacitor decreases less. As a result, the total capacitance that fluctuates in response to pulses is suppressed for the entire differential signal filter circuit 38. This suppresses fluctuations in the characteristics of the differential signal filter circuit 38. This makes it easier to obtain desired characteristics for the output signals output to the first output terminal 56a and the second output terminal 56b.

[0079] In the class D amplifier circuit 30 of the second embodiment, various set values ​​can be determined appropriately in the same way as in the first embodiment. Examples of the set values ​​can be the same as in the first embodiment, for example.

[0080] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various changes and modifications are possible.

[0081] <1> A class D amplifier circuit comprising: a PWM modulation circuit; a drive circuit connected to the PWM modulation circuit; and a low-pass filter circuit connected to the drive circuit, the low-pass filter circuit includes an inductor, a first capacitor, and a second capacitor; the first capacitor and the second capacitor each include a dielectric and electrodes sandwiching the dielectric; the low-pass filter circuit includes an input terminal, a first potential terminal, a second potential terminal, and an output terminal; the input terminal is connected to the drive circuit; the first potential terminal is connected to a first potential; the second potential terminal is connected to a second potential lower than the first potential; the output terminal is connected to a load circuit; one external electrode of the first capacitor is connected to the first potential terminal; one external electrode of the second capacitor is connected to the second potential terminal; the other external electrode of the first capacitor and the other external electrode of the second capacitor are connected to the output terminal; one external electrode of the inductor is connected to the input terminal; The other external electrode of the inductor is connected to an output terminal. Class D amplifier circuit.

[0082] <2> the first capacitor and the second capacitor are each formed of a single four-terminal multilayer ceramic capacitor; The four-terminal multilayer ceramic capacitor includes a plurality of internal electrodes and first to fourth external electrodes, the first external electrode is one external electrode of the first capacitor connected to the first potential terminal, the fourth external electrode is one external electrode of the second capacitor connected to the second potential terminal, the second external electrode and the third external electrode are the other external electrodes of the first capacitor and the other external electrodes of the second capacitor, the plurality of internal electrodes includes a first internal electrode connected to the first external electrode; the plurality of internal electrodes include a second internal electrode that faces the first internal electrode via a dielectric and is connected to the second external electrode and the third external electrode; the plurality of internal electrodes include a third internal electrode that faces the second internal electrode via a dielectric and is connected to the fourth external electrode; <1> The class D amplifier circuit described.

[0083] <3> a PWM modulation circuit, a first drive circuit connected to the PWM modulation circuit, a second drive circuit connected to the PWM modulation circuit, and a differential signal filter circuit connected to the first drive circuit and the second drive circuit; the differential signal filter circuit comprises a first inductor, a second inductor, a first capacitor, and a second capacitor; the first capacitor and the second capacitor each include a dielectric and electrodes sandwiching the dielectric; the differential signal filter circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a reference potential terminal; the first input terminal is connected to the first drive circuit; the second input terminal is connected to the second drive circuit; The reference potential terminal is connected to a reference potential, the first output terminal and the second output terminal are connected to a load circuit; one external electrode of the first capacitor is connected to the first output terminal; one external electrode of the second capacitor is connected to the second output terminal; the other external electrode of the first capacitor and the other external electrode of the second capacitor are connected to the reference potential terminal; one external electrode of the first inductor is connected to the first input terminal; the other external electrode of the first inductor is connected to the first drive circuit; one external electrode of the second inductor is connected to the second input terminal; The other external electrode of the second inductor is connected to the second drive circuit. Class D amplifier circuit.

[0084] <4> the first capacitor and the second capacitor are each formed of a single four-terminal multilayer ceramic capacitor; The four-terminal multilayer ceramic capacitor includes a plurality of internal electrodes and first to fourth external electrodes, the first external electrode is one external electrode of the first capacitor connected to the first output terminal, the fourth external electrode is one external electrode of the second capacitor connected to the second output terminal, the second external electrode and the third external electrode are the other external electrodes of the first capacitor and the other external electrodes of the second capacitor, the plurality of internal electrodes includes a first internal electrode connected to the first external electrode; the plurality of internal electrodes include a second internal electrode that faces the first internal electrode via a dielectric and is connected to the second external electrode and the third external electrode; the plurality of internal electrodes include a third internal electrode that faces the second internal electrode via a dielectric and is connected to the fourth external electrode; <3> The class D amplifier circuit described.

[0085] <5> the load circuit is a speaker; <1> from <4> 10. A class D amplifier circuit according to claim 9.

[0086] <6> The difference between the capacitance of the first capacitor and the capacitance of the second capacitor is within ±50%. <1> from <5> 10. A class D amplifier circuit according to claim 9.

[0087] <7> the first external electrode and the fourth external electrode are disposed on end faces of the four-terminal multilayer ceramic capacitor, the second external electrode and the third external electrode are disposed on side surfaces of the four-terminal multilayer ceramic capacitor. <2> or <4> The class D amplifier circuit described in [Explanation of symbols]

[0088] 1. Capacitor (multilayer ceramic capacitor) 2. Laminate 3 Main Surfaces 4 End face 5 Sides 7 Dielectrics 10 Internal electrode 11 Opposing part 12 Drawer section 20 External electrode 30 Class D amplifier circuit 32 PWM modulation circuit 34 Drive circuit 36 Low-pass filter circuit 38 Differential signal filter circuit 40 Inductor 42 Inductor outer electrode 50 input terminal 54 Reference potential terminal 56 Output terminal 58 Power supply 60 grand 62 Load circuit T Height direction L lengthwise W width direction E1 1st potential (power supply) E2 2nd potential (GND)

Claims

1. a PWM modulation circuit, a first drive circuit connected to the PWM modulation circuit, a second drive circuit connected to the PWM modulation circuit, and a differential signal filter circuit connected to the first drive circuit and the second drive circuit; the differential signal filter circuit comprises a first inductor, a second inductor, a first capacitor, and a second capacitor; the first capacitor and the second capacitor each include a dielectric and electrodes sandwiching the dielectric; the differential signal filter circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a reference potential terminal; the first input terminal is connected to the first drive circuit; the second input terminal is connected to the second drive circuit; The reference potential terminal is connected to a reference potential, the first output terminal and the second output terminal are connected to a load circuit; one external electrode of the first capacitor is connected to the first output terminal; one external electrode of the second capacitor is connected to the second output terminal; the other external electrode of the first capacitor and the other external electrode of the second capacitor are connected to the reference potential terminal; one external electrode of the first inductor is connected to the first input terminal; the other external electrode of the first inductor is connected to the first drive circuit; one external electrode of the second inductor is connected to the second input terminal; The other external electrode of the second inductor is connected to the second drive circuit.

2. the first capacitor and the second capacitor are each formed of a single four-terminal multilayer ceramic capacitor, The four-terminal multilayer ceramic capacitor includes a plurality of internal electrodes and first to fourth external electrodes, the first external electrode is one external electrode of the first capacitor connected to the first output terminal, the fourth external electrode is one external electrode of the second capacitor connected to the second output terminal, the second external electrode and the third external electrode are the other external electrodes of the first capacitor and the other external electrodes of the second capacitor, the plurality of internal electrodes includes a first internal electrode connected to the first external electrode, the plurality of internal electrodes include a second internal electrode that faces the first internal electrode via a dielectric and is connected to the second external electrode and the third external electrode; 2. The class D amplifier circuit according to claim 1, wherein the plurality of internal electrodes include a third internal electrode that faces the second internal electrode via a dielectric and is connected to the fourth external electrode.

3. 3. The class D amplifier circuit according to claim 1, wherein the load circuit is a speaker.

4. 3. The class D amplifier circuit according to claim 1, wherein a difference between the capacitance of the first capacitor and the capacitance of the second capacitor is within ±50%.

5. the first external electrode and the fourth external electrode are disposed on end surfaces of the four-terminal multilayer ceramic capacitor, 3. The class D amplifier circuit according to claim 2, wherein the second external electrode and the third external electrode are disposed on side surfaces of the four-terminal multilayer ceramic capacitor.

6. the first external electrode and the fourth external electrode are disposed on end surfaces of the four-terminal multilayer ceramic capacitor, 5. The class D amplifier circuit according to claim 4, wherein the second external electrode and the third external electrode are disposed on side surfaces of the four-terminal multilayer ceramic capacitor.

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